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2024-03-29T12:52:19Z
User contributions
MediaWiki 1.40.0
https://www.coreboot.org/index.php?title=Board:ecs/p6iwp-fe&diff=9831
Board:ecs/p6iwp-fe
2010-07-22T22:37:03Z
<p>AJenbo: /* Status */</p>
<hr />
<div>This board is very pick about what rom chips it can use and it will fry any chip that doesn't work.<br />
Confirmed chips are: Intel 82802AB<br />
<br />
Chips that dosn't work: PMC Pm49FL004, SST SST49LF004C<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comment = Didn't test vbios only X-server<br />
|Onboard_ethernet_status = Untested<br />
|Onboard_audio_status = Untested<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = Untested<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|PP_status = Untested<br />
|PS2_keyboard_status = Untested<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = Untested<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = Untested<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Welcome_to_coreboot&diff=9818
Welcome to coreboot
2010-06-25T22:44:09Z
<p>AJenbo: </p>
<hr />
<div></div>
AJenbo
https://www.coreboot.org/index.php?title=Board:ecs/p6iwp-fe&diff=9817
Board:ecs/p6iwp-fe
2010-06-25T22:43:43Z
<p>AJenbo: Created page with 'This board is very pick about what rom chips it can use and it will fry any chip that doesn't work. Confirmed chips are: Intel 82802AB Chips that dosn't work: PMC Pm49FL004, SST…'</p>
<hr />
<div>This board is very pick about what rom chips it can use and it will fry any chip that doesn't work.<br />
Confirmed chips are: Intel 82802AB<br />
<br />
Chips that dosn't work: PMC Pm49FL004, SST SST49LF004C<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comment = Didn't test vbios only X-server<br />
|Onboard_ethernet_status = Untested<br />
|Onboard_audio_status = Untested<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = Untested<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|PP_status = Untested<br />
|PS2_keyboard_status = Untested<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = Untested<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = Untested<br />
|Poweroff_status = NO<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxe&diff=9744
Board:gigabyte/ga-6bxe
2010-05-31T15:14:03Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = WIP<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|PP_status = WIP<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = WIP<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Poweroff_status = Untested<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxe&diff=9743
Board:gigabyte/ga-6bxe
2010-05-31T15:12:22Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = WIP<br />
|COM1_status = WIP<br />
|COM1_comments = It's running at 2x speed<br />
|COM2_status = Untested<br />
|PP_status = WIP<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = WIP<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Poweroff_status = Untested<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:soyo/sy-6ba-plus-iii&diff=9740
Board:soyo/sy-6ba-plus-iii
2010-05-31T15:01:33Z
<p>AJenbo: /* Status */</p>
<hr />
<div>[[File:Soyo sy-6ba plus iii.jpg|thumb|right|Soyo SY-6BA+ III]]<br />
<br />
This pages describes how to use coreboot on the [http://web.archive.org/web/20041210124602/www.soyo.com.tw/products/proddesc.php?id=75 Soyo SY-6BA+ III] mainboard. <br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = CPU: L1 I cache: 16K, L1 D cache: 16K<br />
|CPU_L2_status = WIP<br />
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it.<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list.<br />
<br />
|IDE_status = OK<br />
|IDE_CF_status = Untested<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = N/A<br />
|USB_status = OK<br />
|USB_comments = Tested: USB mouse on both USB ports.<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|AGP_cards_comments = <br />
|Mini_PCI_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = Tested: PCI NIC in all 5 PCI slots was tested OK.<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = WIP<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = WIP<br />
|PP_comments = Doing '''modprobe ppdev''' works fine, but further tests were not performed.<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = WIP<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|Sensors_comments = <br />
|Watchdog_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = N/A<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board.<br />
|SMBus_status = N/A<br />
|Reboot_status = OK<br />
|Poweroff_status = No<br />
|LEDs_status = N/A<br />
|LEDs_comments = No special-purpose LEDs available on the board.<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = N/A<br />
|WakeOnMouse_status = N/A<br />
|Flashrom_status = OK<br />
<br />
}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Datasheets&diff=9704
Datasheets
2010-05-18T08:25:27Z
<p>AJenbo: /* Intel 440BX */</p>
<hr />
<div></div>
AJenbo
https://www.coreboot.org/index.php?title=Welcome_to_coreboot&diff=9665
Welcome to coreboot
2010-05-14T23:44:11Z
<p>AJenbo: </p>
<hr />
<div></div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxe&diff=9664
Board:gigabyte/ga-6bxe
2010-05-14T22:51:56Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = WIP<br />
|COM1_status = WIP<br />
|COM1_comments = It's running at 2x speed<br />
|COM2_status = Untested<br />
|PP_status = WIP<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = WIP<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Poweroff_status = Untested<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:soyo/sy-6ba-plus-iii&diff=9644
Board:soyo/sy-6ba-plus-iii
2010-05-09T00:11:55Z
<p>AJenbo: /* Status */</p>
<hr />
<div>[[File:Soyo sy-6ba plus iii.jpg|thumb|right|Soyo SY-6BA+ III]]<br />
<br />
This pages describes how to use coreboot on the [http://web.archive.org/web/20041210124602/www.soyo.com.tw/products/proddesc.php?id=75 Soyo SY-6BA+ III] mainboard. <br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = CPU: L1 I cache: 16K, L1 D cache: 16K<br />
|CPU_L2_status = WIP<br />
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it.<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = OK<br />
|RAM_SDRAM_comments = Works, but currently the RAM settings are hardcoded to one 64MB DIMM and certain speed settings. This will be fixed soon, a patch is on the way.<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list.<br />
<br />
|IDE_status = OK<br />
|IDE_CF_status = Untested<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = N/A<br />
|USB_status = OK<br />
|USB_comments = Tested: USB mouse on both USB ports.<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = Untested<br />
|AGP_cards_comments = <br />
|Mini_PCI_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = Tested: PCI NIC in all 5 PCI slots was tested OK.<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = WIP<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = WIP<br />
|PP_comments = Doing '''modprobe ppdev''' works fine, but further tests were not performed.<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = WIP<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|Sensors_comments = <br />
|Watchdog_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = N/A<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board.<br />
|SMBus_status = N/A<br />
|Reboot_status = Untested<br />
|Poweroff_status = No<br />
|LEDs_status = N/A<br />
|LEDs_comments = No special-purpose LEDs available on the board.<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = N/A<br />
|WakeOnMouse_status = N/A<br />
|Flashrom_status = OK<br />
<br />
}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxe&diff=9643
Board:gigabyte/ga-6bxe
2010-05-09T00:05:59Z
<p>AJenbo: </p>
<hr />
<div>== Status ==<br />
<br />
The code for this board is still not in the trunk contact [[user:AJenbo|Anders Jenbo]] if you need it<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = WIP<br />
|COM1_status = WIP<br />
|COM1_comments = It's running at 2x speed<br />
|COM2_status = Untested<br />
|PP_status = WIP<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = WIP<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Poweroff_status = Untested<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Superiotool&diff=9642
Superiotool
2010-05-08T23:51:08Z
<p>AJenbo: /* Supported devices */</p>
<hr />
<div>'''Superiotool''' is a GPL'd user-space helper tool for coreboot development purposes (but may also be useful for other things). It allows you to detect which [[wikipedia:Super I/O|Super I/O]] you have on your mainboard, and it can provide detailed information about the register contents of the Super I/O.<br />
<br />
This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.<br />
<br />
<gallery><br />
Image:Ite it8705f.jpg|<small>ITE IT8705F</small><br />
Image:Winbond w83977ef.jpg|<small>Winbond W83977EF</small><br />
</gallery><br />
<br />
== Supported devices ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M1535/M1535D/M1535+/M1535D+<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/048024.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M512x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-September/024916.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-July/050471.html 2]<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71862FG / F71863FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71872F/FG / F71806F/FG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71882FG/F71883FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040016.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-November/026831.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F8000<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8228E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8661F/IT8770F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://article.gmane.org/gmane.linux.bios/42100/ 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F/IT8687R<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8702F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8703F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8705F/AF / IT8700F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026913.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8706R<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8708F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024879.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8710F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8711F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 2]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024884.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8720F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8722F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8726F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8510E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8511E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8761E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8780F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97307<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/047843.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87309<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87360<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026991.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87351<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87364<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87365<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87363<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87366<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8739x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/043447.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87591x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8741x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87372<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8374L<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071014/19fe07aa/attachment-0001.htm 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87427<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87373<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xFR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N971<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N972<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N252<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-June/050276.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M172<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xAPM<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C67x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B80x/FDC37M707<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N958FR<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027036.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B77x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B78x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M602<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M60x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B72x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M81x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B27x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027245.html 1]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027248.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B37x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47U33x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B34x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S42x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M10x/112/13x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025451.html 1] <br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B357<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M14x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M15x/192/997<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-December/028269.html 1]<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-February/030897.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S45x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M292<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B387<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B397<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M182<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M584<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| DME1737<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5504<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N217<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5514D-NS<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3112<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3114<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3116<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5317<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5027<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH4307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669FR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N237<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N769<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024883.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N3869/FDC37N869<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N227<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025846.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SIO10N268<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C665GT/IR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C666GT<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686A/VT82C686B<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977CTF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977EF/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040507.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627SF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697HF/F/HG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83L517D/D-F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83637HF/HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627THF/THG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment.txt 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025599.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-August/037685.html 3], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 4]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment-0001.txt 1]<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627DHG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-January/029517.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627UHG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83667HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977F-A/G-A/AF-A/AG-A<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977AF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977TF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627HF/F/HG/G<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025453.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025592.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697SF/UF/UG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025914.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627EHF/EF/EHG/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024887.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025284.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-January/029416.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877AF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-February/002119.html]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877TF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| WPCD376I<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-October/053894.html 1]<br />
| &mdash;<br />
|}<br />
<br />
|}<br />
<br />
'''Extended dumps (EC, HWM) available for:'''<br />
<br />
Use the '''--extra-dump''' option to see the contents of these registers.<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 1]<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond<br />
| W83627THF/THG HWM<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMSC<br />
| LPC47N227 runtime register block<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
<br />
<small><br />
<sup>1</sup> Previosly National Semiconductor, now bought by Winbond.<br /><br />
<sup>2</sup> Register dump output from a running coreboot system (vs. proprietary BIOS).<br /><br />
</small><br />
<br />
== Installation ==<br />
<br />
'''Manual installation'''<br />
<br />
$ svn co svn://coreboot.org/coreboot/trunk/util/superiotool<br />
$ cd superiotool<br />
$ make<br />
$ sudo make install<br />
<br />
'''Debian / Ubuntu'''<br />
<br />
$ apt-get install superiotool<br />
<br />
'''Fedora'''<br />
<br />
$ yum install superiotool<br />
<br />
== Usage ==<br />
<br />
Probe/detect the Super I/O in your mainboard:<br />
<br />
$ superiotool<br />
<br />
Register dump as table of hex-values (if the Super I/O is detected):<br />
<br />
$ superiotool -d<br />
<br />
Please see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool/README README] for further information.<br />
<br />
{{GPL}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9641
Board:gigabyte/ga-6bxc
2010-05-08T19:08:21Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
Nothing special is required to build core boot for this system.<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = WIP<br />
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it. <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = WIP<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = WIP<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = WIP<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = WIP<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Supported_Chipsets_and_Devices&diff=9608
Supported Chipsets and Devices
2010-05-02T19:03:30Z
<p>AJenbo: /* Devices supported in coreboot v4 */</p>
<hr />
<div>'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards.<br />
* If a device is not supported by coreboot v4, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v3|coreboot v3]] for support.<br />
* However, in general it is '''not''' recommended to use coreboot v3 &mdash; this was an experimental development tree which is gradually being merged into v4.<br />
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. It is definately desirable to port boards from v1 to v4 whereever possible.<br />
<br />
See also [[Supported Motherboards]].<br />
<br />
== Devices supported in coreboot v4 ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam10<br />
| style="background:lime" | OK<sup>16</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX1<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX&nbsp;(GX2)<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| LX<br />
| style="background: lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC710<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC925<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7520<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7525<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:yellow" | WIP<sup>11</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82810<br />
| style="background:yellow" | WIP<sup>9</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82855GME<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82855PM<br />
| style="background:red" | WIP<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SiS<br />
| SiS761GX<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601 (PLE133)<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623 (CLE266)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8T890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8M890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN400<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:lime" | OK<sup>14</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CX700<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VX800<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8111<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8131<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8132<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8151<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5530/CS5530A<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5535<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS780/RS785?<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700/SB7x0<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM21000<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5780<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5785<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 6300ESB (ESB6300)<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:yellow" | WIP<sup>6</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801AA/AB&nbsp;(ICH/ICH0)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801BA/BAM&nbsp;(ICH2/ICH2-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA/CAM&nbsp;(ICH3-S/ICH3-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB/DBL/DBM<br/>(ICH4/ICH4-L/ICH4-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801EB/ER&nbsp;(ICH5/ICH5R)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PXHD<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| CK804<br />
| style="background:lime" | OK<sup>17</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<sup>17</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Ricoh<br />
| RL5C476<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966(L)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237A<br />
| style="background:red" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237S<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | <sup>12</sup>, <sup>13</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8661F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8705F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK <sup>8</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:yellow" | OK <sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK <sup>15</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK <sup>15</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC8374<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:yellow" | OK <sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87360<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87366<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87417<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87427<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307 <br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ServerEngines<br />
| PILOT<br />
| style="background:yellow" | OK<sup>18</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M70x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B80x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B78x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B72x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B81x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M60x<br />
| style="background:lime" | OK<sup>3</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B27x<br />
| style="background:lime" | OK<sup>7</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M10x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M112<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M13x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M15x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M192<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B397<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| DME1737<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| SCH5307<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47N217<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686(A/B)<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627DHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627UHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627EHG/HF/EHF/THF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83697HF/HG<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THF<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977TF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:lime" | OK<sup>4</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| MPC74xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC4xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC7xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC970<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Emulated<br />
| QEMU<br />
| style="background:lime" | OK<br />
|}<br />
<br />
'''SOCs'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | SOC<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Elan SC520<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background: lime" | OK<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> Serial output should work for all ITE Super I/Os (but is only tested on the IT8671F and IT8712F). The rest ''could'' work, but is completely untested.<br /><br />
<sup>2</sup> Work in progress.<br /><br />
<sup>3</sup> Serial output on serial port 1 is tested and works, the rest probably not yet (tested on FDC37M602).<br /><br />
<sup>4</sup> The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least).<br /><br />
<sup>5</sup> Pre-RAM serial output works fine, but nothing else, yet.<br /><br />
<sup>6</sup> IDE support is available and tested. SMBus support may work, but is untested. USB support is on our TODO list.<br /><br />
<sup>7</sup> Pre-RAM serial output [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021247.html works fine], everything else is untested.<br /><br />
<sup>8</sup> [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021623.html Works fine] mostly, but support for more obscure features (floppy, game port, MIDI, IR) might need more work.<br /><br />
<sup>9</sup> Works mostly, but currently there are some limitations as to which RAM DIMMs can be used.<br /><br />
<sup>10</sup> These southbridges should all be supported by the (experimental) new code in src/southbridge/intel/i82801xx/ now. Please test this code and use this code for all new ICH* based boards. There's still some old code for the southbridges, but that should not be used anymore.<br /><br />
<sup>11</sup> Sort of works, but the settings are hardcoded for the Tyan S1846. This will be fixed soonish.<br /><br />
<sup>12</sup> All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though.<br /><br />
<sup>13</sup> The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737.<br /><br />
<sup>14</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
<sup>15</sup> The Intel 3100/EP80579 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far.<br /><br />
<sup>16</sup> Barcelona B0-B3 supported.<br /><br />
<sup>17</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br /><br />
<sup>18</sup> Partially supported, but not all features implemented.<br />
</small><br />
<br />
== Devices supported in coreboot v3 ==<br />
<br />
<div style="color: #ff0000">coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 are gradually being merged back into v4.</div><br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8111<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8132<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8151<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:orange" | WIP<sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Generic<br />
| i586<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel<br />
| Core Duo / Core 2 Duo<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| C7<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br />
</small><br />
<br />
== Devices supported in coreboot v1 ==<br />
<br />
Not all devices have been ported from coreboot v1 to coreboot v4, yet (check "v4?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1631<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Alpha<br />
| Tsunami<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD76x<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 430TX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440BX<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>3</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440GX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82815EP<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82860<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7500<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7505<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Micron<br />
| 21PAD<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC/AMD<br />
| GX1<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT694<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1543<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD766<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD768<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PIIX4E<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC/AMD<br />
| CS5530<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:lime" | OK<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 950<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B72X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B78X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B807<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C669<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C67X<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37N769<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83877TF<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<sup>1</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''North-/Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | North/South<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 540<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 550<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 630<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 635<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 730<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 735<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ST<br />
| STPC<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Alpha<br />
| EV6<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| ?<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> The W83977EF works fine with the W83977TF code in coreboot v4 (the pre-RAM serial part at least).<br /><br />
<sup>2</sup> Pre-RAM serial output works in coreboot v4, but the rest is not supported, yet.<br /><br />
<sup>3</sup> Work in progress.<br /><br />
</small><br />
<br />
__FORCETOC__</div>
AJenbo
https://www.coreboot.org/index.php?title=Supported_Chipsets_and_Devices&diff=9607
Supported Chipsets and Devices
2010-05-02T19:02:44Z
<p>AJenbo: /* Devices supported in coreboot v4 */</p>
<hr />
<div>'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards.<br />
* If a device is not supported by coreboot v4, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v3|coreboot v3]] for support.<br />
* However, in general it is '''not''' recommended to use coreboot v3 &mdash; this was an experimental development tree which is gradually being merged into v4.<br />
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. It is definately desirable to port boards from v1 to v4 whereever possible.<br />
<br />
See also [[Supported Motherboards]].<br />
<br />
== Devices supported in coreboot v4 ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam10<br />
| style="background:lime" | OK<sup>16</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX1<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX&nbsp;(GX2)<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| LX<br />
| style="background: lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC710<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC925<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7520<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7525<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:yellow" | WIP<sup>11</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82810<br />
| style="background:yellow" | WIP<sup>9</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82855GME<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82855PM<br />
| style="background:red" | WIP<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SiS<br />
| SiS761GX<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601 (PLE133)<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623 (CLE266)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8T890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8M890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN400<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:lime" | OK<sup>14</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CX700<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VX800<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8111<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8131<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8132<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8151<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5530/CS5530A<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5535<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS780/RS785?<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700/SB7x0<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM21000<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5780<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5785<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 6300ESB (ESB6300)<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:yellow" | WIP<sup>6</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801AA/AB&nbsp;(ICH/ICH0)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801BA/BAM&nbsp;(ICH2/ICH2-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA/CAM&nbsp;(ICH3-S/ICH3-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB/DBL/DBM<br/>(ICH4/ICH4-L/ICH4-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801EB/ER&nbsp;(ICH5/ICH5R)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PXHD<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| CK804<br />
| style="background:lime" | OK<sup>17</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<sup>17</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Ricoh<br />
| RL5C476<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966(L)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237A<br />
| style="background:red" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237S<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | <sup>12</sup>, <sup>13</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8661F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:green" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8705F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK <sup>8</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:yellow" | OK <sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK <sup>15</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK <sup>15</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC8374<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:yellow" | OK <sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87360<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87366<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87417<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87427<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307 <br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ServerEngines<br />
| PILOT<br />
| style="background:yellow" | OK<sup>18</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M70x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B80x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B78x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B72x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B81x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M60x<br />
| style="background:lime" | OK<sup>3</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B27x<br />
| style="background:lime" | OK<sup>7</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M10x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M112<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M13x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M15x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M192<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B397<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| DME1737<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| SCH5307<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47N217<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686(A/B)<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627DHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627UHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627EHG/HF/EHF/THF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83697HF/HG<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THF<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977TF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:lime" | OK<sup>4</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| MPC74xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC4xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC7xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC970<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Emulated<br />
| QEMU<br />
| style="background:lime" | OK<br />
|}<br />
<br />
'''SOCs'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | SOC<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Elan SC520<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background: lime" | OK<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> Serial output should work for all ITE Super I/Os (but is only tested on the IT8671F and IT8712F). The rest ''could'' work, but is completely untested.<br /><br />
<sup>2</sup> Work in progress.<br /><br />
<sup>3</sup> Serial output on serial port 1 is tested and works, the rest probably not yet (tested on FDC37M602).<br /><br />
<sup>4</sup> The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least).<br /><br />
<sup>5</sup> Pre-RAM serial output works fine, but nothing else, yet.<br /><br />
<sup>6</sup> IDE support is available and tested. SMBus support may work, but is untested. USB support is on our TODO list.<br /><br />
<sup>7</sup> Pre-RAM serial output [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021247.html works fine], everything else is untested.<br /><br />
<sup>8</sup> [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021623.html Works fine] mostly, but support for more obscure features (floppy, game port, MIDI, IR) might need more work.<br /><br />
<sup>9</sup> Works mostly, but currently there are some limitations as to which RAM DIMMs can be used.<br /><br />
<sup>10</sup> These southbridges should all be supported by the (experimental) new code in src/southbridge/intel/i82801xx/ now. Please test this code and use this code for all new ICH* based boards. There's still some old code for the southbridges, but that should not be used anymore.<br /><br />
<sup>11</sup> Sort of works, but the settings are hardcoded for the Tyan S1846. This will be fixed soonish.<br /><br />
<sup>12</sup> All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though.<br /><br />
<sup>13</sup> The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737.<br /><br />
<sup>14</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
<sup>15</sup> The Intel 3100/EP80579 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far.<br /><br />
<sup>16</sup> Barcelona B0-B3 supported.<br /><br />
<sup>17</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br /><br />
<sup>18</sup> Partially supported, but not all features implemented.<br />
</small><br />
<br />
== Devices supported in coreboot v3 ==<br />
<br />
<div style="color: #ff0000">coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 are gradually being merged back into v4.</div><br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8111<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8132<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8151<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:orange" | WIP<sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Generic<br />
| i586<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel<br />
| Core Duo / Core 2 Duo<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| C7<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br />
</small><br />
<br />
== Devices supported in coreboot v1 ==<br />
<br />
Not all devices have been ported from coreboot v1 to coreboot v4, yet (check "v4?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1631<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Alpha<br />
| Tsunami<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD76x<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 430TX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440BX<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>3</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440GX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82815EP<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82860<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7500<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7505<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Micron<br />
| 21PAD<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC/AMD<br />
| GX1<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT694<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1543<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD766<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD768<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PIIX4E<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC/AMD<br />
| CS5530<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:lime" | OK<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 950<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B72X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B78X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B807<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C669<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C67X<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37N769<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83877TF<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<sup>1</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''North-/Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | North/South<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 540<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 550<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 630<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 635<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 730<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 735<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ST<br />
| STPC<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Alpha<br />
| EV6<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| ?<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> The W83977EF works fine with the W83977TF code in coreboot v4 (the pre-RAM serial part at least).<br /><br />
<sup>2</sup> Pre-RAM serial output works in coreboot v4, but the rest is not supported, yet.<br /><br />
<sup>3</sup> Work in progress.<br /><br />
</small><br />
<br />
__FORCETOC__</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxe&diff=9604
Board:gigabyte/ga-6bxe
2010-05-02T00:55:48Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
The code for this board is still not in the trunk contact [[user:AJenbo|Anders Jenbo]] if you need it<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = WIP<br />
|COM1_comments = It's running at 2x speed<br />
|COM2_status = Untested<br />
|PP_status = Untested<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Poweroff_status = Untested<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=ASUS_MEDION2001&diff=9603
ASUS MEDION2001
2010-05-02T00:53:12Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
Work on this board in an very early state, but so fare there is serial output. The code for the NB and SB both exists in the V1 branch.<br />
<br />
{{Status|<br />
<br />
|CPU_status = Untested<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = Untested<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = Untested<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = Untested<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = Untested<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = Untested<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|PP_status = Untested<br />
|PS2_keyboard_status = Untested<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = Untested<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = Untested<br />
|Poweroff_status = Untested<br />
|LEDs_status = N/A<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = N/A<br />
|WakeOnMouse_status = N/A<br />
|Flashrom_status = No<br />
|Flashrom_comments = Write always fails so use a different board to flash the ROM<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=ASUS_MEDION2001&diff=9602
ASUS MEDION2001
2010-05-02T00:52:39Z
<p>AJenbo: Created page with '== Status == Work on this board in an very early state, but so fare there is serial output. The code for the NB and SB both exists in the V1 branch. {{Status| |CPU_status = WI…'</p>
<hr />
<div>== Status ==<br />
<br />
Work on this board in an very early state, but so fare there is serial output. The code for the NB and SB both exists in the V1 branch.<br />
<br />
{{Status|<br />
<br />
|CPU_status = WIP<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = Untested<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = Untested<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = Untested<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = Untested<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = Untested<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|PP_status = Untested<br />
|PS2_keyboard_status = Untested<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = Untested<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = Untested<br />
|Poweroff_status = Untested<br />
|LEDs_status = N/A<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = N/A<br />
|WakeOnMouse_status = N/A<br />
|Flashrom_status = No<br />
|Flashrom_comments = Write always fails so use a different board to flash the ROM<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Supported_Chipsets_and_Devices&diff=9581
Supported Chipsets and Devices
2010-04-29T14:26:54Z
<p>AJenbo: /* Devices supported in coreboot v3 */</p>
<hr />
<div>'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards.<br />
* If a device is not supported by coreboot v4, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v3|coreboot v3]] for support.<br />
* However, in general it is '''not''' recommended to use coreboot v3 &mdash; this was an experimental development tree which is gradually being merged into v4.<br />
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. It is definately desirable to port boards from v1 to v4 whereever possible.<br />
<br />
See also [[Supported Motherboards]].<br />
<br />
== Devices supported in coreboot v4 ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam10<br />
| style="background:lime" | OK<sup>16</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX1<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX&nbsp;(GX2)<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| LX<br />
| style="background: lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC710<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC925<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7520<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7525<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:yellow" | WIP<sup>11</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82810<br />
| style="background:yellow" | WIP<sup>9</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82855GME<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82855PM<br />
| style="background:red" | WIP<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SiS<br />
| SiS761GX<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601 (PLE133)<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623 (CLE266)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8T890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8M890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN400<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:lime" | OK<sup>14</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CX700<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VX800<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8111<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8131<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8132<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8151<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5530/CS5530A<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5535<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS780/RS785?<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700/SB7x0<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM21000<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5780<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5785<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 6300ESB (ESB6300)<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:yellow" | WIP<sup>6</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801AA/AB&nbsp;(ICH/ICH0)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801BA/BAM&nbsp;(ICH2/ICH2-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA/CAM&nbsp;(ICH3-S/ICH3-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB/DBL/DBM<br/>(ICH4/ICH4-L/ICH4-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801EB/ER&nbsp;(ICH5/ICH5R)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PXHD<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| CK804<br />
| style="background:lime" | OK<sup>17</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<sup>17</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Ricoh<br />
| RL5C476<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966(L)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237A<br />
| style="background:red" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237S<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | <sup>12</sup>, <sup>13</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8661F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8705F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK <sup>8</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:yellow" | OK <sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK <sup>15</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK <sup>15</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC8374<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:yellow" | OK <sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87360<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87366<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87417<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87427<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307 <br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ServerEngines<br />
| PILOT<br />
| style="background:yellow" | OK<sup>18</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M70x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B80x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B78x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B72x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B81x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M60x<br />
| style="background:lime" | OK<sup>3</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B27x<br />
| style="background:lime" | OK<sup>7</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M10x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M112<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M13x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M15x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M192<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B397<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| DME1737<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| SCH5307<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47N217<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686(A/B)<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627DHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627UHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627EHG/HF/EHF/THF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83697HF/HG<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THF<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977TF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:lime" | OK<sup>4</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| MPC74xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC4xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC7xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC970<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Emulated<br />
| QEMU<br />
| style="background:lime" | OK<br />
|}<br />
<br />
'''SOCs'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | SOC<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Elan SC520<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background: lime" | OK<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> Serial output should work for all ITE Super I/Os (but is only tested on the IT8671F and IT8712F). The rest ''could'' work, but is completely untested.<br /><br />
<sup>2</sup> Work in progress.<br /><br />
<sup>3</sup> Serial output on serial port 1 is tested and works, the rest probably not yet (tested on FDC37M602).<br /><br />
<sup>4</sup> The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least).<br /><br />
<sup>5</sup> Pre-RAM serial output works fine, but nothing else, yet.<br /><br />
<sup>6</sup> IDE support is available and tested. SMBus support may work, but is untested. USB support is on our TODO list.<br /><br />
<sup>7</sup> Pre-RAM serial output [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021247.html works fine], everything else is untested.<br /><br />
<sup>8</sup> [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021623.html Works fine] mostly, but support for more obscure features (floppy, game port, MIDI, IR) might need more work.<br /><br />
<sup>9</sup> Works mostly, but currently there are some limitations as to which RAM DIMMs can be used.<br /><br />
<sup>10</sup> These southbridges should all be supported by the (experimental) new code in src/southbridge/intel/i82801xx/ now. Please test this code and use this code for all new ICH* based boards. There's still some old code for the southbridges, but that should not be used anymore.<br /><br />
<sup>11</sup> Sort of works, but the settings are hardcoded for the Tyan S1846. This will be fixed soonish.<br /><br />
<sup>12</sup> All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though.<br /><br />
<sup>13</sup> The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737.<br /><br />
<sup>14</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
<sup>15</sup> The Intel 3100/EP80579 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far.<br /><br />
<sup>16</sup> Barcelona B0-B3 supported.<br /><br />
<sup>17</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br /><br />
<sup>18</sup> Partially supported, but not all features implemented.<br />
</small><br />
<br />
== Devices supported in coreboot v3 ==<br />
<br />
<div style="color: #ff0000">coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 are gradually being merged back into v4.</div><br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8111<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8132<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8151<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:orange" | WIP<sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Generic<br />
| i586<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel<br />
| Core Duo / Core 2 Duo<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| C7<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br />
</small><br />
<br />
== Devices supported in coreboot v1 ==<br />
<br />
Not all devices have been ported from coreboot v1 to coreboot v4, yet (check "v4?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1631<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Alpha<br />
| Tsunami<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD76x<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 430TX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440BX<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>3</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440GX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82815EP<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82860<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7500<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7505<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Micron<br />
| 21PAD<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC/AMD<br />
| GX1<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT694<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1543<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD766<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD768<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PIIX4E<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC/AMD<br />
| CS5530<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:lime" | OK<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 950<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B72X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B78X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B807<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C669<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C67X<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37N769<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83877TF<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<sup>1</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''North-/Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | North/South<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 540<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 550<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 630<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 635<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 730<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 735<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ST<br />
| STPC<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Alpha<br />
| EV6<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| ?<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> The W83977EF works fine with the W83977TF code in coreboot v4 (the pre-RAM serial part at least).<br /><br />
<sup>2</sup> Pre-RAM serial output works in coreboot v4, but the rest is not supported, yet.<br /><br />
<sup>3</sup> Work in progress.<br /><br />
</small><br />
<br />
__FORCETOC__</div>
AJenbo
https://www.coreboot.org/index.php?title=Supported_Chipsets_and_Devices&diff=9580
Supported Chipsets and Devices
2010-04-29T14:26:36Z
<p>AJenbo: Call v2 v4, it's better to keep it one way in the wiki.</p>
<hr />
<div>'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards.<br />
* If a device is not supported by coreboot v4, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v3|coreboot v3]] for support.<br />
* However, in general it is '''not''' recommended to use coreboot v3 &mdash; this was an experimental development tree which is gradually being merged into v4.<br />
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. It is definately desirable to port boards from v1 to v4 whereever possible.<br />
<br />
See also [[Supported Motherboards]].<br />
<br />
== Devices supported in coreboot v4 ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam10<br />
| style="background:lime" | OK<sup>16</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX1<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX&nbsp;(GX2)<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| LX<br />
| style="background: lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC710<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC925<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7520<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7525<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:yellow" | WIP<sup>11</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82810<br />
| style="background:yellow" | WIP<sup>9</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82855GME<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82855PM<br />
| style="background:red" | WIP<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SiS<br />
| SiS761GX<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601 (PLE133)<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623 (CLE266)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8T890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8M890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN400<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:lime" | OK<sup>14</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CX700<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VX800<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8111<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8131<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8132<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8151<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5530/CS5530A<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5535<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS780/RS785?<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700/SB7x0<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM21000<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5780<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5785<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 6300ESB (ESB6300)<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:yellow" | WIP<sup>6</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801AA/AB&nbsp;(ICH/ICH0)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801BA/BAM&nbsp;(ICH2/ICH2-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA/CAM&nbsp;(ICH3-S/ICH3-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB/DBL/DBM<br/>(ICH4/ICH4-L/ICH4-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801EB/ER&nbsp;(ICH5/ICH5R)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PXHD<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| CK804<br />
| style="background:lime" | OK<sup>17</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<sup>17</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Ricoh<br />
| RL5C476<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966(L)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237A<br />
| style="background:red" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237S<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | <sup>12</sup>, <sup>13</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8661F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8705F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK <sup>8</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:yellow" | OK <sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK <sup>15</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK <sup>15</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC8374<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:yellow" | OK <sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87360<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87366<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87417<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87427<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307 <br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ServerEngines<br />
| PILOT<br />
| style="background:yellow" | OK<sup>18</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M70x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B80x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B78x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B72x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B81x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M60x<br />
| style="background:lime" | OK<sup>3</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B27x<br />
| style="background:lime" | OK<sup>7</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M10x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M112<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M13x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M15x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M192<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B397<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| DME1737<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| SCH5307<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47N217<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686(A/B)<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627DHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627UHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627EHG/HF/EHF/THF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83697HF/HG<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THF<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977TF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:lime" | OK<sup>4</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| MPC74xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC4xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC7xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC970<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Emulated<br />
| QEMU<br />
| style="background:lime" | OK<br />
|}<br />
<br />
'''SOCs'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | SOC<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Elan SC520<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background: lime" | OK<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> Serial output should work for all ITE Super I/Os (but is only tested on the IT8671F and IT8712F). The rest ''could'' work, but is completely untested.<br /><br />
<sup>2</sup> Work in progress.<br /><br />
<sup>3</sup> Serial output on serial port 1 is tested and works, the rest probably not yet (tested on FDC37M602).<br /><br />
<sup>4</sup> The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least).<br /><br />
<sup>5</sup> Pre-RAM serial output works fine, but nothing else, yet.<br /><br />
<sup>6</sup> IDE support is available and tested. SMBus support may work, but is untested. USB support is on our TODO list.<br /><br />
<sup>7</sup> Pre-RAM serial output [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021247.html works fine], everything else is untested.<br /><br />
<sup>8</sup> [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021623.html Works fine] mostly, but support for more obscure features (floppy, game port, MIDI, IR) might need more work.<br /><br />
<sup>9</sup> Works mostly, but currently there are some limitations as to which RAM DIMMs can be used.<br /><br />
<sup>10</sup> These southbridges should all be supported by the (experimental) new code in src/southbridge/intel/i82801xx/ now. Please test this code and use this code for all new ICH* based boards. There's still some old code for the southbridges, but that should not be used anymore.<br /><br />
<sup>11</sup> Sort of works, but the settings are hardcoded for the Tyan S1846. This will be fixed soonish.<br /><br />
<sup>12</sup> All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though.<br /><br />
<sup>13</sup> The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737.<br /><br />
<sup>14</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
<sup>15</sup> The Intel 3100/EP80579 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far.<br /><br />
<sup>16</sup> Barcelona B0-B3 supported.<br /><br />
<sup>17</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br /><br />
<sup>18</sup> Partially supported, but not all features implemented.<br />
</small><br />
<br />
== Devices supported in coreboot v3 ==<br />
<br />
<div style="color: #ff0000">coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 are gradually being merged back into v2.</div><br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8111<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8132<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8151<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:orange" | WIP<sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Generic<br />
| i586<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel<br />
| Core Duo / Core 2 Duo<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| C7<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br />
</small><br />
<br />
== Devices supported in coreboot v1 ==<br />
<br />
Not all devices have been ported from coreboot v1 to coreboot v4, yet (check "v4?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1631<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Alpha<br />
| Tsunami<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD76x<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 430TX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440BX<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>3</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440GX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82815EP<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82860<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7500<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7505<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Micron<br />
| 21PAD<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC/AMD<br />
| GX1<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT694<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1543<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD766<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD768<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PIIX4E<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC/AMD<br />
| CS5530<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:lime" | OK<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 950<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B72X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B78X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B807<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C669<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C67X<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37N769<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83877TF<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<sup>1</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''North-/Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | North/South<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 540<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 550<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 630<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 635<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 730<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 735<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ST<br />
| STPC<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Alpha<br />
| EV6<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| ?<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> The W83977EF works fine with the W83977TF code in coreboot v4 (the pre-RAM serial part at least).<br /><br />
<sup>2</sup> Pre-RAM serial output works in coreboot v4, but the rest is not supported, yet.<br /><br />
<sup>3</sup> Work in progress.<br /><br />
</small><br />
<br />
__FORCETOC__</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxe&diff=9578
Board:gigabyte/ga-6bxe
2010-04-28T23:11:41Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
Work on this board is planed, but has not started yet.<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = WIP<br />
|COM1_comments = It's running at 2x speed<br />
|COM2_status = Untested<br />
|PP_status = Untested<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Poweroff_status = Untested<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Previous_GSoC_Projects&diff=9575
Previous GSoC Projects
2010-04-27T14:06:31Z
<p>AJenbo: /* Improve Linux as a BIOS [http://www.coreboot.org/Build_LinuxBIOS_using_LBdistro] */</p>
<hr />
<div>= Projects 2009 =<br />
<br />
== VGA BIOS for Geode LX ==<br />
<br />
This project's goal is to write a VGA BIOS (PCI option rom) for AMD Geode LX systems (such as the Linutop, Thincan or XO). There exists a [http://savannah.nongnu.org/projects/vgabios free VGA BIOS] but it knows nothing about real hardware. If you really want to kick the iron, this project could be enhanced to contain a complete infrastructure for including hardware initialization code for many different graphics cards.<br />
<br />
=== Links ===<br />
* [http://savannah.nongnu.org/projects/vgabios free VGA BIOS]<br />
<br />
=== Mentors ===<br />
* [[User:Ward|Ward Vandewege]]<br />
* [[User:Stepan|Stefan Reinauer]]<br />
* [[User:MJones|Marc Jones]]<br />
* [[User:Stuge|Peter Stuge]]<br />
<br />
== USB Option ROM for SeaBIOS ==<br />
<br />
SeaBIOS is our latest and greatest way to boot all kinds of different operating systems. It is a coreboot payload that implements 16bit BIOS interrupts as they are needed by nearly all boot loaders today. In the last year, SeaBIOS learned how to cope with coreboot ACPI, and how to boot off SCSI drives. One major feature that we're desperately lacking is USB stick/disk/cdrom booting from SeaBIOS.<br />
USB support for SeaBIOS should be implemented as a PCI option rom, using the [[libpayload]] USB stack. The USB stack currently supports UHCI controllers. Part of this project could also be to add OHCI and EHCI support to the USB stack in libpayload (not a requirement for participation, but would sure be nice!)<br />
<br />
=== Links ===<br />
* [[SeaBIOS]]<br />
* [[libpayload]]<br />
* [http://www.phoenix.com/NR/rdonlyres/56E38DE2-3E6F-4743-835F-B4A53726ABED/0/specsbbs101.pdf BIOS Boot Specification]<br />
* [http://www.phoenix.com/NR/rdonlyres/19FEBD17-DB40-413C-A0B1-1F3F560E222F/0/specsedd30.pdf BIOS Enhanced Disk Drive Specification]<br />
* [http://www.geocities.com/mamanzip/Articles/Low_Cost_Embedded_x86_Teaching_Tool.html#foreword Low Cost Embedded x86 Teaching Tool] by Darmawan Salihun contains an Option ROM example<br />
* Another [http://www.coresystems.de/~stepan/optionrom2.tar.bz2 Option ROM example]<br />
* [[USB Option ROM progess]]<br />
<br />
=== Mentors ===<br />
<br />
* [[User:MJones|Marc Jones]]<br />
* [[User:PatrickGeorgi|Patrick Georgi]]<br />
* [[User:Stepan|Stefan Reinauer]]<br />
<br />
== AVATT part 2 ==<br />
<br />
[[AVATT]] is coreboot+Linux+KVM as hypervisor in the ROM. A first version was done during last GSoC, but there is still a pretty big TODO list.<br />
=== TODO ===<br />
* make the kvm userspace tool not to crash anymore. A possible solution would be to fix the TLS issues from the version of uClibc we currently use (daily snapshots from their SVN tree). This could even mean porting the uClibc-nptl branch to x86 if both of the x86 linuxthreads branches prove to be too hard to fix.<br />
* user-friendly tool that can create and run virtual machines.<br />
* automatically starting the virtual machines at boot.<br />
* get the network to work in qemu since it fails with both coreboot v2 and v3.<br />
* integrate the virt-manager daemon inside the ROM image, if it and its dependencies fit the remaining free space. This needs network support, to really be useful.<br />
* fix compilation on x86_64 boxes by compiling everything in 64bit mode. We need a 64bit hardware anyway since the SVM instructions are available only on recent 64 bit boxes so this shouldn't matter too much, except for some extra wasted ROM space caused by the 64bit code. We can't cross-compile because we're not using a full toolchain, like buildroot does.<br />
* keep the versions as up-to-date as possible but also compatible with each other<br />
<br />
=== Mentors ===<br />
* [[User:Hailfinger|Carl-Daniel Hailfinger]]<br />
* [[User:Rminnich|Ron Minnich]]<br />
* [[User:Stepan|Stefan Reinauer]]<br />
<br />
<br />
= Projects 2008 =<br />
<br />
== SCSI booting in coreboot ==<br />
<br />
Currently coreboot can not boot from an arbitrary SCSI controller. There are two solutions for the problem:<br />
* Use Linux and Kexec. This requires to keep the SCSI driver in the flash chip.<br />
* Use x86emu/vm86/[[ADLO]] and the int13 method. This would allow to use the PCI option rom available on all modern SCSI controllers.<br />
<br />
So we obviously need a solution based on the later. This could as well be implemented as a Linux program, as an intermediate payload, or as a shared library.<br />
<br />
The code you are going to write needs to catch the int13 interrupt vector that the SCSI option rom installs and make it available to arbitrary (firmware/payload) code trying to load something from disk.<br />
<br />
This is a coreboot v3 project.<br />
<br />
== All Virtual All The Time ([[AVATT]]) ==<br />
<br />
The goal here is to build a system that comes up running Linux and KVM from power on reset. From that<br />
point the system could boot anything -- Windows, Linux, *BSD, Plan 9 -- anything that runs<br />
on x86 32 and 64-bit architectures. Coreboot would be <br />
integrated with a Linux kernel and initrd that had KVM built in. The initrd would include the minimal set of tools needed for starting new KVM virtual machine guests. Note that Linux booting from coreboot is a solved <br />
problem, using the buildrom tool, so the main effort here is to develop a minimal KVM infrastructure that<br />
can fit in a 2Mbyte FLASH part. Linux + X11 have been demonstrated in a 1Mbyte part, so we feel that this<br />
task is not impossible, but will be a terrific learning experience for a student, and will provide<br />
the community with a valuable resource when it is finished. The Xen and KVM communities have both asked<br />
for this capability for some time now, so there is a group of people ready to use this system when it is<br />
finished.<br />
<br />
== coreboot graphical port creator ==<br />
<br />
In coreboot v2, every port to a new mainboard requires that you touch a lot of source files with only minimal changes. In version 3 we try to fix this issue and pack all mainboard specific information into a configuration file that we call the Device Tree Source (DTS). <br />
This Device Tree config file is a simple text file describing what static (non-detectable and/or soldered on) devices are used on the mainbard and how they are wired (SPD-ROM, Interrupt Routing, SuperIO, Northbridge, Southbridge, Hypertransport,..). It is mostly organized as a tree (with some special cases, Hypertransport allows cycles for instance)<br />
<br />
The idea is to create a tool, based on the [www.eclipse.org/ Eclipse IDE], Swing, or your favourite portable toolkit, which allows you to drag and drop those components together and describe how they are wired. <br />
<br />
This would be a great help for mainboard vendors that build mainboards of already supported components. No more reading of coreboot code would be required, but rather only the understanding of the hardware, and probably the mainboard schematics.<br />
<br />
This is a coreboot v3 project. It requires good Java and/or Eclipse skills (or whatever toolkit/language you choose)<br />
<br />
== libpayload ==<br />
<br />
There are many, many "payloads" for coreboot these days: Linux, FILO, GRUB2, Tiano Core, Open Firmware, etherboot, and some more to count. All these payloads have a few functions in common that they use to read information from coreboot or change coreboot settings in NVRAM. It would be incredibly useful to unify all this code and enhance it, so that not every coreboot payload has to keep reinventing the wheel.<br />
<br />
<br />
= Projects 2007 =<br />
<br />
<br />
== Booting Windows and other Operating Systems in LinuxBIOS [http://linuxbios.org/Booting_Windows_using_LinuxBIOS]==<br />
<br />
The goal of this sub project is to figure out how to boot Windows Vista/XP/2003. There are three approaches that might proof successful:<br />
<br />
* using a dedicated LinuxBIOS loader (ie. adapting [http://www.reactos.org/ ReactOS] FREELDR)<br />
* booting Windows on top of Linux using [http://www.xmission.com/~ebiederm/files/kexec/README kexec]/[http://kboot.sourceforge.net/ kboot]<br />
* fixing [[ADLO]] so that it boots Vista/XP and removing the mainboard dependencies in it's code.<br />
* Some information on usage of bios services in Windows can be found [http://www.missl.cs.umd.edu/winint/index1.html here] and [http://www.missl.cs.umd.edu/winint/index2.html here].<br />
<br />
== Port GRUB2 to work in LinuxBIOS ==<br />
<br />
[[GRUB2]] is going to be _the_ bootloader of choice in the forseeable future. As such, it could replace both Grub legacy and FILO, the LinuxBIOS hack for grub compatibility. FILO lacks many features that come with GRUB2 with no extra effort.<br />
<br />
This task splits into four sub-problems:<br />
<br />
* Add a target i386-linuxbios, next to i386-pc and i386-efi to the configuration process<br />
* Add an IDE driver that does direct access instead of intXX calls<br />
* Make the build process generate a single static ELF image, like it is done on Sparc<br />
* Add support for reading the memory size from the LinuxBIOS table.<br />
<br />
<br />
== CMOS Config / Device Tree Browser Payload ==<br />
<br />
Unlike other BIOSes, Linux has no such thing as a "CMOS setup". This does not mean that you can not configure it. There is a nice and small Linux command line utility called [http://lxbios.sf.net lxbios] for that purpose. But people are often asking for a builtin config tool. Such a config tool could feature VGA graphics (maybe even VESA?), it should be easy to use, allow to browse information from LinuxBIOS' central structure: the device tree, and provide lxbios functionality with some sex appeal.<br />
<br />
This is a LinuxBIOSv3 project.<br />
<br />
== Open Firmware payload for LinuxBIOS ==<br />
<br />
Mitch Bradley from [http://www.firmworks.com/ Firmworks, Inc.] released the [http://www.openbios.org/OpenFirmware Open Firmware sources] under a BSD license. The released code does work in LinuxBIOS, but could use some proper integration and testing on some hardware or in [http://fabrice.bellard.free.fr/qemu/ Qemu]. <br />
<br />
Some ideas:<br />
<br />
* The released Open Firmware code is very much optimized towards the OLPC. A lot of things don't work yet on other systems, such as using a graphical framebuffer. Therefore things in LinuxBIOS need to be changed. For example, if LinuxBIOS initializes a graphics mode, it should add a LinuxBIOS table entry that specifies the address of the framebuffer and the depth and resolution.<br />
* Add words to view the LinuxBIOS table in OFW<br />
* Add words to change LinuxBIOS CMOS settings from OFW<br />
* For LinuxBIOSv3, the start address of the payload can be variable. This is a fundamental change to v2, and will make life a lot easier and LinuxBIOS a lot more flexible. OFW requires to know its in-rom address at build time. This needs to be fixed to a dynamic behavior<br />
* Also, there's no good documentation on what features can be used and how they can be used. Like the graphical OLPC menu, the built-in web server.<br />
* Get a STOP-A like behavior working in Linux<br />
* Get Smart Firmware working with new compilers<br />
* Get Smart Firmware working as a payload<br />
* Enhance the [[Distributed and Automated Testsystem]] to work with FILO and OpenFirmware payloads, and add The Hayes ANS Forth testsuite.<br />
<br />
Some parts might require cooperation with other GSoC projects:<br />
<br />
* Boot from Non-OFW SCSI controllers by running their int13 handler<br />
* Boot Windows XP/2003/Vista in OFW<br />
<br />
This project might benefit from Forth skills.<br />
<br />
== GNUFI or TianoCore payloads ==<br />
<br />
There are two open source EFI implementations out there. [http://gnufi.blogspot.com/ GNUFI] (or [http://www.hermann-uwe.de/blog/gnufi-the-gnu-firmware-implementation here] or [http://www.gnu.org/software/gnufi/ here]) and [http://www.tianocore.org/ TianoCore]. Try getting those to work as LinuxBIOS payloads, or change LinuxBIOS so it can load them as payloads.<br />
<br />
This project requires no hardware skills, but especially in case of TianoCore might require knowledge of Windows compilers (VC2005?)<br />
<br />
== Boot OpenSolaris, FreeBSD, NetBSD, OpenBSD or other free OSes ==<br />
<br />
LinuxBIOS has (despite its name) been a little Linux centric. A nice project would be to analyze what it takes to get OpenSolaris, the BSDs or other free operating systems to work in LinuxBIOS, without the need for legacy emulation (ie. no [[ADLO]])<br />
<br />
== Improve Linux as a BIOS [http://www.coreboot.org/Build_LinuxBIOS_using_LBdistro]==<br />
<br />
There's a small project called [http://tracker.coreboot.org/trac/buildrom buildrom] which creates a payload from a Linux kernel and some user space utilities. It has been written to work with the OLPC. This project could be enhanced to work on all supported LinuxBIOS motherboards.<br />
<br />
== Porting Flashrom utility to Windows 2000/XP ==<br />
<br />
Flashrom is used to burn LinuxBIOS binary to flash chips in the target motherboards. It runs on Unix/Linux. In this project the flashrom utility is ported from Linux/Unix to Windows 2000/XP. The Windows port is called Winflashrom. The project is divided into two tasks. The first task is to port most of the user space flashrom source code to MinGW and the second task is to code a Windows device driver to provide direct hardware access for the user space code. The difficulty of this task is in providing a reliable Windows device driver for the user space code.</div>
AJenbo
https://www.coreboot.org/index.php?title=Development_Guidelines&diff=9574
Development Guidelines
2010-04-27T13:10:24Z
<p>AJenbo: /* Required Toolchain */</p>
<hr />
<div>= Development Environment =<br />
<br />
== Required Toolchain ==<br />
<br />
* GNU development environment:<br />
** [http://gcc.gnu.org/ GCC] (tested: 4.1.2 prerelease)<br />
** G++<br />
** [http://www.kernel.org/pub/linux/devel/binutils/ binutils] (tested: 2.17.50.0.5)<br />
* libncurses*-dev<br />
* Python (tested: 2.4, 2.5)<br />
* bash (tested: 3.0, 3.1)<br />
* [http://www.acpica.org/downloads/ IASL], now part of the '''ACPICA''' download (package ''pmtools'' or ''iasl'' in many distributions)<br />
* [http://atrey.karlin.mff.cuni.cz/~mj/pciutils.shtml pciutils-devel/pciutils-dev]<br />
<br />
= Coding Guidelines =<br />
<br />
== General Guidelines ==<br />
<br />
* Encapsulate and isolate assembly language<br />
* Code shall not be "commented out"<br />
* No use of floating-point arithmetics<br />
* No hiding of identifiers defined in outer scopes<br />
* Typedefs are unique (device_t?)<br />
* Functions shall have prototype declarations<br />
* Local functions should be declared static<br />
* No definitions in header files<br />
* All variables are assigned before use<br />
* All objects should have fully qualified types (''unsigned int'' instead of ''unsigned'')<br />
* We suggest trying to import more such rules, such as additional ones described in [http://www.misra.org.uk/index.htm MISRA-C 2004] (''Guidelines for the use of C in critical systems'')<br />
<br />
== Comments ==<br />
<br />
=== References ===<br />
<br />
If you are referencing a data sheet or other documentation in the code, please add the name or document number in addition to the URL. Vendors just ''love'' to rearrange their websites (and some remove documentation on their old products altogether)! If we have the name/number (or even just the filename of the PDF) at least there's a chance to google for it again (either on the vendor's site or on some archive).<br />
<br />
== Coding Style ==<br />
<br />
* We use the [http://lxr.linux.no/source/Documentation/CodingStyle Linux kernel coding style] for coreboot.<br />
* You can use the 'indent' tool to fix the coding style like this:<br />
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]<br />
:Do not trust 'indent' blindly, though. It sometimes gets things wrong. Manual corrections may be required.<br />
<br />
= Documentation Guidelines =<br />
<br />
== General Guidelines and Tips ==<br />
<br />
* Documentation should be put into the wiki and/or in the code as Doxygen comments<br />
* Avoid using different styles and looks of documentation<br />
* Document ''what'', not ''how'' (No comments like ''// add one to i'')<br />
* Document assumptions, stipulations etc...<br />
* Document design and concepts!<br />
* Not lots of documentation but good documentation<br />
* Structured documentation<br />
* Focus: Whom are you addressing in your documentation? Write documentation for users, developers, vendors, ...<br />
<br />
== Automatic documentation ==<br />
<br />
* Doxygen-generated API- and code documentation is available at http://qa.coreboot.org/docs/. This documentation is updated on every 10th checkin.<br />
* To create a Doxygen comment, write<br />
/**<br />
* Sample comment.<br />
*/<br />
:or<br />
/** Sample comment. */<br />
* There are a few commands that describe what kind of comment you are adding:<br />
::@param &mdash; input parameters of a function<br />
::@return &mdash; return value of a function<br />
* A list of all commands is available at http://www.stack.nl/~dimitri/doxygen/commands.html<br />
<br />
Full example:<br />
<br />
/**<br />
* Calculate the length of a string.<br />
*<br />
* @param str The input string.<br />
* @return The length of the string, not including the final NUL character.<br />
*/<br />
static inline size_t strlen(const char *str)<br />
{<br />
/* ... */<br />
}<br />
<br />
= Testing =<br />
<br />
Every commit will be processed by the autobuild and autotest system available at http://qa.coreboot.org/. In addition please run autobuild yourself before submitting <br />
patches.<br />
<br />
== autobuild ==<br />
<br />
Autobuild can be found at [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/abuild/abuild coreboot/util/abuild]. <br />
<br />
Please run ''abuild'' '''before''' you commit. <br />
<br />
Autobuild is also running on every check-in to the repository and sending result mails to the coreboot [[Mailinglist|mailing list]]. The results of this build are also available at http://qa.coreboot.org/ in the ''build'' section of each revision.<br />
<br />
== autotest ==<br />
<br />
Each revision is also tested with an automated test system: http://qa.coreboot.org/overview.php?tested=1. If you developed coreboot for a certain mainboard or wish to help improving coreboot's quality by running the testsuite on one of your mainboards, please contact [mailto:info@coresystems.de info@coresystems.de].<br />
<br />
= How to contribute =<br />
<br />
== Creating Patches ==<br />
<br />
* '''Always use a checkout of the latest svn revision of the code'''. Patches that do not apply on the latest svn revision will be rejected!<br />
* Make sure all new and modified files contain the [[Development Guidelines#Common_License_Header|proper license headers]] (see below).<br />
* If your patch is supposed to add new files, please add them to your local repository before creating a diff. Use<br />
svn add path/to/file<br />
* Create your patches by executing the following command in the top-level coreboot directory:<br />
svn diff > ~/some_descriptive_name.patch<br />
* Open the patch in a text-editor and double-check that your changes are correct, and that the patch only contains what you think it contains.<br />
<br />
== Testing your Patch ==<br />
<br />
Patches can be tested against your clean local repository by using the '''patch''' command. Just copy your new patch file to the top-level directory of your clean local repository and issue this command:<br />
<br />
patch -p0 < filename.patch<br />
<br />
== Sign-off Procedure ==<br />
<br />
We employ a similar sign-off procedure for coreboot <br />
[http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html as the Linux developers] do.<br />
Please add a note such as<br />
Signed-off-by: Random J Developer <random@developer.example.org><br />
to your email/patch if you agree with the following Developer's Certificate of Origin 1.1.<br />
<br />
Patches without a Signed-off-by cannot be committed!<br />
<br />
<span style="color:red">You have to use your real name in the Signed-off-by line and in any copyright notices you add.</span> Patches without an associated real name cannot be committed!<br />
<br />
'''Developer's Certificate of Origin 1.1:'''<br />
<br />
By making a contribution to this project, I certify that:<br /><br />
(a) The contribution was created in whole or in part by me and I have<br />
the right to submit it under the open source license indicated in the file; or<br /><br />
(b) The contribution is based upon previous work that, to the best of my<br />
knowledge, is covered under an appropriate open source license and I have the<br />
right under that license to submit that work with modifications, whether created<br />
in whole or in part by me, under the same open source license (unless I am<br />
permitted to submit under a different license), as indicated in the file; or<br /><br />
(c) The contribution was provided directly to me by some other person who<br />
certified (a), (b) or (c) and I have not modified it; and<br /><br />
(d) In the case of each of (a), (b), or (c), I understand and agree that<br />
this project and the contribution are public and that a record of the contribution<br />
(including all personal information I submit with it, including my sign-off) is<br />
maintained indefinitely and may be redistributed consistent with this project or the<br />
open source license indicated in the file.<br />
<br />
<small>Note: The [http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html Developer's Certificate of Origin 1.1] is licensed under the terms of the [http://creativecommons.org/licenses/by-sa/2.5/ Creative Commons Attribution-ShareAlike 2.5 License].</small><br />
<br />
== Reviews ==<br />
<br />
* Send your patch to the [[Mailinglist|mailing list]] for review. Changes that impact a lot of code should also be documented in the [http://tracker.coreboot.org/trac/coreboot/ issue tracker].<br />
** Start the email with a detailed description of what the patch does and why. This text will usually end up in the commit logs so don't clutter it with useless stuff which should not go into the commit message.<br />
** Add a single line containing your "[[Development Guidelines#Sign-off_Procedure|sign-off]]" after the description of the patch.<br />
*** Example: ''Signed-off-by: John Doe <john@example.com>''<br />
** Add a single line which only contains "---". Everything which comes after that line will not be included in the commit message.<br />
* The developers on the mailing list will review and/or test your patch and send comments or suggestions. Please post updated patches to the mailing list again.<br />
* If the patch looks ok to one or more developers, they will reply to your mail with an Acked-by: line.<br />
** Example: ''Acked-by: John Doe <john@example.com>''<br />
* Every non-trivial patch must get at least one Acked-by: by another developer before it can be commited.<br />
** Exception: if you are fixing '''trivial''' things like a typo in a comment, you may specify your own name and email address in the Acked-by: field, and add the word "trivial" in the commit description (in '''addition''' to the commit description).<br />
<br />
== Repository Commits ==<br />
<br />
Commits to the coreboot subversion repository have to be done with a commit comment. This may be short, but descriptive:<br />
<br />
* If anyone involved in coreboot reads your comment in a year, she/he shall still be able to understand what your commit is about, without analyzing the code.<br />
* Double-check that you're really committing what you think you are, e.g. by typing the following in the top-level coreboot directory:<br />
svn diff | less<br />
* Include the following information in the svn commit message:<br />
** The description from the email containing the patch.<br />
** All Signed-off-by: and Acked-by: lines your patch received.<br />
** Reference or close bugs which are fixed by the commit, or are related to it. See [[Development Guidelines#How_to_close_Trac_issues_automatically_via_email|below]] for details.<br />
<br />
= Bug-Tracker =<br />
<br />
== Where is the coreboot bug tracker? ==<br />
<br />
It is available at http://tracker.coreboot.org/. Log in with your svn username and password if you have one.<br />
<br />
== Why do we use a bug tracker? ==<br />
<br />
We want a standardized interface for keeping track of open issues. The [[Mailinglist|mailing list]] is fine for discussion, but long standing issues, plans, goals, milestones can not be tracked there in a sufficient manner. There is no means of quality control via the mailing list. <br />
<br />
Therefore changes that impact a lot of code '''must''' be documented in the bug tracker. Also, please document bugs in the tracker.<br />
<br />
== How can I close Trac issues automatically via svn commits? ==<br />
<br />
It searches commit messages for text in the form of:<br />
* command #1<br />
* command #1, #2<br />
* command #1 & #2<br />
* command #1 and #2<br /><br />
<br />
You can have more then one command in a message. The following commands<br />
are supported. There is more then one spelling for each command, to make<br />
this as user-friendly as possible.<br /><br />
* closes, fixes<br />
The specified issue numbers are closed with the contents of this<br />
commit message being added to it.<br />
* references, refs, addresses, re <br />
The specified issue numbers are left in their current status, but<br />
the contents of this commit message are added to their notes.<br /><br />
A fairly complicated example of what you can do is with a commit message of:<br /><br />
Changed blah and foo to do this or that. Fixes #10 and #12, and refs #12.<br /><br />
This will close #10 and #12, and add a note to #12.<br />
<br />
= License Issues =<br />
<br />
* Contributed code must be GPL'd (preferrably 'GPLv2 or any later version', but 'GPLv2' is fine, too). At the very minimum the code must have a GPL-compatible license.<br />
<br />
== Common License Header ==<br />
<br />
Please quote the full GPL license header text in every file, as shown below. It should contain:<br />
<br />
* The '''year(s)''' when the code was written or modified and a '''copyright note''' of you (or your company, if you are contributing as part of your employment, and thus the copyright belongs to your company). Also, please provide an '''email address''' so that you can be contacted if questions arise.<br />
** Example:<br />
::''Copyright (C) 2006 John Doe <john@example.com>''<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
* An extra line which lists the '''author of the code, if the copyright holder is not the same as the author''' (e.g. if you work for a company and the company owns the copyright).<br />
** Example:<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
::''(Written by Janet Doe <janet@example.com> for Company, Inc.)''<br />
* The full '''GPL header''' as shown below.<br />
<br />
'''Complete example for *.c and *.h files:'''<br />
<br />
/*<br />
* This file is part of the coreboot project.<br />
*<br />
* Copyright (C) 2003-2005 John Doe <john@example.com><br />
* Copyright (C) 2005 Jane Doe <jane@example.com><br />
* Copyright (C) 2006 Company, Inc.<br />
* (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
* Copyright (C) 2007 Joe Doe <joe@example.com><br />
*<br />
* This program is free software; you can redistribute it and/or modify<br />
* it under the terms of the GNU General Public License as published by<br />
* the Free Software Foundation; either version 2 of the License, or<br />
* (at your option) any later version.<br />
*<br />
* This program is distributed in the hope that it will be useful,<br />
* but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
* GNU General Public License for more details.<br />
*<br />
* You should have received a copy of the GNU General Public License<br />
* along with this program; if not, write to the Free Software<br />
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
*/<br />
<br />
'''Complete example for Makefiles, config files, Python files, shell scripts etc.:'''<br />
<br />
##<br />
## This file is part of the coreboot project.<br />
##<br />
## Copyright (C) 2003-2005 John Doe <john@example.com><br />
## Copyright (C) 2005 Jane Doe <jane@example.com><br />
## Copyright (C) 2006 Company, Inc.<br />
## (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
## Copyright (C) 2007 Joe Doe <joe@example.com><br />
##<br />
## This program is free software; you can redistribute it and/or modify<br />
## it under the terms of the GNU General Public License as published by<br />
## the Free Software Foundation; either version 2 of the License, or<br />
## (at your option) any later version.<br />
##<br />
## This program is distributed in the hope that it will be useful,<br />
## but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
## GNU General Public License for more details.<br />
##<br />
## You should have received a copy of the GNU General Public License<br />
## along with this program; if not, write to the Free Software<br />
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
##</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9573
Board:gigabyte/ga-6bxc
2010-04-27T11:37:18Z
<p>AJenbo: </p>
<hr />
<div>== Status ==<br />
<br />
Nothing special is required to build core boot for this system.<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = WIP<br />
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it. <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = WIP<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:asus/p3b-f&diff=9572
Board:asus/p3b-f
2010-04-27T11:34:34Z
<p>AJenbo: </p>
<hr />
<div>This page describes how to use coreboot on the '''[ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/ P3B-F]''' mainboard. It is maintained by [[User:Uwe|Uwe Hermann]].<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
}}<br />
<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Datasheets&diff=9571
Datasheets
2010-04-26T12:38:34Z
<p>AJenbo: /* Intel 82801BA/BAM (ICH2) */</p>
<hr />
<div></div>
AJenbo
https://www.coreboot.org/index.php?title=Datasheets&diff=9570
Datasheets
2010-04-26T12:38:20Z
<p>AJenbo: /* Intel 82815E */</p>
<hr />
<div></div>
AJenbo
https://www.coreboot.org/index.php?title=Datasheets&diff=9569
Datasheets
2010-04-26T12:38:08Z
<p>AJenbo: /* Intel 440BX */</p>
<hr />
<div></div>
AJenbo
https://www.coreboot.org/index.php?title=Datasheets&diff=9568
Datasheets
2010-04-26T12:37:47Z
<p>AJenbo: </p>
<hr />
<div></div>
AJenbo
https://www.coreboot.org/index.php?title=Development_Guidelines&diff=9567
Development Guidelines
2010-04-26T08:13:31Z
<p>AJenbo: /* Required Toolchain */</p>
<hr />
<div>= Development Environment =<br />
<br />
== Required Toolchain ==<br />
<br />
* GNU development environment:<br />
** [http://gcc.gnu.org/ GCC] (tested: 4.1.2 prerelease)<br />
** G++<br />
** [http://www.kernel.org/pub/linux/devel/binutils/ binutils] (tested: 2.17.50.0.5)<br />
* libncurses<br />
* Python (tested: 2.4, 2.5)<br />
* bash (tested: 3.0, 3.1)<br />
* [http://www.acpica.org/downloads/ IASL], now part of the '''ACPICA''' download (package ''pmtools'' or ''iasl'' in many distributions)<br />
* [http://atrey.karlin.mff.cuni.cz/~mj/pciutils.shtml pciutils-devel/pciutils-dev]<br />
<br />
= Coding Guidelines =<br />
<br />
== General Guidelines ==<br />
<br />
* Encapsulate and isolate assembly language<br />
* Code shall not be "commented out"<br />
* No use of floating-point arithmetics<br />
* No hiding of identifiers defined in outer scopes<br />
* Typedefs are unique (device_t?)<br />
* Functions shall have prototype declarations<br />
* Local functions should be declared static<br />
* No definitions in header files<br />
* All variables are assigned before use<br />
* All objects should have fully qualified types (''unsigned int'' instead of ''unsigned'')<br />
* We suggest trying to import more such rules, such as additional ones described in [http://www.misra.org.uk/index.htm MISRA-C 2004] (''Guidelines for the use of C in critical systems'')<br />
<br />
== Comments ==<br />
<br />
=== References ===<br />
<br />
If you are referencing a data sheet or other documentation in the code, please add the name or document number in addition to the URL. Vendors just ''love'' to rearrange their websites (and some remove documentation on their old products altogether)! If we have the name/number (or even just the filename of the PDF) at least there's a chance to google for it again (either on the vendor's site or on some archive).<br />
<br />
== Coding Style ==<br />
<br />
* We use the [http://lxr.linux.no/source/Documentation/CodingStyle Linux kernel coding style] for coreboot.<br />
* You can use the 'indent' tool to fix the coding style like this:<br />
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]<br />
:Do not trust 'indent' blindly, though. It sometimes gets things wrong. Manual corrections may be required.<br />
<br />
= Documentation Guidelines =<br />
<br />
== General Guidelines and Tips ==<br />
<br />
* Documentation should be put into the wiki and/or in the code as Doxygen comments<br />
* Avoid using different styles and looks of documentation<br />
* Document ''what'', not ''how'' (No comments like ''// add one to i'')<br />
* Document assumptions, stipulations etc...<br />
* Document design and concepts!<br />
* Not lots of documentation but good documentation<br />
* Structured documentation<br />
* Focus: Whom are you addressing in your documentation? Write documentation for users, developers, vendors, ...<br />
<br />
== Automatic documentation ==<br />
<br />
* Doxygen-generated API- and code documentation is available at http://qa.coreboot.org/docs/. This documentation is updated on every 10th checkin.<br />
* To create a Doxygen comment, write<br />
/**<br />
* Sample comment.<br />
*/<br />
:or<br />
/** Sample comment. */<br />
* There are a few commands that describe what kind of comment you are adding:<br />
::@param &mdash; input parameters of a function<br />
::@return &mdash; return value of a function<br />
* A list of all commands is available at http://www.stack.nl/~dimitri/doxygen/commands.html<br />
<br />
Full example:<br />
<br />
/**<br />
* Calculate the length of a string.<br />
*<br />
* @param str The input string.<br />
* @return The length of the string, not including the final NUL character.<br />
*/<br />
static inline size_t strlen(const char *str)<br />
{<br />
/* ... */<br />
}<br />
<br />
= Testing =<br />
<br />
Every commit will be processed by the autobuild and autotest system available at http://qa.coreboot.org/. In addition please run autobuild yourself before submitting <br />
patches.<br />
<br />
== autobuild ==<br />
<br />
Autobuild can be found at [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/abuild/abuild coreboot/util/abuild]. <br />
<br />
Please run ''abuild'' '''before''' you commit. <br />
<br />
Autobuild is also running on every check-in to the repository and sending result mails to the coreboot [[Mailinglist|mailing list]]. The results of this build are also available at http://qa.coreboot.org/ in the ''build'' section of each revision.<br />
<br />
== autotest ==<br />
<br />
Each revision is also tested with an automated test system: http://qa.coreboot.org/overview.php?tested=1. If you developed coreboot for a certain mainboard or wish to help improving coreboot's quality by running the testsuite on one of your mainboards, please contact [mailto:info@coresystems.de info@coresystems.de].<br />
<br />
= How to contribute =<br />
<br />
== Creating Patches ==<br />
<br />
* '''Always use a checkout of the latest svn revision of the code'''. Patches that do not apply on the latest svn revision will be rejected!<br />
* Make sure all new and modified files contain the [[Development Guidelines#Common_License_Header|proper license headers]] (see below).<br />
* If your patch is supposed to add new files, please add them to your local repository before creating a diff. Use<br />
svn add path/to/file<br />
* Create your patches by executing the following command in the top-level coreboot directory:<br />
svn diff > ~/some_descriptive_name.patch<br />
* Open the patch in a text-editor and double-check that your changes are correct, and that the patch only contains what you think it contains.<br />
<br />
== Testing your Patch ==<br />
<br />
Patches can be tested against your clean local repository by using the '''patch''' command. Just copy your new patch file to the top-level directory of your clean local repository and issue this command:<br />
<br />
patch -p0 < filename.patch<br />
<br />
== Sign-off Procedure ==<br />
<br />
We employ a similar sign-off procedure for coreboot <br />
[http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html as the Linux developers] do.<br />
Please add a note such as<br />
Signed-off-by: Random J Developer <random@developer.example.org><br />
to your email/patch if you agree with the following Developer's Certificate of Origin 1.1.<br />
<br />
Patches without a Signed-off-by cannot be committed!<br />
<br />
<span style="color:red">You have to use your real name in the Signed-off-by line and in any copyright notices you add.</span> Patches without an associated real name cannot be committed!<br />
<br />
'''Developer's Certificate of Origin 1.1:'''<br />
<br />
By making a contribution to this project, I certify that:<br /><br />
(a) The contribution was created in whole or in part by me and I have<br />
the right to submit it under the open source license indicated in the file; or<br /><br />
(b) The contribution is based upon previous work that, to the best of my<br />
knowledge, is covered under an appropriate open source license and I have the<br />
right under that license to submit that work with modifications, whether created<br />
in whole or in part by me, under the same open source license (unless I am<br />
permitted to submit under a different license), as indicated in the file; or<br /><br />
(c) The contribution was provided directly to me by some other person who<br />
certified (a), (b) or (c) and I have not modified it; and<br /><br />
(d) In the case of each of (a), (b), or (c), I understand and agree that<br />
this project and the contribution are public and that a record of the contribution<br />
(including all personal information I submit with it, including my sign-off) is<br />
maintained indefinitely and may be redistributed consistent with this project or the<br />
open source license indicated in the file.<br />
<br />
<small>Note: The [http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html Developer's Certificate of Origin 1.1] is licensed under the terms of the [http://creativecommons.org/licenses/by-sa/2.5/ Creative Commons Attribution-ShareAlike 2.5 License].</small><br />
<br />
== Reviews ==<br />
<br />
* Send your patch to the [[Mailinglist|mailing list]] for review. Changes that impact a lot of code should also be documented in the [http://tracker.coreboot.org/trac/coreboot/ issue tracker].<br />
** Start the email with a detailed description of what the patch does and why. This text will usually end up in the commit logs so don't clutter it with useless stuff which should not go into the commit message.<br />
** Add a single line containing your "[[Development Guidelines#Sign-off_Procedure|sign-off]]" after the description of the patch.<br />
*** Example: ''Signed-off-by: John Doe <john@example.com>''<br />
** Add a single line which only contains "---". Everything which comes after that line will not be included in the commit message.<br />
* The developers on the mailing list will review and/or test your patch and send comments or suggestions. Please post updated patches to the mailing list again.<br />
* If the patch looks ok to one or more developers, they will reply to your mail with an Acked-by: line.<br />
** Example: ''Acked-by: John Doe <john@example.com>''<br />
* Every non-trivial patch must get at least one Acked-by: by another developer before it can be commited.<br />
** Exception: if you are fixing '''trivial''' things like a typo in a comment, you may specify your own name and email address in the Acked-by: field, and add the word "trivial" in the commit description (in '''addition''' to the commit description).<br />
<br />
== Repository Commits ==<br />
<br />
Commits to the coreboot subversion repository have to be done with a commit comment. This may be short, but descriptive:<br />
<br />
* If anyone involved in coreboot reads your comment in a year, she/he shall still be able to understand what your commit is about, without analyzing the code.<br />
* Double-check that you're really committing what you think you are, e.g. by typing the following in the top-level coreboot directory:<br />
svn diff | less<br />
* Include the following information in the svn commit message:<br />
** The description from the email containing the patch.<br />
** All Signed-off-by: and Acked-by: lines your patch received.<br />
** Reference or close bugs which are fixed by the commit, or are related to it. See [[Development Guidelines#How_to_close_Trac_issues_automatically_via_email|below]] for details.<br />
<br />
= Bug-Tracker =<br />
<br />
== Where is the coreboot bug tracker? ==<br />
<br />
It is available at http://tracker.coreboot.org/. Log in with your svn username and password if you have one.<br />
<br />
== Why do we use a bug tracker? ==<br />
<br />
We want a standardized interface for keeping track of open issues. The [[Mailinglist|mailing list]] is fine for discussion, but long standing issues, plans, goals, milestones can not be tracked there in a sufficient manner. There is no means of quality control via the mailing list. <br />
<br />
Therefore changes that impact a lot of code '''must''' be documented in the bug tracker. Also, please document bugs in the tracker.<br />
<br />
== How can I close Trac issues automatically via svn commits? ==<br />
<br />
It searches commit messages for text in the form of:<br />
* command #1<br />
* command #1, #2<br />
* command #1 & #2<br />
* command #1 and #2<br /><br />
<br />
You can have more then one command in a message. The following commands<br />
are supported. There is more then one spelling for each command, to make<br />
this as user-friendly as possible.<br /><br />
* closes, fixes<br />
The specified issue numbers are closed with the contents of this<br />
commit message being added to it.<br />
* references, refs, addresses, re <br />
The specified issue numbers are left in their current status, but<br />
the contents of this commit message are added to their notes.<br /><br />
A fairly complicated example of what you can do is with a commit message of:<br /><br />
Changed blah and foo to do this or that. Fixes #10 and #12, and refs #12.<br /><br />
This will close #10 and #12, and add a note to #12.<br />
<br />
= License Issues =<br />
<br />
* Contributed code must be GPL'd (preferrably 'GPLv2 or any later version', but 'GPLv2' is fine, too). At the very minimum the code must have a GPL-compatible license.<br />
<br />
== Common License Header ==<br />
<br />
Please quote the full GPL license header text in every file, as shown below. It should contain:<br />
<br />
* The '''year(s)''' when the code was written or modified and a '''copyright note''' of you (or your company, if you are contributing as part of your employment, and thus the copyright belongs to your company). Also, please provide an '''email address''' so that you can be contacted if questions arise.<br />
** Example:<br />
::''Copyright (C) 2006 John Doe <john@example.com>''<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
* An extra line which lists the '''author of the code, if the copyright holder is not the same as the author''' (e.g. if you work for a company and the company owns the copyright).<br />
** Example:<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
::''(Written by Janet Doe <janet@example.com> for Company, Inc.)''<br />
* The full '''GPL header''' as shown below.<br />
<br />
'''Complete example for *.c and *.h files:'''<br />
<br />
/*<br />
* This file is part of the coreboot project.<br />
*<br />
* Copyright (C) 2003-2005 John Doe <john@example.com><br />
* Copyright (C) 2005 Jane Doe <jane@example.com><br />
* Copyright (C) 2006 Company, Inc.<br />
* (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
* Copyright (C) 2007 Joe Doe <joe@example.com><br />
*<br />
* This program is free software; you can redistribute it and/or modify<br />
* it under the terms of the GNU General Public License as published by<br />
* the Free Software Foundation; either version 2 of the License, or<br />
* (at your option) any later version.<br />
*<br />
* This program is distributed in the hope that it will be useful,<br />
* but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
* GNU General Public License for more details.<br />
*<br />
* You should have received a copy of the GNU General Public License<br />
* along with this program; if not, write to the Free Software<br />
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
*/<br />
<br />
'''Complete example for Makefiles, config files, Python files, shell scripts etc.:'''<br />
<br />
##<br />
## This file is part of the coreboot project.<br />
##<br />
## Copyright (C) 2003-2005 John Doe <john@example.com><br />
## Copyright (C) 2005 Jane Doe <jane@example.com><br />
## Copyright (C) 2006 Company, Inc.<br />
## (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
## Copyright (C) 2007 Joe Doe <joe@example.com><br />
##<br />
## This program is free software; you can redistribute it and/or modify<br />
## it under the terms of the GNU General Public License as published by<br />
## the Free Software Foundation; either version 2 of the License, or<br />
## (at your option) any later version.<br />
##<br />
## This program is distributed in the hope that it will be useful,<br />
## but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
## GNU General Public License for more details.<br />
##<br />
## You should have received a copy of the GNU General Public License<br />
## along with this program; if not, write to the Free Software<br />
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
##</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9566
Board:gigabyte/ga-6bxc
2010-04-26T00:14:53Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
Nothing special is required to build core boot for this system.<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = WIP<br />
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it. <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = WIP<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = I have it fully working but need to submit the patch.<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Development_Guidelines&diff=9565
Development Guidelines
2010-04-25T17:14:55Z
<p>AJenbo: /* Required Toolchain */</p>
<hr />
<div>= Development Environment =<br />
<br />
== Required Toolchain ==<br />
<br />
* GNU development environment:<br />
** [http://gcc.gnu.org/ GCC] (tested: 4.1.2 prerelease)<br />
** [http://www.kernel.org/pub/linux/devel/binutils/ binutils] (tested: 2.17.50.0.5)<br />
* libncurses<br />
* Python (tested: 2.4, 2.5)<br />
* bash (tested: 3.0, 3.1)<br />
* [http://www.acpica.org/downloads/ IASL], now part of the '''ACPICA''' download (package ''pmtools'' or ''iasl'' in many distributions)<br />
* [http://atrey.karlin.mff.cuni.cz/~mj/pciutils.shtml pciutils-devel/pciutils-dev]<br />
<br />
= Coding Guidelines =<br />
<br />
== General Guidelines ==<br />
<br />
* Encapsulate and isolate assembly language<br />
* Code shall not be "commented out"<br />
* No use of floating-point arithmetics<br />
* No hiding of identifiers defined in outer scopes<br />
* Typedefs are unique (device_t?)<br />
* Functions shall have prototype declarations<br />
* Local functions should be declared static<br />
* No definitions in header files<br />
* All variables are assigned before use<br />
* All objects should have fully qualified types (''unsigned int'' instead of ''unsigned'')<br />
* We suggest trying to import more such rules, such as additional ones described in [http://www.misra.org.uk/index.htm MISRA-C 2004] (''Guidelines for the use of C in critical systems'')<br />
<br />
== Comments ==<br />
<br />
=== References ===<br />
<br />
If you are referencing a data sheet or other documentation in the code, please add the name or document number in addition to the URL. Vendors just ''love'' to rearrange their websites (and some remove documentation on their old products altogether)! If we have the name/number (or even just the filename of the PDF) at least there's a chance to google for it again (either on the vendor's site or on some archive).<br />
<br />
== Coding Style ==<br />
<br />
* We use the [http://lxr.linux.no/source/Documentation/CodingStyle Linux kernel coding style] for coreboot.<br />
* You can use the 'indent' tool to fix the coding style like this:<br />
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]<br />
:Do not trust 'indent' blindly, though. It sometimes gets things wrong. Manual corrections may be required.<br />
<br />
= Documentation Guidelines =<br />
<br />
== General Guidelines and Tips ==<br />
<br />
* Documentation should be put into the wiki and/or in the code as Doxygen comments<br />
* Avoid using different styles and looks of documentation<br />
* Document ''what'', not ''how'' (No comments like ''// add one to i'')<br />
* Document assumptions, stipulations etc...<br />
* Document design and concepts!<br />
* Not lots of documentation but good documentation<br />
* Structured documentation<br />
* Focus: Whom are you addressing in your documentation? Write documentation for users, developers, vendors, ...<br />
<br />
== Automatic documentation ==<br />
<br />
* Doxygen-generated API- and code documentation is available at http://qa.coreboot.org/docs/. This documentation is updated on every 10th checkin.<br />
* To create a Doxygen comment, write<br />
/**<br />
* Sample comment.<br />
*/<br />
:or<br />
/** Sample comment. */<br />
* There are a few commands that describe what kind of comment you are adding:<br />
::@param &mdash; input parameters of a function<br />
::@return &mdash; return value of a function<br />
* A list of all commands is available at http://www.stack.nl/~dimitri/doxygen/commands.html<br />
<br />
Full example:<br />
<br />
/**<br />
* Calculate the length of a string.<br />
*<br />
* @param str The input string.<br />
* @return The length of the string, not including the final NUL character.<br />
*/<br />
static inline size_t strlen(const char *str)<br />
{<br />
/* ... */<br />
}<br />
<br />
= Testing =<br />
<br />
Every commit will be processed by the autobuild and autotest system available at http://qa.coreboot.org/. In addition please run autobuild yourself before submitting <br />
patches.<br />
<br />
== autobuild ==<br />
<br />
Autobuild can be found at [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/abuild/abuild coreboot/util/abuild]. <br />
<br />
Please run ''abuild'' '''before''' you commit. <br />
<br />
Autobuild is also running on every check-in to the repository and sending result mails to the coreboot [[Mailinglist|mailing list]]. The results of this build are also available at http://qa.coreboot.org/ in the ''build'' section of each revision.<br />
<br />
== autotest ==<br />
<br />
Each revision is also tested with an automated test system: http://qa.coreboot.org/overview.php?tested=1. If you developed coreboot for a certain mainboard or wish to help improving coreboot's quality by running the testsuite on one of your mainboards, please contact [mailto:info@coresystems.de info@coresystems.de].<br />
<br />
= How to contribute =<br />
<br />
== Creating Patches ==<br />
<br />
* '''Always use a checkout of the latest svn revision of the code'''. Patches that do not apply on the latest svn revision will be rejected!<br />
* Make sure all new and modified files contain the [[Development Guidelines#Common_License_Header|proper license headers]] (see below).<br />
* If your patch is supposed to add new files, please add them to your local repository before creating a diff. Use<br />
svn add path/to/file<br />
* Create your patches by executing the following command in the top-level coreboot directory:<br />
svn diff > ~/some_descriptive_name.patch<br />
* Open the patch in a text-editor and double-check that your changes are correct, and that the patch only contains what you think it contains.<br />
<br />
== Testing your Patch ==<br />
<br />
Patches can be tested against your clean local repository by using the '''patch''' command. Just copy your new patch file to the top-level directory of your clean local repository and issue this command:<br />
<br />
patch -p0 < filename.patch<br />
<br />
== Sign-off Procedure ==<br />
<br />
We employ a similar sign-off procedure for coreboot <br />
[http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html as the Linux developers] do.<br />
Please add a note such as<br />
Signed-off-by: Random J Developer <random@developer.example.org><br />
to your email/patch if you agree with the following Developer's Certificate of Origin 1.1.<br />
<br />
Patches without a Signed-off-by cannot be committed!<br />
<br />
<span style="color:red">You have to use your real name in the Signed-off-by line and in any copyright notices you add.</span> Patches without an associated real name cannot be committed!<br />
<br />
'''Developer's Certificate of Origin 1.1:'''<br />
<br />
By making a contribution to this project, I certify that:<br /><br />
(a) The contribution was created in whole or in part by me and I have<br />
the right to submit it under the open source license indicated in the file; or<br /><br />
(b) The contribution is based upon previous work that, to the best of my<br />
knowledge, is covered under an appropriate open source license and I have the<br />
right under that license to submit that work with modifications, whether created<br />
in whole or in part by me, under the same open source license (unless I am<br />
permitted to submit under a different license), as indicated in the file; or<br /><br />
(c) The contribution was provided directly to me by some other person who<br />
certified (a), (b) or (c) and I have not modified it; and<br /><br />
(d) In the case of each of (a), (b), or (c), I understand and agree that<br />
this project and the contribution are public and that a record of the contribution<br />
(including all personal information I submit with it, including my sign-off) is<br />
maintained indefinitely and may be redistributed consistent with this project or the<br />
open source license indicated in the file.<br />
<br />
<small>Note: The [http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html Developer's Certificate of Origin 1.1] is licensed under the terms of the [http://creativecommons.org/licenses/by-sa/2.5/ Creative Commons Attribution-ShareAlike 2.5 License].</small><br />
<br />
== Reviews ==<br />
<br />
* Send your patch to the [[Mailinglist|mailing list]] for review. Changes that impact a lot of code should also be documented in the [http://tracker.coreboot.org/trac/coreboot/ issue tracker].<br />
** Start the email with a detailed description of what the patch does and why. This text will usually end up in the commit logs so don't clutter it with useless stuff which should not go into the commit message.<br />
** Add a single line containing your "[[Development Guidelines#Sign-off_Procedure|sign-off]]" after the description of the patch.<br />
*** Example: ''Signed-off-by: John Doe <john@example.com>''<br />
** Add a single line which only contains "---". Everything which comes after that line will not be included in the commit message.<br />
* The developers on the mailing list will review and/or test your patch and send comments or suggestions. Please post updated patches to the mailing list again.<br />
* If the patch looks ok to one or more developers, they will reply to your mail with an Acked-by: line.<br />
** Example: ''Acked-by: John Doe <john@example.com>''<br />
* Every non-trivial patch must get at least one Acked-by: by another developer before it can be commited.<br />
** Exception: if you are fixing '''trivial''' things like a typo in a comment, you may specify your own name and email address in the Acked-by: field, and add the word "trivial" in the commit description (in '''addition''' to the commit description).<br />
<br />
== Repository Commits ==<br />
<br />
Commits to the coreboot subversion repository have to be done with a commit comment. This may be short, but descriptive:<br />
<br />
* If anyone involved in coreboot reads your comment in a year, she/he shall still be able to understand what your commit is about, without analyzing the code.<br />
* Double-check that you're really committing what you think you are, e.g. by typing the following in the top-level coreboot directory:<br />
svn diff | less<br />
* Include the following information in the svn commit message:<br />
** The description from the email containing the patch.<br />
** All Signed-off-by: and Acked-by: lines your patch received.<br />
** Reference or close bugs which are fixed by the commit, or are related to it. See [[Development Guidelines#How_to_close_Trac_issues_automatically_via_email|below]] for details.<br />
<br />
= Bug-Tracker =<br />
<br />
== Where is the coreboot bug tracker? ==<br />
<br />
It is available at http://tracker.coreboot.org/. Log in with your svn username and password if you have one.<br />
<br />
== Why do we use a bug tracker? ==<br />
<br />
We want a standardized interface for keeping track of open issues. The [[Mailinglist|mailing list]] is fine for discussion, but long standing issues, plans, goals, milestones can not be tracked there in a sufficient manner. There is no means of quality control via the mailing list. <br />
<br />
Therefore changes that impact a lot of code '''must''' be documented in the bug tracker. Also, please document bugs in the tracker.<br />
<br />
== How can I close Trac issues automatically via svn commits? ==<br />
<br />
It searches commit messages for text in the form of:<br />
* command #1<br />
* command #1, #2<br />
* command #1 & #2<br />
* command #1 and #2<br /><br />
<br />
You can have more then one command in a message. The following commands<br />
are supported. There is more then one spelling for each command, to make<br />
this as user-friendly as possible.<br /><br />
* closes, fixes<br />
The specified issue numbers are closed with the contents of this<br />
commit message being added to it.<br />
* references, refs, addresses, re <br />
The specified issue numbers are left in their current status, but<br />
the contents of this commit message are added to their notes.<br /><br />
A fairly complicated example of what you can do is with a commit message of:<br /><br />
Changed blah and foo to do this or that. Fixes #10 and #12, and refs #12.<br /><br />
This will close #10 and #12, and add a note to #12.<br />
<br />
= License Issues =<br />
<br />
* Contributed code must be GPL'd (preferrably 'GPLv2 or any later version', but 'GPLv2' is fine, too). At the very minimum the code must have a GPL-compatible license.<br />
<br />
== Common License Header ==<br />
<br />
Please quote the full GPL license header text in every file, as shown below. It should contain:<br />
<br />
* The '''year(s)''' when the code was written or modified and a '''copyright note''' of you (or your company, if you are contributing as part of your employment, and thus the copyright belongs to your company). Also, please provide an '''email address''' so that you can be contacted if questions arise.<br />
** Example:<br />
::''Copyright (C) 2006 John Doe <john@example.com>''<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
* An extra line which lists the '''author of the code, if the copyright holder is not the same as the author''' (e.g. if you work for a company and the company owns the copyright).<br />
** Example:<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
::''(Written by Janet Doe <janet@example.com> for Company, Inc.)''<br />
* The full '''GPL header''' as shown below.<br />
<br />
'''Complete example for *.c and *.h files:'''<br />
<br />
/*<br />
* This file is part of the coreboot project.<br />
*<br />
* Copyright (C) 2003-2005 John Doe <john@example.com><br />
* Copyright (C) 2005 Jane Doe <jane@example.com><br />
* Copyright (C) 2006 Company, Inc.<br />
* (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
* Copyright (C) 2007 Joe Doe <joe@example.com><br />
*<br />
* This program is free software; you can redistribute it and/or modify<br />
* it under the terms of the GNU General Public License as published by<br />
* the Free Software Foundation; either version 2 of the License, or<br />
* (at your option) any later version.<br />
*<br />
* This program is distributed in the hope that it will be useful,<br />
* but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
* GNU General Public License for more details.<br />
*<br />
* You should have received a copy of the GNU General Public License<br />
* along with this program; if not, write to the Free Software<br />
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
*/<br />
<br />
'''Complete example for Makefiles, config files, Python files, shell scripts etc.:'''<br />
<br />
##<br />
## This file is part of the coreboot project.<br />
##<br />
## Copyright (C) 2003-2005 John Doe <john@example.com><br />
## Copyright (C) 2005 Jane Doe <jane@example.com><br />
## Copyright (C) 2006 Company, Inc.<br />
## (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
## Copyright (C) 2007 Joe Doe <joe@example.com><br />
##<br />
## This program is free software; you can redistribute it and/or modify<br />
## it under the terms of the GNU General Public License as published by<br />
## the Free Software Foundation; either version 2 of the License, or<br />
## (at your option) any later version.<br />
##<br />
## This program is distributed in the hope that it will be useful,<br />
## but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
## GNU General Public License for more details.<br />
##<br />
## You should have received a copy of the GNU General Public License<br />
## along with this program; if not, write to the Free Software<br />
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
##</div>
AJenbo
https://www.coreboot.org/index.php?title=Development_Guidelines&diff=9564
Development Guidelines
2010-04-25T17:13:58Z
<p>AJenbo: </p>
<hr />
<div>= Development Environment =<br />
<br />
== Required Toolchain ==<br />
<br />
* GNU development environment:<br />
** [http://gcc.gnu.org/ GCC] (tested: 4.1.2 prerelease)<br />
** [http://www.kernel.org/pub/linux/devel/binutils/ binutils] (tested: 2.17.50.0.5)<br />
** libncurses * Python (tested: 2.4, 2.5)<br />
* bash (tested: 3.0, 3.1)<br />
* [http://www.acpica.org/downloads/ IASL], now part of the '''ACPICA''' download (package ''pmtools'' or ''iasl'' in many distributions)<br />
* [http://atrey.karlin.mff.cuni.cz/~mj/pciutils.shtml pciutils-devel/pciutils-dev]<br />
<br />
= Coding Guidelines =<br />
<br />
== General Guidelines ==<br />
<br />
* Encapsulate and isolate assembly language<br />
* Code shall not be "commented out"<br />
* No use of floating-point arithmetics<br />
* No hiding of identifiers defined in outer scopes<br />
* Typedefs are unique (device_t?)<br />
* Functions shall have prototype declarations<br />
* Local functions should be declared static<br />
* No definitions in header files<br />
* All variables are assigned before use<br />
* All objects should have fully qualified types (''unsigned int'' instead of ''unsigned'')<br />
* We suggest trying to import more such rules, such as additional ones described in [http://www.misra.org.uk/index.htm MISRA-C 2004] (''Guidelines for the use of C in critical systems'')<br />
<br />
== Comments ==<br />
<br />
=== References ===<br />
<br />
If you are referencing a data sheet or other documentation in the code, please add the name or document number in addition to the URL. Vendors just ''love'' to rearrange their websites (and some remove documentation on their old products altogether)! If we have the name/number (or even just the filename of the PDF) at least there's a chance to google for it again (either on the vendor's site or on some archive).<br />
<br />
== Coding Style ==<br />
<br />
* We use the [http://lxr.linux.no/source/Documentation/CodingStyle Linux kernel coding style] for coreboot.<br />
* You can use the 'indent' tool to fix the coding style like this:<br />
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]<br />
:Do not trust 'indent' blindly, though. It sometimes gets things wrong. Manual corrections may be required.<br />
<br />
= Documentation Guidelines =<br />
<br />
== General Guidelines and Tips ==<br />
<br />
* Documentation should be put into the wiki and/or in the code as Doxygen comments<br />
* Avoid using different styles and looks of documentation<br />
* Document ''what'', not ''how'' (No comments like ''// add one to i'')<br />
* Document assumptions, stipulations etc...<br />
* Document design and concepts!<br />
* Not lots of documentation but good documentation<br />
* Structured documentation<br />
* Focus: Whom are you addressing in your documentation? Write documentation for users, developers, vendors, ...<br />
<br />
== Automatic documentation ==<br />
<br />
* Doxygen-generated API- and code documentation is available at http://qa.coreboot.org/docs/. This documentation is updated on every 10th checkin.<br />
* To create a Doxygen comment, write<br />
/**<br />
* Sample comment.<br />
*/<br />
:or<br />
/** Sample comment. */<br />
* There are a few commands that describe what kind of comment you are adding:<br />
::@param &mdash; input parameters of a function<br />
::@return &mdash; return value of a function<br />
* A list of all commands is available at http://www.stack.nl/~dimitri/doxygen/commands.html<br />
<br />
Full example:<br />
<br />
/**<br />
* Calculate the length of a string.<br />
*<br />
* @param str The input string.<br />
* @return The length of the string, not including the final NUL character.<br />
*/<br />
static inline size_t strlen(const char *str)<br />
{<br />
/* ... */<br />
}<br />
<br />
= Testing =<br />
<br />
Every commit will be processed by the autobuild and autotest system available at http://qa.coreboot.org/. In addition please run autobuild yourself before submitting <br />
patches.<br />
<br />
== autobuild ==<br />
<br />
Autobuild can be found at [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/abuild/abuild coreboot/util/abuild]. <br />
<br />
Please run ''abuild'' '''before''' you commit. <br />
<br />
Autobuild is also running on every check-in to the repository and sending result mails to the coreboot [[Mailinglist|mailing list]]. The results of this build are also available at http://qa.coreboot.org/ in the ''build'' section of each revision.<br />
<br />
== autotest ==<br />
<br />
Each revision is also tested with an automated test system: http://qa.coreboot.org/overview.php?tested=1. If you developed coreboot for a certain mainboard or wish to help improving coreboot's quality by running the testsuite on one of your mainboards, please contact [mailto:info@coresystems.de info@coresystems.de].<br />
<br />
= How to contribute =<br />
<br />
== Creating Patches ==<br />
<br />
* '''Always use a checkout of the latest svn revision of the code'''. Patches that do not apply on the latest svn revision will be rejected!<br />
* Make sure all new and modified files contain the [[Development Guidelines#Common_License_Header|proper license headers]] (see below).<br />
* If your patch is supposed to add new files, please add them to your local repository before creating a diff. Use<br />
svn add path/to/file<br />
* Create your patches by executing the following command in the top-level coreboot directory:<br />
svn diff > ~/some_descriptive_name.patch<br />
* Open the patch in a text-editor and double-check that your changes are correct, and that the patch only contains what you think it contains.<br />
<br />
== Testing your Patch ==<br />
<br />
Patches can be tested against your clean local repository by using the '''patch''' command. Just copy your new patch file to the top-level directory of your clean local repository and issue this command:<br />
<br />
patch -p0 < filename.patch<br />
<br />
== Sign-off Procedure ==<br />
<br />
We employ a similar sign-off procedure for coreboot <br />
[http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html as the Linux developers] do.<br />
Please add a note such as<br />
Signed-off-by: Random J Developer <random@developer.example.org><br />
to your email/patch if you agree with the following Developer's Certificate of Origin 1.1.<br />
<br />
Patches without a Signed-off-by cannot be committed!<br />
<br />
<span style="color:red">You have to use your real name in the Signed-off-by line and in any copyright notices you add.</span> Patches without an associated real name cannot be committed!<br />
<br />
'''Developer's Certificate of Origin 1.1:'''<br />
<br />
By making a contribution to this project, I certify that:<br /><br />
(a) The contribution was created in whole or in part by me and I have<br />
the right to submit it under the open source license indicated in the file; or<br /><br />
(b) The contribution is based upon previous work that, to the best of my<br />
knowledge, is covered under an appropriate open source license and I have the<br />
right under that license to submit that work with modifications, whether created<br />
in whole or in part by me, under the same open source license (unless I am<br />
permitted to submit under a different license), as indicated in the file; or<br /><br />
(c) The contribution was provided directly to me by some other person who<br />
certified (a), (b) or (c) and I have not modified it; and<br /><br />
(d) In the case of each of (a), (b), or (c), I understand and agree that<br />
this project and the contribution are public and that a record of the contribution<br />
(including all personal information I submit with it, including my sign-off) is<br />
maintained indefinitely and may be redistributed consistent with this project or the<br />
open source license indicated in the file.<br />
<br />
<small>Note: The [http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html Developer's Certificate of Origin 1.1] is licensed under the terms of the [http://creativecommons.org/licenses/by-sa/2.5/ Creative Commons Attribution-ShareAlike 2.5 License].</small><br />
<br />
== Reviews ==<br />
<br />
* Send your patch to the [[Mailinglist|mailing list]] for review. Changes that impact a lot of code should also be documented in the [http://tracker.coreboot.org/trac/coreboot/ issue tracker].<br />
** Start the email with a detailed description of what the patch does and why. This text will usually end up in the commit logs so don't clutter it with useless stuff which should not go into the commit message.<br />
** Add a single line containing your "[[Development Guidelines#Sign-off_Procedure|sign-off]]" after the description of the patch.<br />
*** Example: ''Signed-off-by: John Doe <john@example.com>''<br />
** Add a single line which only contains "---". Everything which comes after that line will not be included in the commit message.<br />
* The developers on the mailing list will review and/or test your patch and send comments or suggestions. Please post updated patches to the mailing list again.<br />
* If the patch looks ok to one or more developers, they will reply to your mail with an Acked-by: line.<br />
** Example: ''Acked-by: John Doe <john@example.com>''<br />
* Every non-trivial patch must get at least one Acked-by: by another developer before it can be commited.<br />
** Exception: if you are fixing '''trivial''' things like a typo in a comment, you may specify your own name and email address in the Acked-by: field, and add the word "trivial" in the commit description (in '''addition''' to the commit description).<br />
<br />
== Repository Commits ==<br />
<br />
Commits to the coreboot subversion repository have to be done with a commit comment. This may be short, but descriptive:<br />
<br />
* If anyone involved in coreboot reads your comment in a year, she/he shall still be able to understand what your commit is about, without analyzing the code.<br />
* Double-check that you're really committing what you think you are, e.g. by typing the following in the top-level coreboot directory:<br />
svn diff | less<br />
* Include the following information in the svn commit message:<br />
** The description from the email containing the patch.<br />
** All Signed-off-by: and Acked-by: lines your patch received.<br />
** Reference or close bugs which are fixed by the commit, or are related to it. See [[Development Guidelines#How_to_close_Trac_issues_automatically_via_email|below]] for details.<br />
<br />
= Bug-Tracker =<br />
<br />
== Where is the coreboot bug tracker? ==<br />
<br />
It is available at http://tracker.coreboot.org/. Log in with your svn username and password if you have one.<br />
<br />
== Why do we use a bug tracker? ==<br />
<br />
We want a standardized interface for keeping track of open issues. The [[Mailinglist|mailing list]] is fine for discussion, but long standing issues, plans, goals, milestones can not be tracked there in a sufficient manner. There is no means of quality control via the mailing list. <br />
<br />
Therefore changes that impact a lot of code '''must''' be documented in the bug tracker. Also, please document bugs in the tracker.<br />
<br />
== How can I close Trac issues automatically via svn commits? ==<br />
<br />
It searches commit messages for text in the form of:<br />
* command #1<br />
* command #1, #2<br />
* command #1 & #2<br />
* command #1 and #2<br /><br />
<br />
You can have more then one command in a message. The following commands<br />
are supported. There is more then one spelling for each command, to make<br />
this as user-friendly as possible.<br /><br />
* closes, fixes<br />
The specified issue numbers are closed with the contents of this<br />
commit message being added to it.<br />
* references, refs, addresses, re <br />
The specified issue numbers are left in their current status, but<br />
the contents of this commit message are added to their notes.<br /><br />
A fairly complicated example of what you can do is with a commit message of:<br /><br />
Changed blah and foo to do this or that. Fixes #10 and #12, and refs #12.<br /><br />
This will close #10 and #12, and add a note to #12.<br />
<br />
= License Issues =<br />
<br />
* Contributed code must be GPL'd (preferrably 'GPLv2 or any later version', but 'GPLv2' is fine, too). At the very minimum the code must have a GPL-compatible license.<br />
<br />
== Common License Header ==<br />
<br />
Please quote the full GPL license header text in every file, as shown below. It should contain:<br />
<br />
* The '''year(s)''' when the code was written or modified and a '''copyright note''' of you (or your company, if you are contributing as part of your employment, and thus the copyright belongs to your company). Also, please provide an '''email address''' so that you can be contacted if questions arise.<br />
** Example:<br />
::''Copyright (C) 2006 John Doe <john@example.com>''<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
* An extra line which lists the '''author of the code, if the copyright holder is not the same as the author''' (e.g. if you work for a company and the company owns the copyright).<br />
** Example:<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
::''(Written by Janet Doe <janet@example.com> for Company, Inc.)''<br />
* The full '''GPL header''' as shown below.<br />
<br />
'''Complete example for *.c and *.h files:'''<br />
<br />
/*<br />
* This file is part of the coreboot project.<br />
*<br />
* Copyright (C) 2003-2005 John Doe <john@example.com><br />
* Copyright (C) 2005 Jane Doe <jane@example.com><br />
* Copyright (C) 2006 Company, Inc.<br />
* (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
* Copyright (C) 2007 Joe Doe <joe@example.com><br />
*<br />
* This program is free software; you can redistribute it and/or modify<br />
* it under the terms of the GNU General Public License as published by<br />
* the Free Software Foundation; either version 2 of the License, or<br />
* (at your option) any later version.<br />
*<br />
* This program is distributed in the hope that it will be useful,<br />
* but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
* GNU General Public License for more details.<br />
*<br />
* You should have received a copy of the GNU General Public License<br />
* along with this program; if not, write to the Free Software<br />
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
*/<br />
<br />
'''Complete example for Makefiles, config files, Python files, shell scripts etc.:'''<br />
<br />
##<br />
## This file is part of the coreboot project.<br />
##<br />
## Copyright (C) 2003-2005 John Doe <john@example.com><br />
## Copyright (C) 2005 Jane Doe <jane@example.com><br />
## Copyright (C) 2006 Company, Inc.<br />
## (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
## Copyright (C) 2007 Joe Doe <joe@example.com><br />
##<br />
## This program is free software; you can redistribute it and/or modify<br />
## it under the terms of the GNU General Public License as published by<br />
## the Free Software Foundation; either version 2 of the License, or<br />
## (at your option) any later version.<br />
##<br />
## This program is distributed in the hope that it will be useful,<br />
## but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
## GNU General Public License for more details.<br />
##<br />
## You should have received a copy of the GNU General Public License<br />
## along with this program; if not, write to the Free Software<br />
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
##</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9563
Board:gigabyte/ga-6bxc
2010-04-25T15:21:31Z
<p>AJenbo: </p>
<hr />
<div>== Status ==<br />
<br />
Nothing special is required to build core boot for this system.<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = WIP<br />
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it. <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = WIP<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but some non standard modules that worked partially in BIOS are rejected (initram.c).<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9560
Board:gigabyte/ga-6bxc
2010-04-22T22:46:55Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
Nothing special is required to build core boot for this system.<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = WIP<br />
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it. <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = WIP<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but some non standard modules that worked partially in BIOS are rejected (initram.c).<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Reboot_comments = Graphic dosn't clear on reboot.<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9556
Board:gigabyte/ga-6bxc
2010-04-22T10:59:07Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
Nothing special is required to build core boot for this system.<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but some non standard modules that worked partially in BIOS are rejected (initram.c).<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Reboot_comments = Graphic dosn't clear on reboot.<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9555
Board:gigabyte/ga-6bxc
2010-04-22T10:17:31Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but some non standard modules that worked partially in BIOS are rejected (initram.c).<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Reboot_comments = Graphic dosn't clear on reboot.<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9554
Board:gigabyte/ga-6bxc
2010-04-22T10:15:54Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but some non standard modules that worked partially in BIOS are rejected (initram.c).<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|Speaker_comments = beep only works after running $ modprobe pcspkr<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Reboot_comments = Graphic dosn't clear on reboot.<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9553
Board:gigabyte/ga-6bxc
2010-04-22T10:15:04Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but some non standard modules that worked partially in BIOS are rejected (initram.c).<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|Speaker_comments = beep only works after running $ modprobe pcspkr<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Reboot_comments = Graphic dosn't clear<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9552
Board:gigabyte/ga-6bxc
2010-04-22T10:06:47Z
<p>AJenbo: </p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but currently some modules that worked partialy with the original BIOS is being rejected, probably because of hardcoded settings in the NB code.<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|Speaker_comments = beep only works after running $ modprobe pcspkr<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Reboot_comments = Graphic dosn't clear<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9551
Board:gigabyte/ga-6bxc
2010-04-22T00:48:28Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but currently some modules that worked partialy with the original BIOS is being rejected, probably because of hardcoded settings in the NB code.<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|Speaker_comment = beep only works after running $ modprobe pcspkr<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Reboot_comment = Graphic dosn't clear<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comment = NIC is powered off when the system is off<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9550
Board:gigabyte/ga-6bxc
2010-04-22T00:36:01Z
<p>AJenbo: </p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but currently some modules that worked partialy with the original BIOS is being rejected, probably because of hardcoded settings in the NB code.<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|Speaker_comment = beep only works after running $ modprobe pcspkr<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Reboot_comment = Graphic dosn't clear<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9549
Board:gigabyte/ga-6bxc
2010-04-22T00:35:23Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but currently some modules that worked partialy with the original BIOS is being rejected, probably because of hardcoded settings in the NB code.<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PP_status = Only tested via modprobe<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|Speaker_comment = beep only works after running $ modprobe pcspkr<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Reboot_comment = Graphic dosn't clear<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9548
Board:gigabyte/ga-6bxc
2010-04-21T23:59:10Z
<p>AJenbo: /* Status */</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but currently some modules that worked partialy with the original BIOS is being rejected, probably because of hardcoded settings in the NB code.<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|PP_status = OK<br />
|PP_status = Only tested via modprobe<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|Speaker_comment = beep only works after running $ modprobe pcspkr<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Reboot_comment = Graphic dosn't clear<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9547
Board:gigabyte/ga-6bxc
2010-04-21T23:55:55Z
<p>AJenbo: </p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but currently some modules that worked partialy with the original BIOS is being rejected, probably because of hardcoded settings in the NB code.<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = Untested<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|PP_status = Untested<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|Speaker_comment = beep only works after running $ modprobe pcspkr<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = OK<br />
|Reboot_comment = Graphic dosn't clear<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=9546
Board:gigabyte/ga-6bxc
2010-04-21T23:17:52Z
<p>AJenbo: </p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = WIP<br />
|RAM_SDRAM_comments = Works, but currently some modules that worked partialy with the original BIOS is being rejected, probably because of hardcoded settings in the NB code.<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = Untested<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|PP_status = Untested<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = Untested<br />
|Poweroff_status = Untested<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Memtest86&diff=9545
Memtest86
2010-04-21T21:43:02Z
<p>AJenbo: /* coreboot */</p>
<hr />
<div>[[Image:Qemu memtest.png|thumb|right|The [[Memtest86]] payload.]]<br />
<br />
'''[http://www.memtest86.com/ Memtest86]''' is a program which checks your RAM modules.<br />
<br />
It can be run from within GRUB, but also as a coreboot payload (i.e. included in your ROM chip).<br />
<br />
== Building ==<br />
<br />
=== Memtest86 ===<br />
<br />
mkdir foo<br />
cd foo<br />
wget http://www.memtest86.com/memtest86-3.5.tar.gz<br />
tar xfvz memtest86-3.5.tar.gz<br />
cd memtest86-3.5<br />
(Optional: edit '''config.h''' and set '''#define SERIAL_CONSOLE_DEFAULT 1''' for serial support)<br />
make<br />
<br />
The file '''memtest''' is your final payload which you can use with coreboot (v2 or v3), either on real hardware or in a QEMU image.<br />
<br />
=== coreboot ===<br />
<br />
Finally, you have to build coreboot (v3 in this example) with Memtest86 as payload:<br />
<br />
cd ..<br />
svn co svn://coreboot.org/repository/coreboot-v3 '''-r656'''<br />
cp memtest86-3.5/memtest coreboot-v3/payload.elf<br />
cd coreboot-v3<br />
make menuconfig<br />
<br />
Now enter the '''Payload''' menu and select '''Payload type''' and then '''An ELF executable payload file'''. Now exit the menu, save your settings, and build coreboot:<br />
<br />
make<br />
<br />
The file '''build/coreboot.rom''' (or '''build/bios.bin''') is your final coreboot v3 image, which also contains the payload.<br />
<br />
== Running Memtest86 in QEMU ==<br />
<br />
For running the coreboot+Memtest86 image in QEMU, you need a patched version of '''vgabios-cirrus.bin''' in your '''build''' directory first:<br />
<br />
cd build<br />
wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip<br />
unzip Vgabios-cirrus.zip<br />
cd ..<br />
<br />
You can now run coreboot and Memtest86 in QEMU:<br />
<br />
qemu -L build -hda /dev/zero -serial stdio<br />
<br />
== Ready-made QEMU image ==<br />
<br />
Please follow [http://www.coreboot.org/QEMU#coreboot_v3_.2B_Memtest86 these instructions] if you want to try out coreboot and Memtest86 in [[QEMU]].<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=VIA_NAB7400&diff=9544
VIA NAB7400
2010-04-21T14:13:36Z
<p>AJenbo: </p>
<hr />
<div>This page describes how to use coreboot on the '''VIA NAB7400''' mainboard.<br />
<br />
This page is a work in progress.<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments =Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = OK<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = OK<br />
|IDE_comments = <br />
|IDE_CF_status = OK<br />
|IDE_CF_comments = <br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|CDROM_DVD_comments = <br />
|SATA_status = No<br />
|SATA_comments = Doesn't work, yet. PATA Only<br />
|USB_status = OK<br />
|USB_comments = Only with FILO, Not Yet With LAB<br />
|Onboard_VGA_status = OK with X<br />
|Onboard_VGA_comments = No Console VGA Yet<br />
|Onboard_ethernet_status = Not yet<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments =<br />
|PCIE_x1_status = N/A<br />
|PCIE_x1_comments = <br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x16_comments = <br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|Floppy_comments = <br />
|COM1_status = OK<br />
|COM2_status = Not tested<br />
|PP_status = Not tested<br />
|PP_comments = <br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|Game_port_comments = <br />
|IR_status = Not tested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Not tested<br />
|Sensors_comments = <br />
|Watchdog_status = OK<br />
|Watchdog_comments = <br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|CPUfreq_comments = <br />
|Powersave_status = N/A<br />
|ACPI_status = ?<br />
|ACPI_comments = <br />
|Reboot_status = OK<br />
|Poweroff_status = <br />
|LEDs_status = OK<br />
|LEDs_comments = <br />
|HPET_status = Not tested<br />
|HPET_comments = <br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = SST 512KB + 1MB, PMC 512KB, 2MB not yet<br />
<br />
}}<br />
<br />
<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxe&diff=9543
Board:gigabyte/ga-6bxe
2010-04-21T14:04:59Z
<p>AJenbo: </p>
<hr />
<div>== Status ==<br />
<br />
Work on this board is planed, but has not started yet.<br />
<br />
{{Status|<br />
<br />
|CPU_status = Untested<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = Untested<br />
|RAM_SDRAM_status = Untested<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = Untested<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = Untested<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = Untested<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = Untested<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = Untested<br />
|COM2_status = Untested<br />
|PP_status = Untested<br />
|PS2_keyboard_status = Untested<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|CPUfreq_status = N/A<br />
|Powersave_status = Untested<br />
|ACPI_status = Untested<br />
|Reboot_status = Untested<br />
|Poweroff_status = Untested<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = Untested<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
AJenbo
https://www.coreboot.org/index.php?title=Board:asus/p2b-f&diff=9542
Board:asus/p2b-f
2010-04-21T12:43:50Z
<p>AJenbo: /* Troubleshooting */</p>
<hr />
<div>[[Image:Asus_p2b-f.jpg|thumb|The ASUS P2B-F, revision 1.00]]<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = CPU: L1 I cache: 16K, L1 D cache: 16K<br />
|CPU_L2_status = WIP<br />
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it.<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = WIP<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list.<br />
<br />
|IDE_status = Untested<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = N/A<br />
|USB_status = OK<br />
|USB_comments = Tested: USB keyboard in both USB ports.<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|AGP_cards_comments = Tested: AGP graphics card (ATI 3D Rage Pro AGP 1X/2X).<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = Tested: PCI VGA card in all five PCI slots.<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|PP_status = OK<br />
|PP_comments = Doing '''modprobe ppdev''' works fine, but further tests were not performed.<br />
|PS2_keyboard_status = WIP<br />
|PS2_mouse_status = WIP<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments = Works fine, you can use the '''w83781d''', '''i2c-piix4''', and '''eeprom''' kernel modules.<br />
|Watchdog_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = N/A<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board.<br />
|SMBus_status = Untested<br />
|Reboot_status = WIP<br />
|Poweroff_status = No<br />
|LEDs_status = N/A<br />
|LEDs_comments = No special-purpose LEDs available on the board.<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = <br />
|WakeOnLAN_status = <br />
|WakeOnKeyboard_status = <br />
|WakeOnMouse_status = <br />
|Flashrom_status = OK<br />
|Flashrom_comments = Works on both the vendor BIOS as well as on coreboot.<br />
<br />
}}<br />
== Build tutorial ==<br />
<br />
First, before thinking of using coreboot, make sure you have a backup of your current BIOS image(see [[Flashrom]]), and the correct facilities to replace that image, if it becomes corrupt. Assuming you have a backup and restore procedure, continue with the following(which may destroy your board anyways! you have been warned!)<br />
<br />
It is recommended that you have a known good PCI video card, a known good single sided PC100 non-ecc dimm, and a known good null modem cable before you proceed, for error recovery. At this point, it is recommended that you have many dimms, as the timings are compiled into the bios, and theres no good way to know your dimm is going to work after flashing.<br />
<br />
CoreBoot has multiple [[Payloads]] used for the boot process ([[SeaBIOS]], [[FILO]], [[GRUB2]], etc), and you must build a payload first, so that CoreBoot can build it into itsself.<br />
<br />
after your payload is compiled(assuming you compiled the [[FILO]] payload), copy the resulting file to /tmp/filo.elf, then:<br />
<br />
Check out a copy of coreboot<br />
$ svn co svn://coreboot.org/coreboot/trunk coreboot<br />
<br />
Build the files used to build the bios<br />
$ cd coreboot/targets<br />
$ ./buildtarget asus/p2b-f<br />
<br />
Build the bios itsself<br />
$ cd asus/p2b-f/p2b-f<br />
$ make -s<br />
<br />
The resulting '''coreboot.rom''' is your coreboot ROM image you can flash using [[flashrom]].<br />
<br />
== Troubleshooting ==<br />
<br />
So, you installed coreboot, and now your board doesn't boot?<br />
<br />
First, check the serial port, and see what sort of output you're getting. <br />
<br />
The following is what the section of coreboot on the P2B-F shows when enabling ram:<br />
<br />
RAM Enable 1: Apply NOP<br />
RAM Enable 2: Precharge all<br />
RAM Enable 3: CBR<br />
RAM Enable 4: Mode register set<br />
RAM Enable 5: Normal operation<br />
RAM Enable 6: Enable refresh<br />
Enabling refresh (DRAMC = 0x09) for DIMM 00<br />
<br />
If in your output, you do not see the 'Enabling refresh' line, your ram chip is not being detected, or refreshed. try a different dimm, and make sure you're placing it in slot 1 (the slot closest to the CPU).<br />
<br />
If this doesn't solve your problem, remove all the PCI or ISA components. then remove your IDE and floppy devices, and try again. If that still does not give you output on the serial port, you likely have a bad flash or bad cable (you did test it, right?). if you get partial output from the serial, but do not get to the point where you see your payload booting your system, then its time to upload the serial output you're getting after simplifying your hardware configuration to a paste website, and drop by IRC or the mailing list, and ask for help.<br />
<br />
= Known Working Revisions =<br />
<br />
Coreboot revision 3949 + filo 0.5.6 version 85 (keyboard does not work! builds a 128K image, make sure to slim filo down!)<br />
<br />
{{GPL}}</div>
AJenbo