https://www.coreboot.org/api.php?action=feedcontributions&user=Kmalkki&feedformat=atomcoreboot - User contributions [en]2024-03-29T04:46:30ZUser contributionsMediaWiki 1.40.0https://www.coreboot.org/index.php?title=User:Kmalkki/draft_board_status_2&diff=13667User:Kmalkki/draft board status 22014-05-10T15:16:19Z<p>Kmalkki: Created page with "== Motherboards supported in coreboot == {| border="0" style="font-size: smaller" |- bgcolor="#6699ff" ! align="left" | Vendor ! align="left" | Mainboard ! align="left" | Lat..."</p>
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<div></div>Kmalkkihttps://www.coreboot.org/index.php?title=User:Kmalkki/draft_board_status&diff=13666User:Kmalkki/draft board status2014-05-10T14:22:20Z<p>Kmalkki: </p>
<hr />
<div></div>Kmalkkihttps://www.coreboot.org/index.php?title=Board:samsung/lumpy&diff=13665Board:samsung/lumpy2014-05-10T12:27:15Z<p>Kmalkki: </p>
<hr />
<div>see [[Chromebooks|Chromebooks]]<br />
= aka Samsung Lumpy aka Samsung XE550C22-H02US =<br />
<br />
Features a "Multi Card Slot 4- in-1 (SD/SDHC/SDXC/MMC)"<br />
<br />
== Status ==<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = Core i5-2467M, FCBGA1023<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = ?<br />
|CPU_virt_status = ?<br />
|CPU_virt_status_comments = Untested<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = OK<br />
|RAM_SODIMM_comments = One SODIMM slot.<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_dualchannel_status = ?<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = mSATA. This chromebook comes with a SanDisk SDSA4DH-016G. Tested larger SSD (mSATA crucial m4 256GB), works ok<br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Multihead OK with DP++ to HDMI to DVI converters. <br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Realtek 8111/8168<br />
|Onboard_wireless = OK<br />
|Onboard_wireless_comments = Atheros AR9300 (ar5bhb116), 802.11 a/b/g/n<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = Untested<br />
|Onboard_modem_comments = Qualcomm WWAN modem, t77z204t12/pkrnvwe396/3229b-e396. You most likely need a SIM card to use this modem.<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = Untested<br />
|Smartcard_comments = A SIM card slot is available.<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_CF_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|Mini_PCI_cards_comments = Half-length slot (WLAN) with PCIe. Full-length (WWAN) slot with USB2.<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM1_comments = no on-board RS232 connector<br />
|COM2_status = OK<br />
|COM2_comments = with Oxford OXPCIe952 replacing WLAN card in mini-PCI-e slot<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = WIP<br />
|Speaker_comments = http://review.coreboot.org/#/c/1410/<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = ?<br />
|Watchdog_status = ?<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = N/A<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
<br />
|Flashrom_status = OK<br />
|Flashrom_comments = needs assembly of a jumper to the mainboard<br />
}}</div>Kmalkkihttps://www.coreboot.org/index.php?title=User:Kmalkki/draft_board_status&diff=13663User:Kmalkki/draft board status2014-05-09T08:19:19Z<p>Kmalkki: Created page with "== Motherboards supported in coreboot == {| border="0" style="font-size: smaller" |- bgcolor="#6699ff" ! align="left" | Vendor ! align="left" | Mainboard ! align="left" | Lat..."</p>
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<div></div>Kmalkkihttps://www.coreboot.org/index.php?title=GSoC&diff=13299GSoC2014-02-06T09:44:28Z<p>Kmalkki: </p>
<hr />
<div></div>Kmalkkihttps://www.coreboot.org/index.php?title=EHCI_Gadget_Debug&diff=12143EHCI Gadget Debug2013-08-26T18:54:53Z<p>Kmalkki: /* Loading */</p>
<hr />
<div>== Introduction ==<br />
This page is about using embedded GNU/Linux devices in order to get the USB debug logs.<br />
<br />
== Howto ==<br />
=== Patching ===<br />
Download the [[:File:Ehci-debug-gadget-patches.tar.gz|patches]] that maintain TTY connected while debug target power-cycles or when host controller is reset.<br />
<br />
Apply the patches from one of the v3.8- or v3.10-debug-gadget directories on your kernel build tree.<br />
<br />
=== Compiling ===<br />
* You need to be familiar with (cross) compiling your kernel.<br />
* (Cross) compile it as usual but during the configuration do the following:<br />
Go into Device Drivers:<br />
Device Drivers ---><br />
Then go into USB support:<br />
[*] USB support ---><br />
Then go into USB Gadget Support:<br />
<M> USB Gadget Support ---><br />
Then enable the following option:<br />
<M> EHCI Debug Device Gadget<br />
Then select the serial option:<br />
EHCI Debug Device mode (serial) ---><br />
<br />
=== Loading ===<br />
Remove all usb gadget drivers such as g_ehter or g_mass_storage with rmmod then do:<br />
modprobe g_dbgp<br />
<br />
=== Running ===<br />
I recommend to open the TTY before starting debug target. Doing it the other way<br />
around slows down the debug target boot and seems to confuse serial gadget framework.<br />
<br />
You may want to disable some CR/LF translations on the device:<br />
stty -icrnl -inlcr -F /dev/ttyGS0<br />
<br />
You can directly open the device node, possibly redirecting to file:<br />
cat /dev/ttyGS0<br />
.. or use a terminal client:<br />
picocom -ir /dev/ttyGS0<br />
<br />
=== Finding the USB debug port ===<br />
See [[EHCI Debug Port#Finding the USB debug port]]<br />
<br />
== Tested hardware ==<br />
{| class="wikitable" border="1"<br />
! Brand and Device<br />
! kernel used<br />
! Target devices<br />
! works?<br />
|-<br />
! [http://projects.goldelico.com/p/gta04-main/ Goldelico GTA04 A3]<br />
| [https://github.com/goldelico/gta04-kernel/commits/neil-plus neil-plus kernel and branch (3.7)]<br />
| Lenovo X60<br />
| {{yes}}<br />
|-<br />
! [http://wiki.buglabs.net/index.php/Welcome_to_BUG_Wiki Buglabs's bug 2.0]<br />
| [https://github.com/buglabs/bug20-2.6.35-linaro/commits/master bug20-2.6.35-linaro's master (2.6.35) ]<br />
| Lenovo X60<br />
| {{yes}}<br />
|-<br />
|}</div>Kmalkkihttps://www.coreboot.org/index.php?title=EHCI_Gadget_Debug&diff=12142EHCI Gadget Debug2013-08-26T18:46:42Z<p>Kmalkki: /* Compiling */</p>
<hr />
<div>== Introduction ==<br />
This page is about using embedded GNU/Linux devices in order to get the USB debug logs.<br />
<br />
== Howto ==<br />
=== Patching ===<br />
Download the [[:File:Ehci-debug-gadget-patches.tar.gz|patches]] that maintain TTY connected while debug target power-cycles or when host controller is reset.<br />
<br />
Apply the patches from one of the v3.8- or v3.10-debug-gadget directories on your kernel build tree.<br />
<br />
=== Compiling ===<br />
* You need to be familiar with (cross) compiling your kernel.<br />
* (Cross) compile it as usual but during the configuration do the following:<br />
Go into Device Drivers:<br />
Device Drivers ---><br />
Then go into USB support:<br />
[*] USB support ---><br />
Then go into USB Gadget Support:<br />
<M> USB Gadget Support ---><br />
Then enable the following option:<br />
<M> EHCI Debug Device Gadget<br />
Then select the serial option:<br />
EHCI Debug Device mode (serial) ---><br />
<br />
=== Loading ===<br />
Remove all usb gadget drivers such as g_ehter or g_mass_storage with rmmod then do:<br />
modprobe g_dbgp<br />
<br />
=== Finding the USB debug port ===<br />
See [[EHCI Debug Port#Finding the USB debug port]]<br />
<br />
== Tested hardware ==<br />
{| class="wikitable" border="1"<br />
! Brand and Device<br />
! kernel used<br />
! Target devices<br />
! works?<br />
|-<br />
! [http://projects.goldelico.com/p/gta04-main/ Goldelico GTA04 A3]<br />
| [https://github.com/goldelico/gta04-kernel/commits/neil-plus neil-plus kernel and branch (3.7)]<br />
| Lenovo X60<br />
| {{yes}}<br />
|-<br />
! [http://wiki.buglabs.net/index.php/Welcome_to_BUG_Wiki Buglabs's bug 2.0]<br />
| [https://github.com/buglabs/bug20-2.6.35-linaro/commits/master bug20-2.6.35-linaro's master (2.6.35) ]<br />
| Lenovo X60<br />
| {{yes}}<br />
|-<br />
|}</div>Kmalkkihttps://www.coreboot.org/index.php?title=File:Ehci-debug-gadget-patches.tar.gz&diff=12141File:Ehci-debug-gadget-patches.tar.gz2013-08-26T18:42:06Z<p>Kmalkki: </p>
<hr />
<div></div>Kmalkkihttps://www.coreboot.org/index.php?title=DIY_EHCI_debug_dongle&diff=11639DIY EHCI debug dongle2013-03-22T19:43:11Z<p>Kmalkki: </p>
<hr />
<div>== Hardware ==<br />
<br />
A dongle to debug target with [[EHCI Debug Port]] capability can be built using two Cypress CY7C68013A (aka FX2LP) USB device chips.<br />
Theory of operation is described in Cypress Application Note AN63787[http://www.cypress.com/?rID=45850].<br />
<br />
There are a few boards in the 10-15 EUR pricerange to choose from and a dozen suppliers in ebay.<br />
<br />
A slower uni-directional boot console has been demonstrated to work with one FX2LP and a TTL-UART-to-USB adapter. In theory at least, some JTAG dongles with FX2LP could be used to capture coreboot console from EHCI debug port.<br />
<br />
== Prototype ==<br />
==== LCSoft FX2LP ====<br />
<br />
[[Image:fx2lp_lcsoft_1.JPG|x240px|LCSoft]]<br />
[[Image:fx2lp_lcsoft_2.JPG|x240px|LCSoft]]<br />
<br />
Schematics for [[:File:fx2lp lcsoft schematic A.pdf|prototype board]] and [[:File:ehci lcsoft revA0.pdf|required modification]].<br />
<br />
<br />
== Firmware ==<br />
<br />
Firmware is built with sdcc using fx2lib.<br />
<br />
Original git repository [http://git.stackframe.org/?p=fx2lib]. Offline.<br />
<br />
Recent updates are here [http://bitbucket.org/kmalkki/fx2lib].</div>Kmalkkihttps://www.coreboot.org/index.php?title=File:Ehci_lcsoft_revA0.pdf&diff=11638File:Ehci lcsoft revA0.pdf2013-03-22T19:22:08Z<p>Kmalkki: EHCI debug dongle modification for LCSoft FX2LP prototype board.</p>
<hr />
<div>EHCI debug dongle modification for LCSoft FX2LP prototype board.</div>Kmalkkihttps://www.coreboot.org/index.php?title=Project_Ideas&diff=11637Project Ideas2013-03-22T18:42:37Z<p>Kmalkki: /* coreboot panic room */</p>
<hr />
<div>The following are some ideas that have come up in the community. Some are more or less suitable for [[GSoC]] and prospective students' application should expand on some ideas and pair back others.<br />
<br />
== Linux Firmware Kit, BITS ==<br />
<br />
There are various test suites for firmware aspects, esp. those that interacts with the operating systems. Unfortunately, some of these projects are dead, some seem to be forked and developed semi-publically, and having all that stuff in lots of different places is a big hassle.<br />
<br />
The goal of this project is to pick up the pieces, and create a single tool (most likely a bootable CD/USB drive image) that can be booted on vendor BIOS (for the Red Hat and Canonical developers that work on these) as well as coreboot (preferably seabios and FILO to improve testability - is an issue created/fixed by coreboot or seabios?). This can then be improved in various ways.<br />
<br />
There's also intel-gpu-tools that might have some useful tests (at least for intel-boards): http://article.gmane.org/gmane.comp.video.dri.devel/63948<br />
<br />
When applying for this task, please state in your proposal what you think might be worthy extensions to the existing tests.<br />
<br />
Required knowledge for this task: Minimal coreboot and firmware experience, but you should have some idea of the boot process of a Linux system (as these test suites are mostly Linux based). GSoC probably won't provide enough time to learn all that (Linux boot process, firmware interfaces such as ACPI) and still develop the tools in some useful way.<br />
<br />
'''Links'''<br />
* https://wiki.ubuntu.com/Kernel/Reference/fwts<br />
* http://biosbits.org/ <br />
* http://linuxfirmwarekit.org/<br />
* [[Supported Motherboards]]<br />
<br />
'''Mentors'''<br />
* [[User:MJones|Marc Jones]]<br />
<br />
== Infrastructure for automatic code checking ==<br />
We already have a build bot that builds various configurations of coreboot. It would be nice to extend it with various code validation routines, for example:<br />
* Validate that there's no regression in doxygen documentation (eg. are all arguments to functions still explained in @param tags, eg. after new arguments were added?)<br />
* Make code lint clean (and maybe extend lint to not fall into our traps), and run lint over the tree. Report regressions<br />
* Use LLVM's static code checking facilities, report regressions.<br />
* Work on code coverage support for coreboot code (dump data into ram, or via serial. Provide tools to fetch it). Analyse that data.<br />
<br />
'''Links'''<br />
* LLVM tools: [http://clang.llvm.org/StaticAnalysis.html Clang static analyser], [http://llvm.org/ProjectsWithLLVM/#Calysto SSA assertion checker], http://klee.llvm.org/<br />
* Lint tools: [http://lclint.cs.virginia.edu/ Splint]<br />
* Coverage: [http://ltp.sourceforge.net/test/coverage/lcov.php LCOV], [http://ggcov.sourceforge.net GGCOV]<br />
* Semantic Tester: https://code.google.com/p/c-semantics/<br />
* [http://frama-c.com/ Frama-C]<br />
<br />
'''Mentors'''<br />
* [[User:Stepan|Stefan Reinauer]], [[User:PatrickGeorgi|Patrick Georgi]]<br />
<br />
== coreboot test suite ==<br />
Create a test suite to gather and report coreboot mainboard and payload settings. This project may leverage libpayload, coreinfo, memtest86, BITS, and other tools like benchmarks for CPU and RAM performance. Konstantin Aladyshev reported according to the benchmark [http://www.cs.virginia.edu/stream/ STREAM], RAM access on his system with coreboot is four times slower than with the proprietary vendor BIOS. Such issues should be easily spotted with the test suite.<br />
<br />
The suite should gather result and report them at summary and detailed levels. The goal is to help coreboot developers identify problems and to test coreboot features. This project should work closely with the testing rig and test reporting projects. It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.<br />
<br />
'''Links'''<br />
* [http://biosbits.org/ BITS]<br />
* [[Supported Motherboards]]<br />
<br />
'''Mentors'''<br />
* [[User:MJones|Marc Jones]], [[User:PatrickGeorgi|Patrick Georgi]]<br />
<br />
== coreboot cheap testing rig ==<br />
The goal of this project is to create a cheap testing rig which works with the existing board test infrastructure. We have a hardware test system since 2006:<br />
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/Slides-LinuxBIOS-QA.pdf Quality Assurance Talk (Slides)]<br />
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/TestIntegrationManual.pdf Test Integration Manual]<br />
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/DevelopersManual.pdf Test Developers Manual]<br />
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/TestSpecification.pdf Test Specification]<br />
<br />
The initial version of our testing rig used a remote power switch and was rather expensive. With cheaper technologies such as X10, it's possible to drop the testing costs per board significantly.<br />
<br />
'''Links'''<br />
* [[InSystemFlasher]] is a cheap DIY hardware prototype for building an automated testing rig for modern SPI-based boards. This could be used as a starting point.<br />
<br />
'''Mentors'''<br />
* [[User:Stepan|Stefan Reinauer]]<br />
<br />
== coreboot mainboard test result reporting ==<br />
One of the biggest challenges in coreboot is support many systems in the same codebase. As systems age and coreboot continues to develop, the condition of mainboards becomes unknown. This project would define a coreboot test results reporting mechanism, gather data, and report passing and failing systems on a webpage. This project would work closely with the coreboot test suite project and/or the hardware test rig project. A good example of test results gathering and reporting is done by the Phoronix/Openbenchmark. The student should investigate other test and reporting solutions to leverage the best options for coreboot. It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.<br />
<br />
'''Links'''<br />
* http://openbenchmarking.org/<br />
* http://www.coreboot.org/Supported_Motherboards<br />
<br />
'''Mentors'''<br />
* [[User:Stepan|Stefan Reinauer]]<br />
* [[User:MJones|Marc Jones]]<br />
<br />
<br />
== coreboot ports for mainboards == <br />
Identify potential mainboards to port based on the recently release cpu and chipset support. The goal would be to support publicly available platforms with a number of payloads and operating systems.<br />
<br />
'''Mentors'''<br />
<br />
* [[User:ruik|Rudolf Marek]]<br />
<br />
== Tianocore as payload ==<br />
<br />
What SeaBIOS is for PC-BIOS interfaces, Tianocore is for UEFI - in fact, it's the reference implementation that most commercial UEFIs are built on. While coreboot favors other design goals than UEFI, it's really useful to support this standard that's being pushed on the market, just like SeaBIOS really helped coreboot by providing a BIOS "frontend".<br />
<br />
There's already some code, but there's still much room for improvement: A graphics driver that uses a preinitialized (by coreboot) framebuffer. A CBFS driver so Tiano can access coreboot flash storage. Based on that, a flash driver (maybe adapted from flashrom) to implement non-volatile variable storage by writing to flash.<br />
<br />
Possible tasks depend a lot on existing knowledge of the candidate. Few of the tasks are large enough to fill the entire GSoC time frame with one of them. Feel free to discuss with us on IRC what a suitable target could be for you.<br />
<br />
'''Links'''<br />
* http://www.tianocore.org/<br />
* https://github.com/pgeorgi/edk2/tree/coreboot-pkg<br />
<br />
<br />
'''Mentors'''<br />
* [[User:Stepan|Stefan Reinauer]]<br />
* [[User:PatrickGeorgi|Patrick Georgi]]<br />
<br />
<br />
== coreboot ACPI 4.0 and S3 power management support ==<br />
coreboot has support for ACPI tables and S3 support for some platforms, but it is very mainboard specific and moslty based on ACPI 2.0. Create a generic solution for ACPI 4.0 table generation and S3 support.<br />
<br />
'''Mentors'''<br />
*<br />
<br />
<br />
==coreboot port to ARM SOC's with PCIe==<br />
<br />
[http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm Xilinx Zynq-7030]<br />
<br />
[http://www.altera.com/devices/fpga/cyclone-v-fpgas/hard-processor-system/cyv-soc-hps.html Altera Cyclone V ]<br />
<br />
[http://www.st.com/internet/mcu/product/251211.jsp ST spear1340]<br />
<br />
<br />
[[ARM]] SOC's with PCIe are available. These systems can take advantage of coreboot's strength in properly configuring PCI devices, fast boot time and payload support.<br />
<br />
Note that coreboot has in the past supported three different CPUs (x86, Alpha, PPC), so the structure is there for adding in a new processor family. <br />
We will need to find the right platform to do the work, but I (Ron) can provide a board and JTAG debugger if needed. <br />
<br />
There was an ARM project started in 2011. <br />
<br />
http://blogs.coreboot.org/blog/2011/05/11/gsoc2011-project-porting-coreboot-to-arm-architecture/<br />
<br />
'''Mentors'''<br />
* Bari Ari<br />
* [[User:Rminnich|Ron Minnich]]<br />
* [[User:Jason Wang|QingPei Wang]]<br />
<br />
== coreboot panic room ==<br />
<br />
Create a safe boot solution for coreboot to easily and cheaply recover the system. <br />
<br />
The basic idea is that the system flash image always contains executable for SerialICE. Instead of loading a coreboot romstage, firmware can boot to SerialICE based on some GPIO state, a keypress sequence or a logged failure on earlier boots. It is possible to integrate this into the coreboot build tree as a bootblock option, in the same spot as the fallback/normal switch and the simple loader.<br />
<br />
Having this capability opens up new possibilities:<br />
<br />
During the lifetime of a mainboard, new requirements for ACPI hacks and CPU microcodes introduce the need to update boot firmware at customer site. The firmware shall have recovery path against any failures during the firmware update process. The most straight-forward solution is to do intelligent allocation of files in the CBFS such that files critical to the recovery are located on write-protected pages. The recovery path shall require only an USB mass-storage with compatible filesystem (ext2, fat32).<br />
<br />
The ability to dual-boot reduces the amount of tools required to reverse-engineer proprietary BIOS on ports for new mainboards. It is increasingly common that the flash chips are a) not socketed or b) physically hard to access (laptops). Even if chipset support existed already for a board, there are a lot of configuration registers for PCI-e links and GPIO signals that are difficult to get right by code disassembly only. With panic room implementation there would be no need to use external programmers or flashchip hot-swap method to alternate between SerialICE (for proprietary BIOS) and coreboot romstage boots.<br />
<br />
SerialICE requires minimal hardware resources and does not require installed RAM or display hardware. It could be used as the first power-on environment after mainboard PCB verification and assembly to verify integrated components enumerate correctly. At the end of this first power-on, actual board firmware can be programmed without the need for external programmers and SOIC-8 clips, as the SPI controller embedded in the chipset can be used instead. As setting up EHCI debug port console is fairly simple across different chipsets, it can be used to print detailed diagnostics instead of POST codes on LPC bus.<br />
<br />
<br />
GSoC 2011 project [http://blogs.coreboot.org/blog/2011/05/09/gsoc-project-coreboot-panic-room-diagnostics-also-remote-flashing/] was able to:<br />
* Link flashrom with libpayload and flash from USB drive in a pre-OS environment.<br />
* Optimise flashrom memory usage to flash in pre-ram/cache-as-ram environment.<br />
* Build SerialICE boot ROM inside the coreboot tree and share some of the PnP/SuperIO source code.<br />
* Demonstrate booting alternative payload on keypress.<br />
<br />
<br />
There are remaining open tasks to:<br />
* Bring the GSoC 2011 patches up-to-date with current flashrom and libpayload trees.<br />
* Create generic solution to jump to recovery mode using input from GPIOs and/or use of power-button override.<br />
* Use SMBus/SMLink to send POST failure codes over ethernet using integrated network controllers.<br />
* After panic(), dump RAM contents before they are overwritten.<br />
<br />
<br />
'''Mentors'''<br />
* [[User:Rminnich|Ron Minnich]]<br />
<br />
== Board config infrastructure ==<br />
<br />
Design data structures that host information about the board layout so coreboot can better initialize components and generate all kinds of tables (mptable, pirq, acpi, ...) from that dynamically (at build or runtime, as appropriate). Adapt boards to use that instead of the current hardcodes.<br />
<br />
'''Links'''<br />
* ?<br />
<br />
'''Mentors'''<br />
* ?<br />
<br />
<br />
== Refactor AMD code ==<br />
<br />
AMD K8 and AMD Fam10 are different enough to have their own code. This is unfortunate, as you have to decide which CPU type you use in a given mainboard. Refactor AMD code so a single image can support both chip types on a given board. Also move tables from get_bus_conf and the like to the device tree or kconfig options (or runtime detection), as appropriate.<br />
<br />
Alternatively, figure out a way how to build them in parallel and have coreboot select the right one on runtime.<br />
<br />
'''Links'''<br />
* ?<br />
<br />
'''Mentors'''<br />
* [[User:Stepan|Stefan Reinauer]]</div>Kmalkkihttps://www.coreboot.org/index.php?title=File:Fx2lp_lcsoft_schematic_A.pdf&diff=11624File:Fx2lp lcsoft schematic A.pdf2013-03-20T08:20:01Z<p>Kmalkki: LCSoft FX2LP prototype Rev A schematic
Published with permission of Shenzhen LC Technology CO., LTD.
http://www.lctech-inc.com/</p>
<hr />
<div>LCSoft FX2LP prototype Rev A schematic<br />
Published with permission of Shenzhen LC Technology CO., LTD.<br />
http://www.lctech-inc.com/</div>Kmalkkihttps://www.coreboot.org/index.php?title=GSoC&diff=11623GSoC2013-03-20T06:36:09Z<p>Kmalkki: /* People involved */</p>
<hr />
<div></div>Kmalkkihttps://www.coreboot.org/index.php?title=GSoC&diff=11603GSoC2013-03-17T21:34:03Z<p>Kmalkki: </p>
<hr />
<div></div>Kmalkkihttps://www.coreboot.org/index.php?title=DIY_EHCI_debug_dongle&diff=11600DIY EHCI debug dongle2013-03-17T06:03:18Z<p>Kmalkki: Prototype debug dongle with FX2LP boards</p>
<hr />
<div>== Hardware ==<br />
<br />
An EHCI debug dongle can be built using two Cypress FX2LP prototyping boards with CY7C68013A.<br />
There are a few boards in the 10-15 EUR pricerange to choose from and a dozen suppliers in ebay.<br />
<br />
[[Image:fx2lp_lcsoft_1.JPG|x240px|LCSoft]]<br />
[[Image:fx2lp_lcsoft_2.JPG|x240px|LCSoft]]<br />
<br />
<br />
A slower uni-directional boot console has been demonstrated to work with one such board and a TTL-UART-to-USB adapter.<br />
<br />
== Schematics ==<br />
<br />
Schematic is modified from Cypress Application Note AN63787 [http://www.cypress.com/?rID=45850].<br />
<br />
<br />
== Dongle firmware ==<br />
<br />
Firmware is built with sdcc using fx2lib.<br />
<br />
Original git repository [http://git.stackframe.org/?p=fx2lib]. Offline.<br />
<br />
Recent updates are here [http://bitbucket.org/kmalkki/fx2lib].</div>Kmalkkihttps://www.coreboot.org/index.php?title=File:Fx2lp_lcsoft_2.JPG&diff=11599File:Fx2lp lcsoft 2.JPG2013-03-17T05:50:08Z<p>Kmalkki: Debug dongle boxed.</p>
<hr />
<div>Debug dongle boxed.</div>Kmalkkihttps://www.coreboot.org/index.php?title=File:Fx2lp_lcsoft_1.JPG&diff=11598File:Fx2lp lcsoft 1.JPG2013-03-17T05:41:44Z<p>Kmalkki: LCSoft FX2LP boards connected back-to-back.</p>
<hr />
<div>LCSoft FX2LP boards connected back-to-back.</div>Kmalkkihttps://www.coreboot.org/index.php?title=Project_Ideas&diff=11597Project Ideas2013-03-16T15:45:47Z<p>Kmalkki: /* coreboot panic room */</p>
<hr />
<div>The following are some ideas that have come up in the community. Some are more or less suitable for GSoC and prospective students' application should expand on some ideas and pair back others.<br />
<br />
== Linux Firmware Kit, BITS ==<br />
<br />
There are various test suites for firmware aspects, esp. those that interacts with the operating systems. Unfortunately, some of these projects are dead, some seem to be forked and developed semi-publically, and having all that stuff in lots of different places is a big hassle.<br />
<br />
The goal of this project is to pick up the pieces, and create a single tool (most likely a bootable CD/USB drive image) that can be booted on vendor BIOS (for the Red Hat and Canonical developers that work on these) as well as coreboot (preferably seabios and FILO to improve testability - is an issue created/fixed by coreboot or seabios?). This can then be improved in various ways.<br />
<br />
There's also intel-gpu-tools that might have some useful tests (at least for intel-boards): http://article.gmane.org/gmane.comp.video.dri.devel/63948<br />
<br />
When applying for this task, please state in your proposal what you think might be worthy extensions to the existing tests.<br />
<br />
Required knowledge for this task: Not so much coreboot/firmware level, but you should have some idea of the boot process of a Linux system (as these test suites are mostly Linux based). GSoC probably won't provide enough time to learn all that (Linux boot process, firmware interfaces such as ACPI) and still develop the tools in some useful way.<br />
<br />
Further reading: https://wiki.ubuntu.com/Kernel/Reference/fwts http://biosbits.org/ http://linuxfirmwarekit.org/<br />
<br />
== Infrastructure for automatic code checking ==<br />
We already have a build bot that builds various configurations of coreboot. It would be nice to extend it with various code validation routines, for example:<br />
* Validate that there's no regression in doxygen documentation (eg. are all arguments to functions still explained in @param tags, eg. after new arguments were added?)<br />
* Make code lint clean (and maybe extend lint to not fall into our traps), and run lint over the tree. Report regressions<br />
* Use LLVM's static code checking facilities, report regressions.<br />
* Work on code coverage support for coreboot code (dump data into ram, or via serial. Provide tools to fetch it). Analyse that data.<br />
<br />
'''Links'''<br />
* LLVM tools: [http://clang.llvm.org/StaticAnalysis.html Clang static analyser], [http://llvm.org/ProjectsWithLLVM/#Calysto SSA assertion checker], http://klee.llvm.org/<br />
* Lint tools: [http://lclint.cs.virginia.edu/ Splint]<br />
* Coverage: [http://ltp.sourceforge.net/test/coverage/lcov.php LCOV], [http://ggcov.sourceforge.net GGCOV]<br />
* Semantic Tester: https://code.google.com/p/c-semantics/<br />
* [http://frama-c.com/ Frama-C]<br />
<br />
'''Mentors'''<br />
* [[User:Stepan|Stefan Reinauer]], [[User:PatrickGeorgi|Patrick Georgi]]<br />
<br />
== coreboot test suite ==<br />
Create a test suite to gather and report coreboot mainboard and payload settings. This project may leverage libpayload, coreinfo, memtest86, BITS, and other tools like benchmarks for CPU and RAM performance. Konstantin Aladyshev reported according to the benchmark [http://www.cs.virginia.edu/stream/ STREAM], RAM access on his system with coreboot is four times slower than with the proprietary vendor BIOS. Such issues should be easily spotted with the test suite.<br />
<br />
The suite should gather result and report them at summary and detailed levels. The goal is to help coreboot developers identify problems and to test coreboot features. This project should work closely with the testing rig and test reporting projects. It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.<br />
<br />
'''Links'''<br />
* [http://biosbits.org/ BITS]<br />
* [[Supported Motherboards]]<br />
<br />
'''Mentors'''<br />
* [[User:MJones|Marc Jones]], [[User:PatrickGeorgi|Patrick Georgi]]<br />
<br />
== coreboot cheap testing rig ==<br />
The goal of this project is to create a cheap testing rig which works with the existing board test infrastructure. We have a hardware test system since 2006:<br />
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/Slides-LinuxBIOS-QA.pdf Quality Assurance Talk (Slides)]<br />
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/TestIntegrationManual.pdf Test Integration Manual]<br />
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/DevelopersManual.pdf Test Developers Manual]<br />
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/TestSpecification.pdf Test Specification]<br />
<br />
The initial version of our testing rig used a remote power switch and was rather expensive. With cheaper technologies such as X10, it's possible to drop the testing costs per board significantly.<br />
<br />
'''Links'''<br />
* [[InSystemFlasher]] is a cheap DIY hardware prototype for building an automated testing rig for modern SPI-based boards. This could be used as a starting point.<br />
<br />
'''Mentors'''<br />
* [[User:Stepan|Stefan Reinauer]]<br />
<br />
== coreboot mainboard test result reporting ==<br />
One of the biggest challenges in coreboot is support many systems in the same codebase. As systems age and coreboot continues to develop, the condition of mainboards becomes unknown. This project would define a coreboot test results reporting mechanism, gather data, and report passing and failing systems on a webpage. This project would work closely with the coreboot test suite project and/or the hardware test rig project. A good example of test results gathering and reporting is done by the Phoronix/Openbenchmark. The student should investigate other test and reporting solutions to leverage the best options for coreboot. It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.<br />
<br />
'''Links'''<br />
* http://openbenchmarking.org/<br />
* http://www.coreboot.org/Supported_Motherboards<br />
<br />
'''Mentors'''<br />
* [[User:Stepan|Stefan Reinauer]]<br />
* [[User:MJones|Marc Jones]]<br />
<br />
<br />
== coreboot ports for Family14 mainboards == <br />
Identify potential mainboards to port based on the recently released AMD Family 14 support. The goal would be to support publicly available plaftorms with a number of payloads and operating systems.<br />
<br />
'''Mentors'''<br />
*[[User:Jason Wang|QingPei Wang]]<br />
<br />
<br />
== coreboot ACPI/S3/power managment ==<br />
coreboot has support for ACPI tables and S3 support for some platforms, but it is very mainboard specific. Create a generic solution for ACPI table generation and S3 support.<br />
<br />
'''Mentors'''<br />
*<br />
<br />
<br />
==coreboot port to ARM SOC's with PCIe==<br />
<br />
[http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm Xilinx Zynq-7030]<br />
<br />
[http://www.altera.com/devices/fpga/cyclone-v-fpgas/hard-processor-system/cyv-soc-hps.html Altera Cyclone V ]<br />
<br />
[http://www.st.com/internet/mcu/product/251211.jsp ST spear1340]<br />
<br />
<br />
[[ARM]] SOC's with PCIe are available. These systems can take advantage of coreboot's strength in properly configuring PCI devices, fast boot time and payload support.<br />
<br />
Note that coreboot has in the past supported three different CPUs (x86, Alpha, PPC), so the structure is there for adding in a new processor family. <br />
We will need to find the right platform to do the work, but I (Ron) can provide a board and JTAG debugger if needed. <br />
<br />
There was an ARM project started in 2011. <br />
<br />
http://blogs.coreboot.org/blog/2011/05/11/gsoc2011-project-porting-coreboot-to-arm-architecture/<br />
<br />
'''Mentors'''<br />
* Bari Ari<br />
* [[User:Rminnich|Ron Minnich]]<br />
* [[User:Jason Wang|QingPei Wang]]<br />
<br />
== coreboot panic room ==<br />
<br />
Create a safe boot solution for coreboot to easily and cheaply recover the system in case of a panic(). <br />
<br />
Ron would like to base this solution around SerialICE. The basic idea is that the system always boots to SerialICE. There is a test in CMOS for 'last boot worked' and, if this is set, SerialICE finds a coreboot in cbfs and runs it. If 'last boot worked' is not set, or the user hits some magic keyboard sequence, SerialICE takes control. <br />
<br />
SerialICE needs to be extended (not much) to make this work. Having this capability would make it possible for Ron to get some very hard ports working that are just not possible today. At the same time, there are lots of hardware boards to test this idea on, so it should be easy to get it working.<br />
<br />
It might be possible to integrate this into the coreboot build as a bootblock option (in the same spot as the fallback/normal switch and the simple loader).<br />
<br />
<br />
GSoC 2011 project [http://blogs.coreboot.org/blog/2011/05/09/gsoc-project-coreboot-panic-room-diagnostics-also-remote-flashing/] was able to:<br />
* Link flashrom with libpayload and flash from USB drive in a pre-OS environment.<br />
* Optimise flashrom memory usage to flash in pre-ram/cache-as-ram environment.<br />
* Build SerialICE boot ROM inside the coreboot tree and share some of the PnP/SuperIO source code.<br />
* Demonstrate booting alternative payload on keypress.<br />
<br />
<br />
There are remaining open tasks to:<br />
* Bring the GSoC 2011 patches up-to-date with current flashrom and libpayload trees.<br />
* Create generic solution to jump to recovery mode using input from GPIOs and/or use of power-button override.<br />
* Use SMBus/SMLink to send POST failure codes over ethernet using integrated network controllers.<br />
* After panic(), dump RAM contents before they are overwritten.<br />
<br />
<br />
'''Mentors'''<br />
* [[User:Rminnich|Ron Minnich]]<br />
<br />
== Board config infrastructure ==<br />
<br />
Design data structures that host information about the board layout so coreboot can better initialize components and generate all kinds of tables (mptable, pirq, acpi, ...) from that dynamically (at build or runtime, as appropriate). Adapt boards to use that instead of the current hardcodes.<br />
<br />
'''Links'''<br />
* ?<br />
<br />
'''Mentors'''<br />
* ?<br />
<br />
<br />
== Refactor AMD code ==<br />
<br />
AMD K8 and AMD Fam10 are different enough to have their own code. This is unfortunate, as you have to decide which CPU type you use in a given mainboard. Refactor AMD code so a single image can support both chip types on a given board. Also move tables from get_bus_conf and the like to the device tree or kconfig options (or runtime detection), as appropriate.<br />
<br />
Alternatively, figure out a way how to build them in parallel and have coreboot select the right one on runtime.<br />
<br />
'''Links'''<br />
* ?<br />
<br />
'''Mentors'''<br />
* [[User:Stepan|Stefan Reinauer]]<br />
<br />
<br />
== Tianocore as payload ==<br />
<br />
What SeaBIOS is for PC-BIOS interfaces, Tianocore is for UEFI - in fact, it's the reference implementation that most commercial UEFIs are built on. While coreboot favors other design goals than UEFI, it's really useful to support this standard that's being pushed on the market, just like SeaBIOS really helped coreboot by providing a BIOS "frontend".<br />
<br />
There's already some code, but there's still much room for improvement: A graphics driver that uses a preinitialized (by coreboot) framebuffer. A CBFS driver so Tiano can access coreboot flash storage. Based on that, a flash driver (maybe adapted from flashrom) to implement non-volatile variable storage by writing to flash.<br />
<br />
Possible tasks depend a lot on existing knowledge of the candidate. Few of the tasks are large enough to fill the entire GSoC time frame with one of them. Feel free to discuss with us on IRC what a suitable target could be for you.<br />
<br />
'''Links'''<br />
* http://www.tianocore.org/<br />
* https://github.com/pgeorgi/edk2/tree/coreboot-pkg<br />
<br />
<br />
'''Mentors'''<br />
* [[User:Stepan|Stefan Reinauer]]<br />
* [[User:PatrickGeorgi|Patrick Georgi]]</div>Kmalkkihttps://www.coreboot.org/index.php?title=GSoC&diff=11588GSoC2013-03-15T18:23:04Z<p>Kmalkki: /* People involved */</p>
<hr />
<div></div>Kmalkkihttps://www.coreboot.org/index.php?title=Board:aopen/dxplplusu&diff=11494Board:aopen/dxplplusu2013-02-12T15:33:01Z<p>Kmalkki: Created page with "== Status == {{Status| |CPU_status = OK |CPU_comments = |CPU_L1_status = OK |CPU_L1_comments = |CPU_L2_status = OK |CPU_L2_comments = |CPU_L3_status = OK |CPU_multiple_st..."</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = <br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = <br />
|CPU_L3_status = OK<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_multicore_comments =<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = OK<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = OK<br />
|RAM_ecc_comments = 2 secs scrub for 8GB.<br />
<br />
|Onboard_SCSI_status = OK<br />
|Onboard_SCSI_comments = No boot from SCSI drives.<br />
|IDE_status = OK<br />
|IDE_comments = <br />
|IDE_25_status = N/A<br />
|IDE_CF_status = <br />
|CDROM_DVD_status = OK<br />
|SATA_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = N/A<br />
|Onboard_VGA_comments = <br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = <br />
|Onboard_audio_status = untested<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = OK<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PS2_keyboard_status = Untested<br />
|PS2_mouse_status = Untested<br />
|PP_status = Untested<br />
|PP_comments =<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = ?<br />
<br />
|Sensors_status = Untested<br />
|Sensors_comments =<br />
|CPUfreq_status = N/A<br />
|CPUfreq_comments =<br />
|Powersave_status = N/A<br />
|Powersave_comments =<br />
|ACPI_status = OK<br />
|ACPI_comments = IRQ routing, not much else in ACPI.<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = N/A<br />
|Suspend_comments = <br />
|LEDs_status = N/A<br />
|HPET_status = Unknown<br />
|RNG_status = ?<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = OK<br />
|WakeOnKeyboard_status = N/A<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}</div>Kmalkkihttps://www.coreboot.org/index.php?title=Supported_Chipsets_and_Devices&diff=11491Supported Chipsets and Devices2013-02-12T13:56:23Z<p>Kmalkki: </p>
<hr />
<div>'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards.<br />
* If a device is not supported by coreboot v4, try [[Supported_Chipsets_and_Devices/v1|checking coreboot v1]] or [[Supported_Chipsets_and_Devices/v3|coreboot v3]] for support.<br />
* In general it is '''not''' recommended to use coreboot v3 &mdash; this was an experimental development tree which is gradually being merged into v4.<br />
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. However, it is definitely desirable to port boards from v1 to v4 whereever possible.<br />
<br />
See also [[Supported Motherboards]].<br />
<br />
== Devices supported in coreboot v4 ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam14h - G-Series<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam12h - Llano<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam10h<br />
| style="background:lime" | OK<sup>16</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX1<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX&nbsp;(GX2)<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| LX<br />
| style="background: lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7505<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7520<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7525<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 5000P<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82810<br />
| style="background:yellow" | WIP<sup>9</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82855<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| SCH US15W (Poulsbo)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SiS<br />
| SiS761GX<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601 (PLE133)<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623 (CLE266)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8T890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8M890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN400<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:lime" | OK<sup>14</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CX700<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VX800<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8111<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8131<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8132<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8151<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5530/CS5530A<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5535<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS780/RS785<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700/SB7x0<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SR56x0<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB5100<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB800<br />
| style="background: lime " | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM21000<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5780<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5785<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 6300ESB (ESB6300)<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801AA/AB&nbsp;(ICH/ICH0)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801BA/BAM&nbsp;(ICH2/ICH2-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA/CAM&nbsp;(ICH3-S/ICH3-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB/DBL/DBM<br/>(ICH4/ICH4-L/ICH4-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801EB/ER&nbsp;(ICH5/ICH5R)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PXHD<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| SCH US15W (Poulsbo)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| CK804<br />
| style="background:lime" | OK<sup>17</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<sup>17</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Ricoh<br />
| RL5C476<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966(L)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237A<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237S<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | OK<sup>12</sup>, <sup>13</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71859<br />
| style="background:yellow" | OK<sup>19</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71863F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71872F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71889<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F81865F<br />
| style="background:yellow" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8661F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8705F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<sup>15</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<sup>15</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC8374<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87360<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87366<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87382<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87384<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87392<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87417<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87427<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307 <br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ServerEngines<br />
| PILOT<br />
| style="background:yellow" | OK<sup>18</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M70x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B80x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B78x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B72x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B81x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M60x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B27x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M10x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M112<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M13x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M15x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M192<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B397<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| DME1737<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| SCH5307<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47N217<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686(A/B)<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627DHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627UHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627EHG/HF/EHF/THF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83697HF/HG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THF/THG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977TF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:lime" | OK<sup>4</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Emulated<br />
| QEMU<br />
| style="background:lime" | OK<br />
|}<br />
<br />
'''SOCs'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | SOC<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Elan SC520<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background: yellow" | OK<sup>20</sup><br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>4</sup> The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least).<br /><br />
<sup>5</sup> Pre-RAM serial output works fine, but nothing else, yet.<br /><br />
<sup>9</sup> Works mostly, but currently there are some limitations as to which RAM DIMMs can be used.<br /><br />
<sup>12</sup> All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though.<br /><br />
<sup>13</sup> The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737.<br /><br />
<sup>14</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
<sup>15</sup> The Intel 3100/EP80579 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far.<br /><br />
<sup>16</sup> Two implementations: Rev B-C supported in coreboot, Rev D-E support via AGESA<br /><br />
<sup>17</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br /><br />
<sup>18</sup> Partially supported, but not all features implemented.<br /><br />
<sup>19</sup> Only support for serial port 1 implemented, everything else is unsupported so far due to lack of datasheet.<br /><br />
<sup>20</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
</small><br />
<br />
__FORCETOC__</div>Kmalkki