Developer Manual
The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
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This work is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or any later version. This work is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. |
This is work in progress!
Introduction
Hardware Overview
LinuxBIOS Overview
Serial output and the Super I/O
The Super I/O is a chip found on most of today's mainboards which is — among other things — responsible for the serial ports of the mainboard (e.g. COM1, COM2). This chip usually the first thing you'll want to support, as it's required to get serial debugging output from the mainboard (via a null-modem cable and the proper software, e.g. minicom).
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Winbond W83977EF Super I/O.
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ITE IT8705F Super I/O.
Northbridge
RAM init
Resources:
- Understanding DDR Serial Presence Detect (SPD) Table
- Micron 512 MB SDRAM Datasheet (PDF) -- contains some helpful explanations