[LinuxBIOS] [PATCH] probe_superio: Cosmetics, cleanup, better structure

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Sat Sep 1 21:00:57 CEST 2007


On 31.08.2007 19:38, Robert Millan wrote:
> On Wed, Aug 29, 2007 at 06:35:23PM +0200, Carl-Daniel Hailfinger wrote:
>>> SuperI/O found at 0x2e: id=0x8712, chipver=0x7
>>> ITE IT8712
>>> switching to LDN 0x4
>>> idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6
>>> val 01 02 90 00 00 00 80 00 0a 00 80 00 ff
>>> def 00 02 90 02 30 09 00 00 00 00 00 NA NA
>> ldn 0x4, idx 0x70: interrupt level of environment controller.
>> prop: 0x00, lb 0x09. change?
>>
>>> switching to LDN 0x5
>>> idx 30 60 61 62 63 70 71 f0
>>> val 01 00 60 00 64 01 02 68
>>> def 01 00 60 00 64 01 02 00
>> ldn 0x5, idx 0xf0: keyboard special config.
>> prop: 0x68, lb 0x40.
>> prop: no irq sharing, lb: active irq sharing. change?
>> prop: kbc clock 8mhz, lb: kbc clock 12mhz. FIX!
>>
>> IF you fix the stuff mentioned above, PS/2 keyboard should work fine.
>> PCI is not affected by SuperIO config. USB keyboard can be investigated
>> later if the PS/2 fixes don't help.
> 
> Thanks for the hints.  I changed the mentioned registers to the same values
> they had with propietary BIOS, but to no avail.  Attaching a diff of my
> changes.
> 
> Any idea?  Should I go after all the other disparities?

Only those which I listed in my earlier mail plus the following list:

--- propietary  2007-09-01 20:21:24.000000000 +0200
+++ lb  2007-09-01 20:21:24.000000000 +0200
 switching to LDN 0x2 (serial port 2)
 idx 30 60 61 70
-val 00 00 00 00
+val 01 02 f8 03
prop disables com2 an clears baseaddr+irq.
FIX.

 switching to LDN 0x3
 idx f0
-val 0b
+val 03
fascinating. the board can output post codes via parallel port.
maybe?

 switching to LDN 0x4
 idx 62 63 70
-val 00 00 00
+val 02 30 09
pme direct access addr + ec interrupt level
FIX.

 switching to LDN 0x5
 idx f0
-val 68
+val 40
keyboard clock etc.
FIX.

 switching to LDN 0x7
 idx 25 27 62 b2 ba c0 c2 c8 ca cb
-val 00 05 08 01 01 00 05 00 05 00
+val 01 00 00 00 00 01 00 01 00 40
idx 25: pin 84 smart card present? maybe?
idx 27: gpio 30+32. FIX.
idx 62: simeple i/o base addr. FIX.
idx b2: gpio pin set 3: gpio invert polarity. FIX.
idx ba: gpio pin set 3: gpio pullup. FIX.
idx c0: simple i/o set 1: enable. FIX.
idx c2: simple i/o set 3: enable. FIX.
idx c8: simple i/o set 1: input mode. FIX.
idx ca: simple i/o set 3: input mode. FIX.
idx cb: simple i/o set 4: input mode. FIX.

 switching to LDN 0x8
 idx 30 61
-val 01 30
+val 00 00
ok.

 switching to LDN 0x9
 idx 30
-val 01
+val 00
ok.

You patch in the other mail looked fine. Fix the issues mentioned above
as "FIX" and post another probe_superio from a lb boot after fixes.

Regards,
Carl-Daniel




More information about the coreboot mailing list