[LinuxBIOS] [LinuxBIOSv2] WIP Support for RCA RM4100 - i82830 Complete

joe at smittys.pointclark.net joe at smittys.pointclark.net
Tue Sep 18 04:34:35 CEST 2007


Here you go Uwe,
i82830 northbridge code is done. Works great. Note: Checkout the  
generic spd_get_dimm_size()function in raminit.c, there is a pretty  
cool way to get each side of a dimm's size only using SPD 5 and 31  
(original idea from Corey, Thanks). Works for dimms up to 2GB. Works  
on SDRAM and DDR, DDR2, maybe more.

Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>
Acked-by: Joseph Smith <joe at smittys.pointclark.net>

RCA RM4100 is still having problems below with PCI to PCI Bridge  
(i82801DB Southbridge issue?). Please submit as "WIP". Note: this  
board is classified as a Set-top-box.

Signed-off-by: Joseph Smith <joe at smittys.pointclark.net>
Acked-by: Joseph Smith <joe at smittys.pointclark.net>

Thanks - Joe

Quoting Uwe Hermann <uwe at hermann-uwe.de>:

> On Mon, Sep 17, 2007 at 09:06:19AM -0400, joe at smittys.pointclark.net wrote:
>> > Well I figured out what the problem is. I have a parity error in the
>> > PD_STS?Primary Device Status Register 0x06 and can't clear the bit 15.
>> > When I try it just goes back to 0x8080. I am supposed to be able to
>> > clear this bit by writing a 1 to the bit location. Why won't it let me
>> > clear this bit?? Hugh...this is so frustrating...I am so close:-(
>> >

>> Anyone??
>
> We're not so good at guessing. Please post your code and a boot log
> captured using exactly that code so we can help you debug this.
>
>
> Uwe.


-------------- next part --------------
Index: src/mainboard/rca/rm4100/Config.lb
===================================================================
--- src/mainboard/rca/rm4100/Config.lb	(revision 0)
+++ src/mainboard/rca/rm4100/Config.lb	(revision 0)
@@ -0,0 +1,197 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+	depends "$(MAINBOARD)/failover.c ./romcc" 
+	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+	depends "$(MAINBOARD)/failover.c ./romcc"
+	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E 
+	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
+	action	"./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc 
+	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	action	"./romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds 
+	mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files 
+##
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i82830
+	device pci_domain 0 on 
+		device pci 0.0 on end # Host bridge: Intel Corporation 82830 830 Chipset Host Bridge
+		device pci 1.0 off end # Host-AGP Bridge
+		device pci 2.0 off end # VGA compatible controller: Intel Corporation 82830 CGC
+		chip southbridge/intel/i82801xx
+			device pci 1d.0 on end # USB UHCI Controller #1
+			device pci 1d.1 on end # USB UHCI Controller #2
+			device pci 1d.2 on end # USB UHCI Controller #3
+			device pci 1d.7 on end # USB2 EHCI Controller
+			device pci 1e.0 on end # PCI bridge: Intel Corporation 82801 PCI Bridge
+			device pci 1f.0 on # ISA bridge: Intel Corporation 82801DB LPC Interface SouthBridge
+				chip superio/smsc/smscsuperio 
+					device pnp 2e.0 off # Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.3 off # Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.4 on # Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.5 off # Com2 / IR
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.7 on # Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1 # Keyboard interrupt
+						irq 0x72 = 12 # Mouse interrupt
+					end
+					device pnp 2e.9 off end # Game Port
+					device pnp 2e.a off end # PME
+					device pnp 2e.b off end # MPU-401
+				end
+			end
+			device pci 1f.1 on end # IDE interface: Intel Corporation 82801DB IDE Controller
+			device pci 1f.3 on end # SMBus: Intel Corporation 82801DB SMBus Controller
+			device pci 1f.5 on end # Multimedia audio controller: AC'97 Audio Controller
+			device pci 1f.6 on end # Modem: AC'97 Modem Controller
+		end
+	end
+	chip cpu/intel/socket_PGA370
+	end
+end
+

Property changes on: src/mainboard/rca/rm4100/Config.lb
___________________________________________________________________
Name: svn:executable
   + *

Index: src/mainboard/rca/rm4100/spd_table.h
===================================================================
--- src/mainboard/rca/rm4100/spd_table.h	(revision 0)
+++ src/mainboard/rca/rm4100/spd_table.h	(revision 0)
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <spd.h>
+
+struct spd_entry {
+	unsigned int address;
+	unsigned int data;
+	};
+
+/* The onboard 128MB PC133 memory does not have a SPD eeprom so the
+ * values have to be set manually, 
+ * the onboard memory is located in socket1 (0x51).
+*/
+
+const struct spd_entry spd_table [] = 
+{
+{2,	0x04}, /* (Fundamental) memory type */
+{4,	0x09}, /* Number of column address bits */
+{6,	0x40}, /* Module data width (LSB) */
+{5,	0x01}, /* Number of module rows (banks) */
+{9,	0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
+{10,	0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
+{31,	0x20}, /* Density of each row on module */
+};

Property changes on: src/mainboard/rca/rm4100/spd_table.h
___________________________________________________________________
Name: svn:executable
   + *

Index: src/mainboard/rca/rm4100/irq_tables.c
===================================================================
--- src/mainboard/rca/rm4100/irq_tables.c	(revision 0)
+++ src/mainboard/rca/rm4100/irq_tables.c	(revision 0)
@@ -0,0 +1,42 @@
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+ * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
+ *
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,  /* u32 signature */
+	PIRQ_VERSION,    /* u16 version   */
+	32+16*12,	 /* there can be total 12 devices on the bus */
+	0x00,		 /* Where the interrupt router lies (bus) */
+	(0x1f<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	0,		 /* IRQs devoted exclusively to PCI usage */
+	0x8086,		 /* Vendor */
+	0x24cc,		 /* Device */
+	0,		 /* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x50,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x01,(0x08<<3)|0x0, {{0x68, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x1f<<3)|0x0, {{0x62, 0xdef8}, {0x61, 0xdef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x1d<<3)|0x0, {{0x60, 0xdef8}, {0x63, 0xdef8}, {0x62, 0xdef8}, {0x6b, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x00<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x01,(0x00<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0},
+		{0x01,(0x01<<3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x1, 0x0},
+		{0x01,(0x02<<3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0},
+		{0x01,(0x09<<3)|0x0, {{0x63, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x01,(0x06<<3)|0x0, {{0x61, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x01,(0x07<<3)|0x0, {{0x63, 0xdef8}, {0x62, 0xdef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x02<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
\ No newline at end of file

Property changes on: src/mainboard/rca/rm4100/irq_tables.c
___________________________________________________________________
Name: svn:executable
   + *

Index: src/mainboard/rca/rm4100/debug.c
===================================================================
--- src/mainboard/rca/rm4100/debug.c	(revision 0)
+++ src/mainboard/rca/rm4100/debug.c	(revision 0)
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void dump_spd_registers(const struct mem_controller *ctrl)
+{
+	int i;
+	print_debug("\r\n");
+	for(i = 0; i < 4; i++) {
+		unsigned device;
+		device = ctrl->channel0[i];
+		if (device) {
+			int j;
+			print_debug("dimm: "); 
+			print_debug_hex8(i); 
+			print_debug(".0: ");
+			print_debug_hex8(device);
+			for(j = 0; j < 256; j++) {
+				int status;
+				unsigned char byte;
+				if ((j & 0xf) == 0) {
+					print_debug("\r\n");
+					print_debug_hex8(j);
+					print_debug(": ");
+				}
+				status = smbus_read_byte(device, j);
+				if (status < 0) {
+					print_debug("bad device\r\n");
+					break;
+				}
+				byte = status & 0xff;
+				print_debug_hex8(byte);
+				print_debug_char(' ');
+			}
+			print_debug("\r\n");
+		}
+	}
+}
+
+static void dump_smbus_registers(void)
+{
+	unsigned device;
+        print_debug("\r\n");
+        for(device = 1; device < 0x80; device++) {
+                int j;
+		if( smbus_read_byte(device, 0) < 0 ) continue;
+                print_debug("smbus: ");
+                print_debug_hex8(device);
+
+                for(j = 0; j < 256; j++) {
+                	int status; 
+                        unsigned char byte;
+                        status = smbus_read_byte(device, j);
+                        if (status < 0) {
+				break;
+                        }
+                        if ((j & 0xf) == 0) {
+                	        print_debug("\r\n");
+                                print_debug_hex8(j);
+                                print_debug(": ");
+                        }
+                        byte = status & 0xff;
+                        print_debug_hex8(byte);
+                        print_debug_char(' ');
+                }
+                print_debug("\r\n");
+	}	
+}
+
+static void probe_spd_rom(void)
+{
+	int i, status;
+	print_debug("\r\n");
+	for(i = 0; i < 256; i++) {
+		status = smbus_read_byte(i, 0);
+		if (status >= 0) {
+			print_debug("SPD located at 0x");
+			print_debug_hex8(i);
+			print_debug("\r\n");
+		}
+	}
+	if (i >= 255) print_debug("No SPD Rom found");
+}
+
+static void print_debug_pci_dev(unsigned dev)
+{
+	print_debug("PCI: ");
+	print_debug_hex8((dev >> 16) & 0xff);
+	print_debug_char(':');
+	print_debug_hex8((dev >> 11) & 0x1f);
+	print_debug_char('.');
+	print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0); 
+		dev <= PCI_DEV(0, 0x1f, 0x7); 
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		print_debug_pci_dev(dev);
+		print_debug("\r\n");
+	}
+}
+
+static void dump_pci_device(unsigned dev)
+{
+	int i;
+	print_debug_pci_dev(dev);
+	print_debug("\r\n");
+	
+	for(i = 0; i <= 255; i++) {
+		unsigned char val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = pci_read_config8(dev, i);
+		print_debug_char(' ');
+		print_debug_hex8(val);
+		if ((i & 0x0f) == 0x0f) {
+			print_debug("\r\n");
+		}
+	}
+}
+
+static void dump_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0); 
+		dev <= PCI_DEV(0, 0x1f, 0x7); 
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		dump_pci_device(dev);
+	}
+}
+
+static void dump_mem(unsigned start, unsigned end)
+{
+        unsigned i;
+	print_debug("dump_mem:");
+        for(i=start;i<end;i++) {
+		if((i & 0xf)==0) {	
+			print_debug("\r\n");
+			print_debug_hex32(i);
+			print_debug(":");
+		}
+		print_debug(" ");
+		print_debug_hex8((unsigned char)*((unsigned char *)i));
+        }
+        print_debug("\r\n");
+ }
+

Property changes on: src/mainboard/rca/rm4100/debug.c
___________________________________________________________________
Name: svn:executable
   + *

Index: src/mainboard/rca/rm4100/Options.lb
===================================================================
--- src/mainboard/rca/rm4100/Options.lb	(revision 0)
+++ src/mainboard/rca/rm4100/Options.lb	(revision 0)
@@ -0,0 +1,190 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses HAVE_OPTION_TABLE
+uses USE_OPTION_TABLE
+uses CONFIG_ROM_PAYLOAD
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses HAVE_MP_TABLE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses CONFIG_UDELAY_TSC
+uses CONFIG_IDE
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses DEBUG
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE  = 524288
+
+###
+### Build options
+###
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT = 1
+
+##
+## no MP table
+##
+default HAVE_MP_TABLE = 0
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET = 0
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE = 1
+default IRQ_SLOT_COUNT = 12
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE = 0
+
+## IDE Support
+default CONFIG_IDE = 1
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 131072
+default FALLBACK_SIZE = 196608
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE = 0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE = 0x4000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = 0
+
+default _RAMBASE = 0x00004000
+
+default CONFIG_ROM_PAYLOAD = 1
+
+##
+## The default compiler
+##
+default CROSS_COMPILE = ""
+default CC = "$(CROSS_COMPILE)gcc -m32"
+default HOSTCC = "gcc"
+
+##
+## VGA Console
+## NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS
+##	    to VGA.rom
+default CONFIG_CONSOLE_VGA = 0
+default CONFIG_PCI_ROM_RUN = 0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250 = 1
+
+## Select the serial console baud rate
+default TTYS0_BAUD = 115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE = 0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS = 0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable               
+## ALERT      2   action must be taken immediately 
+## CRIT       3   critical conditions              
+## ERR        4   error conditions                 
+## WARNING    5   warning conditions               
+## NOTICE     6   normal but significant condition 
+## INFO       7   informational                    
+## DEBUG      8   debug-level messages             
+## SPEW       9   Way too many details             
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL = 9
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL = 9
+
+default DEBUG = 0
+
+default CONFIG_UDELAY_TSC = 1
+end
+

Property changes on: src/mainboard/rca/rm4100/Options.lb
___________________________________________________________________
Name: svn:executable
   + *

Index: src/mainboard/rca/rm4100/failover.c
===================================================================
--- src/mainboard/rca/rm4100/failover.c	(revision 0)
+++ src/mainboard/rca/rm4100/failover.c	(revision 0)
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include "arch/romcc_io.h"
+#include "pc80/mc146818rtc_early.c"
+
+static unsigned long main(unsigned long bist)
+{
+	/* This is the primary cpu how should I boot? */
+	if (do_normal_boot()) {
+		goto normal_image;
+	}
+	else {
+		goto fallback_image;
+	}
+ normal_image:
+	asm volatile ("jmp __normal_image" 
+		: /* outputs */ 
+		: "a" (bist) /* inputs */
+		: /* clobbers */
+		);
+ cpu_reset:
+	asm volatile ("jmp __cpu_reset"
+		: /* outputs */ 
+		: "a"(bist) /* inputs */
+		: /* clobbers */
+		);
+ fallback_image:
+	return bist;
+}

Property changes on: src/mainboard/rca/rm4100/failover.c
___________________________________________________________________
Name: svn:executable
   + *

Index: src/mainboard/rca/rm4100/chip.h
===================================================================
--- src/mainboard/rca/rm4100/chip.h	(revision 0)
+++ src/mainboard/rca/rm4100/chip.h	(revision 0)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_rca_rm4100_ops;
+
+struct mainboard_rca_rm4100_config {
+	int nothing;
+};

Property changes on: src/mainboard/rca/rm4100/chip.h
___________________________________________________________________
Name: svn:executable
   + *

Index: src/mainboard/rca/rm4100/auto.c
===================================================================
--- src/mainboard/rca/rm4100/auto.c	(revision 0)
+++ src/mainboard/rca/rm4100/auto.c	(revision 0)
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "northbridge/intel/i82830/raminit.h"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "spd_table.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
+#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
+
+/* The onboard 128MB PC133 memory does not have a SPD eeprom so the
+ * values have to be set manually, 
+ * the onboard memory is located in socket1 (0x51).
+*/
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	int i;
+
+	if (device == 0x50){
+		return smbus_read_byte(device, address);
+	} else if (device == 0x51){
+		for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){
+			if (spd_table[i].address == address){
+				return spd_table[i].data;
+			}
+		}
+		return 0xFF; /* This line returns 0xFF when address not found */
+	} else {
+		return 0xFF; /* returns 0xFF on any failures */
+	}
+}
+
+static void ac97_io_enable(void)
+{
+	device_t dev;
+
+	/* Set the ac97 audio device staticly. */
+	dev = PCI_DEV(0x0, 0x1f, 0x5);
+
+	/* Enable access to the IO space. */
+	pci_write_config8(dev, 0x41, 0x01);
+}
+
+/* TODO: Not needed? */
+void udelay(int usecs) 
+{
+	int i;
+	for (i = 0; i < usecs; i++)
+		outb(i&0xff, 0x80);
+}
+
+#include "debug.c"
+#include "lib/delay.c"
+
+#include "northbridge/intel/i82830/raminit.c"
+#include "sdram/generic_sdram.c"
+
+static void main(unsigned long bist)
+{
+	static const struct mem_controller memctrl[] = {
+		{
+		 .d0 = PCI_DEV(0, 0, 0),
+		 .channel0 = {0x50, 0x51},
+		 }
+	};
+
+	if (bist == 0)
+		early_mtrr_init();
+
+	enable_smbus();
+
+	smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	uart_init();
+	console_init();
+
+	/* Halt if there was a built in self test failure. */
+	report_bist_failure(bist);
+
+	/* dump_spd_registers(&memctrl[0]); */
+	/* dump_smbus_registers(); */
+	/* probe_spd_rom(); */
+
+	/* sdram_initialize() runs out of registers. */
+	/* sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); */
+
+	sdram_set_registers(memctrl);
+	sdram_set_spd_registers(memctrl);
+	sdram_enable(0, memctrl);
+
+	/* print_pci_devices(); */
+	/* dump_pci_devices(); */
+
+	/* Check RAM. */
+	/* ram_check(0, 640 * 1024); */
+
+	ac97_io_enable();
+}

Property changes on: src/mainboard/rca/rm4100/auto.c
___________________________________________________________________
Name: svn:executable
   + *

Index: src/mainboard/rca/rm4100/cmos.layout
===================================================================
--- src/mainboard/rca/rm4100/cmos.layout	(revision 0)
+++ src/mainboard/rca/rm4100/cmos.layout	(revision 0)
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+

Property changes on: src/mainboard/rca/rm4100/cmos.layout
___________________________________________________________________
Name: svn:executable
   + *

Index: src/mainboard/rca/rm4100/mainboard.c
===================================================================
--- src/mainboard/rca/rm4100/mainboard.c	(revision 0)
+++ src/mainboard/rca/rm4100/mainboard.c	(revision 0)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_rca_rm4100_ops = {
+	CHIP_NAME("RCA RM4100 Mainboard")
+};

Property changes on: src/mainboard/rca/rm4100/mainboard.c
___________________________________________________________________
Name: svn:executable
   + *

Index: src/northbridge/intel/i82830/Config.lb
===================================================================
--- src/northbridge/intel/i82830/Config.lb	(revision 0)
+++ src/northbridge/intel/i82830/Config.lb	(revision 0)
@@ -0,0 +1,22 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config chip.h
+object northbridge.o

Property changes on: src/northbridge/intel/i82830/Config.lb
___________________________________________________________________
Name: svn:executable
   + *

Index: src/northbridge/intel/i82830/i82830.h
===================================================================
--- src/northbridge/intel/i82830/i82830.h	(revision 0)
+++ src/northbridge/intel/i82830/i82830.h	(revision 0)
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define VID 0X00     /* Vendor Identification Register - Default Value 0X8086 - 16 bits Read Only */
+#define DID 0X02     /* Device Identification Register - Default Value 0X3575 - 16 bits Read Only */
+#define RID 0X08     /* Revision Identification Register - Default Value 0X04 - 8 bits Read Only */
+#define SUBC 0X0A     /* SUB-Class Code Register - Default Value 0X00 - 8 bits Read Only */
+#define BCC 0X0B     /* Base Class Code Register - Default Value 0X06 - 8 bits Read Only */
+#define MLT 0X0D     /* Master Latency Timer Register - Default Value 0X00 - 8 bits Read Only */
+#define HDR 0X0E     /* Header Type Register - Default Value 0X00 - 8 bits Read Only */
+#define CAPPTR 0X34     /* Capablities Pointer - Default Value 0X40 - 8 bits Read Only */
+
+#define PCICMD0 0X04  /* PCI Command Register - Default Value 0X0006 - 16 bits */
+#define PCISTS 0X06  /* PCI Status Register - Default Value 0X0010 - 16 bits */
+
+#define SVID 0X2C    /* Subsystem Vendor ID - Default Value 0X0000 - 16 bits */
+#define SID 0X2E    /* Subsystem ID - Default Value 0X0000 - 16 bits */
+
+#define RRBAR 0X48    /* Register Range Base Address Register - Default Value 0X00000000 - 32 bits */
+#define GCC0 0X50    /* GMCH Control Register #0 - Default Value 0XA072 - 16 bits */
+#define GCC1 0X52    /* GMCH Control Register #1 - Default Value 0X0000 - 16 bits */
+#define FDHC 0X58    /* Fixed DRAM Hole Control Register - Default Value 0X00 - 8 bits */
+#define PAM0 0X59     /* Programable Attribute Map Register #0 - Default Value 0X00 - 8 bits */
+#define PAM1 0X5A     /* Programable Attribute Map Register #1 - Default Value 0X00 - 8 bits */
+#define PAM2 0X5B     /* Programable Attribute Map Register #2 - Default Value 0X00 - 8 bits */
+#define PAM3 0X5C     /* Programable Attribute Map Register #3 - Default Value 0X00 - 8 bits */
+#define PAM4 0X5D     /* Programable Attribute Map Register #4 - Default Value 0X00 - 8 bits */
+#define PAM5 0X5E     /* Programable Attribute Map Register #5 - Default Value 0X00 - 8 bits */
+#define PAM6 0X5F     /* Programable Attribute Map Register #6 - Default Value 0X00 - 8 bits */
+#define DRB 0X60     /* DRAM Row Boundary Register #0 - Default Value 0X00 - 8 bits */
+#define DRB1 0X61     /* DRAM Row Boundary Register #1 - Default Value 0X00 - 8 bits */
+#define DRB2 0X62     /* DRAM Row Boundary Register #2 - Default Value 0X00 - 8 bits */
+#define DRB3 0X63     /* DRAM Row Boundary Register #3 - Default Value 0X00 - 8 bits */
+#define DRA 0X70     /* DRAM Row Attribute Register #0 - Default Value 0XFF - 8 bits */
+#define DRA1 0X71     /* DRAM Row Attribute Register #1 - Default Value 0XFF - 8 bits */
+#define DRT	0X78     /* DRAM Timing Register - Default Value 0X00000010 - 32 bits */
+#define DRC  0X7C     /* DRAM Controller Mode Register #0 - Default Value 0X00000000 - 32 bits */
+#define DRC1 0X7D     /* DRAM Controller Mode Register #1 - Default Value 0X00000000 - 32 bits */
+#define DRC2 0X7E     /* DRAM Controller Mode Register #2 - Default Value 0X00000000 - 32 bits */
+#define DRC3 0X7F     /* DRAM Controller Mode Register #3 - Default Value 0X00000000 - 32 bits */
+#define DTC	0X8C     /* DRAM Throttling Control Register - Default Value 0X00000000 - 32 bits */
+#define SMRAM 0X90   /* System Management RAM Control Register - Default Value 0X02 - 8 bits */
+#define ESMRAMC 0X91 /* Extended System Management RAM Control Register - Default Value 0X38 - 8 bits */
+
+#define ERRSTS 0X92    /* Error Status Register - Default Value 0X0000 - 16 bits */
+#define ERRCMD 0X94    /* Error Command Register - Default Value 0X0000 - 16 bits */
+
+#define BUFF_SC 0XEC     /* System Memory Buffer Strength Control Register - Default Value 0X00000000 - 32 bits */
+
+#define APBASE 0X10    /* Aperture Base Configuration Register - Default Value 0X00000008 - 32 bits */
+#define APSIZE 0XB4     /* Apterture Size - Default Value 0X00 - 8 bits */
+#define ATTBASE 0XB8     /* Aperture Translation Table Base Register - Default Value 0X00000000 - 32 bits */
+
+
+

Property changes on: src/northbridge/intel/i82830/i82830.h
___________________________________________________________________
Name: svn:executable
   + *

Index: src/northbridge/intel/i82830/raminit.c
===================================================================
--- src/northbridge/intel/i82830/raminit.c	(revision 0)
+++ src/northbridge/intel/i82830/raminit.c	(revision 0)
@@ -0,0 +1,489 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <spd.h>
+#include <sdram_mode.h>
+#include <delay.h>
+#include "i82830.h"
+
+/*-----------------------------------------------------------------------------
+Macros and definitions.
+-----------------------------------------------------------------------------*/
+
+/* Uncomment this to enable debugging output. */
+/* #define DEBUG_RAM_SETUP 1 */
+
+/* Debugging macros. */
+#if defined(DEBUG_RAM_SETUP)
+#define PRINT_DEBUG(x)		print_debug(x)
+#define PRINT_DEBUG_HEX8(x)	print_debug_hex8(x)
+#define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
+#define PRINT_DEBUG_HEX32(x)	print_debug_hex32(x)
+#define DUMPNORTH()		dump_pci_device(PCI_DEV(0, 0, 0))
+#else
+#define PRINT_DEBUG(x)
+#define PRINT_DEBUG_HEX8(x)
+#define PRINT_DEBUG_HEX16(x)
+#define PRINT_DEBUG_HEX32(x)
+#define DUMPNORTH()
+#endif
+
+/* DRC[10:8] - Refresh Mode Select (RMS).
+ * 0x0 for Self Refresh
+ * 0x1 for Refresh interval 15.6 us for 133MHz
+ * 0x2 for Refresh interval 7.8 us for 133MHz
+ * 0x7 /* Refresh interval 128 Clocks. (Fast Refresh Mode)
+ */
+#define RAM_COMMAND_REFRESH    0x1
+
+/* DRC[6:4] - SDRAM Mode Select (SMS). */
+#define RAM_COMMAND_NOP		 0x1
+#define RAM_COMMAND_PRECHARGE	 0x2
+#define RAM_COMMAND_MRS		 0x3
+#define RAM_COMMAND_CBR		 0x6
+#define RAM_COMMAND_NORMAL	 0x7
+
+/*-----------------------------------------------------------------------------
+SDRAM configuration functions.
+-----------------------------------------------------------------------------*/
+
+/**
+ * Send the specified RAM command to all DIMMs.
+ *
+ * @param Memory controller
+ * @param TODO
+ * @param TODO
+ */
+static void do_ram_command(const struct mem_controller *ctrl, uint32_t command, uint32_t addr_offset)
+{
+	uint8_t reg;
+
+	/* Configure the RAM command. */
+	reg = pci_read_config32(ctrl->d0, DRC);
+	/* Clear bits 29, 10-8, 6-4. */
+	reg &= 0xdffff88f;
+	reg |= command << 4;
+      /* If RAM_COMMAND_NORMAL set the refresh mode and IC bit. */
+	if (command == RAM_COMMAND_NORMAL) {
+	reg |= ((RAM_COMMAND_REFRESH << 8) | (1 << 29));
+      }
+	pci_write_config32(ctrl->d0, DRC, reg);
+
+	PRINT_DEBUG("    Sending RAM command 0x");
+	PRINT_DEBUG_HEX32(reg);
+	PRINT_DEBUG(" to 0x");
+	PRINT_DEBUG_HEX32(0 + addr_offset);
+	PRINT_DEBUG("\r\n");
+
+	/* Read from (DIMM start address + addr_offset).
+	 * First offset is always 0.
+	 */
+	read32(0 + addr_offset);
+}
+
+/*-----------------------------------------------------------------------------
+DIMM-independant configuration functions.
+-----------------------------------------------------------------------------*/
+
+struct dimm_size {
+	unsigned long side1;
+	unsigned long side2;
+};
+
+static struct dimm_size spd_get_dimm_size(unsigned device)
+{
+	struct dimm_size sz;
+	int i, module_density, dimm_banks;
+	sz.side1 = 0;
+	module_density = spd_read_byte(device, 31);
+	dimm_banks = spd_read_byte(device, 5);
+
+	/* Find the size of side1 */
+	/* Find the larger value. The larger value is always side1 */	
+	for (i = 512; i >= 0; i >>= 1) {
+		if ((module_density & i) == i) {
+			sz.side1 = i;
+			break;
+		}
+	}
+
+	/* Set to 0 in case it's single sided */
+	sz.side2 = 0;
+
+	/* Test if it's a dual-sided dimm */
+	if (dimm_banks > 1) {
+
+		/* Test to see if there's a second value, if so it's asymmetrical */
+		if (module_density != i) {
+
+		/* Find the second value, picking up where we left off */
+		/* i >>= 1 done initially to make sure we don't get the same value again */
+			for (i >>= 1; i >= 0; i >>= 1) {
+				if (module_density == (sz.side1 | i)) {
+					sz.side2 = i;
+					break;
+				}
+			}
+
+		/* If not, it's symmetrical */
+		} else {
+		sz.side2 = sz.side1;
+		}
+	}
+	/* SPD byte 31 is the memory size divided by 4 so we
+	 * need to muliply by 4 to get the total size.
+	 */
+	sz.side1 <<= 2;
+	sz.side2 <<= 2;
+	return sz;
+}
+
+static void spd_set_dram_size(const struct mem_controller *ctrl)
+{
+	int i, value, drb1, drb2;
+
+	for (i = 0; i < DIMM_SOCKETS; i++) {
+		struct dimm_size sz;
+		unsigned device;
+		device = ctrl->channel0[i];
+		drb1 = 0;
+		drb2 = 0;
+
+		/* First check if a DIMM is actually present. */
+		if (spd_read_byte(device, 2) == 0x4) {
+			print_debug("Found DIMM in slot ");
+			print_debug_hex8(i);
+			print_debug("\r\n");
+
+			sz = spd_get_dimm_size(device);
+
+			/* WISHLIST: would be nice to display it as decimal? */
+			print_debug("DIMM is 0x");
+			print_debug_hex16(sz.side1);
+			print_debug(" on side 1\r\n");
+			print_debug("DIMM is 0x");
+			print_debug_hex16(sz.side2);
+			print_debug(" on side 2\r\n");
+
+			/* Test for PC133 (i82830 only supports PC133) */
+			/* PC133 SPD9 - cycle time is always 75 */
+			if (spd_read_byte(device, 9) != 0x75) {
+				print_err("SPD9 DIMM Is Not PC133 Compatable\r\n");
+				die("HALT\r\n");
+			}
+			/* PC133 SPD10 - access time is always 54 */
+			if (spd_read_byte(device, 10) != 0x54) {
+				print_err("SPD10 DIMM Is Not PC133 Compatable\r\n");
+				die("HALT\r\n");
+			}
+
+			/* The i82830 can't handle DIMMs smaller than 32MB per
+			 * side or larger than 256MB per side. It also can
+			 * only support a symmetrical dual-sided dimm.
+			 */
+			if ((sz.side1 < 32)) {
+				print_err("DIMMs smaller than 32MB per side\r\n");
+				print_err("are not supported on this board\r\n");
+				die("HALT\r\n");
+			}
+
+			if ((sz.side2 != 0) && (sz.side2 < 32)) {
+				print_err("DIMMs smaller than 32MB per side\r\n");
+				print_err("are not supported on this board\r\n");
+				die("HALT\r\n");
+			}
+
+			if ((sz.side1 > 256) || (sz.side2 > 256)) {
+				print_err("DIMMs larger than 256MB per side\r\n");
+				print_err("are not supported on this board\r\n");
+				die("HALT\r\n");
+			}
+
+			if ((sz.side2 != 0) && (sz.side1 != sz.side2)) {
+				print_err("This board only supports\r\n");
+				print_err("symmetrical dual-sided DIMMs\r\n");
+				die("HALT\r\n");
+			}
+
+			/* We need to divide size by 32 to set up the
+			 * DRB registers.
+			*/
+			if (sz.side1 > 0) {
+				drb1 = sz.side1 >> 5;
+			}
+			if (sz.side2 > 0) {
+				drb2 = sz.side2 >> 5;
+			}
+		} else {
+			PRINT_DEBUG("No DIMM found in slot ");
+			PRINT_DEBUG_HEX8(i);
+			PRINT_DEBUG("\r\n");
+
+			/* If there's no DIMM in the slot, set value to 0. */
+			drb1 = 0;
+			drb2 = 0;
+		}
+      	/* Set the value for DRAM Row Boundary Registers */
+		if (i == 0) {
+			pci_write_config8(ctrl->d0, DRB, drb1);
+			pci_write_config8(ctrl->d0, DRB + 1, drb1 + drb2);
+			PRINT_DEBUG("DRB 0x");
+			PRINT_DEBUG_HEX8(DRB);
+			PRINT_DEBUG(" has been set to 0x");
+			PRINT_DEBUG_HEX8(drb1);
+			PRINT_DEBUG("\r\n");
+			PRINT_DEBUG("DRB1 0x");
+			PRINT_DEBUG_HEX8(DRB + 1);
+			PRINT_DEBUG(" has been set to 0x");
+			PRINT_DEBUG_HEX8(drb1 + drb2);
+			PRINT_DEBUG("\r\n");
+		} else if (i == 1) {
+			value = pci_read_config8(ctrl->d0, DRB + 1);
+			pci_write_config8(ctrl->d0, DRB + 2, value + drb1);
+			pci_write_config8(ctrl->d0, DRB + 3, value + drb1 + drb2);
+			PRINT_DEBUG("DRB2 0x");
+			PRINT_DEBUG_HEX8(DRB + 2);
+			PRINT_DEBUG(" has been set to 0x");
+			PRINT_DEBUG_HEX8(value + drb1);
+			PRINT_DEBUG("\r\n");
+			PRINT_DEBUG("DRB3 0x");
+			PRINT_DEBUG_HEX8(DRB + 3);
+			PRINT_DEBUG(" has been set to 0x");
+			PRINT_DEBUG_HEX8(value + drb1 + drb2);
+			PRINT_DEBUG("\r\n");
+		}
+	}
+}
+
+static void set_dram_row_attributes(const struct mem_controller *ctrl)
+{
+	int i, dra, col, width, value;
+
+	for (i = 0; i < DIMM_SOCKETS; i++) {
+		unsigned device;
+		device = ctrl->channel0[i];
+
+		/* First check if a DIMM is actually present. */
+		if (spd_read_byte(device, 2) == 0x4) {
+			print_debug("Found DIMM in slot ");
+			print_debug_hex8(i);
+			print_debug(", setting DRA...\r\n");
+
+			dra = 0x00;
+
+			/* columns */
+			col = spd_read_byte(device, 4);
+
+			/* data width */
+			width = spd_read_byte(device, 6);
+
+			/* calculate page size in bits */
+			value = ((1 << col) * width);
+
+			/* convert to Kilobytes */
+			dra = ((value / 8) >> 10);
+
+			/* # of banks of DIMM (single or double sided) */
+			value = spd_read_byte(device, 5);
+
+			if (value == 1) {
+				/* 2KB */
+				if (dra == 0x2) {
+					dra = 0xF0;
+				/* 4KB */
+				} else if (dra == 0x4) {
+					dra = 0xF1;
+				/* 8KB */
+				} else if (dra == 0x8) {
+					dra = 0xF2;
+				/* 16KB */
+				} else if (dra == 0x10) {
+					dra = 0xF3;
+				} else {
+					print_err("Page size not supported\r\n");
+					die("HALT\r\n");
+				}
+			} else if (value == 2) {
+				/* 2KB */
+				if (dra == 0x2) {
+					dra = 0x00;
+				/* 4KB */
+				} else if (dra == 0x4) {
+					dra = 0x11;
+				/* 8KB */
+				} else if (dra == 0x8) {
+					dra = 0x22;
+				/* 16KB */
+				} else if (dra == 0x10) {
+					dra = 0x33;
+				} else {
+					print_err("Page size not supported\r\n");
+					die("HALT\r\n");
+				}
+			}else {
+				print_err("# of banks of DIMM not supported\r\n");
+				die("HALT\r\n");
+			}
+
+		} else {
+			PRINT_DEBUG("No DIMM found in slot ");
+			PRINT_DEBUG_HEX8(i);
+			PRINT_DEBUG(", setting DRA to 0xFF\r\n");
+
+			/* If there's no DIMM in the slot, set dra value to 0xFF. */
+			dra = 0xFF;
+		}
+
+		/* Set the value for DRAM Row Attribute Registers */
+      	pci_write_config8(ctrl->d0, DRA + i, dra);
+		PRINT_DEBUG("DRA 0x");
+		PRINT_DEBUG_HEX8(DRA + i);
+		PRINT_DEBUG(" has been set to 0x");
+		PRINT_DEBUG_HEX8(dra);
+		PRINT_DEBUG("\r\n");
+	}
+}
+
+static void set_dram_timing(const struct mem_controller *ctrl)
+{
+	/* Set the value for DRAM Timing Register */
+	pci_write_config32(ctrl->d0, DRT, 0x00000010);
+}
+
+static void set_dram_buffer_strength(const struct mem_controller *ctrl)
+{
+	/* TODO: This needs to be set according to the DRAM tech
+	 * (x8, x16, or x32). Argh, Intel provides no docs on this!
+	 * Currently, it needs to be pulled from the output of
+	 * lspci -xxx Rx92
+	*/
+
+	/* Set the value for System Memory Buffer Strength Control Registers */
+	pci_write_config32(ctrl->d0, BUFF_SC, 0xFC9FC909);
+}
+
+/*-----------------------------------------------------------------------------
+Public interface.
+-----------------------------------------------------------------------------*/
+
+static void sdram_set_registers(const struct mem_controller *ctrl)
+{
+	unsigned value;
+	value = 0;
+
+	PRINT_DEBUG("Setting initial registers....\r\n");
+
+	/* Set the value for PCI Command Register */
+	pci_write_config16(ctrl->d0, PCICMD0, 0x0006);
+
+	/* Set the value for PCI Status Register */
+	pci_write_config16(ctrl->d0, PCISTS, 0x0010);
+
+      /* Set the value for GMCH Control Register #0 */
+      pci_write_config16(ctrl->d0, GCC0, 0xA072);
+
+	/* Set the value for GMCH Control Register #1
+	 * Only set bits 6-0, bits 15-7 are reserved.
+	 */
+	value = pci_read_config16(ctrl->d0, GCC1);
+	value |= 0x20;
+	pci_write_config16(ctrl->d0, GCC1, value);
+
+	/* Set the value for Fixed DRAM Hole Control Register */
+	pci_write_config8(ctrl->d0, FDHC, 0x00);
+
+	/* Set the value for Aperture Base Configuration Register  */
+	pci_write_config32(ctrl->d0, APBASE, 0x00000008);
+
+	/* Set the value for Register Range Base Address Register */
+	pci_write_config32(ctrl->d0, RRBAR, 0x00000000);
+
+	/* Set the value for Programable Attribute Map Registers
+	 * Ideally, this should be R/W for as many ranges as possible.
+	 */
+	pci_write_config8(ctrl->d0, PAM0, 0x30);
+	pci_write_config8(ctrl->d0, PAM1, 0x33);
+	pci_write_config8(ctrl->d0, PAM2, 0x33);
+	pci_write_config8(ctrl->d0, PAM3, 0x33);
+	pci_write_config8(ctrl->d0, PAM4, 0x33);
+	pci_write_config8(ctrl->d0, PAM5, 0x33);
+	pci_write_config8(ctrl->d0, PAM6, 0x33);
+
+	/* Set the value for DRAM Throttling Control Register */
+	pci_write_config32(ctrl->d0, DTC, 0x00000000);
+
+	/* Set the value for System Management RAM Control Register */
+	pci_write_config8(ctrl->d0, SMRAM, 0x02);
+
+	/* Set the value for Extended System Management RAM Control Register */
+	pci_write_config8(ctrl->d0, ESMRAMC, 0x38);
+
+	PRINT_DEBUG("Initial registers have been set.\r\n");
+}
+
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+{
+	spd_set_dram_size(ctrl);
+
+	set_dram_row_attributes(ctrl);
+
+	set_dram_timing(ctrl);
+
+	set_dram_buffer_strength(ctrl);
+}
+
+static void sdram_enable(int controllers, const struct mem_controller *ctrl)
+{
+	int i;
+
+	/* 0. Wait until power/voltages and clocks are stable (200us). */
+	udelay(200);
+
+	/* 1. Apply NOP. */
+	PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+	do_ram_command(ctrl, RAM_COMMAND_NOP, 0);
+	udelay(200);
+
+	/* 2. Precharge all. Wait tRP. */
+	PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+	do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
+	udelay(1);
+
+	/* 3. Perform 8 refresh cycles. Wait tRC each time. */
+	PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+	do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
+	for (i = 0; i < 8; i++) {
+		read32(0);
+		udelay(1);
+	}
+
+	/* 4. Mode register set. Wait two memory cycles. */
+	PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+	do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0);
+	udelay(2);
+
+	/* 5. Normal operation (enables refresh) */
+	PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+	do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
+	udelay(1);
+
+	PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+	DUMPNORTH();
+}

Property changes on: src/northbridge/intel/i82830/raminit.c
___________________________________________________________________
Name: svn:executable
   + *

Index: src/northbridge/intel/i82830/northbridge.c
===================================================================
--- src/northbridge/intel/i82830/northbridge.c	(revision 0)
+++ src/northbridge/intel/i82830/northbridge.c	(revision 0)
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include "chip.h"
+#include "northbridge.h"
+#include "i82830.h"
+
+static void northbridge_init(device_t dev)
+{
+	printk_spew("Northbridge init\n");
+}
+
+static struct device_operations northbridge_operations = {
+	.read_resources	= pci_dev_read_resources,
+	.set_resources	= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= northbridge_init,
+	.enable		= 0,
+	.ops_pci		= 0,
+};
+
+static struct pci_driver northbridge_driver __pci_driver = {
+	.ops	= &northbridge_operations,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x3575,
+};
+
+#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
+
+static void pci_domain_read_resources(device_t dev)
+{
+	struct resource *resource;
+
+	/* Initialize the system wide io space constraints */
+	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	resource->limit = 0xffffUL;
+	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+	/* Initialize the system wide memory resources constraints */
+	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	resource->limit = 0xffffffffULL;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+}
+
+static void ram_resource(device_t dev, unsigned long index,
+			 unsigned long basek, unsigned long sizek)
+{
+	struct resource *resource;
+
+	if (!sizek) {
+		return;
+	}
+	resource = new_resource(dev, index);
+	resource->base = ((resource_t) basek) << 10;
+	resource->size = ((resource_t) sizek) << 10;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void tolm_test(void *gp, struct device *dev, struct resource *new)
+{
+	struct resource **best_p = gp;
+	struct resource *best;
+	best = *best_p;
+	if (!best || (best->base > new->base)) {
+		best = new;
+	}
+	*best_p = best;
+}
+
+static uint32_t find_pci_tolm(struct bus *bus)
+{
+	struct resource *min;
+	uint32_t tolm;
+	min = 0;
+	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+	tolm = 0xffffffffUL;
+	if (min && tolm > min->base) {
+		tolm = min->base;
+	}
+	return tolm;
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+	device_t mc_dev;
+        uint32_t pci_tolm;
+
+        pci_tolm = find_pci_tolm(&dev->link[0]);
+	mc_dev = dev->link[0].children;
+	if (mc_dev) {
+		/* Figure out which areas are/should be occupied by RAM.
+		 * This is all computed in kilobytes and converted to/from
+		 * the memory controller right at the edges.
+		 * Having different variables in different units is
+		 * too confusing to get right.  Kilobytes are good up to
+		 * 4 Terabytes of RAM...
+		 */
+
+		unsigned long tomk, tolmk;
+		int idx;
+
+		/* Get the value of the highest DRB. This tells the end of
+		 * the physical memory.  The units are ticks of 32MB
+		 * i.e. 1 means 32MB.
+		 */
+		tomk = ((unsigned long)pci_read_config8(mc_dev, DRB+3)) << 15;
+
+		printk_debug("Setting RAM size to %d\n", tomk);
+
+		/* Compute the top of Low memory */
+		tolmk = pci_tolm >> 10;
+		if (tolmk >= tomk) {
+			/* The PCI hole does does not overlap the memory.
+			 */
+			tolmk = tomk;
+		}
+
+		/* Report the memory regions */
+		idx = 10;
+		ram_resource(dev, idx++, 0, 640);
+		ram_resource(dev, idx++, 1024, tolmk - 1024);
+	}
+	assign_resources(&dev->link[0]);
+}
+
+static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+	return max;
+}
+
+static struct device_operations pci_domain_ops = {
+	.read_resources	= pci_domain_read_resources,
+	.set_resources	= pci_domain_set_resources,
+	.enable_resources	= enable_childrens_resources,
+	.init			= 0,
+	.scan_bus		= pci_domain_scan_bus,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(&dev->link[0]);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+	.read_resources	= cpu_bus_noop,
+	.set_resources	= cpu_bus_noop,
+	.enable_resources	= cpu_bus_noop,
+	.init			= cpu_bus_init,
+	.scan_bus		= 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+	struct device_path;
+
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+		pci_set_method(dev);
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_i82830_ops = {
+	CHIP_NAME("Intel 82830 Northbridge")
+	.enable_dev = enable_dev,
+};

Property changes on: src/northbridge/intel/i82830/northbridge.c
___________________________________________________________________
Name: svn:executable
   + *

Index: src/northbridge/intel/i82830/raminit.h
===================================================================
--- src/northbridge/intel/i82830/raminit.h	(revision 0)
+++ src/northbridge/intel/i82830/raminit.h	(revision 0)
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_INTEL_I82830_RAMINIT_H
+#define NORTHBRIDGE_INTEL_I82830_RAMINIT_H
+
+/* The 82830 supports max. 2 dual-sided SO-DIMMs. */
+#define DIMM_SOCKETS	2
+
+struct mem_controller {
+	device_t d0;
+	uint16_t channel0[DIMM_SOCKETS];
+};
+
+#endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */

Property changes on: src/northbridge/intel/i82830/raminit.h
___________________________________________________________________
Name: svn:executable
   + *

Index: src/northbridge/intel/i82830/chip.h
===================================================================
--- src/northbridge/intel/i82830/chip.h	(revision 0)
+++ src/northbridge/intel/i82830/chip.h	(revision 0)
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_intel_i82830_config {
+};
+
+extern struct chip_operations northbridge_intel_i82830_ops;

Property changes on: src/northbridge/intel/i82830/chip.h
___________________________________________________________________
Name: svn:executable
   + *

Index: src/northbridge/intel/i82830/northbridge.h
===================================================================
--- src/northbridge/intel/i82830/northbridge.h	(revision 0)
+++ src/northbridge/intel/i82830/northbridge.h	(revision 0)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_INTEL_I82830_NORTHBRIDGE_H
+#define NORTHBRIDGE_INTEL_I82830_NORTHBRIDGE_H
+
+extern unsigned int i82830_scan_root_bus(device_t root, unsigned int max);
+
+#endif /* NORTHBRIDGE_INTEL_I82830_NORTHBRIDGE_H */

Property changes on: src/northbridge/intel/i82830/northbridge.h
___________________________________________________________________
Name: svn:executable
   + *

Index: targets/rca/rm4100/Config.lb
===================================================================
--- targets/rca/rm4100/Config.lb	(revision 0)
+++ targets/rca/rm4100/Config.lb	(revision 0)
@@ -0,0 +1,47 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Joseph Smith <joe at smittys.pointclark.net>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target rm4100
+mainboard rca/rm4100
+
+## Total number of bytes allocated for LinuxBIOS use
+## (normal AND fallback images and payloads).
+option ROM_SIZE = 524288
+
+## Debugging
+## option DEBUG = 1
+
+romimage "normal"
+	option USE_FALLBACK_IMAGE = 0
+	option ROM_IMAGE_SIZE = 131072
+	option LINUXBIOS_EXTRA_VERSION = ".0Normal"
+	payload /etc/hosts
+#	payload /home/amp/filo-0.5/filo.elf
+end
+
+romimage "fallback" 
+	option USE_FALLBACK_IMAGE = 1
+	option ROM_IMAGE_SIZE = 131072
+	option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
+	payload /etc/hosts
+#	payload /home/amp/filo-0.5/filo.elf
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

Property changes on: targets/rca/rm4100/Config.lb
___________________________________________________________________
Name: svn:executable
   + *

-------------- next part --------------


LinuxBIOS-2.0.0.0Fallback Wed Sep 12 07:11:03 EDT 2007 starting...
Setting initial registers....
Initial registers have been set.
No DIMM found in slot 00
DRB 0x60 has been set to 0x00
DRB1 0x61 has been set to 0x00
Found DIMM in slot 01
DIMM is 0x0080 on side 1
DIMM is 0x0000 on side 2
DRB2 0x62 has been set to 0x04
DRB3 0x63 has been set to 0x04
No DIMM found in slot 00, setting DRA to 0xFF
DRA 0x70 has been set to 0xff
Found DIMM in slot 01, setting DRA...
DRA 0x71 has been set to 0xf1
RAM Enable 1: Apply NOP
    Sending RAM command 0x00000010 to 0x00000000
RAM Enable 2: Precharge all
    Sending RAM command 0x00000020 to 0x00000000
RAM Enable 3: CBR
    Sending RAM command 0x00000060 to 0x00000000
RAM Enable 4: Mode register set
    Sending RAM command 0x00000030 to 0x000001d0
RAM Enable 5: Normal operation
    Sending RAM command 0x20000170 to 0x00000000
Northbridge following SDRAM init:
PCI: 00:00.00
00: 86 80 75 35 06 00 10 00 04 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e
50: 72 a0 20 00 00 00 00 00 00 30 33 33 33 33 33 33
60: 00 00 04 04 00 00 00 00 00 00 00 00 00 00 00 00
70: ff f1 ff ff 00 00 00 00 10 00 00 00 70 01 00 20
80: 00 00 00 00 00 00 00 00 00 90 00 40 00 00 00 00
90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 09 c9 9f fc
f0: 11 11 01 00 00 00 0b 05 37 d6 30 d0 22 d0 23 cf
Copying LinuxBIOS to RAM.
Jumping to LinuxBIOS.
LinuxBIOS-2.0.0.0Fallback Wed Sep 12 07:11:03 EDT 2007 booting...
end 6cfb8727, start 0
32-bit delta 1566
calibrate_tsc 32-bit result is 1566
clocks_per_usec: 1566
Enumerating buses...
scan_static_bus for Root Device
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/3575] ops
PCI: 00:00.0 [8086/3575] enabled
PCI: devfn 0x9, bad id 0xffffffff
PCI: devfn 0xa, bad id 0xffffffff
PCI: devfn 0xb, bad id 0xffffffff
PCI: devfn 0xc, bad id 0xffffffff
PCI: devfn 0xd, bad id 0xffffffff
PCI: devfn 0xe, bad id 0xffffffff
PCI: devfn 0xf, bad id 0xffffffff
PCI: 00:02.0 [8086/3577] disabled
PCI: devfn 0x11, bad id 0xffffffff
PCI: devfn 0x12, bad id 0xffffffff
PCI: devfn 0x13, bad id 0xffffffff
PCI: devfn 0x14, bad id 0xffffffff
PCI: devfn 0x15, bad id 0xffffffff
PCI: devfn 0x16, bad id 0xffffffff
PCI: devfn 0x17, bad id 0xffffffff
PCI: devfn 0x18, bad id 0xffffffff
PCI: devfn 0x20, bad id 0xffffffff
PCI: devfn 0x28, bad id 0xffffffff
PCI: devfn 0x30, bad id 0xffffffff
PCI: devfn 0x38, bad id 0xffffffff
PCI: devfn 0x40, bad id 0xffffffff
PCI: devfn 0x48, bad id 0xffffffff
PCI: devfn 0x50, bad id 0xffffffff
PCI: devfn 0x58, bad id 0xffffffff
PCI: devfn 0x60, bad id 0xffffffff
PCI: devfn 0x68, bad id 0xffffffff
PCI: devfn 0x70, bad id 0xffffffff
PCI: devfn 0x78, bad id 0xffffffff
PCI: devfn 0x80, bad id 0xffffffff
PCI: devfn 0x88, bad id 0xffffffff
PCI: devfn 0x90, bad id 0xffffffff
PCI: devfn 0x98, bad id 0xffffffff
PCI: devfn 0xa0, bad id 0xffffffff
PCI: devfn 0xa8, bad id 0xffffffff
PCI: devfn 0xb0, bad id 0xffffffff
PCI: devfn 0xb8, bad id 0xffffffff
PCI: devfn 0xc0, bad id 0xffffffff
PCI: devfn 0xc8, bad id 0xffffffff
PCI: devfn 0xd0, bad id 0xffffffff
PCI: devfn 0xd8, bad id 0xffffffff
PCI: devfn 0xe0, bad id 0xffffffff
PCI: 00:1d.0 [8086/24c2] ops
PCI: 00:1d.0 [8086/24c2] enabled
PCI: 00:1d.1 [8086/24c4] ops
PCI: 00:1d.1 [8086/24c4] enabled
PCI: 00:1d.2 [8086/24c7] ops
PCI: 00:1d.2 [8086/24c7] enabled
PCI: devfn 0xeb, bad id 0xffffffff
PCI: devfn 0xec, bad id 0xffffffff
PCI: devfn 0xed, bad id 0xffffffff
PCI: devfn 0xee, bad id 0xffffffff
PCI: 00:1d.7 [8086/24cd] ops
PCI: 00:1d.7 [8086/24cd] enabled
PCI: 00:1e.0 [8086/244e] bus ops
PCI: 00:1e.0 [8086/244e] enabled
PCI: 00:1f.0 [8086/24c0] bus ops
PCI: 00:1f.0 [8086/24c0] enabled
PCI: 00:1f.1 [8086/24cb] ops
PCI: 00:1f.1 [8086/24cb] enabled
PCI: devfn 0xfa, bad id 0xffffffff
PCI: 00:1f.3 [8086/24c3] enabled
PCI: devfn 0xfc, bad id 0xffffffff
PCI: 00:1f.5 [8086/24c5] ops
PCI: 00:1f.5 [8086/24c5] enabled
PCI: 00:1f.6 [8086/24c6] ops
PCI: 00:1f.6 [8086/24c6] enabled
PCI: devfn 0xff, bad id 0xffffffff
do_pci_scan_bridge for PCI: 00:1e.0
PCI: pci_scan_bus for bus 01
PCI: devfn 0x0, bad id 0xffffffff
PCI: devfn 0x8, bad id 0xffffffff
PCI: devfn 0x10, bad id 0xffffffff
PCI: devfn 0x18, bad id 0xffffffff
PCI: devfn 0x20, bad id 0xffffffff
PCI: devfn 0x28, bad id 0xffffffff
PCI: devfn 0x30, bad id 0xffffffff
PCI: devfn 0x38, bad id 0xffffffff
PCI: devfn 0x40, bad id 0xffffffff
PCI: devfn 0x48, bad id 0xffffffff
PCI: devfn 0x50, bad id 0xffffffff
PCI: devfn 0x58, bad id 0xffffffff
PCI: devfn 0x60, bad id 0xffffffff
PCI: devfn 0x68, bad id 0xffffffff
PCI: devfn 0x70, bad id 0xffffffff
PCI: devfn 0x78, bad id 0xffffffff
PCI: devfn 0x80, bad id 0xffffffff
PCI: devfn 0x88, bad id 0xffffffff
PCI: devfn 0x90, bad id 0xffffffff
PCI: devfn 0x98, bad id 0xffffffff
PCI: devfn 0xa0, bad id 0xffffffff
PCI: devfn 0xa8, bad id 0xffffffff
PCI: devfn 0xb0, bad id 0xffffffff
PCI: devfn 0xb8, bad id 0xffffffff
PCI: devfn 0xc0, bad id 0xffffffff
PCI: devfn 0xc8, bad id 0xffffffff
PCI: devfn 0xd0, bad id 0xffffffff
PCI: devfn 0xd8, bad id 0xffffffff
PCI: devfn 0xe0, bad id 0xffffffff
PCI: devfn 0xe8, bad id 0xffffffff
PCI: devfn 0xf0, bad id 0xffffffff
PCI: devfn 0xf8, bad id 0xffffffff
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:1f.0
Found SMSC Super I/O (ID=0x60, rev=0x01)
PNP: 002e.0 disabled
PNP: 002e.3 disabled
PNP: 002e.4 enabled
PNP: 002e.5 disabled
PNP: 002e.7 enabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
PNP: 002e.b disabled
scan_static_bus for PCI: 00:1f.0 done
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
Allocating resources...
Reading resources...
Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0
Root Device read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:1e.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done
PCI: 00:1e.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12 done
PCI: 00:1e.0 1c <- [0x000000f000 - 0x000000efff] bus 01 io
PCI: 00:1e.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 01 prefmem
PCI: 00:1e.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 01 mem
PCI: 00:1f.0 read_resources bus 0 link: 0
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
PCI: 00:1f.5 10 *  [0x00000400 - 0x000004ff] io
PCI: 00:1f.6 10 *  [0x00000800 - 0x000008ff] io
PCI: 00:1f.6 14 *  [0x00000c00 - 0x00000c7f] io
PCI: 00:1f.5 14 *  [0x00000c80 - 0x00000cbf] io
PCI: 00:1d.0 20 *  [0x00000cc0 - 0x00000cdf] io
PCI: 00:1d.1 20 *  [0x00000ce0 - 0x00000cff] io
PCI: 00:1d.2 20 *  [0x00001000 - 0x0000101f] io
PCI: 00:1f.3 20 *  [0x00001020 - 0x0000103f] io
PCI: 00:1f.1 20 *  [0x00001040 - 0x0000104f] io
PCI: 00:1f.1 10 *  [0x00001050 - 0x00001057] io
PCI: 00:1f.1 18 *  [0x00001060 - 0x00001067] io
PCI: 00:1f.1 14 *  [0x00001070 - 0x00001073] io
PCI: 00:1f.1 1c *  [0x00001080 - 0x00001083] io
Root Device compute_allocate_io: base: 00001084 size: 00000c84 align: 8 gran: 0 done
Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:1d.7 10 *  [0x00000000 - 0x000003ff] mem
PCI: 00:1f.1 24 *  [0x00001000 - 0x000013ff] mem
PCI: 00:1f.5 18 *  [0x00002000 - 0x000021ff] mem
PCI: 00:1f.5 1c *  [0x00003000 - 0x000030ff] mem
Root Device compute_allocate_mem: base: 00003100 size: 00003100 align: 10 gran: 0 done
Done reading resources.
Setting resources...
Root Device compute_allocate_io: base: 00001000 size: 00000c84 align: 8 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:1f.5 10 *  [0x00001000 - 0x000010ff] io
PCI: 00:1f.6 10 *  [0x00001400 - 0x000014ff] io
PCI: 00:1f.6 14 *  [0x00001800 - 0x0000187f] io
PCI: 00:1f.5 14 *  [0x00001880 - 0x000018bf] io
PCI: 00:1d.0 20 *  [0x000018c0 - 0x000018df] io
PCI: 00:1d.1 20 *  [0x000018e0 - 0x000018ff] io
PCI: 00:1d.2 20 *  [0x00001c00 - 0x00001c1f] io
PCI: 00:1f.3 20 *  [0x00001c20 - 0x00001c3f] io
PCI: 00:1f.1 20 *  [0x00001c40 - 0x00001c4f] io
PCI: 00:1f.1 10 *  [0x00001c50 - 0x00001c57] io
PCI: 00:1f.1 18 *  [0x00001c60 - 0x00001c67] io
PCI: 00:1f.1 14 *  [0x00001c70 - 0x00001c73] io
PCI: 00:1f.1 1c *  [0x00001c80 - 0x00001c83] io
Root Device compute_allocate_io: base: 00001c84 size: 00000c84 align: 8 gran: 0 done
Root Device compute_allocate_mem: base: febfcc00 size: 00003100 align: 10 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:1d.7 10 *  [0xfebfd000 - 0xfebfd3ff] mem
PCI: 00:1f.1 24 *  [0xfebfe000 - 0xfebfe3ff] mem
PCI: 00:1f.5 18 *  [0xfebff000 - 0xfebff1ff] mem
PCI: 00:1f.5 1c *  [0xfec00000 - 0xfec000ff] mem
Root Device compute_allocate_mem: base: fec00100 size: 00003500 align: 10 gran: 0 done
Root Device assign_resources, bus 0 link: 0
Setting RAM size to 131072
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:1d.0 20 <- [0x00000018c0 - 0x00000018df] io
PCI: 00:1d.1 20 <- [0x00000018e0 - 0x00000018ff] io
PCI: 00:1d.2 20 <- [0x0000001c00 - 0x0000001c1f] io
PCI: 00:1d.7 10 <- [0x00febfd000 - 0x00febfd3ff] mem
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 002e.4 60 <- [0x00000003f8 - 0x00000003ff] io
PNP: 002e.4 70 <- [0x0000000004 - 0x0000000004] irq
PNP: 002e.7 60 <- [0x0000000060 - 0x0000000060] io
PNP: 002e.7 62 <- [0x0000000064 - 0x0000000064] io
PNP: 002e.7 70 <- [0x0000000001 - 0x0000000001] irq
PNP: 002e.7 72 <- [0x000000000c - 0x000000000c] irq
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.1 10 <- [0x0000001c50 - 0x0000001c57] io
PCI: 00:1f.1 14 <- [0x0000001c70 - 0x0000001c73] io
PCI: 00:1f.1 18 <- [0x0000001c60 - 0x0000001c67] io
PCI: 00:1f.1 1c <- [0x0000001c80 - 0x0000001c83] io
PCI: 00:1f.1 20 <- [0x0000001c40 - 0x0000001c4f] io
PCI: 00:1f.1 24 <- [0x00febfe000 - 0x00febfe3ff] mem
PCI: 00:1f.3 20 <- [0x0000001c20 - 0x0000001c3f] io
PCI: 00:1f.5 10 <- [0x0000001000 - 0x00000010ff] io
PCI: 00:1f.5 14 <- [0x0000001880 - 0x00000018bf] io
PCI: 00:1f.5 18 <- [0x00febff000 - 0x00febff1ff] mem
PCI: 00:1f.5 1c <- [0x00fec00000 - 0x00fec000ff] mem
PCI: 00:1f.6 10 <- [0x0000001400 - 0x00000014ff] io
PCI: 00:1f.6 14 <- [0x0000001800 - 0x000000187f] io
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 146
PCI: 00:1d.0 cmd <- 141
PCI: 00:1d.1 cmd <- 141
PCI: 00:1d.2 cmd <- 141
PCI: 00:1d.7 subsystem <- 00/00
PCI: 00:1d.7 cmd <- 142
PCI: 00:1e.0 bridge ctrl <- 0003
PCI: 00:1e.0 cmd <- 141


LinuxBIOS-2.0.0.0Fallback Wed Sep 12 07:11:03 EDT 2007 starting...
Setting initial registers....
Initial registers have been set.
No DIMM found in slot 00
DRB 0x60 has been set to 0x00
DRB1 0x61 has been set to 0x00
Found DIMM in slot 01
DIMM is 0x0080 on side 1
DIMM is 0x0000 on side 2
DRB2 0x62 has been set to 0x04
DRB3 0x63 has been set to 0x04
No DIMM found in slot 00, setting DRA to 0xFF
DRA 0x70 has been set to 0xff
Found DIMM in slot 01, setting DRA...
DRA 0x71 has been set to 0xf1
RAM Enable 1: Apply NOP
    Sending RAM command 0x00000010 to 0x00000000
RAM Enable 2: Precharge all
    Sending RAM command 0x00000020 to 0x00000000
RAM Enable 3: CBR
    Sending RAM command 0x00000060 to 0x00000000
RAM Enable 4: Mode register set
    Sending RAM command 0x00000030 to 0x000001d0
RAM Enable 5: Normal operation
    Sending RAM command 0x20000170 to 0x00000000
Northbridge following SDRAM init:
PCI: 00:00.00
00: 86 80 75 35 06 00 10 00 04 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e
50: 72 a0 20 00 00 00 00 00 00 30 33 33 33 33 33 33
60: 00 00 04 04 00 00 00 00 00 00 00 00 00 00 00 00
70: ff f1 ff ff 00 00 00 00 10 00 00 00 70 01 00 20
80: 00 00 00 00 00 00 00 00 00 90 00 40 00 00 00 00
90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 09 c9 9f fc
f0: 11 11 01 00 00 00 0b 05 37 d6 30 cf 22 cf 23 cf
Copying LinuxBIOS to RAM.
Jumping to LinuxBIOS.
LinuxBIOS-2.0.0.0Fallback Wed Sep 12 07:11:03 EDT 2007 booting...
end 6cfab38d, start 0
32-bit delta 1566
calibrate_tsc 32-bit result is 1566
clocks_per_usec: 1566
Enumerating buses...
scan_static_bus for Root Device
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/3575] ops
PCI: 00:00.0 [8086/3575] enabled
PCI: devfn 0x9, bad id 0xffffffff
PCI: devfn 0xa, bad id 0xffffffff
PCI: devfn 0xb, bad id 0xffffffff
PCI: devfn 0xc, bad id 0xffffffff
PCI: devfn 0xd, bad id 0xffffffff
PCI: devfn 0xe, bad id 0xffffffff
PCI: devfn 0xf, bad id 0xffffffff
PCI: 00:02.0 [8086/3577] disabled
PCI: devfn 0x11, bad id 0xffffffff
PCI: devfn 0x12, bad id 0xffffffff
PCI: devfn 0x13, bad id 0xffffffff
PCI: devfn 0x14, bad id 0xffffffff
PCI: devfn 0x15, bad id 0xffffffff
PCI: devfn 0x16, bad id 0xffffffff
PCI: devfn 0x17, bad id 0xffffffff
PCI: devfn 0x18, bad id 0xffffffff
PCI: devfn 0x20, bad id 0xffffffff
PCI: devfn 0x28, bad id 0xffffffff
PCI: devfn 0x30, bad id 0xffffffff
PCI: devfn 0x38, bad id 0xffffffff
PCI: devfn 0x40, bad id 0xffffffff
PCI: devfn 0x48, bad id 0xffffffff
PCI: devfn 0x50, bad id 0xffffffff
PCI: devfn 0x58, bad id 0xffffffff
PCI: devfn 0x60, bad id 0xffffffff
PCI: devfn 0x68, bad id 0xffffffff
PCI: devfn 0x70, bad id 0xffffffff
PCI: devfn 0x78, bad id 0xffffffff
PCI: devfn 0x80, bad id 0xffffffff
PCI: devfn 0x88, bad id 0xffffffff
PCI: devfn 0x90, bad id 0xffffffff
PCI: devfn 0x98, bad id 0xffffffff
PCI: devfn 0xa0, bad id 0xffffffff
PCI: devfn 0xa8, bad id 0xffffffff
PCI: devfn 0xb0, bad id 0xffffffff
PCI: devfn 0xb8, bad id 0xffffffff
PCI: devfn 0xc0, bad id 0xffffffff
PCI: devfn 0xc8, bad id 0xffffffff
PCI: devfn 0xd0, bad id 0xffffffff
PCI: devfn 0xd8, bad id 0xffffffff
PCI: devfn 0xe0, bad id 0xffffffff
PCI: 00:1d.0 [8086/24c2] ops
PCI: 00:1d.0 [8086/24c2] enabled
PCI: 00:1d.1 [8086/24c4] ops
PCI: 00:1d.1 [8086/24c4] enabled
PCI: 00:1d.2 [8086/24c7] ops
PCI: 00:1d.2 [8086/24c7] enabled
PCI: devfn 0xeb, bad id 0xffffffff
PCI: devfn 0xec, bad id 0xffffffff
PCI: devfn 0xed, bad id 0xffffffff
PCI: devfn 0xee, bad id 0xffffffff
PCI: 00:1d.7 [8086/24cd] ops
PCI: 00:1d.7 [8086/24cd] enabled
PCI: 00:1e.0 [8086/244e] bus ops
PCI: 00:1e.0 [8086/244e] enabled
PCI: 00:1f.0 [8086/24c0] bus ops
PCI: 00:1f.0 [8086/24c0] enabled
PCI: 00:1f.1 [8086/24cb] ops
PCI: 00:1f.1 [8086/24cb] enabled
PCI: devfn 0xfa, bad id 0xffffffff
PCI: 00:1f.3 [8086/24c3] enabled
PCI: devfn 0xfc, bad id 0xffffffff
PCI: 00:1f.5 [8086/24c5] ops
PCI: 00:1f.5 [8086/24c5] enabled
PCI: 00:1f.6 [8086/24c6] ops
PCI: 00:1f.6 [8086/24c6] enabled
PCI: devfn 0xff, bad id 0xffffffff
do_pci_scan_bridge for PCI: 00:1e.0
PCI: pci_scan_bus for bus 01
PCI: devfn 0x0, bad id 0xffffffff
PCI: devfn 0x8, bad id 0xffffffff
PCI: devfn 0x10, bad id 0xffffffff
PCI: devfn 0x18, bad id 0xffffffff
PCI: devfn 0x20, bad id 0xffffffff
PCI: devfn 0x28, bad id 0xffffffff
PCI: devfn 0x30, bad id 0xffffffff
PCI: devfn 0x38, bad id 0xffffffff
PCI: devfn 0x40, bad id 0xffffffff
PCI: devfn 0x48, bad id 0xffffffff
PCI: devfn 0x50, bad id 0xffffffff
PCI: devfn 0x58, bad id 0xffffffff
PCI: devfn 0x60, bad id 0xffffffff
PCI: devfn 0x68, bad id 0xffffffff
PCI: devfn 0x70, bad id 0xffffffff
PCI: devfn 0x78, bad id 0xffffffff
PCI: devfn 0x80, bad id 0xffffffff
PCI: devfn 0x88, bad id 0xffffffff
PCI: devfn 0x90, bad id 0xffffffff
PCI: devfn 0x98, bad id 0xffffffff
PCI: devfn 0xa0, bad id 0xffffffff
PCI: devfn 0xa8, bad id 0xffffffff
PCI: devfn 0xb0, bad id 0xffffffff
PCI: devfn 0xb8, bad id 0xffffffff
PCI: devfn 0xc0, bad id 0xffffffff
PCI: devfn 0xc8, bad id 0xffffffff
PCI: devfn 0xd0, bad id 0xffffffff
PCI: devfn 0xd8, bad id 0xffffffff
PCI: devfn 0xe0, bad id 0xffffffff
PCI: devfn 0xe8, bad id 0xffffffff
PCI: devfn 0xf0, bad id 0xffffffff
PCI: devfn 0xf8, bad id 0xffffffff
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:1f.0
Found SMSC Super I/O (ID=0x60, rev=0x01)
PNP: 002e.0 disabled
PNP: 002e.3 disabled
PNP: 002e.4 enabled
PNP: 002e.5 disabled
PNP: 002e.7 enabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
PNP: 002e.b disabled
scan_static_bus for PCI: 00:1f.0 done
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
Allocating resources...
Reading resources...
Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0
Root Device read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:1e.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done
PCI: 00:1e.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12 done
PCI: 00:1e.0 1c <- [0x000000f000 - 0x000000efff] bus 01 io
PCI: 00:1e.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 01 prefmem
PCI: 00:1e.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 01 mem
PCI: 00:1f.0 read_resources bus 0 link: 0
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
PCI: 00:1f.5 10 *  [0x00000400 - 0x000004ff] io
PCI: 00:1f.6 10 *  [0x00000800 - 0x000008ff] io
PCI: 00:1f.6 14 *  [0x00000c00 - 0x00000c7f] io
PCI: 00:1f.5 14 *  [0x00000c80 - 0x00000cbf] io
PCI: 00:1d.0 20 *  [0x00000cc0 - 0x00000cdf] io
PCI: 00:1d.1 20 *  [0x00000ce0 - 0x00000cff] io
PCI: 00:1d.2 20 *  [0x00001000 - 0x0000101f] io
PCI: 00:1f.3 20 *  [0x00001020 - 0x0000103f] io
PCI: 00:1f.1 20 *  [0x00001040 - 0x0000104f] io
PCI: 00:1f.1 10 *  [0x00001050 - 0x00001057] io
PCI: 00:1f.1 18 *  [0x00001060 - 0x00001067] io
PCI: 00:1f.1 14 *  [0x00001070 - 0x00001073] io
PCI: 00:1f.1 1c *  [0x00001080 - 0x00001083] io
Root Device compute_allocate_io: base: 00001084 size: 00000c84 align: 8 gran: 0 done
Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:1d.7 10 *  [0x00000000 - 0x000003ff] mem
PCI: 00:1f.1 24 *  [0x00001000 - 0x000013ff] mem
PCI: 00:1f.5 18 *  [0x00002000 - 0x000021ff] mem
PCI: 00:1f.5 1c *  [0x00003000 - 0x000030ff] mem
Root Device compute_allocate_mem: base: 00003100 size: 00003100 align: 10 gran: 0 done
Done reading resources.
Setting resources...
Root Device compute_allocate_io: base: 00001000 size: 00000c84 align: 8 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:1f.5 10 *  [0x00001000 - 0x000010ff] io
PCI: 00:1f.6 10 *  [0x00001400 - 0x000014ff] io
PCI: 00:1f.6 14 *  [0x00001800 - 0x0000187f] io
PCI: 00:1f.5 14 *  [0x00001880 - 0x000018bf] io
PCI: 00:1d.0 20 *  [0x000018c0 - 0x000018df] io
PCI: 00:1d.1 20 *  [0x000018e0 - 0x000018ff] io
PCI: 00:1d.2 20 *  [0x00001c00 - 0x00001c1f] io
PCI: 00:1f.3 20 *  [0x00001c20 - 0x00001c3f] io
PCI: 00:1f.1 20 *  [0x00001c40 - 0x00001c4f] io
PCI: 00:1f.1 10 *  [0x00001c50 - 0x00001c57] io
PCI: 00:1f.1 18 *  [0x00001c60 - 0x00001c67] io
PCI: 00:1f.1 14 *  [0x00001c70 - 0x00001c73] io
PCI: 00:1f.1 1c *  [0x00001c80 - 0x00001c83] io
Root Device compute_allocate_io: base: 00001c84 size: 00000c84 align: 8 gran: 0 done
Root Device compute_allocate_mem: base: febfcc00 size: 00003100 align: 10 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:1d.7 10 *  [0xfebfd000 - 0xfebfd3ff] mem
PCI: 00:1f.1 24 *  [0xfebfe000 - 0xfebfe3ff] mem
PCI: 00:1f.5 18 *  [0xfebff000 - 0xfebff1ff] mem
PCI: 00:1f.5 1c *  [0xfec00000 - 0xfec000ff] mem
Root Device compute_allocate_mem: base: fec00100 size: 00003500 align: 10 gran: 0 done
Root Device assign_resources, bus 0 link: 0
Setting RAM size to 131072
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:1d.0 20 <- [0x00000018c0 - 0x00000018df] io
PCI: 00:1d.1 20 <- [0x00000018e0 - 0x00000018ff] io
PCI: 00:1d.2 20 <- [0x0000001c00 - 0x0000001c1f] io
PCI: 00:1d.7 10 <- [0x00febfd000 - 0x00febfd3ff] mem
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 002e.4 60 <- [0x00000003f8 - 0x00000003ff] io
PNP: 002e.4 70 <- [0x0000000004 - 0x0000000004] irq
PNP: 002e.7 60 <- [0x0000000060 - 0x0000000060] io
PNP: 002e.7 62 <- [0x0000000064 - 0x0000000064] io
PNP: 002e.7 70 <- [0x0000000001 - 0x0000000001] irq
PNP: 002e.7 72 <- [0x000000000c - 0x000000000c] irq
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.1 10 <- [0x0000001c50 - 0x0000001c57] io
PCI: 00:1f.1 14 <- [0x0000001c70 - 0x0000001c73] io
PCI: 00:1f.1 18 <- [0x0000001c60 - 0x0000001c67] io
PCI: 00:1f.1 1c <- [0x0000001c80 - 0x0000001c83] io
PCI: 00:1f.1 20 <- [0x0000001c40 - 0x0000001c4f] io
PCI: 00:1f.1 24 <- [0x00febfe000 - 0x00febfe3ff] mem
PCI: 00:1f.3 20 <- [0x0000001c20 - 0x0000001c3f] io
PCI: 00:1f.5 10 <- [0x0000001000 - 0x00000010ff] io
PCI: 00:1f.5 14 <- [0x0000001880 - 0x00000018bf] io
PCI: 00:1f.5 18 <- [0x00febff000 - 0x00febff1ff] mem
PCI: 00:1f.5 1c <- [0x00fec00000 - 0x00fec000ff] mem
PCI: 00:1f.6 10 <- [0x0000001400 - 0x00000014ff] io
PCI: 00:1f.6 14 <- [0x0000001800 - 0x000000187f] io
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 146
PCI: 00:1d.0 cmd <- 141
PCI: 00:1d.1 cmd <- 141
PCI: 00:1d.2 cmd <- 141
PCI: 00:1d.7 subsystem <- 00/00
PCI: 00:1d.7 cmd <- 142
PCI: 00:1e.0 bridge ctrl <- 0003
PCI: 00:1e.0 cmd <- 141


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