[coreboot] .. Re: .. Re: Via epia
jtd
jtd at mtnl.net.in
Sat Mar 22 11:05:54 CET 2008
On Friday 21 March 2008 12:11 am, mercury at wirebros.com wrote:
> Don't worry, my first few builds failed (dead MB), but finally I
> got it working.
Everything builds fine. But no ouput.
Running the bios with
qemu -L ~ -fda fdosorig.img -nographic
Serial controller not found
>
> Post your config.lb
attached.
> post lspci output
tavera:~# lspci -tvnn
-[0000:00]-+-00.0 VIA Technologies, Inc. VT8623 [Apollo CLE266]
[1106:3123]
+-01.0-[0000:01]----00.0 VIA Technologies, Inc. VT8623
[Apollo CLE266] integrated CastleRock graphics [1106:3122]
+-0d.0 Realtek Semiconductor Co., Ltd.
RTL-8139/8139C/8139C+ [10ec:8139]
+-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
Controller [1106:3038]
+-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
Controller [1106:3038]
+-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
Controller [1106:3038]
+-10.3 VIA Technologies, Inc. USB 2.0 [1106:3104]
+-11.0 VIA Technologies, Inc. VT8235 ISA Bridge
[1106:3177]
+-11.1 VIA Technologies, Inc.
VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE [1106:0571]
\-11.5 VIA Technologies, Inc. VT8233/A/8235/8237 AC97
Audio Controller [1106:3059]
tavera:~#
--
Rgds
JTD
-------------- next part --------------
##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0
end
##
## Compute the start location and size size of
## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
## Set all of the defaults for an x86 architecture
##
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
object vgabios.o
if HAVE_ACPI_TABLES
object fadt.o
object dsdt.o
object acpi_tables.o
end
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
##
dir /pc80
config chip.h
chip northbridge/via/vt8623
device apic_cluster 0 on
chip cpu/via/model_centaur
device apic 0 on end
end
end
device pci_domain 0 on
device pci 0.0 on end # Northbridge
device pci 0.1 on # AGP bridge
chip drivers/pci/onboard # Integrated VGA
device pci 1.0 on end
register "rom_address" = "0xfffc0000"
end
end
chip southbridge/via/vt8235
register "enable_native_ide" = "1"
register "enable_com_ports" = "1"
register "enable_keyboard" = "1"
device pci 10.0 on end # USB 1.1
device pci 10.1 on end # USB 1.1
device pci 10.2 on end # USB 1.1
device pci 10.3 on end # USB 2.0
device pci 11.0 on # Southbridge
chip superio/ite/it8705f
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # COM1 Parallel Port
io 0x60 = 0x3f8
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.4 on # HWM
io 0x60 = 0x0290
end
device pnp 2e.5 off end # GPIO3
device pnp 2e.6 off end # GAME port
device pnp 2e.7 off end # CIR
device pnp 2e.8 off end # MIDI
end
end
device pci 11.1 on end # IDE
# 2-4 non existant?
device pci 11.5 on end # AC97 Audio
device pci 11.6 off end # AC97 Modem
# device pci 13.0 on end # Ethernet
end
# This is on the EPIA MII, not the M.
# chip southbridge/ricoh/rl5c476
# register "enable_cf" = "1"
# device pci 0a.0 on end
# device pci 0a.1 on end
# end
end
end
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