[coreboot] epia-cn patch
Rudolf Marek
r.marek at assembler.cz
Thu May 15 17:29:27 CEST 2008
Hi AAron
I just checked the stuff I know from other VIA chipsets, the mem init and
configs I skipped, perhaps it is OK.
> Index: src/include/device/pci_ids.h
> ===================================================================
> --- src/include/device/pci_ids.h (revision 3321)
> +++ src/include/device/pci_ids.h (working copy)
> @@ -1160,6 +1160,7 @@
> #define PCI_DEVICE_ID_VIA_K8T890CE_BR 0xb188
> #define PCI_DEVICE_ID_VIA_VT6420_SATA 0x3149
> #define PCI_DEVICE_ID_VIA_VT8237R_LPC 0x3227
> +#define PCI_DEVICE_ID_VIA_VT8237R_SATA 0x3149
Why not use PCI_DEVICE_ID_VIA_VT6420_SATA as I did?
> #define PCI_DEVICE_ID_VIA_CN700_AGP 0x0314
> #define PCI_DEVICE_ID_VIA_CN700_ERR 0x1314
> #define PCI_DEVICE_ID_VIA_CN700_HOST 0x2314
> +}
> +
> +#include "northbridge/via/cn700/raminit.c"
> +
> +static void enable_mainboard_devices(void)
> +{
> + device_t dev;
> + u8 reg;
> +
> + /*
> + * If I enbale sata, filo will not find the ide disk, so I'll disable sata here
> + * To not conflict with pci sepc, I'll move ide device from 00:0f.1 to 00:0f.0
Please try attached patch. Thanks. I'm booting from first SATA at filo with hd0
as first SATA and second sata as hd2 imho the first ide disk will be hd4.
> + */
> + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_SATA), 0);
> + if (dev != PCI_DEV_INVALID) {
> + /* enable backdoor */
> + reg = pci_read_config8(dev, 0xd1);
> + reg |= 0x08;
> + pci_write_config8(dev, 0xd1, reg);
> + /* enable pata */
> + reg = pci_read_config8(dev, 0x49);
> + reg |= 0x80;
> + pci_write_config8(dev, 0x49, reg);
> + }
> + else
snip
> /* AGTL+ Compensation Status */
> @@ -135,206 +133,297 @@
> pci_write_config8(dev, 0x79, 0xaa);
> /* Address Strobe Input Delay Control */
> pci_write_config8(dev, 0x7a, 0x24);
> - /* Address CKG Rising/Falling Time Control */
> - pci_write_config8(dev, 0x7b, 0x00);
> + // Address CKG Rising/Falling Time Control
> + pci_write_config8(dev, 0x7b, 0xaa);
> /* Address CKG Clock Rising/Falling Time Control */
> pci_write_config8(dev, 0x7c, 0x00);
> /* Undefined (can't remember why I did this) */
lol ;)
> - pci_write_config8(dev, 0x7d, 0x6d);
> + pci_write_config8(dev, 0x7d, 0x6d);
> + pci_write_config8(dev, 0x7e, 0x00);
> + pci_write_config8(dev, 0x7f, 0x00);
> + pci_write_config8(dev, 0x80, 0x1b);
> + pci_write_config8(dev, 0x81, 0x0a);
> + pci_write_config8(dev, 0x82, 0x0a);
> + pci_write_config8(dev, 0x83, 0x0a);
>
> - /* VLink Control */
> - pci_write_config8(ctrl->d0f7, 0xb0, 0x05);
> - pci_write_config8(ctrl->d0f7, 0xb1, 0x01);
Just a question do you have in plan to support also some other pairs like VT8237A/S?
> + pci_write_config8(ctrl->d0f3, 0x86, 0x29);
> + /* SMM and APIC decoding mirror */
> + pci_write_config8(ctrl->d0f7, 0xe6, 0x29);
Hmm too dangerous please can you copy 0x86 reg to 0xe6?
>
> - /* Disable cross bank/multi page mode */
> - pci_write_config8(ctrl->d0f3, DDR_PAGE_CTL, 0x80);
> +
> Index: src/northbridge/via/cn700/northbridge.c
> ===================================================================
> --- src/northbridge/via/cn700/northbridge.c (revision 3321)
> +++ src/northbridge/via/cn700/northbridge.c (working copy)
> @@ -1,6 +1,8 @@
> /*
> * This file is part of the coreboot project.
> *
> + * Copyright (C) 2008 VIA Technologies, Inc.
> + * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
> * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
> *
> * This program is free software; you can redistribute it and/or modify
> @@ -35,9 +37,8 @@
> static void memctrl_init(device_t dev)
> {
> u16 reg16;
> + u8 ranks;
>
> - pci_write_config8(dev, 0x86, 0x2d);
> -
> /* Set up the vga framebuffer size */
> reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15);
> pci_write_config16(dev, 0xa0, reg16);
> @@ -45,8 +46,41 @@
> /* Set up VGA timers */
> pci_write_config8(dev, 0xa2, 0x44);
>
> - pci_write_config16(dev, 0xb0, 0xaa60);
> + for (ranks = 0x4b; ranks >= 0x48; ranks--) {
> + if (pci_read_config8(dev, ranks)) {
> + ranks -= 0x48;
> + break;
> + }
> + }
> + if (ranks == 0x47)
> + ranks = 0x00;
> + reg16 = 0xaae0;
> + reg16 |= ranks;
> + /* GMINT Misc. FrameBuffer rank */
> + pci_write_config16(dev, 0xb0, reg16);
> + /* AGPCINT Misc. */
> pci_write_config8(dev, 0xb8, 0x08);
> +
> + /* shadown ram */
> + u8 shadowreg;
> + shadowreg = pci_read_config8(dev, 0x83);
> + /* 0xf0000-0xfffff */
> + shadowreg |= 0x30;
> + pci_write_config8(dev, 0x83, shadowreg);
> + /* PAGE C, D, E are all read write enable */
> + pci_write_config8(dev, 0x80, 0xff);
> + pci_write_config8(dev, 0x81, 0xff);
> + pci_write_config8(dev, 0x82, 0xff);
> + /* vlink mirror */
Again here please can you do the copy of registers or someone else will forgot
that below ff MUST be same as above ;)
> + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
> + if (dev) {
> + pci_write_config8(dev, 0x61, 0xff);
> + pci_write_config8(dev, 0x62, 0xff);
> + pci_write_config8(dev, 0x64, 0xff);
> + shadowreg = pci_read_config8(dev, 0x63);
> + shadowreg |= 0x30;
> + pci_write_config8(dev, 0x63, shadowreg);
This is tricky with other then VT8237R there is new registers for whole range.
Please can you check if it is OK I mean that only two bits are for the whole
region? Typical symptoms are random disk read lockup and controller reset - when
DMA goes to the region of 0xE0000-0xEFFFF.
Here is my note from:
http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_ctrl.c
/*
* All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
* So the NB reg is quite inconsistent, we expect there only 0xff or
0x00,
* and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64!
*/
Rudolf
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