[coreboot] inline asm peculiarities in v3

[ron minnich]

On Thu, Sep 4, 2008 at 8:32 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hi,
>
> I decided to look at all cases of inline asm in our v3 code and I found
> a few bits which either work by accident or need better documentation.
>
> We use __asm__ and asm, __volatile__ and volatile. Can we please decide
> which one we want, then I'll switch the tree over.

somebody who knows better than me the implications can comment.

>
> northbridge/amd/geodelx/vsmsetup.c:143
>> __asm__(".text\n" "real_mode_switch_end:\n");
>> extern char real_mode_switch_end[];
> AFAICS the compiler and linker are free to place the resulting code
> anywhere in the binary independent of each other.

Not a problem. The "extern" is simply making the label available to C.
They don't depend on any trickiness.

>
> include/arch/x86/amd/k8/k8.h:746
>> static void disable_cache_as_ram_bsp(void)
>> {
>>         __asm__ volatile (
>> //              "pushl %eax\n\t"
>>                 "pushl %edx\n\t"
>>                 "pushl %ecx\n\t"
>>         );
>>
>>         disable_cache_as_ram();
>>         __asm__ volatile (
>>                 "popl %ecx\n\t"
>>                 "popl %edx\n\t"
>> //                "popl %eax\n\t"
>>         );
>> }
> The pushl and popl instructions seem to serve no real purpose. Kill them?

My rule with the Clever v2 code is not to modify it until I understand
it. So I did not touch these because I don't know what function they
serve. That's one reason that I am bringing code over and leaving it
ugly to start. Let's leave this alone until K8 is working.

>
> The K8 CAR disabling has inline asm depending on good compiler behaviour
> and luck. Patch will be sent separately.
>

Thank you.

ron