[coreboot] acpi stuff for winxp
Kevin O'Connor
kevin at koconnor.net
Mon Sep 8 00:55:32 CEST 2008
Hi Rudolf,
As requested, I'm sending the current diff for my tree. It's a wild
scattering of half baked things. I'll describe the important stuff
here - the rest of the patch is just junk:
* Windows really wants fadt->smi_cmd, fadt->acpi_enable, and
fadt->acpi_disable to be non zero.
* The coreboot acpi_facs_t table has incorrect pad (it has 33, but it
should be 31). I'm not sure if this confuses Windows, or if it
causes other acpi tables to be aligned in a way that Windows doesn't
like.
* Windows needs a _CRS definition for PCI0. I grabbed one from qemu
after applying a patch proposed on the qemu mailing list:
http://lists.nongnu.org/archive/html/qemu-devel/2008-08/txtXJHrYIW0Lp.txt
* Windows install needs an ACPI KBD definition - otherwise you can't
use the keyboard during the install. Again, I just copied it (along
with MOU, RTC, FD0) from qemu.
I've also disabled coreboot from running the vga rom. I do want
coreboot to copy the rom into ram - but only so seabios can run it.
I've also hacked coreboot so that it puts the pir, mptable, and acpi
tables into high memory - this ensures that they wont get overwritten
when the seabios payload is deployed. (Seabios will find the tables
that need to be in 0xf0000 and relocate them.)
-Kevin
-------------- next part --------------
Index: src/mainboard/via/epia-m/dsdt.c
===================================================================
--- src/mainboard/via/epia-m/dsdt.c (revision 3556)
+++ src/mainboard/via/epia-m/dsdt.c (working copy)
@@ -1,28 +1,28 @@
/*
*
* Intel ACPI Component Architecture
- * ASL Optimizing Compiler version 20060127 [Apr 23 2006]
+ * ASL Optimizing Compiler version 20061109 [Feb 21 2008]
* Copyright (C) 2000 - 2006 Intel Corporation
* Supports ACPI Specification Revision 3.0a
*
- * Compilation of "dsdt.asl" - Wed Sep 6 11:36:08 2006
+ * Compilation of "dsdt.asl" - Sun Sep 7 18:46:51 2008
*
* C source code output
*
*/
unsigned char AmlCode[] =
{
- 0x44,0x53,0x44,0x54,0xF0,0x03,0x00,0x00, /* 00000000 "DSDT...." */
- 0x01,0x03,0x4C,0x58,0x42,0x49,0x4F,0x53, /* 00000008 "..LXBIOS" */
+ 0x44,0x53,0x44,0x54,0x67,0x05,0x00,0x00, /* 00000000 "DSDTg..." */
+ 0x01,0x8E,0x4C,0x58,0x42,0x49,0x4F,0x53, /* 00000008 "..LXBIOS" */
0x4C,0x58,0x42,0x2D,0x44,0x53,0x44,0x54, /* 00000010 "LXB-DSDT" */
0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
- 0x27,0x01,0x06,0x20,0x10,0x12,0x5F,0x50, /* 00000020 "'.. .._P" */
+ 0x09,0x11,0x06,0x20,0x10,0x12,0x5F,0x50, /* 00000020 "... .._P" */
0x52,0x5F,0x5B,0x83,0x0B,0x43,0x50,0x55, /* 00000028 "R_[..CPU" */
0x30,0x00,0x10,0x04,0x00,0x00,0x06,0x08, /* 00000030 "0......." */
0x5F,0x53,0x30,0x5F,0x12,0x06,0x04,0x00, /* 00000038 "_S0_...." */
0x00,0x00,0x00,0x08,0x5F,0x53,0x35,0x5F, /* 00000040 "...._S5_" */
0x12,0x08,0x04,0x0A,0x02,0x0A,0x02,0x00, /* 00000048 "........" */
- 0x00,0x10,0x4E,0x39,0x5F,0x53,0x42,0x5F, /* 00000050 "..N9_SB_" */
+ 0x00,0x10,0x46,0x41,0x5F,0x53,0x42,0x5F, /* 00000050 "..FA_SB_" */
0x5B,0x82,0x44,0x06,0x4C,0x4E,0x4B,0x41, /* 00000058 "[.D.LNKA" */
0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0, /* 00000060 "._HID.A." */
0x0C,0x0F,0x08,0x5F,0x55,0x49,0x44,0x01, /* 00000068 "..._UID." */
@@ -74,7 +74,7 @@
0x0A,0x06,0x23,0x20,0x06,0x18,0x79,0x00, /* 000001D8 "..# ..y." */
0xA4,0x42,0x55,0x46,0x46,0x14,0x06,0x5F, /* 000001E0 ".BUFF.._" */
0x53,0x52,0x53,0x01,0x14,0x06,0x5F,0x44, /* 000001E8 "SRS..._D" */
- 0x49,0x53,0x00,0x5B,0x82,0x4B,0x1F,0x50, /* 000001F0 "IS.[.K.P" */
+ 0x49,0x53,0x00,0x5B,0x82,0x43,0x27,0x50, /* 000001F0 "IS.[.C'P" */
0x43,0x49,0x30,0x08,0x5F,0x48,0x49,0x44, /* 000001F8 "CI0._HID" */
0x0C,0x41,0xD0,0x0A,0x03,0x08,0x5F,0x41, /* 00000200 ".A...._A" */
0x44,0x52,0x00,0x08,0x5F,0x55,0x49,0x44, /* 00000208 "DR.._UID" */
@@ -138,5 +138,51 @@
0x01,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43, /* 000003D8 "....LNKC" */
0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01, /* 000003E0 "........" */
0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00, /* 000003E8 "...LNKD." */
-
+ 0x08,0x5F,0x43,0x52,0x53,0x11,0x42,0x07, /* 000003F0 "._CRS.B." */
+ 0x0A,0x6E,0x88,0x0D,0x00,0x02,0x0C,0x00, /* 000003F8 ".n......" */
+ 0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00, /* 00000400 "........" */
+ 0x00,0x01,0x47,0x01,0xF8,0x0C,0xF8,0x0C, /* 00000408 "..G....." */
+ 0x01,0x08,0x88,0x0D,0x00,0x01,0x0C,0x03, /* 00000410 "........" */
+ 0x00,0x00,0x00,0x00,0xF7,0x0C,0x00,0x00, /* 00000418 "........" */
+ 0xF8,0x0C,0x88,0x0D,0x00,0x01,0x0C,0x03, /* 00000420 "........" */
+ 0x00,0x00,0x00,0x0D,0xFF,0xFF,0x00,0x00, /* 00000428 "........" */
+ 0x00,0xF3,0x87,0x17,0x00,0x00,0x0C,0x03, /* 00000430 "........" */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x0A,0x00, /* 00000438 "........" */
+ 0xFF,0xFF,0x0B,0x00,0x00,0x00,0x00,0x00, /* 00000440 "........" */
+ 0x00,0x00,0x02,0x00,0x87,0x17,0x00,0x00, /* 00000448 "........" */
+ 0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000450 "........" */
+ 0x00,0xE0,0xFF,0xFF,0xBF,0xFE,0x00,0x00, /* 00000458 "........" */
+ 0xC0,0x1E,0x00,0x00,0x00,0x00,0x79,0x00, /* 00000460 "......y." */
+ 0x10,0x4E,0x0F,0x2E,0x5F,0x53,0x42,0x5F, /* 00000468 ".N.._SB_" */
+ 0x50,0x43,0x49,0x30,0x5B,0x82,0x2D,0x52, /* 00000470 "PCI0[.-R" */
+ 0x54,0x43,0x5F,0x08,0x5F,0x48,0x49,0x44, /* 00000478 "TC_._HID" */
+ 0x0C,0x41,0xD0,0x0B,0x00,0x08,0x5F,0x43, /* 00000480 ".A...._C" */
+ 0x52,0x53,0x11,0x18,0x0A,0x15,0x47,0x01, /* 00000488 "RS....G." */
+ 0x70,0x00,0x70,0x00,0x10,0x02,0x22,0x00, /* 00000490 "p.p..."." */
+ 0x01,0x47,0x01,0x72,0x00,0x72,0x00,0x02, /* 00000498 ".G.r.r.." */
+ 0x06,0x79,0x00,0x5B,0x82,0x44,0x04,0x4B, /* 000004A0 ".y.[.D.K" */
+ 0x42,0x44,0x5F,0x08,0x5F,0x48,0x49,0x44, /* 000004A8 "BD_._HID" */
+ 0x0C,0x41,0xD0,0x03,0x03,0x14,0x09,0x5F, /* 000004B0 ".A....._" */
+ 0x53,0x54,0x41,0x00,0xA4,0x0A,0x0F,0x14, /* 000004B8 "STA....." */
+ 0x29,0x5F,0x43,0x52,0x53,0x00,0x08,0x54, /* 000004C0 ")_CRS..T" */
+ 0x4D,0x50,0x5F,0x11,0x18,0x0A,0x15,0x47, /* 000004C8 "MP_....G" */
+ 0x01,0x60,0x00,0x60,0x00,0x01,0x01,0x47, /* 000004D0 ".`.`...G" */
+ 0x01,0x64,0x00,0x64,0x00,0x01,0x01,0x22, /* 000004D8 ".d.d..."" */
+ 0x02,0x00,0x79,0x00,0xA4,0x54,0x4D,0x50, /* 000004E0 "..y..TMP" */
+ 0x5F,0x5B,0x82,0x33,0x4D,0x4F,0x55,0x5F, /* 000004E8 "_[.3MOU_" */
+ 0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0, /* 000004F0 "._HID.A." */
+ 0x0F,0x13,0x14,0x09,0x5F,0x53,0x54,0x41, /* 000004F8 "...._STA" */
+ 0x00,0xA4,0x0A,0x0F,0x14,0x19,0x5F,0x43, /* 00000500 "......_C" */
+ 0x52,0x53,0x00,0x08,0x54,0x4D,0x50,0x5F, /* 00000508 "RS..TMP_" */
+ 0x11,0x08,0x0A,0x05,0x22,0x00,0x10,0x79, /* 00000510 "...."..y" */
+ 0x00,0xA4,0x54,0x4D,0x50,0x5F,0x5B,0x82, /* 00000518 "..TMP_[." */
+ 0x47,0x04,0x46,0x44,0x43,0x30,0x08,0x5F, /* 00000520 "G.FDC0._" */
+ 0x48,0x49,0x44,0x0C,0x41,0xD0,0x07,0x00, /* 00000528 "HID.A..." */
+ 0x14,0x09,0x5F,0x53,0x54,0x41,0x00,0xA4, /* 00000530 ".._STA.." */
+ 0x0A,0x0F,0x14,0x2C,0x5F,0x43,0x52,0x53, /* 00000538 "...,_CRS" */
+ 0x00,0x08,0x42,0x55,0x46,0x30,0x11,0x1B, /* 00000540 "..BUF0.." */
+ 0x0A,0x18,0x47,0x01,0xF2,0x03,0xF2,0x03, /* 00000548 "..G....." */
+ 0x00,0x04,0x47,0x01,0xF7,0x03,0xF7,0x03, /* 00000550 "..G....." */
+ 0x00,0x01,0x22,0x40,0x00,0x2A,0x04,0x00, /* 00000558 ".."@.*.." */
+ 0x79,0x00,0xA4,0x42,0x55,0x46,0x30,
};
Index: src/mainboard/via/epia-m/acpi_tables.c
===================================================================
--- src/mainboard/via/epia-m/acpi_tables.c (revision 3556)
+++ src/mainboard/via/epia-m/acpi_tables.c (working copy)
@@ -32,6 +32,9 @@
return current;
}
+#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1)
+#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
@@ -65,6 +68,7 @@
* We explicitly add these tables later on:
*/
printk_debug("ACPI: * FACS\n");
+ current = ALIGN(current, 64);
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
Index: src/mainboard/via/epia-m/fadt.c
===================================================================
--- src/mainboard/via/epia-m/fadt.c (revision 3556)
+++ src/mainboard/via/epia-m/fadt.c (working copy)
@@ -28,128 +28,56 @@
memset((void *)fadt,0,sizeof(acpi_fadt_t));
memcpy(header->signature,"FACP",4);
- header->length = 244;
+ header->length = 0x74;
header->revision = 1;
memcpy(header->oem_id,OEM_ID,6);
memcpy(header->oem_table_id,"COREBOOT",8);
memcpy(header->asl_compiler_id,ASLC,4);
- header->asl_compiler_revision=0;
fadt->firmware_ctrl=facs;
fadt->dsdt= dsdt;
- fadt->preferred_pm_profile=0;
fadt->sci_int=5;
- fadt->smi_cmd = 0;
- fadt->acpi_enable = 0;
- fadt->acpi_disable = 0;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0x0;
+ fadt->smi_cmd = 0x42F;
+ fadt->acpi_enable = 0xf1;
+ fadt->acpi_disable = 0xf0;
fadt->pm1a_evt_blk = 0x400;
- fadt->pm1b_evt_blk = 0x0;
fadt->pm1a_cnt_blk = 0x404;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = 0x0;
fadt->pm_tmr_blk = 0x408;
fadt->gpe0_blk = 0x420;
- fadt->gpe1_blk = 0x0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 0;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 4;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
- fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 90;
fadt->p_lvl3_lat = 900;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 0;
fadt->duty_width = 1;
fadt->day_alrm = 125;
fadt->mon_alrm = 126;
fadt->century = 50;
- fadt->iapc_boot_arch = 0x1;
- fadt->flags = 0x4a5;
+ //fadt->iapc_boot_arch = 0x1;
+ fadt->flags = 0x75;
- fadt->reset_reg.space_id = 0;
- fadt->reset_reg.bit_width = 0;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0x0;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 0;
+#if 0
fadt->x_firmware_ctl_l = facs;
- fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = dsdt;
- fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 4;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.resv = 3;
fadt->x_pm1a_evt_blk.addrl = 0x400;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-
fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 2;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.resv = 2;
fadt->x_pm1a_cnt_blk.addrl = 0x404;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = 0x0;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 4;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.resv = 3;
fadt->x_pm_tmr_blk.addrl = 0x408;
- fadt->x_pm_tmr_blk.addrh = 0x0;
+#endif
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 0;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = 0x420;
- fadt->x_gpe0_blk.addrh = 0x0;
-
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-
+ header->checksum = acpi_checksum((void *)fadt, 0x74);
}
Index: src/mainboard/via/epia-m/vgabios.c
===================================================================
--- src/mainboard/via/epia-m/vgabios.c (revision 3556)
+++ src/mainboard/via/epia-m/vgabios.c (working copy)
@@ -132,6 +132,7 @@
/* The address arguments to this function are PHYSICAL ADDRESSES */
static void real_mode_switch_call_vga(unsigned long devfn)
{
+ return;
__asm__ __volatile__ (
// paranoia -- does ecx get saved? not sure. This is
// the easiest safe thing to do.
@@ -232,6 +233,7 @@
epia-m does not always autosence the main console so forcing it on is good !! */
void vga_enable_console()
{
+ return;
__asm__ __volatile__ (
/* paranoia -- does ecx get saved? not sure. This is
* the easiest safe thing to do. */
@@ -584,7 +586,7 @@
}
printk_debug("biosint: Bailing out\n");
// "longjmp"
- vga_exit();
+ //vga_exit();
break;
case PCIBIOS:
Index: src/mainboard/via/epia-m/dsdt.asl
===================================================================
--- src/mainboard/via/epia-m/dsdt.asl (revision 3556)
+++ src/mainboard/via/epia-m/dsdt.asl (working copy)
@@ -248,10 +248,141 @@
})
+ Name (_CRS, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x00FF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0100, // Address Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Address Range Minimum
+ 0x0CF8, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x08, // Address Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0CF8, // Address Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0D00, // Address Range Minimum
+ 0xFFFF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0xF300, // Address Length
+ ,, , TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x000A0000, // Address Range Minimum
+ 0x000BFFFF, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00020000, // Address Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinNotFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0xE0000000, // Address Range Minimum
+ 0xFEBFFFFF, // Address Range Maximum
+ 0x1EC00000, // Address Translation Offset
+ 0x00000000, // Address Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
} // End of PCI0
} // End of _SB
+ Scope(\_SB.PCI0) {
+ /* Real-time clock */
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0070, 0x0070, 0x10, 0x02)
+ IRQNoFlags () {8}
+ IO (Decode16, 0x0072, 0x0072, 0x02, 0x06)
+ })
+ }
+
+ /* Keyboard seems to be important for WinXP install */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0060, // Address Range Minimum
+ 0x0060, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x01, // Address Length
+ )
+ IO (Decode16,
+ 0x0064, // Address Range Minimum
+ 0x0064, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x01, // Address Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate ()
+ {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 floppy controller */
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ Return (BUF0)
+ }
+ }
+
+ }
+
} // End of Definition Block
Index: src/mainboard/via/epia-cn/Config.lb
===================================================================
--- src/mainboard/via/epia-cn/Config.lb (revision 3556)
+++ src/mainboard/via/epia-cn/Config.lb (working copy)
@@ -90,14 +90,17 @@
device pci 0.4 on end # Power Management
device pci 0.7 on end # V-Link Controller
device pci 1.0 on end # PCI Bridge
+ device pci 09.0 on end # Ethernet
+ device pci 0b.0 on end # Ethernet
chip southbridge/via/vt8237r # Southbridge
+ device pci f.1 on end # IDE
# Enable both IDE channels.
register "ide0_enable" = "1"
register "ide1_enable" = "1"
# Both cables are 40pin.
register "ide0_80pin_cable" = "0"
register "ide1_80pin_cable" = "0"
- device pci f.0 on end # IDE
+ device pci f.0 on end # SATA
register "fn_ctrl_lo" = "0x80"
register "fn_ctrl_hi" = "0x1d"
device pci 10.0 on end # OHCI
@@ -107,7 +110,7 @@
device pci 10.4 on end # EHCI
device pci 10.5 on end # UDCI
device pci 11.0 on # Southbridge LPC
- chip superio/via/vt1211 # Super I/O
+ chip superio/fintek/f71805f # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
@@ -133,7 +136,6 @@
end
device pci 11.5 on end # AC'97 audio
# device pci 11.6 off end # AC'97 Modem
- device pci 12.0 on end # Ethernet
end
end
device apic_cluster 0 on # APIC cluster
Index: src/northbridge/via/cn700/vgabios.c
===================================================================
--- src/northbridge/via/cn700/vgabios.c (revision 3556)
+++ src/northbridge/via/cn700/vgabios.c (working copy)
@@ -132,6 +132,7 @@
/* The address arguments to this function are PHYSICAL ADDRESSES */
static void real_mode_switch_call_vga(unsigned long devfn)
{
+ return;
__asm__ __volatile__ (
// paranoia -- does ecx get saved? not sure. This is
// the easiest safe thing to do.
@@ -232,6 +233,7 @@
epia-m does not always autosence the main console so forcing it on is good !! */
void vga_enable_console()
{
+ return;
__asm__ __volatile__ (
/* paranoia -- does ecx get saved? not sure. This is
* the easiest safe thing to do. */
@@ -356,7 +358,8 @@
/* declare rom address here - keep any config data out of the way
* of core LXB stuff */
- rom = 0xfff80000;
+ //rom = 0xfff80000;
+ rom = 0xfffc0000;
pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
printk_debug("rom base, size: %x\n", rom);
@@ -584,7 +587,7 @@
}
printk_debug("biosint: Bailing out\n");
// "longjmp"
- vga_exit();
+ //vga_exit();
break;
case PCIBIOS:
Index: src/northbridge/via/cn700/vga.c
===================================================================
--- src/northbridge/via/cn700/vga.c (revision 3556)
+++ src/northbridge/via/cn700/vga.c (working copy)
@@ -44,10 +44,12 @@
{
u8 reg8;
+#if 0
print_debug("Copying BOCHS Bios to 0xf000\n");
/* Copy BOCHS BIOS from 4G-ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
* This is for compatibility with the VGA ROM's BIOS callbacks */
memcpy(0xf0000, (0xffffffff - ROM_SIZE - 0xffff), 0x10000);
+#endif
printk_debug("Initializing VGA\n");
@@ -79,6 +81,7 @@
//printk_debug("Enable VGA console\n");
//vga_enable_console();
+#if 0
/* It's not clear if these need to be programmed before or after
* the VGA bios runs. Try both, clean up later */
/* Set memory rate to 200MHz */
@@ -96,6 +99,7 @@
/* Clear the BOCHs Bios out of memory, so it doesn't confuse linux */
memset(0xf0000, 0, 0x10000);
+#endif
}
static void vga_read_resources(device_t dev)
Index: src/arch/i386/boot/tables.c
===================================================================
--- src/arch/i386/boot/tables.c (revision 3556)
+++ src/arch/i386/boot/tables.c (working copy)
@@ -42,8 +42,8 @@
unsigned long low_table_start, low_table_end, new_low_table_end;
unsigned long rom_table_start, rom_table_end;
- rom_table_start = 0xf0000;
- rom_table_end = 0xf0000;
+ rom_table_start = ((1024-32)*1024*1024) - 64*1024;
+ rom_table_end = rom_table_start;
/* Start low addr at 16 bytes instead of 0 because of a buglet
* in the generic linux unzip code, as it tests for the a20 line.
*/
@@ -67,9 +67,10 @@
post_code(0x96);
/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
- new_low_table_end = write_smp_table(low_table_end); // low_table_end is 0x10 at this point
+ rom_table_end = write_smp_table(rom_table_end);
+ rom_table_end = (rom_table_end+1023) & ~1023;
-#if HAVE_MP_TABLE==1
+#if 0 // HAVE_MP_TABLE==1
/* Don't write anything in the traditional x86 BIOS data segment,
* for example the linux kernel smp need to use 0x467 to pass reset vector
* or use 0x40e/0x413 for EBDA finding...
Index: src/arch/i386/include/arch/acpi.h
===================================================================
--- src/arch/i386/include/arch/acpi.h (revision 3556)
+++ src/arch/i386/include/arch/acpi.h (working copy)
@@ -285,7 +285,7 @@
u32 x_firmware_waking_vector_l;
u32 x_firmware_waking_vector_h;
u8 version;
- u8 resv[33];
+ u8 resv[31];
} __attribute__ ((packed)) acpi_facs_t;
/* These are implemented by the target port */
Index: targets/emulation/qemu-x86/Config.lb
===================================================================
--- targets/emulation/qemu-x86/Config.lb (revision 3556)
+++ targets/emulation/qemu-x86/Config.lb (working copy)
@@ -14,7 +14,9 @@
option ROM_IMAGE_SIZE=0x10000
option COREBOOT_EXTRA_VERSION="-GRUB2"
# payload /home/stepan/core.img
- payload ../payload.elf
+# payload ../payload.elf
+# payload /home/kevin/src/coreboot/filo-0.5/filo.elf
+ payload /home/kevin/src/coreboot/legacybios/out/bios.bin.elf
end
buildrom ./coreboot.rom ROM_SIZE "image"
Index: targets/amd/serengeti_cheetah/Config.lb
===================================================================
--- targets/amd/serengeti_cheetah/Config.lb (revision 3556)
+++ targets/amd/serengeti_cheetah/Config.lb (working copy)
@@ -21,6 +21,8 @@
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option CONFIG_CONSOLE_VGA=1
+ option CONFIG_PCI_ROM_RUN=1
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
@@ -38,7 +40,8 @@
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
- payload ../payload.elf
+ payload /home/kevin/src/coreboot/legacybios/out/bios.bin.elf
+# payload ../payload.elf
end
romimage "fallback"
@@ -50,6 +53,8 @@
# option ROM_IMAGE_SIZE=0x15800
option XIP_ROM_SIZE=0x40000
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option CONFIG_CONSOLE_VGA=1
+ option CONFIG_PCI_ROM_RUN=1
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
@@ -71,7 +76,9 @@
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
- payload ../payload.elf
+# payload $(HOME)/src/coreboot/filo-0.5/filo.elf
+ payload /home/kevin/src/coreboot/legacybios/out/bios.bin.elf
+# payload ../payload.elf
end
romimage "failover"
Index: targets/via/epia-m/Config.lb
===================================================================
--- targets/via/epia-m/Config.lb (revision 3556)
+++ targets/via/epia-m/Config.lb (working copy)
@@ -4,12 +4,11 @@
mainboard via/epia-m
option MAXIMUM_CONSOLE_LOGLEVEL=8
-option DEFAULT_CONSOLE_LOGLEVEL=8
+option DEFAULT_CONSOLE_LOGLEVEL=1
option CONFIG_CONSOLE_SERIAL8250=1
-option ROM_SIZE=256*1024
+option ROM_SIZE=256*1024 - 64*1024
-
option HAVE_OPTION_TABLE=1
option CONFIG_ROM_PAYLOAD=1
option HAVE_FALLBACK_BOOT=1
@@ -21,7 +20,7 @@
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
-option FALLBACK_SIZE=131072
+option FALLBACK_SIZE=ROM_SIZE
## Coreboot C code runs at this location in RAM
option _RAMBASE=0x00004000
@@ -42,7 +41,9 @@
#option ROM_IMAGE_SIZE=128*1024
option ROM_IMAGE_SIZE=60*1024
option COREBOOT_EXTRA_VERSION=".0-Fallback"
- payload $(HOME)/svn/payload.elf
+# payload $(HOME)/svn/payload.elf
+# payload $(HOME)/src/coreboot/filo-0.5/filo.elf
+ payload $(HOME)/src/coreboot/legacybios/out/bios.bin.elf
end
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback"
Index: targets/via/epia-cn/Config.lb
===================================================================
--- targets/via/epia-cn/Config.lb (revision 3556)
+++ targets/via/epia-cn/Config.lb (working copy)
@@ -33,11 +33,13 @@
# Generate the final ROM like this:
# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
#
-option ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024)
+#option ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024)
+option ROM_SIZE = (256 * 1024) - (64 * 1024)
romimage "image"
option COREBOOT_EXTRA_VERSION = "-epiacn"
- payload ../payload.elf
+# payload ../payload.elf
+ payload $(HOME)/src/coreboot/legacybios/out/bios.bin.elf
end
buildrom ./coreboot.rom ROM_SIZE "image"
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