[coreboot] v2: [RFC] Dynamic RAM detection for intel/i440bx

[Tim ter Laak]

On Sun, 14 Sep 2008, Mats Erik Andersson wrote:

> Hello all,
>
> I send a patch which is not intended for insertion as is,
> but I have to draw the line somewhere in order to get your
> comments.

Thanks. I'll do some testing with this one.

> The patch alters
>
>  coreboot-v2/src/northbridge/intel/i440bx/raminit.c
>
> and it implements dynamic calculation of the registers
> DRB#, RPS and PGPOL. It does this using alternate methods,
> chosen by macro switches in the beginning of the file.

I guess you'd like feedback on success/failure for both methods?

> These differences are probably due to my
> incomplete understanding of the northbridge register MBSC, as
> well as the buffer strength bits in NBXCFG.

The basics of buffer strength boil down to this: The Northbridge is the 
source of address and control signals; the DRAM chips on the DIMMs are 
loads on these signals. The bigger the load on a particular signal, the 
stronger the signal needs to be asserted by the northbridge, so as to make 
the signal strong enough within the required time.

Usually, the load on the data lines depends only on the number of DIMM 
"sides" that are present. The load on address and other control lines also 
depends on the number of chips each "side" consists of (which is related 
to the data width of the DRAM chips). When more chips need to be connected 
to the same signal, the load is higher and the buffer needs to be 
stronger.

Unfortunately, blindly setting the buffers to the biggest strength is not 
a good idea either, as this will result in signal "overshoot" when the 
actual load is rather low. This means the signal will rapidly fluctuate 
before stabilizing on its final value, which may take too long.

The exact implementation details are unknown to me though. I guess I'll 
put different combinations of DIMMs in the board and see how the stock 
BIOS sets up the MBSC.

> Since ms6147 only has two DIMM-slots, I have not been able to
> test the patch for use with USE_DIMM2 or USE_DIMM3 activated.

The AB-BM6 I'm working on has 3 slots, and I usually have all 3 populated. 
For my first test I didn't have USE_DIMM2 activated, but it still booted 
into Coreinfo with the full 384 MB (3 * 128) reported. Probably there's a 
lot of luck involved there.

> The function do_ram_command() has two outcommented work arounds
> in order to activate the different RAM position, but a true dynamic
> code has not yet been taken into consideration.

Having looked at the code in i82830/raminit.c (as suggested by 
Joseph Smith, I think), I would suggest we copy and adjust that. Hopefully 
romcc can find the registers for the loop and the address calculation...
It also contains some code for SPD-based setup of RAM parameters, did you 
have a look there as well for inspiration?

Finally, a somewhat related question for a wider audience:
For obvious reasons I wanted to change to Memtest as my payload. As it 
turns out, the size of that is almost 100 kB, which is bigger than the 
64kB available (256 kB flashchip, normal and fallback images with each 64 
kB for coreboot and 64 kb for payload). I'm going to look if it is 
possible to make an image with only normal or fallback, and give the extra 
space to the payload. If anyone has some pointers for me, they would be 
most appreciated.

Kind regards,
 	Tim.