Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
The Advanced Configuration & Power Interface is an industry standard for letting the OS control power management.
Advanced Graphics Port, a point-to-point channel for attaching a video card to a mainboard with AGP slot.
The memory range that is set aside for AGP access.
The Advanced Host Controller Interface. Describes the register-level interface for a SATA host controller.
Advanced Programmable Interrupt Controller. An advanced version of a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound.
Base Address Register (on PCI device).
Basic Input/Output System.
The Built-In Self Test, a selftest run by the processor when it is first started. Usually, any nonzero value indicates that the selftest failed.
Cache as RAM.
Complementary metal oxyde semiconductor, a class of semiconductors. In the coreboot context CMOS (which is a bit of a misnomer here) usually refers to a chunk of non-volatile memory (NVRAM) in the PC, though.
Central processing unit (e.g. an Athlon64).
C Run Time 0 - This is now called the romstage in coreboot.
Sources that make up the romstage in coreboot, see crt0.
Decode Control Register.
Device ID, a way of identifying the hardware in question. See VID for more info.
Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card. DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.
Differentiated System Descriptor Table, generated by BIOS and necessary for ACPI. Implementation of ACPI in coreboot needs to be done in a "cleanroom" development process to avoid legal issues.
Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).
Enhanced Host Controller Interface (USB host controller).
Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.
The Framebuffer is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen. A framebuffer is either:
Graphics Address Relocation Table.
Graphics Aperture Translation Table.
Graphic NorthBridge.
Part of the newer AMD Fusion chips.
General Purpose Ports.
Part of the newer AMD Fusion chips.
General Purpose Input/Output.
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.
Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient inter-IC control.
Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?
Interrupt ReQuest (Handler).
Debugging and test 4-wire interface named after an organization which defined it.
is the Linuxbios ARchiver, now called Lightweight ARchiver. It is a small utility that we use to create and change coreboot images and their modules.
Low Pin Count, an interface aimed at replacing the ISA bus.
Least Recently Used, a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.
Memory training is a very complex technlogical area. We are accumulating references to it as we find them.
It is amazing, but there is very little out there.
Media Independent Interface. This is a chip commonly found on ethernet devices, together with a PHY.
Memory-mapped I/O and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.
Multi Processor Table. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.
Memory Type Range Register. This can be used to control the way a processor accesses memory ranges.
Open Host Controller Interface. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).
Programmable Attribute Map. Hardware registers that describe how certain memory areas are accessed. The BIOS areas have a flash chip mapped on top of a piece of memory. By changing the PAM registers, accesses to these memory areas can be mapped to either the RAM or the flash device. Shadowing is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the PAM registers are part of the southbridge of a system.
Page Attribute Table. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.
Performance Acceleration Technology.
Peripheral Component Interconnect.
PHY layer device. A device that provides low level access to the physical layer.
A Programmable Interrupt Controller is a device to control peripheral devices, offloading the main CPU.
Programmed Input/Output interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.
Programmable Interrupt Routing?
PCI IRQ routing table,
Plastic Leaded Chip Carrier, a square surface-mount chip package.
Phase Locked Loop is a device to keep (electrical) signals synchronised throughout the system.
The Power On Self Test is a test to check that devices the computer will rely on are functioning, and initializes devices.
Remote Direct Memory Access is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.
Revision control systems.
Southbridge. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...
SideBand Addressing.
RAM which content is copied from ROM residing at the same address for speedup purposes.
Serial Input/Output.
The System Management Bus is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.
System Management Mode. Processor mode that is mainly used for power management purposes.
System Management Random Access Memory.
Small-Outline Integrated Circuit.
Serial Presence Detect. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.
The Serial Peripheral Interface Bus is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.
The SuperIO is the chip that provides floppy, serial and parallel functionality/ports.
Physical board format - a wider version of ATX with different standoff placement https://en.wikipedia.org/wiki/SSI_EEB
If your desired case has enough space for an SSI-EEB motherboard on the board tray you can always drill and tap (thread) your own holes for the standoffs if you do not wish to buy another enclosure. (remove the tray first and wipe it off to make sure there is no metal dust or fragments before you put it back)
Translation Lookaside Buffer. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.
Strong UnCacheable. Memory type setting in MTRR/PAT.
UnCacheable. Memory type setting in MTRR/PAT.
Universal Host Controller Interface. USB standard.
Unified Media Interface
The purpose of the VGAcon (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).
Vendor ID, a way of identifying the hardware manufacturer.
A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.
VERSAmodule Eurocard Bus or Versa Module Europa Bus. A computer bus originally developed for the Motorola 68000.
Write-Back. Memory type setting in MTRR/PAT.
Write-Combining. Memory type setting in MTRR/PAT.
Write Protected. Memory type setting in MTRR/PAT.
Write-Through. Memory type setting in MTRR/PAT.