This site lists all previous Google summer of Code projects related to coreboot.

2014

Generic Interface using alternate CBFS access patterns for ARM SoCs

• http://blogs.coreboot.org/blog/2014/05/01/moin-a-new-beginning/
• http://blogs.coreboot.org/blog/2014/05/11/pre-gsoc-set-up-phase-i/
• http://blogs.coreboot.org/blog/2014/05/20/pre-gsoc-set-up-phase-ii/
• http://blogs.coreboot.org/blog/2014/05/29/cbfs_media-week-1/
• http://blogs.coreboot.org/blog/2014/06/09/gsoc-2014-cbfs_media-updates/
• http://blogs.coreboot.org/blog/2014/06/24/gsoc-2014cbfs_media-stage-1-mission-accomplished/
• http://blogs.coreboot.org/blog/2014/07/04/gsoc-2014-cbfs_media-stage-2/
• http://blogs.coreboot.org/blog/2014/07/17/gsoc-2014-payload-loading-success/

Enhance early coreboot debugging

• http://blogs.coreboot.org/blog/2014/05/05/gsoc-early-debugging-the-very-short-introduction/
• http://blogs.coreboot.org/blog/2014/05/30/gsoc-board-status-update/
• http://blogs.coreboot.org/blog/2014/08/03/gsoc-infrastructure-along-the-way-something-went-terribly-wrong/

flashrom

• http://blogs.coreboot.org/blog/2014/05/04/gsoc-2014-flashrom-do-i-need-to-introduce-myself/
• http://blogs.coreboot.org/blog/2014/06/04/gsoc-2014-flashrom-rise-like-a-phoenix/
• http://blogs.coreboot.org/blog/2014/07/30/gsoc-2014-flashrom-support-for-intel-bay-trail-rangeleyavoton-and-wildcat-point/

2013

coreboot cheap testing rig

The goal of this project is to create a cheap testing rig which works with the existing board test infrastructure. We have a hardware test system since 2006:

• Quality Assurance Talk (Slides)
• Test Integration Manual
• Test Developers Manual
• Test Specification

The initial version of our testing rig used a remote power switch and was rather expensive. With cheaper technologies such as X10, it's possible to drop the testing costs per board significantly.

Links

• InSystemFlasher is a cheap DIY hardware prototype for building an automated testing rig for modern SPI-based boards. This could be used as a starting point.

Report

• http://blogs.coreboot.org/blog/2013/06/20/hello/
• http://blogs.coreboot.org/blog/2013/07/01/gsoc-coreboot-progress-till-week-2/
• http://blogs.coreboot.org/blog/2013/07/19/gsoc-coreboot-week-3-and-4/
• http://blogs.coreboot.org/blog/2013/08/07/gsoc-coreboot-week-5-7-redesigning-the-test-interface-board/
• http://blogs.coreboot.org/blog/2013/09/09/gsoc-coreboot-test-interface-board-complete/
• Final report with download

A universal USB-based FWH/LPC/SPI programmer

While flashing SPI chips can be done externally with relative ease using flashrom, hardware to program FWH and LPC chips is beyond the reach of most enthusiasts. Cortex-M processors have become well-established in the open source community due to their low cost and extensive ecosystem. This makes them an ideal candidate for a universal ROM programmer. I propose a hardware/software/firmware ecosystem for a universal ROM programmer based on Cortex-M processors.

Report

• http://blogs.coreboot.org/blog/2013/06/07/hello-world/
• http://blogs.coreboot.org/blog/2013/06/09/launch-control-and-a-brief-test-flight/
• http://blogs.coreboot.org/blog/2013/06/14/a-biology-laboratory-dissecting-the-lpc-bus/
• http://blogs.coreboot.org/blog/2013/06/23/vultureprog-meet-the-contenders/
• http://blogs.coreboot.org/blog/2013/06/29/qiprog-the-soft-side-of-vultureprog/
• http://blogs.coreboot.org/blog/2013/07/03/cooking-with-thin-spaghetti-the-hard-side-of-vultureprog/
• http://blogs.coreboot.org/blog/2013/07/20/qiprog-expanding-the-flight-range/
• http://blogs.coreboot.org/blog/2013/07/25/vultureprog-equipped-for-galactic-travel/
• http://blogs.coreboot.org/blog/2013/08/07/vultureprog-command-center/
• http://blogs.coreboot.org/blog/2013/08/14/3265/
• http://blogs.coreboot.org/blog/2013/08/20/a-brief-progress-sheet/
• http://blogs.coreboot.org/blog/2013/08/27/retrofitting-qiprog-for-the-space-age/
• http://blogs.coreboot.org/blog/2013/09/25/pencils-down/
• Final report with download

Prepare for the lack of super-io UARTs and serialports on new mainboards

There are some common debugging problems people come across when starting a port of a new mainboard for coreboot. First is the flashchip being soldered on the mainboard and second is the lack of serial port connector. I attempt to attack both of these on some level. My primary goals are to add support for memory-mapped serial UARTs and the ECHI debug port mechanism on the commonly used payloads, and to integrate a pre-OS flash writing mechanism in the toolchain to allow easy and safe deployment of new coreboot builds.

Results

• http://blogs.coreboot.org/blog/2013/06/07/new-coreboot-debugging-solutions/
• http://blogs.coreboot.org/blog/2013/06/25/kick-starting-with-some-maintenance/
• http://blogs.coreboot.org/blog/2013/07/02/now-it-is-broken-now-it-is-not/
• http://blogs.coreboot.org/blog/2013/07/09/gsoc-early-debugging-art-of-refactor/
• http://blogs.coreboot.org/blog/2013/08/06/gsoc-early-debugging-agesa-woes/
• http://blogs.coreboot.org/blog/2013/08/20/gsoc-early-debugging-usb-submission/
• http://blogs.coreboot.org/blog/2013/08/28/gsoc-early-debugging-bridging-the-gap/
• http://blogs.coreboot.org/blog/2013/09/05/gsoc-early-debugging-more-connectivity/
• http://blogs.coreboot.org/blog/2013/09/23/gsoc-early-debugging-closure/
• Final report with download

flashrom: infrastructure improvements galore

The plan is to tackle some long-standing infrastructure problems that have to be fixed eventually if we want to continue current and future flash chips. The expected outcome of my GSoC programming are the following new features:

• Support for multiple read/write operations
• Support for 4-byte addresses
• Improved (SPI) probing

Results

• http://blogs.coreboot.org/blog/2013/05/28/gsoc-2013-flashrom-hi-there-again/
• http://blogs.coreboot.org/blog/2013/06/26/gsoc-2013-flashrom-week-1-while1/
• http://blogs.coreboot.org/blog/2013/07/01/gsoc-2013-flashrom-week-2/
• http://blogs.coreboot.org/blog/2013/07/10/gsoc-2013-flashrom-week-3/
• http://blogs.coreboot.org/blog/2013/07/16/gsoc-2013-flashrom-week-4/
• http://blogs.coreboot.org/blog/2013/08/12/gsoc-2013-flashrom-blog-post-5/
• http://blogs.coreboot.org/blog/2013/08/29/gsoc-2013-flashrom-blog-post-6/
• http://blogs.coreboot.org/blog/2013/09/04/gsoc-2013-flashrom-blog-post-7/
• http://blogs.coreboot.org/blog/2013/09/12/gsoc-2013-flashrom-blog-post-8/
• Final report with download

2012 - No GSoC

Regretfully, coreboot was not selected for GSoC 2012.

2011 Projects

Spice Payload

The rationale behind the Coreboot Spice Payload is a software component to provide a virtualized desktop to small devices with minimal hardware and software resources. Once the most of the intensive CPU and GPU tasks are moved to the spice server it is possible to set poor devices with a full functional desktop and minimal software requirements in the client side.

Links

• http://blogs.coreboot.org/blog/2011/05/18/gsoc-2011-coreboot-spice-payload/
• http://blogs.coreboot.org/blog/2011/05/21/gsoc-2011-new-toys-comming-part-i/
• http://blogs.coreboot.org/blog/2011/06/15/gsoc-2011-week-2-coreboot-spice-payload/
• http://blogs.coreboot.org/blog/2011/07/12/spice-payload-before-midterm-gsoc-report/
• http://blogs.coreboot.org/blog/2011/07/14/gsoc-2011-new-toys-comming-part-ii/
• http://blogs.coreboot.org/blog/2011/07/15/gsoc2011-spice-payload-midterm-report/
• http://blogs.coreboot.org/blog/2011/07/25/gsoc2011-coreboot-spice-payload-oe-and-rootfs/
• http://blogs.coreboot.org/blog/2011/08/24/gsoc-spice-payload-report/

Student

• Leandro Dorileo

Mentors

• Marc Jones

Porting coreboot to ARM

This includes building basic ARM layout for coreboot and porting it to some available SOCs.

ARM SOC's with PCIe are now on the market for tablets, netbooks and servers. These systems can take advantage of coreboot's strength in properly configuring PCI, SAS, SATA and SCSI devices; fast boot times; and payload support.

Links

• http://blogs.coreboot.org/blog/2011/05/11/gsoc2011-project-porting-coreboot-to-arm-architecture/
• http://blogs.coreboot.org/blog/2011/06/05/gsoc2011week-1-analysis-of-u-boot-arm-boot-code/
• http://blogs.coreboot.org/blog/2011/06/25/gsoc2011week-5-the-layout-of-coreboot-rom-and-cbfstool-for-arm/
• http://blogs.coreboot.org/blog/2011/07/15/gsoc2011-midterm-report/
• http://blogs.coreboot.org/blog/2011/07/20/gsoc2011week-9-boot-arm-using-coreboot-to-romstage/

Student

• Yang Bai (Hamo)

Mentors

• Wang Qing Pei

Coreboot panic room. Diagnostics (also remote flashing)

To help developing coreboot code, we have to set-up remote diagnostics (also flashing) interface in coreboot. We will be able to renew a bricked board through serial port or even do some research through registers in case of panic(). This will enable easier development of CAR, chipset, payloads code.

Links

• http://blogs.coreboot.org/blog/2011/05/09/gsoc-project-coreboot-panic-room-diagnostics-also-remote-flashing/
• http://blogs.coreboot.org/blog/2011/07/01/ts/
• http://blogs.coreboot.org/blog/2011/07/15/panic/
• http://blogs.coreboot.org/blog/2011/08/10/gsoc-2011-little-trip/

Student

• Tadas Slotkus

Mentors

• Stefan Reinauer

flashrom: add support for the EC inside Intel's ICHs

Flashrom is a program used to read and write directly from/to flash memories such as "BIOS" chips on computer mainboards. In the case of PCs and laptops the access to the memory chips is often controlled by the chipset or other chips (embedded controllers). In the case of newer Intel chipsets it is unknown how the unlocking exactly works and there is no public datasheet explaining it. This project tries to reverse engineer how it works and will re-implement it to allow flashrom to work with newer Intel chipsets when they are configured to be "locked down".

Links

• http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/
• http://blogs.coreboot.org/blog/2011/06/24/gsoc-2011-flashrom-part-2-sfdp/
• http://blogs.coreboot.org/blog/2011/07/15/gsoc-2011-flashrom-part-3-midterm-evaluation/
• http://blogs.coreboot.org/blog/2011/08/13/gsoc-2011-flashrom-part-4-recap/
• http://blogs.coreboot.org/blog/2011/08/17/gsoc-2011-flashrom-part-5-–-dear-intel/

Student

• Stefan Tauner

Mentors

• Carl-Daniel Hailfinger

2010 Projects

USB drivers for libpayload

OHCI and XHCI drivers for libpayload.

Notice that libpayload code must be licensed BSD-style (so ports from FILO, SeaBIOS or Linux won't work). Pick a given set and tell us why it's enough work for the allocated time, but not too much for you. Also, which sources (if any) you want to draw from. We will not accept code that has been taken from other (GPL) projects. If you are taking this project you have to be willing and capable of writing your own hardware drivers.

Links

• http://blogs.coreboot.org/blog/author/patrickgeorgi/

Student

• Patrick Georgi

Mentors

• Stefan Reinauer

TianoCore on coreboot

Tiano Core is Intel's EFI implementation. Unlike coreboot, it is not a firmware, but rather a bootloader. In 2008 there was an initial port of TianoCore to run on coreboot, but there are many things left to do.

• Improve Tiano Core / EDK2 running as a coreboot payload
• Implement a coreboot framebuffer driver for Tiano Core
• Implement a coreboot flash filesystem (CBFS) driver for Tiano Core
• Integrate and automate check out and build process of Tiano Core
• Create CorebootPkg using OVMF instead of DUET.
• Provide a script that creates working binaries for the EDK shell, EDK apps, FAT driver(?), ...
• The final work must compile on a cross gcc, and coreboot's crossgcc script has to be adapted so it can build this compiler (if the default script is not capable of doing so yet)

This project requires no hardware skills, but especially in case of TianoCore will require knowledge of Microsoft compilers as well as the GNU tool chain.

Student

• Robert Austin

Links

• http://blogs.coreboot.org/blog/author/robertaustin/
• Tiano Core
• https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2/

Mentors

• Ron Minnich
• Stefan Reinauer
• Marc Jones

Payload infrastructure

Incorporate payload building into the coreboot build. kconfig options could be added for supported payloads, those payload could be updated to build with kconfig as well. Payloads that build with libpayload need would need default configs. Payloads should also be built with the crossgcc tools. This is related to the libpayload and board config infrastructure above. ---MJones

Student

• Cai Bai Yin

Links

• http://blogs.coreboot.org/blog/author/caibaiyin/

Mentors

• MJones

flashrom

Note: The list below is an idea collection. Individual list items are simple enough to serve only as partial GSoC task, but they are grouped to reasonable tasks. If you're interested, please talk to us on the flashrom mailing list and/or on IRC irc://irc.freenode.net/#flashrom

http://www.flashrom.org/GSoC/2010 has more flashrom ideas and suggestions.

Student

• Carl-Daniel Hailfinger

Links

• http://blogs.coreboot.org/blog/author/carldanielhailfinger/

Mentor

• Stefan Rienaur

coreboot mass-porting to AMD 780 series mainboards

Grab a couple of AMD 780 based mainboards and port coreboot to it.

Student

• Qing Pei (Jason) Wang

Links

• http://blogs.coreboot.org/blog/author/wangqingpei/

Mentors

• Ron Minnich
• Stefan Reinauer
• Marc Jones

Projects 2009

VGA BIOS for Geode LX

This project's goal is to write a VGA BIOS (PCI option rom) for AMD Geode LX systems (such as the Linutop, Thincan or XO). There exists a free VGA BIOS but it knows nothing about real hardware. If you really want to kick the iron, this project could be enhanced to contain a complete infrastructure for including hardware initialization code for many different graphics cards.

Links

• free VGA BIOS

Mentors

• Ward Vandewege
• Stefan Reinauer
• Marc Jones
• Peter Stuge

USB Option ROM for SeaBIOS

SeaBIOS is our latest and greatest way to boot all kinds of different operating systems. It is a coreboot payload that implements 16bit BIOS interrupts as they are needed by nearly all boot loaders today. In the last year, SeaBIOS learned how to cope with coreboot ACPI, and how to boot off SCSI drives. One major feature that we're desperately lacking is USB stick/disk/cdrom booting from SeaBIOS. USB support for SeaBIOS should be implemented as a PCI option rom, using the libpayload USB stack. The USB stack currently supports UHCI controllers. Part of this project could also be to add OHCI and EHCI support to the USB stack in libpayload (not a requirement for participation, but would sure be nice!)

Links

• SeaBIOS
• libpayload
• BIOS Boot Specification
• BIOS Enhanced Disk Drive Specification
• Low Cost Embedded x86 Teaching Tool by Darmawan Salihun contains an Option ROM example
• Another Option ROM example

Mentors

• Marc Jones
• Patrick Georgi
• Stefan Reinauer

AVATT part 2

AVATT is coreboot+Linux+KVM as hypervisor in the ROM. A first version was done during last GSoC, but there is still a pretty big TODO list.

TODO

• make the kvm userspace tool not to crash anymore. A possible solution would be to fix the TLS issues from the version of uClibc we currently use (daily snapshots from their SVN tree). This could even mean porting the uClibc-nptl branch to x86 if both of the x86 linuxthreads branches prove to be too hard to fix.
• user-friendly tool that can create and run virtual machines.
• automatically starting the virtual machines at boot.
• get the network to work in qemu since it fails with both coreboot v2 and v3.
• integrate the virt-manager daemon inside the ROM image, if it and its dependencies fit the remaining free space. This needs network support, to really be useful.
• fix compilation on x86_64 boxes by compiling everything in 64bit mode. We need a 64bit hardware anyway since the SVM instructions are available only on recent 64 bit boxes so this shouldn't matter too much, except for some extra wasted ROM space caused by the 64bit code. We can't cross-compile because we're not using a full toolchain, like buildroot does.
• keep the versions as up-to-date as possible but also compatible with each other

Mentors

• Carl-Daniel Hailfinger
• Ron Minnich
• Stefan Reinauer

Projects 2008

SCSI booting in coreboot

Currently coreboot can not boot from an arbitrary SCSI controller. There are two solutions for the problem:

• Use Linux and Kexec. This requires to keep the SCSI driver in the flash chip.
• Use x86emu/vm86/ADLO and the int13 method. This would allow to use the PCI option rom available on all modern SCSI controllers.

So we obviously need a solution based on the later. This could as well be implemented as a Linux program, as an intermediate payload, or as a shared library.

The code you are going to write needs to catch the int13 interrupt vector that the SCSI option rom installs and make it available to arbitrary (firmware/payload) code trying to load something from disk.

This is a coreboot v3 project.

All Virtual All The Time (AVATT)

The goal here is to build a system that comes up running Linux and KVM from power on reset. From that point the system could boot anything -- Windows, Linux, *BSD, Plan 9 -- anything that runs on x86 32 and 64-bit architectures. Coreboot would be integrated with a Linux kernel and initrd that had KVM built in. The initrd would include the minimal set of tools needed for starting new KVM virtual machine guests. Note that Linux booting from coreboot is a solved problem, using the buildrom tool, so the main effort here is to develop a minimal KVM infrastructure that can fit in a 2Mbyte FLASH part. Linux + X11 have been demonstrated in a 1Mbyte part, so we feel that this task is not impossible, but will be a terrific learning experience for a student, and will provide the community with a valuable resource when it is finished. The Xen and KVM communities have both asked for this capability for some time now, so there is a group of people ready to use this system when it is finished.

coreboot graphical port creator

In coreboot v2, every port to a new mainboard requires that you touch a lot of source files with only minimal changes. In version 3 we try to fix this issue and pack all mainboard specific information into a configuration file that we call the Device Tree Source (DTS). This Device Tree config file is a simple text file describing what static (non-detectable and/or soldered on) devices are used on the mainbard and how they are wired (SPD-ROM, Interrupt Routing, SuperIO, Northbridge, Southbridge, Hypertransport,..). It is mostly organized as a tree (with some special cases, Hypertransport allows cycles for instance)

The idea is to create a tool, based on the [www.eclipse.org/ Eclipse IDE], Swing, or your favourite portable toolkit, which allows you to drag and drop those components together and describe how they are wired.

This would be a great help for mainboard vendors that build mainboards of already supported components. No more reading of coreboot code would be required, but rather only the understanding of the hardware, and probably the mainboard schematics.

This is a coreboot v3 project. It requires good Java and/or Eclipse skills (or whatever toolkit/language you choose)

libpayload

There are many, many "payloads" for coreboot these days: Linux, FILO, GRUB2, Tiano Core, Open Firmware, etherboot, and some more to count. All these payloads have a few functions in common that they use to read information from coreboot or change coreboot settings in NVRAM. It would be incredibly useful to unify all this code and enhance it, so that not every coreboot payload has to keep reinventing the wheel.

Projects 2007

Booting Windows and other Operating Systems in LinuxBIOS [1]

The goal of this sub project is to figure out how to boot Windows Vista/XP/2003. There are three approaches that might proof successful:

• using a dedicated LinuxBIOS loader (ie. adapting ReactOS FREELDR)
• booting Windows on top of Linux using kexec/kboot
• fixing ADLO so that it boots Vista/XP and removing the mainboard dependencies in it's code.
• Some information on usage of bios services in Windows can be found here and here.

Port GRUB2 to work in LinuxBIOS

GRUB2 is going to be _the_ bootloader of choice in the forseeable future. As such, it could replace both Grub legacy and FILO, the LinuxBIOS hack for grub compatibility. FILO lacks many features that come with GRUB2 with no extra effort.

This task splits into four sub-problems:

• Add a target i386-linuxbios, next to i386-pc and i386-efi to the configuration process
• Add an IDE driver that does direct access instead of intXX calls
• Make the build process generate a single static ELF image, like it is done on Sparc
• Add support for reading the memory size from the LinuxBIOS table.

CMOS Config / Device Tree Browser Payload

Unlike other BIOSes, Linux has no such thing as a "CMOS setup". This does not mean that you can not configure it. There is a nice and small Linux command line utility called lxbios for that purpose. But people are often asking for a builtin config tool. Such a config tool could feature VGA graphics (maybe even VESA?), it should be easy to use, allow to browse information from LinuxBIOS' central structure: the device tree, and provide lxbios functionality with some sex appeal.

This is a LinuxBIOSv3 project.

Open Firmware payload for LinuxBIOS

Mitch Bradley from Firmworks, Inc. released the Open Firmware sources under a BSD license. The released code does work in LinuxBIOS, but could use some proper integration and testing on some hardware or in Qemu.

Some ideas:

• The released Open Firmware code is very much optimized towards the OLPC. A lot of things don't work yet on other systems, such as using a graphical framebuffer. Therefore things in LinuxBIOS need to be changed. For example, if LinuxBIOS initializes a graphics mode, it should add a LinuxBIOS table entry that specifies the address of the framebuffer and the depth and resolution.
• Add words to view the LinuxBIOS table in OFW
• Add words to change LinuxBIOS CMOS settings from OFW
• For LinuxBIOSv3, the start address of the payload can be variable. This is a fundamental change to v2, and will make life a lot easier and LinuxBIOS a lot more flexible. OFW requires to know its in-rom address at build time. This needs to be fixed to a dynamic behavior
• Also, there's no good documentation on what features can be used and how they can be used. Like the graphical OLPC menu, the built-in web server.
• Get a STOP-A like behavior working in Linux
• Get Smart Firmware working with new compilers
• Get Smart Firmware working as a payload
• Enhance the Distributed and Automated Testsystem to work with FILO and OpenFirmware payloads, and add The Hayes ANS Forth testsuite.

Some parts might require cooperation with other GSoC projects:

• Boot from Non-OFW SCSI controllers by running their int13 handler
• Boot Windows XP/2003/Vista in OFW

This project might benefit from Forth skills.

GNUFI or TianoCore payloads

There are two open source EFI implementations out there. GNUFI (or here or here) and TianoCore. Try getting those to work as LinuxBIOS payloads, or change LinuxBIOS so it can load them as payloads.

This project requires no hardware skills, but especially in case of TianoCore might require knowledge of Windows compilers (VC2005?)

Boot OpenSolaris, FreeBSD, NetBSD, OpenBSD or other free OSes

LinuxBIOS has (despite its name) been a little Linux centric. A nice project would be to analyze what it takes to get OpenSolaris, the BSDs or other free operating systems to work in LinuxBIOS, without the need for legacy emulation (ie. no ADLO)

Improve Linux as a BIOS [2]

There's a small project called buildrom which creates a payload from a Linux kernel and some user space utilities. It has been written to work with the OLPC. This project could be enhanced to work on all supported LinuxBIOS motherboards.

Porting Flashrom utility to Windows 2000/XP

Flashrom is used to burn LinuxBIOS binary to flash chips in the target motherboards. It runs on Unix/Linux. In this project the flashrom utility is ported from Linux/Unix to Windows 2000/XP. The Windows port is called Winflashrom. The project is divided into two tasks. The first task is to port most of the user space flashrom source code to MinGW and the second task is to code a Windows device driver to provide direct hardware access for the user space code. The difficulty of this task is in providing a reliable Windows device driver for the user space code.