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https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14893
Board:lenovo/g505s
2014-12-06T14:26:48Z
<p>Eocallaghan: /* Known Issues */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
* S3 Suspend/Resume - Nasty looking '''dmesg''' messages seen in Note 2. [https://lkml.org/lkml/2012/3/28/249 LKML] [https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1152484 bug report] [http://lxr.free-electrons.com/source/arch/x86/kernel/cpu/perf_event_amd_ibs.c#L784 force_ibs_eilvt_setup()].<br />
* "''AGP: Please enable the IOMMU option in the BIOS setup''" showing up in '''dmesg''' - Pass '''iommu=noaperture''' to the kernel boot args to ask the IOMMU not to touch the aperture for AGP.<br />
* "'''Re-enabling disabled Topology Extensions Support'''" showing up in '''dmesg''' - See Note 1.<br />
<br />
Note 1: Look in '''src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c''' for<br />
<br />
if (PkgType == PACKAGE_TYPE_FM2) {<br />
CpuMsrData |= BIT54;<br />
}<br />
<br />
this is the wrong package type for us. Fixed in [http://review.coreboot.org/#/c/7671/ 7671]<br />
<br />
<br />
Note 2: Look in '''src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c''' and '''src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c'''.<br />
<br />
Backport fixes that pertain to '''MSR 0x00000413''' and '''MSR 0xC0000408'''. The following in seen in '''dmesg''' on S3 resume:<br />
<br />
[ 396.828594] [Firmware Bug]: cpu 0, try to use APIC500 (LVT offset 0) for vector 0xf9, but the register is already in use for vector 0x400 on another cpu<br />
[ 396.828596] [Firmware Bug]: cpu 0, failed to setup threshold interrupt for bank 4, block 0 (MSR00000413=0xc000000001000000)<br />
[ 396.828597] [Firmware Bug]: cpu 0, try to use APIC500 (LVT offset 0) for vector 0xf9, but the register is already in use for vector 0x400 on another cpu<br />
[ 396.828599] [Firmware Bug]: cpu 0, failed to setup threshold interrupt for bank 4, block 1 (MSRC0000408=0xc000000001000000)<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments =<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = XHCI requires blob (so disabled by default)<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = 64KByte AtomBIOS blob needed<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Qualcomm Atheros QCA8172 Fast Ethernet<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = miniPCIe (populated with Qualcomm Atheros QCA9565 / AR9565 Wireless Network Adapter)<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status =<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = OK<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E (SO8, soldered) 4MB SPI Flash<br />
<br />
}}<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14892
Board:lenovo/g505s
2014-12-06T14:26:03Z
<p>Eocallaghan: /* Known Issues */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
* S3 Suspend/Resume - Nasty looking '''dmesg''' messages seen in Note 2. [https://lkml.org/lkml/2012/3/28/249 LKML] [https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1152484 bug report] [http://lxr.free-electrons.com/source/arch/x86/kernel/cpu/perf_event_amd_ibs.c#L784 force_ibs_eilvt_setup()].<br />
* "''AGP: Please enable the IOMMU option in the BIOS setup''" showing up in '''dmesg''' - Pass '''iommu=noaperture''' to the kernel boot args to ask the IOMMU not to touch the aperture for AGP.<br />
* "'''Re-enabling disabled Topology Extensions Support'''" showing up in '''dmesg''' - See Note 1.<br />
<br />
Note 1: Look in '''src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c''' for<br />
<br />
if (PkgType == PACKAGE_TYPE_FM2) {<br />
CpuMsrData |= BIT54;<br />
}<br />
<br />
this is the wrong package type for us. Fixed in [http://review.coreboot.org/#/c/7671/ 7671]<br />
<br />
<br />
Note 2: Look in '''src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c''' and '''src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c'''<br />
Backport fixes that pertain to '''MSR 0x00000413' and '''MSR 0xC0000408'''. The following in seen in '''dmesg''' on S3 resume:<br />
<br />
[ 396.828594] [Firmware Bug]: cpu 0, try to use APIC500 (LVT offset 0) for vector 0xf9, but the register is already in use for vector 0x400 on another cpu<br />
[ 396.828596] [Firmware Bug]: cpu 0, failed to setup threshold interrupt for bank 4, block 0 (MSR00000413=0xc000000001000000)<br />
[ 396.828597] [Firmware Bug]: cpu 0, try to use APIC500 (LVT offset 0) for vector 0xf9, but the register is already in use for vector 0x400 on another cpu<br />
[ 396.828599] [Firmware Bug]: cpu 0, failed to setup threshold interrupt for bank 4, block 1 (MSRC0000408=0xc000000001000000)<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments =<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = XHCI requires blob (so disabled by default)<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = 64KByte AtomBIOS blob needed<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Qualcomm Atheros QCA8172 Fast Ethernet<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = miniPCIe (populated with Qualcomm Atheros QCA9565 / AR9565 Wireless Network Adapter)<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status =<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = OK<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E (SO8, soldered) 4MB SPI Flash<br />
<br />
}}<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14888
Board:lenovo/g505s
2014-12-06T08:12:40Z
<p>Eocallaghan: /* Known Issues */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
* "''AGP: Please enable the IOMMU option in the BIOS setup''" showing up in '''dmesg''' - Pass '''iommu=noaperture''' to the kernel boot args to ask the IOMMU not to touch the aperture for AGP.<br />
* "'''Re-enabling disabled Topology Extensions Support'''" showing up in '''dmesg''' - See Note 1.<br />
<br />
Note 1: Look in '''src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c''' for<br />
<br />
if (PkgType == PACKAGE_TYPE_FM2) {<br />
CpuMsrData |= BIT54;<br />
}<br />
<br />
this is the wrong package type for us.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments =<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = XHCI requires blob (so disabled by default)<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = 64KByte AtomBIOS blob needed<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Qualcomm Atheros QCA8172 Fast Ethernet<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = miniPCIe (populated with Qualcomm Atheros QCA9565 / AR9565 Wireless Network Adapter)<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status =<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = OK<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E (SO8, soldered) 4MB SPI Flash<br />
<br />
}}<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14877
Board:lenovo/g505s
2014-12-05T10:33:21Z
<p>Eocallaghan: /* Status */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
* "''AGP: Please enable the IOMMU option in the BIOS setup''" showing up in '''dmesg''' - Pass '''iommu=noaperture''' to the kernel boot args to ask the IOMMU not to touch the aperture for AGP.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments =<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = XHCI requires blob (so disabled by default)<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = 64KByte AtomBIOS blob needed<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Qualcomm Atheros QCA8172 Fast Ethernet<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = miniPCIe (populated with Qualcomm Atheros QCA9565 / AR9565 Wireless Network Adapter)<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status =<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = OK<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E (SO8, soldered) 4MB SPI Flash<br />
<br />
}}<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14876
Board:lenovo/g505s
2014-12-05T10:30:32Z
<p>Eocallaghan: /* Status */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
* "''AGP: Please enable the IOMMU option in the BIOS setup''" showing up in '''dmesg''' - Pass '''iommu=noaperture''' to the kernel boot args to ask the IOMMU not to touch the aperture for AGP.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments =<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = XHCI requires blob (so disabled by default)<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = 64KByte AtomBIOS blob needed<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments =<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status =<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = OK<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E (SO8, soldered) 4MB SPI Flash<br />
<br />
}}<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14875
Board:lenovo/g505s
2014-12-05T10:27:59Z
<p>Eocallaghan: /* Status */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
* "''AGP: Please enable the IOMMU option in the BIOS setup''" showing up in '''dmesg''' - Pass '''iommu=noaperture''' to the kernel boot args to ask the IOMMU not to touch the aperture for AGP.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments =<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments =<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status =<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = OK<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E (SO8, soldered) 4MB SPI Flash<br />
<br />
}}<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14874
Board:lenovo/g505s
2014-12-05T10:26:00Z
<p>Eocallaghan: /* Known Issues */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
* "''AGP: Please enable the IOMMU option in the BIOS setup''" showing up in '''dmesg''' - Pass '''iommu=noaperture''' to the kernel boot args to ask the IOMMU not to touch the aperture for AGP.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments =<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments =<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E (SO8, soldered) 4MB SPI Flash<br />
<br />
}}<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14852
Board:lenovo/g505s
2014-12-02T11:34:24Z
<p>Eocallaghan: /* Issue Analysis */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments =<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments =<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E (SO8, soldered) 4MB SPI Flash<br />
<br />
}}<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14851
Board:lenovo/g505s
2014-12-02T11:34:04Z
<p>Eocallaghan: /* Coreboot boot log */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments =<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments =<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E (SO8, soldered) 4MB SPI Flash<br />
<br />
}}<br />
<br />
== Issue Analysis ==<br />
<br />
...<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14850
Board:lenovo/g505s
2014-12-02T11:32:08Z
<p>Eocallaghan: /* Status */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments =<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments =<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E (SO8, soldered) 4MB SPI Flash<br />
<br />
}}<br />
<br />
== Issue Analysis ==<br />
<br />
...<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#jetway.2Fnf81-t56n-lf] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14849
Board:lenovo/g505s
2014-12-02T11:29:47Z
<p>Eocallaghan: /* Status */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments =<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = miniPCIe slot works, mSATA/miniPCIe slot does not!?<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = CIR header currently turned off in devicetree.cb<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E 2MB SPI Flash<br />
<br />
}}<br />
<br />
== Issue Analysis ==<br />
<br />
...<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#jetway.2Fnf81-t56n-lf] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14848
Board:lenovo/g505s
2014-12-02T11:29:03Z
<p>Eocallaghan: /* Building a coreboot image */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' externally run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
and internally run:<br />
flashrom -p internal:laptop=force_I_want_a_brick -w build/coreboot.rom<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments = Tested with 4GB two-rank module.<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = miniPCIe slot works, mSATA/miniPCIe slot does not!?<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = CIR header currently turned off in devicetree.cb<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E 2MB SPI Flash<br />
<br />
}}<br />
<br />
== Issue Analysis ==<br />
<br />
...<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#jetway.2Fnf81-t56n-lf] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14847
Board:lenovo/g505s
2014-12-02T11:20:11Z
<p>Eocallaghan: </p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work! Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -c "MX25L1605A/MX25L1606E" -w build/coreboot.rom<br />
''assuming'' you have a SPI flasher setup.<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments = Tested with 4GB two-rank module.<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = miniPCIe slot works, mSATA/miniPCIe slot does not!?<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = CIR header currently turned off in devicetree.cb<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E 2MB SPI Flash<br />
<br />
}}<br />
<br />
== Issue Analysis ==<br />
<br />
...<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#jetway.2Fnf81-t56n-lf] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14846
Board:lenovo/g505s
2014-12-02T11:19:47Z
<p>Eocallaghan: /* Known Issues */</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* S3 Suspend/Resume - You will need a Console verbosity set to at least "BIOS_INFO" or greater for it to work!<br />
Coreboot is likely too fast for the Embedded Controller firmware on the S3 resume hot path.<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -c "MX25L1605A/MX25L1606E" -w build/coreboot.rom<br />
''assuming'' you have a SPI flasher setup.<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments = Tested with 4GB two-rank module.<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = miniPCIe slot works, mSATA/miniPCIe slot does not!?<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = CIR header currently turned off in devicetree.cb<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E 2MB SPI Flash<br />
<br />
}}<br />
<br />
== Issue Analysis ==<br />
<br />
...<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#jetway.2Fnf81-t56n-lf] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Build_HOWTO&diff=14833
Build HOWTO
2014-11-29T15:09:32Z
<p>Eocallaghan: /* Compiling with Clang/LLVM */</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on.<br />
* Enter the '''Payload''' menu.<br />
** By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process. If you want to use another payload:<br />
*** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
*** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
You also need to build crossgcc:<br />
<br />
$ '''make crossgcc'''<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
... We now build with clang/llvm.<br />
<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
== Known issues ==<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Build_HOWTO&diff=14832
Build HOWTO
2014-11-29T15:08:40Z
<p>Eocallaghan: </p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on.<br />
* Enter the '''Payload''' menu.<br />
** By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process. If you want to use another payload:<br />
*** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
*** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
You also need to build crossgcc:<br />
<br />
$ '''make crossgcc'''<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
...<br />
<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 [META] Compiling the Coreboot with clang]<br />
<br />
== Known issues ==<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:asus/m5a99fx-pro-r2&diff=14814
Board:asus/m5a99fx-pro-r2
2014-11-25T12:02:52Z
<p>Eocallaghan: </p>
<hr />
<div>This page describes how to use coreboot on the '''[https://www.asus.com/Motherboards/M5A99FX_PRO_R20 Asus M5A99FX-PRO-R2]''' mainboard.<br />
<br />
This page is a work in progress. '''[http://review.coreboot.org/#/c/7580/ review]'''<br />
<br />
== Known Issues ==<br />
<br />
* ??<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''Supports AM3+ 32 nm CPU''' CPU Support<br />
* '''AMD 990FX/SB950''' Southbridge<br />
* '''IT8721F''' ITE IT8721F Super I/O<br />
* '''RTL8111F''' Realtek RTL8111F network controllers<br />
* '''ALC892''' 6-Channel HD Audio (via Realtek ALC892), AC97 AD/DA<br />
<br />
=== Details ===<br />
<br />
2 x PCIe 2.0 x16 (dual x16)<br />
2 x PCIe 2.0 x16 (x4 mode, black)<br />
1 x PCIe 2.0 x1<br />
1 x PCI <br />
<br />
=== super io ===<br />
<br />
$ sudo superiotool -d<br />
superiotool r4.0-5814-g0a57e99<br />
Found ITE IT8721F (id=0x8721, rev=0x1) at 0x2e<br />
No dump available for this Super I/O<br />
<br />
=== lspci-tvnn ===<br />
<br />
-[0000:00]-+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (external gfx0 port B) [1002:5a14]<br />
+-02.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] Bonaire [1002:6658]<br />
| \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] Device [1002:aac0]<br />
+-04.0-[02]--<br />
+-0b.0-[03]--<br />
+-0d.0-[04]--<br />
+-11.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391]<br />
+-12.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397]<br />
+-12.2 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396]<br />
+-13.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397]<br />
+-13.2 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396]<br />
+-14.0 Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller [1002:4385]<br />
+-14.2 Advanced Micro Devices, Inc. [AMD/ATI] SBx00 Azalia (Intel HDA) [1002:4383]<br />
+-14.3 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d]<br />
+-14.4-[05]--<br />
+-14.5 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI2 Controller [1002:4399]<br />
+-15.0-[06]----00.0 ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:0612]<br />
+-15.1-[07]----00.0 ASMedia Technology Inc. Device [1b21:1142]<br />
+-15.2-[08]----00.0 ASMedia Technology Inc. Device [1b21:1142]<br />
+-15.3-[09]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168]<br />
+-16.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397]<br />
+-16.2 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396]<br />
+-18.0 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 0 [1022:1600]<br />
+-18.1 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 1 [1022:1601]<br />
+-18.2 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 2 [1022:1602]<br />
+-18.3 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 3 [1022:1603]<br />
+-18.4 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 4 [1022:1604]<br />
\-18.5 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 5 [1022:1605]<br />
<br />
<br />
=== lspci-vvv ===<br />
<br />
00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (external gfx0 port B) (rev 02)<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (external gfx0 port B)<br />
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-<br />
Capabilities: <access denied><br />
<br />
00:02.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (PCI express gpp port B) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0<br />
I/O behind bridge: 0000e000-0000efff<br />
Memory behind bridge: fea00000-feafffff<br />
Prefetchable memory behind bridge: 00000000c0000000-00000000d07fffff<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:04.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (PCI express gpp port D) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=02, subordinate=02, sec-latency=0<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:0b.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (NB-SB link) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=03, subordinate=03, sec-latency=0<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:0d.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (external gfx1 port B) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=04, subordinate=04, sec-latency=0<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:11.0 SATA controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) (prog-if 01 [AHCI 1.0])<br />
Subsystem: ASUSTeK Computer Inc. Device 84dd<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32<br />
Interrupt: pin A routed to IRQ 19<br />
Region 0: I/O ports at f040 [size=8]<br />
Region 1: I/O ports at f030 [size=4]<br />
Region 2: I/O ports at f020 [size=8]<br />
Region 3: I/O ports at f010 [size=4]<br />
Region 4: I/O ports at f000 [size=16]<br />
Region 5: Memory at feb0b000 (32-bit, non-prefetchable) [size=1K]<br />
Capabilities: <access denied><br />
Kernel driver in use: ahci<br />
Kernel modules: ahci<br />
<br />
00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller (prog-if 10 [OHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 18<br />
Region 0: Memory at feb0a000 (32-bit, non-prefetchable) [size=4K]<br />
Kernel driver in use: ohci-pci<br />
Kernel modules: ohci_pci<br />
<br />
00:12.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller (prog-if 20 [EHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin B routed to IRQ 17<br />
Region 0: Memory at feb09000 (32-bit, non-prefetchable) [size=256]<br />
Capabilities: <access denied><br />
Kernel driver in use: ehci-pci<br />
Kernel modules: ehci_pci<br />
<br />
00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller (prog-if 10 [OHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 20<br />
Region 0: Memory at feb08000 (32-bit, non-prefetchable) [size=4K]<br />
Kernel driver in use: ohci-pci<br />
Kernel modules: ohci_pci<br />
<br />
00:13.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller (prog-if 20 [EHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin B routed to IRQ 21<br />
Region 0: Memory at feb07000 (32-bit, non-prefetchable) [size=256]<br />
Capabilities: <access denied><br />
Kernel driver in use: ehci-pci<br />
Kernel modules: ehci_pci<br />
<br />
00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller (rev 42)<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller<br />
Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Kernel driver in use: piix4_smbus<br />
Kernel modules: i2c_piix4, sp5100_tco<br />
<br />
00:14.2 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 Azalia (Intel HDA) (rev 40)<br />
Subsystem: ASUSTeK Computer Inc. Device 84fb<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 16<br />
Region 0: Memory at feb00000 (64-bit, non-prefetchable) [size=16K]<br />
Capabilities: <access denied><br />
Kernel driver in use: snd_hda_intel<br />
Kernel modules: snd_hda_intel<br />
<br />
00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 LPC host controller (rev 40)<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 LPC host controller<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0<br />
<br />
00:14.4 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 PCI to PCI Bridge (rev 40) (prog-if 01 [Subtractive decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop+ ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 64<br />
Bus: primary=00, secondary=05, subordinate=05, sec-latency=64<br />
Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
<br />
00:14.5 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI2 Controller (prog-if 10 [OHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI2 Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin C routed to IRQ 18<br />
Region 0: Memory at feb06000 (32-bit, non-prefetchable) [size=4K]<br />
Kernel driver in use: ohci-pci<br />
Kernel modules: ohci_pci<br />
<br />
00:15.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB700/SB800/SB900 PCI to PCI bridge (PCIE port 0) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=06, subordinate=06, sec-latency=0<br />
I/O behind bridge: 0000d000-0000dfff<br />
Memory behind bridge: fe900000-fe9fffff<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:15.1 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB700/SB800/SB900 PCI to PCI bridge (PCIE port 1) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=07, subordinate=07, sec-latency=0<br />
Memory behind bridge: fe800000-fe8fffff<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:15.2 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB900 PCI to PCI bridge (PCIE port 2) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=08, subordinate=08, sec-latency=0<br />
Memory behind bridge: fe700000-fe7fffff<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:15.3 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB900 PCI to PCI bridge (PCIE port 3) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=09, subordinate=09, sec-latency=0<br />
I/O behind bridge: 0000c000-0000cfff<br />
Prefetchable memory behind bridge: 00000000d0900000-00000000d09fffff<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:16.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller (prog-if 10 [OHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 22<br />
Region 0: Memory at feb05000 (32-bit, non-prefetchable) [size=4K]<br />
Kernel driver in use: ohci-pci<br />
Kernel modules: ohci_pci<br />
<br />
00:16.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller (prog-if 20 [EHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin B routed to IRQ 23<br />
Region 0: Memory at feb04000 (32-bit, non-prefetchable) [size=256]<br />
Capabilities: <access denied><br />
Kernel driver in use: ehci-pci<br />
Kernel modules: ehci_pci<br />
<br />
00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 0<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Capabilities: <access denied><br />
<br />
00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 1<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
<br />
00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 2<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Kernel modules: amd64_edac_mod<br />
<br />
00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 3<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Capabilities: <access denied><br />
Kernel driver in use: k10temp<br />
Kernel modules: k10temp<br />
<br />
00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 4<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Kernel driver in use: fam15h_power<br />
Kernel modules: fam15h_power<br />
<br />
00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 5<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
<br />
01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Bonaire (prog-if 00 [VGA controller])<br />
Subsystem: ASUSTeK Computer Inc. Device 048f<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 91<br />
Region 0: Memory at c0000000 (64-bit, prefetchable) [size=256M]<br />
Region 2: Memory at d0000000 (64-bit, prefetchable) [size=8M]<br />
Region 4: I/O ports at e000 [size=256]<br />
Region 5: Memory at fea00000 (32-bit, non-prefetchable) [size=256K]<br />
Expansion ROM at fea40000 [disabled] [size=128K]<br />
Capabilities: <access denied><br />
Kernel driver in use: radeon<br />
Kernel modules: radeon<br />
<br />
01:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device aac0<br />
Subsystem: ASUSTeK Computer Inc. Device aac0<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin B routed to IRQ 90<br />
Region 0: Memory at fea60000 (64-bit, non-prefetchable) [size=16K]<br />
Capabilities: <access denied><br />
Kernel driver in use: snd_hda_intel<br />
Kernel modules: snd_hda_intel<br />
<br />
06:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) (prog-if 01 [AHCI 1.0])<br />
Subsystem: ASUSTeK Computer Inc. Device 84b7<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 88<br />
Region 0: I/O ports at d050 [size=8]<br />
Region 1: I/O ports at d040 [size=4]<br />
Region 2: I/O ports at d030 [size=8]<br />
Region 3: I/O ports at d020 [size=4]<br />
Region 4: I/O ports at d000 [size=32]<br />
Region 5: Memory at fe900000 (32-bit, non-prefetchable) [size=512]<br />
Capabilities: <access denied><br />
Kernel driver in use: ahci<br />
Kernel modules: ahci<br />
<br />
07:00.0 USB controller: ASMedia Technology Inc. Device 1142 (prog-if 30 [XHCI])<br />
Subsystem: ASUSTeK Computer Inc. Device 85bf<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 21<br />
Region 0: Memory at fe800000 (64-bit, non-prefetchable) [size=32K]<br />
Capabilities: <access denied><br />
Kernel driver in use: xhci_hcd<br />
Kernel modules: xhci_hcd<br />
<br />
08:00.0 USB controller: ASMedia Technology Inc. Device 1142 (prog-if 30 [XHCI])<br />
Subsystem: ASUSTeK Computer Inc. Device 85bf<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 22<br />
Region 0: Memory at fe700000 (64-bit, non-prefetchable) [size=32K]<br />
Capabilities: <access denied><br />
Kernel driver in use: xhci_hcd<br />
Kernel modules: xhci_hcd<br />
<br />
09:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 09)<br />
Subsystem: ASUSTeK Computer Inc. P8H77-I Motherboard<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 89<br />
Region 0: I/O ports at c000 [size=256]<br />
Region 2: Memory at d0904000 (64-bit, prefetchable) [size=4K]<br />
Region 4: Memory at d0900000 (64-bit, prefetchable) [size=16K]<br />
Capabilities: <access denied><br />
Kernel driver in use: r8169<br />
Kernel modules: r8169<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Asus/M5A99FX-PRO-R2 under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -w build/coreboot.rom<br />
''assuming'' you have a SPI flasher setup.<br />
<br />
== Status ==<br />
<br />
TODO<br />
<br />
== Issue Analysis ==<br />
<br />
???<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#asus.m5a99fx-pro-r2] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/g505s&diff=14805
Board:lenovo/g505s
2014-11-24T04:31:32Z
<p>Eocallaghan: initial</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://shop.lenovo.com/gb/en/laptops/lenovo/g-series/g505s/ Lenovo G505S]''' mainboard.<br />
<br />
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.<br />
<br />
== Known Issues ==<br />
<br />
* ...<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''AMD A-series''' AMD A10-5750M APU<br />
* '''AMD AGESA Hudson''' part of the chipset, AMD AGESA Hudson southbridge<br />
* '''ENE KB9012 EC''' However we use the ENE932 EC driver in coreboot's tree.<br />
<br />
=== Details ===<br />
<br />
...<br />
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Lenovo/G505S under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -c "MX25L1605A/MX25L1606E" -w build/coreboot.rom<br />
''assuming'' you have a SPI flasher setup.<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments = Tested with 4GB two-rank module.<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = miniPCIe slot works, mSATA/miniPCIe slot does not!?<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = CIR header currently turned off in devicetree.cb<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L1606E 2MB SPI Flash<br />
<br />
}}<br />
<br />
== Issue Analysis ==<br />
<br />
...<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#jetway.2Fnf81-t56n-lf] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=VGA_support&diff=14706
VGA support
2014-10-23T09:40:50Z
<p>Eocallaghan: </p>
<hr />
<div>== VGA initialization in coreboot ==<br />
<br />
Since coreboot v4 you can configure VGA initialization in Kconfig. For older versions of coreboot check the history of this page.<br />
<br />
First do:<br />
<br />
<source lang="bash"><br />
$ make menuconfig<br />
</source><br />
<br />
Then go<br />
Chipset ---><br />
[*] Setup bridges on path to VGA adapter <br />
[*] Run VGA option ROMs<br />
Option ROM execution type (Native mode) ---><br />
<br />
Alternatively you can choose the "Secure mode" to run the VGA option rom in a contained environment.<br />
<br />
If you have no on-board graphics, you are done configuring coreboot at this point. You may exit configuration, and run make to get your VGA enabled coreboot image.<br />
<br />
=== On-board Video Devices ===<br />
<br />
If you run coreboot on a system with on-board graphics, you have to embed a VGA on the top level, enter the file name of your option rom and the PCI ID of the associated graphics device in the form <vendor_id>,<device_id>:<br />
<br />
VGA BIOS ---><br />
[*] Add a VGA BIOS image<br />
(oprom-0.rom) VGA BIOS path and filename<br />
(8086,27a2) VGA device PCI IDs<br />
<br />
That's it, exit configuration, and run make to get your VGA enabled coreboot image.<br />
<br />
== How to retrieve a good video bios ==<br />
<br />
=== UEFI Method ===<br />
<br />
UEFI's format is more structured than that of a traditional flat binary BIOS. In order to extract the VBIOS Option ROM you will need<br />
to parse out the UEFI Volumes and sub-Volumes out the UEFI filesystem using the [https://github.com/LongSoft/UEFITool UEFITool].<br />
<br />
Look for the " CSMCORE " DXE Driver ?usually having the hash 'a062cf1f-8473-4aa3-8793-600bc4ffe9a8'? and extract the RAW Section to a file.<br />
<br />
=== RECOMMENDED: Extracting from your vendor bios image ===<br />
<br />
The recommended method is to take your mainboard vendor's BIOS image and extract the VGA BIOS using a tool called [[bios_extract]].<br />
<br />
$ git clone http://review.coreboot.org/p/bios_extract.git<br />
<br />
This is the most reliable way:<br />
* You are guaranteed to get an image that fits to your onboard VGA<br />
* Even if your VGA BIOS uses self-modifying code you get a correct image<br />
<br />
Decompress your rom image with:<br />
$ ./bios_extract hdmag217.rom<br />
<br />
If bios_decode fails with a message like<br />
Using file "hdmag217.rom" (513kB)<br />
Found Phoenix BIOS "Phoenix ServerBIOS 3 Release 6.0 "<br />
Version "DEVEL4E0", created on 03/20/06 at 14:37:39.<br />
Error: Invalid module signature at 0x80581<br />
<br />
then you have to cut the flash chip description off the image. In this case the BIOS image is 512KB, so you do<br />
$ dd if=hdmag217.rom of=hdma.rom bs=512k count=1<br />
1+0 records in<br />
1+0 records out<br />
524288 bytes transferred in 0.000883 secs (593688784 bytes/sec)<br />
<br />
<br />
You will get an output similar to this:<br />
<br />
Using file "hdma.rom" (512kB)<br />
Found Phoenix BIOS "Phoenix ServerBIOS 3 Release 6.0 "<br />
Version "DEVEL4E0", created on 03/20/06 at 14:37:39.<br />
0x715FC ( 27134 bytes) -> romexec_0.rom<br />
0x6E1CB ( 13338 bytes) -> strings_0.rom (29401 bytes)<br />
0x6D65D ( 2899 bytes) -> display_0.rom (4128 bytes)<br />
0x6B62E ( 8208 bytes) -> update_0.rom<br />
0x6B1E3 ( 1072 bytes) -> decompcode_0.rom [0x5000:0xB6D0]<br />
0x6564F ( 23421 bytes) -> oprom_0.rom (36864 bytes)<br />
0x65608 ( 44 bytes) -> tcpa_H_0.rom (32 bytes)<br />
0x65592 ( 91 bytes) -> acpi_1.rom (116 bytes)<br />
0x65519 ( 94 bytes) -> acpi_2.rom (244 bytes)<br />
0x654ED ( 13 bytes) -> tcpa_*_0.rom<br />
0x64D4F ( 1927 bytes) -> bioscode_0.rom (31382 bytes) [0xF000:0x856A]<br />
0x60020 ( 19728 bytes) -> romexec_1.rom<br />
0x570D9 ( 36656 bytes) -> oprom_1.rom (61440 bytes)<br />
0x4DB9D ( 38177 bytes) -> oprom_2.rom (63488 bytes)<br />
0x46493 ( 30447 bytes) -> oprom_3.rom (65536 bytes)<br />
0x41DAB ( 18125 bytes) -> logo_0.rom (310162 bytes)<br />
0x39CA5 ( 25439 bytes) -> oprom_4.rom (51200 bytes)<br />
0x36005 ( 15493 bytes) -> setup_0.rom (37682 bytes)<br />
0x325D7 ( 14867 bytes) -> template_0.rom (37728 bytes)<br />
0x2FA36 ( 11142 bytes) -> miser_0.rom (16208 bytes)<br />
0x2E63C ( 5087 bytes) -> tcpa_Q_0.rom (16096 bytes)<br />
0x2D7C3 ( 3678 bytes) -> acpi_0.rom (10464 bytes)<br />
0x1FA2A ( 41023 bytes) -> bioscode_1.rom (56080 bytes) [0xE000:0x40F0]<br />
0x14FE0 ( 43567 bytes) -> bioscode_2.rom (62416 bytes) [0x6000:0xCC30]<br />
0x0EB4C ( 25721 bytes) -> bioscode_3.rom (36976 bytes) [0x6000:0x3BC0]<br />
0x0D0A0 ( 6801 bytes) -> bioscode_4.rom (31856 bytes) [0x5000:0xBF50]<br />
<br />
Now you can check the option roms (oprom_?.rom) with the tool romheaders which is part of the [http://www.openfirmware.info/FCODE_suite FCode Suite]:<br />
<br />
$ romheaders oprom_0.rom <br />
<br />
Image 1:<br />
PCI Expansion ROM Header:<br />
Signature: 0x55aa (Ok)<br />
CPU unique data: 0x48 0xeb 0x7b 0x01 0x76 0x00 0x00 0x00<br />
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00<br />
Pointer to PCI Data Structure: 0x017c<br />
<br />
PCI Data Structure:<br />
Signature: 0x50434952 'PCIR' (Ok)<br />
Vendor ID: 0x1002<br />
Device ID: 0x4752<br />
Vital Product Data: 0x0000<br />
PCI Data Structure Length: 0x0018 (24 bytes)<br />
PCI Data Structure Revision: 0x00<br />
Class Code: 0x030000 (VGA Display controller)<br />
Image Length: 0x0048 blocks (36864 bytes)<br />
Revision Level of Code/Data: 0x0421<br />
Code Type: 0x00 (Intel x86)<br />
Last-Image Flag: 0x80 (last image in rom)<br />
Reserved: 0x0000<br />
<br />
Platform specific data for x86 compliant option rom:<br />
Initialization Size: 0x48 (36864 bytes)<br />
Entry point for INIT function: 0x80<br />
<br />
Congratulations, that's your option rom (compare PCI IDs and Class Code to find it among the option roms).<br />
<br />
=== Downloading ===<br />
<br />
There are sites that have video bios roms on their website. (I know of this one for nvidia cards: [http://whitebunny.demon.nl/hardware/chipset_nvidia.html])<br />
<br />
For Intel onboard graphics you can download the vbios(vga bios) from Intel's download section. The vbios is included with some versions of the graphics driver. The summary will say something like "NOTE:These materials are intended for use by developers.Includes VBIOS". The actual vbios file is the *.dat file included with the graphics driver.<br />
<br />
=== Extracting from the system (if everything else fails) ===<br />
<br />
However you might be able to retrieve your on-board video bios with Linux as well.<br />
<br />
* Boot up a machine with a commercial bios (not coreboot) with the video card you wish to work under coreboot.<br />
* You can see where and how much your card's bios is using by doing a <br />
<source lang="bash">grep 'Video ROM' /proc/iomem</source><br />
* From the command line enter:<br /><source lang="bash">dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768</source> This assumes you card's bios is cached at 0xc0000, and is 64K long.<br />
<br /><source lang="bash">dd if=/dev/mem of=video.bios.bin.4 bs=65536 count=1 skip=12</source><br />
This works for many of the VIA Epia boards.<br><br />
Alternatively you can automatically generate it using this nice script from Peter Stuge:<br /><br />
<source lang="bash"><br />
cat /proc/iomem | grep 'Video ROM' | (read m; m=${m/ :*}; s=${m/-*}; e=${m/*-}; \<br />
dd if=/dev/mem of=vgabios.bin bs=1c skip=$[0x$s] count=$[$[0x$e]-$[0x$s]+1])<br />
</source><br />
* You now have a video bios image<br />
<br />
== YABEL ==<br />
* Yabel can be used to trace the VGA option rom. <br />
* However its ability to prevent the option rom to do nasty things is limited: Often the GPU ofter a way(For instance trough an IO BAR) to access arbitrary locations in RAM, so limiting access to the GPU's PCI device to the option rom wound't contain it completely.<br />
<br />
See [[Coreboot Options]] for more information about the option.<br />
<br />
[[Category:Blobs]]</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14157
Board:lenovo/t530
2014-09-19T16:55:50Z
<p>Eocallaghan: /* Outline */</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments = Native<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = <br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L3206E 4MB SPI Flash<br />
<br />
}}<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* GbE firmware<br />
* System flash (7M)<br />
<br />
The 'Descriptor' region locks the flash and so you need to flash externally. ME firmware region is not readable from the CPU.<br />
<br />
More precisely:<br />
<br />
0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br />
0x58: 0x0bff0500 FREG1: BIOS region (0x00500000-0x00bfffff) is read-write.<br />
0x5C: 0x04ff0003 FREG2: Warning: Management Engine region (0x00003000-0x004fffff) is locked.<br />
0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write<br />
<br />
=== Outline ===<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Dismantle machine.<br />
* Connect external SPI flasher to the 4MB chip.<br />
<br />
Remark: You will need a SOIC clip to connect an external SPI programmer.<br />
<br />
=== Flashing Process ===<br />
<br />
1.) Read out the flash to make a backup '''Twice''', compare to ensure they match and then save a<br />
copy of it on external media:<br />
<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
'''If they don't match, do not proceed and if the file size is 8M you are flashing the wrong chip.'''<br />
<br />
2.) Since you have to write only top 4M out of the 12M coreboot.rom, first split out those 4M by:<br />
<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
Then use flashrom to flash top.rom.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14156
Board:lenovo/t530
2014-09-19T16:44:23Z
<p>Eocallaghan: </p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments = Native<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = <br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L3206E 4MB SPI Flash<br />
<br />
}}<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* GbE firmware<br />
* System flash (7M)<br />
<br />
The 'Descriptor' region locks the flash and so you need to flash externally. ME firmware region is not readable from the CPU.<br />
<br />
More precisely:<br />
<br />
0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br />
0x58: 0x0bff0500 FREG1: BIOS region (0x00500000-0x00bfffff) is read-write.<br />
0x5C: 0x04ff0003 FREG2: Warning: Management Engine region (0x00003000-0x004fffff) is locked.<br />
0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write<br />
<br />
=== Outline ===<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. If you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
Remark: You will need a SOIC clip to connect an external SPI programmer.<br />
<br />
=== Flashing Process ===<br />
<br />
1.) Read out the flash to make a backup '''Twice''', compare to ensure they match and then save a<br />
copy of it on external media:<br />
<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
'''If they don't match, do not proceed and if the file size is 8M you are flashing the wrong chip.'''<br />
<br />
2.) Since you have to write only top 4M out of the 12M coreboot.rom, first split out those 4M by:<br />
<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
Then use flashrom to flash top.rom.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14155
Board:lenovo/t530
2014-09-19T16:43:24Z
<p>Eocallaghan: /* Flashing */</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments = Native<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = <br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L3206E 4MB SPI Flash<br />
<br />
}}<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* GbE firmware<br />
* System flash (7M)<br />
<br />
The 'Descriptor' region locks the flash and so you need to flash externally. ME firmware region is not readable from the CPU.<br />
<br />
More precisely:<br />
<br />
0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br />
0x58: 0x0bff0500 FREG1: BIOS region (0x00500000-0x00bfffff) is read-write.<br />
0x5C: 0x04ff0003 FREG2: Warning: Management Engine region (0x00003000-0x004fffff) is locked.<br />
0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write<br />
<br />
=== Outline ===<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. If you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
Remark: You will need a SOIC clip to connect an external SPI programmer.<br />
<br />
=== Flashing Process ===<br />
<br />
1.) Read out the flash to make a backup '''Twice''', compare to ensure they match and then save a<br />
copy of it on external media:<br />
<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
'''If they don't match, do not proceed and if the file size is 8M you are flashing the wrong chip.'''<br />
<br />
2.) Since you have to write only top 4M out of the 12M coreboot.rom, first split out those 4M by:<br />
<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
Then use flashrom to flash top.rom.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14154
Board:lenovo/t530
2014-09-19T16:43:07Z
<p>Eocallaghan: /* GPIO layout */</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments = Native<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = <br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L3206E 4MB SPI Flash<br />
<br />
}}<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* GbE firmware<br />
* System flash (7M)<br />
<br />
The 'Descriptor' region locks the flash and so you need to flash externally. ME firmware region is not readable from the CPU.<br />
<br />
More precisely:<br />
<br />
0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br />
0x58: 0x0bff0500 FREG1: BIOS region (0x00500000-0x00bfffff) is read-write.<br />
0x5C: 0x04ff0003 FREG2: Warning: Management Engine region (0x00003000-0x004fffff) is locked.<br />
0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write<br />
<br />
<br />
=== Outline ===<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. If you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
Remark: You will need a SOIC clip to connect an external SPI programmer.<br />
<br />
=== Flashing Process ===<br />
<br />
1.) Read out the flash to make a backup '''Twice''', compare to ensure they match and then save a<br />
copy of it on external media:<br />
<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
'''If they don't match, do not proceed and if the file size is 8M you are flashing the wrong chip.'''<br />
<br />
2.) Since you have to write only top 4M out of the 12M coreboot.rom, first split out those 4M by:<br />
<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
Then use flashrom to flash top.rom.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14153
Board:lenovo/t530
2014-09-19T16:42:41Z
<p>Eocallaghan: /* General Purpose Events layout */</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments = Native<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = <br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L3206E 4MB SPI Flash<br />
<br />
}}<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* GbE firmware<br />
* System flash (7M)<br />
<br />
The 'Descriptor' region locks the flash and so you need to flash externally. ME firmware region is not readable from the CPU.<br />
<br />
More precisely:<br />
<br />
0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br />
0x58: 0x0bff0500 FREG1: BIOS region (0x00500000-0x00bfffff) is read-write.<br />
0x5C: 0x04ff0003 FREG2: Warning: Management Engine region (0x00003000-0x004fffff) is locked.<br />
0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write<br />
<br />
<br />
=== Outline ===<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. If you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
Remark: You will need a SOIC clip to connect an external SPI programmer.<br />
<br />
=== Flashing Process ===<br />
<br />
1.) Read out the flash to make a backup '''Twice''', compare to ensure they match and then save a<br />
copy of it on external media:<br />
<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
'''If they don't match, do not proceed and if the file size is 8M you are flashing the wrong chip.'''<br />
<br />
2.) Since you have to write only top 4M out of the 12M coreboot.rom, first split out those 4M by:<br />
<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
Then use flashrom to flash top.rom.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14152
Board:lenovo/t530
2014-09-19T16:40:54Z
<p>Eocallaghan: /* Flashing */</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments = Native<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = <br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L3206E 4MB SPI Flash<br />
<br />
}}<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GPE? - EC SCI<br />
* GPE? - EC SMI<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* GbE firmware<br />
* System flash (7M)<br />
<br />
The 'Descriptor' region locks the flash and so you need to flash externally. ME firmware region is not readable from the CPU.<br />
<br />
More precisely:<br />
<br />
0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only.<br />
0x58: 0x0bff0500 FREG1: BIOS region (0x00500000-0x00bfffff) is read-write.<br />
0x5C: 0x04ff0003 FREG2: Warning: Management Engine region (0x00003000-0x004fffff) is locked.<br />
0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write<br />
<br />
<br />
=== Outline ===<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. If you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
Remark: You will need a SOIC clip to connect an external SPI programmer.<br />
<br />
=== Flashing Process ===<br />
<br />
1.) Read out the flash to make a backup '''Twice''', compare to ensure they match and then save a<br />
copy of it on external media:<br />
<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
'''If they don't match, do not proceed and if the file size is 8M you are flashing the wrong chip.'''<br />
<br />
2.) Since you have to write only top 4M out of the 12M coreboot.rom, first split out those 4M by:<br />
<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
Then use flashrom to flash top.rom.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14151
Board:lenovo/t530
2014-09-19T16:28:32Z
<p>Eocallaghan: /* Status */</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = Always on<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = Always on<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = OK<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_DDR3_comments = Native<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = ?<br />
<br />
|IDE_status = N/A<br />
|IDE_CF_status = N/A<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|SATA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = BIOS/console: works.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_audio_comments = Basic two channel audio works fine.<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|Mini_PCI_cards_comments =<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = <br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = <br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = N/A<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|IR_comments = <br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments =<br />
|Watchdog_status = Pending<br />
|Watchdog_comments = What needs to be done here??<br />
|SMBus_status = OK<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Mostly working, needs a good Review!<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|Poweroff_comments =<br />
|LEDs_status = N/A<br />
|HPET_status = OK <br />
|RNG_status = OK<br />
|WakeOnModem_status = N/A<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = MXIC MX25L3206E 4MB SPI Flash<br />
<br />
}}<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GPE? - EC SCI<br />
* GPE? - EC SMI<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14133
Board:lenovo/t530
2014-09-15T14:38:35Z
<p>Eocallaghan: Undo revision 14132 by Phcoder (talk)</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Status ==<br />
Thanks for your interest in Lenovo T530 port.<br />
Issues:<br />
* EHCI output failure after sysagent<br />
* no S3<br />
* no MRC cache<br />
* MRC needs watchdog<br />
* yellow USB port isn't powered in power-off state.<br />
<br />
(Tested on X230 *not tested* on the T530):<br />
* RAM module combinations of 8G+8G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
Not tested:<br />
* mini displayport (probably works)<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
!!! WARNING !!!<br />
<br />
The ME is pretty much completely evil in both every imaginable and unimaginable way!<br />
This Coreboot port really only serves the purpose of two things:<br />
<br />
1.) Increasing the attack surface of the ME controller.<br />
<br />
2.) Replacing UEFI junk.<br />
<br />
There is very little "freedom" gained from Coreboot as the ME controller is /so/ utterly pervasive!<br />
Do your research!<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GPE? - EC SCI<br />
* GPE? - EC SMI<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14129
Board:lenovo/t530
2014-09-13T17:47:39Z
<p>Eocallaghan: /* Proprietary components status */</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Status ==<br />
Thanks for your interest in Lenovo T530 port.<br />
Issues:<br />
* EHCI output failure after sysagent<br />
* no S3<br />
* no MRC cache<br />
* MRC needs watchdog<br />
* yellow USB port isn't powered in power-off state.<br />
<br />
(Tested on X230 *not tested* on the T530):<br />
* RAM module combinations of 8G+8G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
Not tested:<br />
* mini displayport (probably works)<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
!!! WARNING !!!<br />
<br />
The ME is pretty much completely evil in both every imaginable and unimaginable way!<br />
This Coreboot port really only serves the purpose of two things:<br />
<br />
1.) Increasing the attack surface of the ME controller.<br />
<br />
2.) Replacing UEFI junk.<br />
<br />
There is very little "freedom" gained from Coreboot as the ME controller is /so/ utterly pervasive!<br />
Do your research!<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GPE? - EC SCI<br />
* GPE? - EC SMI<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14128
Board:lenovo/t530
2014-09-13T17:47:05Z
<p>Eocallaghan: /* Proprietary components status */</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Status ==<br />
Thanks for your interest in Lenovo T530 port.<br />
Issues:<br />
* EHCI output failure after sysagent<br />
* no S3<br />
* no MRC cache<br />
* MRC needs watchdog<br />
* yellow USB port isn't powered in power-off state.<br />
<br />
(Tested on X230 *not tested* on the T530):<br />
* RAM module combinations of 8G+8G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
Not tested:<br />
* mini displayport (probably works)<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* ME(Management Engine) => you do not have to touch it (just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it (just leave it where it is)<br />
<br />
!!! WARNING !!!<br />
<br />
The ME is pretty much completely evil in both every imaginable and unimaginable way!<br />
This Coreboot port really only serves the purpose of two things:<br />
<br />
1.) Increasing the attack surface of the ME controller.<br />
2.) Replacing UEFI junk.<br />
<br />
There is very little "freedom" gained from Coreboot as the ME controller is /so/ utterly pervasive!<br />
Do your research!<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GPE? - EC SCI<br />
* GPE? - EC SMI<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14127
Board:lenovo/t530
2014-09-13T17:43:24Z
<p>Eocallaghan: /* Known issues */</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Status ==<br />
Thanks for your interest in Lenovo T530 port.<br />
Issues:<br />
* EHCI output failure after sysagent<br />
* no S3<br />
* no MRC cache<br />
* MRC needs watchdog<br />
* yellow USB port isn't powered in power-off state.<br />
<br />
(Tested on X230 *not tested* on the T530):<br />
* RAM module combinations of 8G+8G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
Not tested:<br />
* mini displayport (probably works)<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* VGA option rom<br />
* MRC<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GPE? - EC SCI<br />
* GPE? - EC SMI<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14123
Board:lenovo/t530
2014-09-11T18:52:06Z
<p>Eocallaghan: /* Known issues */</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Known issues ==<br />
<br />
The following issues need to be resolved:<br />
* Can't see SeaBIOS payload output on LVDS screen<br />
* Keyboard does not work in SeaBIOS but does once Linux is up.<br />
* Backlight control just makes the screen flicker.<br />
* S3: Suspend works, Resume works up to showing the X WM then the machine powers off ~ ME/EC?? http://review.coreboot.org/#/c/6876<br />
* S3: No lid event to S3. http://review.coreboot.org/#/c/6877<br />
<br />
== Status ==<br />
Thanks for your interest in Lenovo T530 port.<br />
Issues:<br />
* EHCI output failure after sysagent<br />
* no S3<br />
* no MRC cache<br />
* MRC needs watchdog<br />
* yellow USB port isn't powered in power-off state.<br />
<br />
(Tested on X230 *not tested* on the T530):<br />
* RAM module combinations of 8G+8G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
Not tested:<br />
* mini displayport (probably works)<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* VGA option rom<br />
* MRC<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GPE? - EC SCI<br />
* GPE? - EC SMI<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14122
Board:lenovo/t530
2014-09-11T18:11:21Z
<p>Eocallaghan: </p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Known issues ==<br />
<br />
The following issues need to be resolved:<br />
* Can't see SeaBIOS payload output on LVDS screen<br />
* Keyboard does not work in SeaBIOS but does once Linux is up.<br />
* Mouse does not work in Linux, but randomly sometimes does?<br />
* Backlight control just makes the screen flicker.<br />
* S3: Suspend works, Resume works up to showing the X WM then the machine powers off ~ ME/EC?? http://review.coreboot.org/#/c/6876<br />
* S3: No lid event to S3. http://review.coreboot.org/#/c/6877<br />
<br />
== Status ==<br />
Thanks for your interest in Lenovo T530 port.<br />
Issues:<br />
* EHCI output failure after sysagent<br />
* no S3<br />
* no MRC cache<br />
* MRC needs watchdog<br />
* yellow USB port isn't powered in power-off state.<br />
<br />
(Tested on X230 *not tested* on the T530):<br />
* RAM module combinations of 8G+8G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
Not tested:<br />
* mini displayport (probably works)<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* VGA option rom<br />
* MRC<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GPE? - EC SCI<br />
* GPE? - EC SMI<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:lenovo/t530&diff=14121
Board:lenovo/t530
2014-09-11T16:30:06Z
<p>Eocallaghan: Current issues</p>
<hr />
<div>== Specification ==<br />
<br />
The machine has:<br />
- Chipset: Intel QM77<br />
- GPU's: Intel Integrated HD Graphics<br />
: Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology<br />
and pci configuration of:<br />
-[0000:00]-+-00.0 8086:0154<br />
+-02.0 8086:0166<br />
+-16.0 8086:1e3a<br />
+-19.0 8086:1502<br />
+-1a.0 8086:1e2d<br />
+-1b.0 8086:1e20<br />
+-1c.0-[02]----00.0 1180:e823<br />
+-1c.1-[03]----00.0 8086:4238<br />
+-1c.2-[04-0b]--<br />
+-1d.0 8086:1e26<br />
+-1f.0 8086:1e55<br />
+-1f.2 8086:1e03<br />
\-1f.3 8086:1e22<br />
<br />
== Known issues ==<br />
<br />
The following issues need to be resolved:<br />
* Can't see SeaBIOS payload output on LVDS screen<br />
* Keyboard does not work in SeaBIOS but does once Linux is up.<br />
* Mouse does not work in Linux, but randomly sometimes does?<br />
* Backlight control just makes the screen flicker.<br />
* S3: Suspend works, Resume works up to showing the X WM then the machine powers off ~ ME/EC??<br />
* S3: No lid event to S3.<br />
<br />
== Status ==<br />
Thanks for your interest in Lenovo T530 port.<br />
Issues:<br />
* EHCI output failure after sysagent<br />
* no S3<br />
* no MRC cache<br />
* MRC needs watchdog<br />
* yellow USB port isn't powered in power-off state.<br />
<br />
(Tested on X230 *not tested* on the T530):<br />
* RAM module combinations of 8G+8G<br />
* USB (both 2.0 and 3.0 ports)<br />
* Video (both internal and VGA)<br />
* Expresscard slot (including hotplugging)<br />
* Sound (integrated speakers, integrated mic, external headphones, external mic)<br />
* LAN<br />
* mini-PCIe slots (both wlan and wwan)<br />
* Linux (through GRUB-as-payload)<br />
* Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)<br />
* SD card slot<br />
* Thermal management<br />
* Fingerprint reader.<br />
* Webcam<br />
* Keyboard backlight<br />
* Thinklight.<br />
* bluetooth<br />
* dock<br />
* msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)<br />
Not tested:<br />
* mini displayport (probably works)<br />
<br />
== Proprietary components status ==<br />
* CPU Microcode (optional)<br />
* VGA option rom<br />
* MRC<br />
* ME(Management Engine) => you do not have to touch it(just leave it where it is)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== GPIO layout ==<br />
<br />
This information should not be considered reliable in any way, shape or form<br />
<br />
* GPIO57 - OUT - controls..<br />
<br />
== General Purpose Events layout ==<br />
<br />
* GPE? - EC SCI<br />
* GPE? - EC SMI<br />
<br />
== Flashing ==<br />
<br />
[[File:T530_SPI_chips.jpg|thumb|Location of the SPI chips]]<br />
<br />
T530 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 4 parts:<br />
<br />
* Descriptor (12K)<br />
* ME firmware (5M-12K)<br />
* System flash (7M)<br />
<br />
ME firmware is not readable.<br />
Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).<br />
<br />
Proceeds as follows:<br />
* Turn off your laptop, remove battery and AC adapter.<br />
* Remove the keyboard.<br />
* Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that's the only chip you need to reflash.<br />
<br />
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate<br />
3.3V source. Make sure not to feed more than 3.3V ot the chip. I used<br />
buspirate as flasher and 3.3V power lines from another computer.<br />
<br />
* Read the flash. Twice. Compare the files to be sure. Save a copy of it on<br />
external media.<br />
flashrom -p <yourprogrammer> -r flash.bin<br />
flashrom -p <yourprogrammer> -r flash2.bin<br />
diff flash.bin flash2.bin<br />
<br />
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.<br />
<br />
* Write the flash. Since you have to write only top 4M, first split out those 4M:<br />
dd of=top.rom bs=1M if=build/coreboot.rom skip=8<br />
<br />
* Use flashrom to flash top.rom.<br />
<br />
If you have trouble reading the chip successfully,<br />
the most common problems are<br />
*insufficient power supply <br />
*bad contacts<br />
*too long wires<br />
*bad pinout<br />
The cable shipped with buspirate was too long, and needed to be trimmed.<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]</div>
Eocallaghan
https://www.coreboot.org/index.php?title=User_talk:Eocallaghan&diff=13772
User talk:Eocallaghan
2014-07-19T17:07:16Z
<p>Eocallaghan: </p>
<hr />
<div>You can find me floating in #coreboot as ''funfunctor''<br />
<br />
== Sections deserving their own page ==<br />
* [[User_talk:Eocallaghan/Secure_RAM_API | IDEAPAGE: Mitigation ageist attack on encryption keys in memory after cold boot]]<br />
* [[User_talk:Eocallaghan/EOL_ROMCC_BOARDS | IDEAPAGE: List ROMCC dependant boards to possibly EOL]]<br />
* [[User_talk:Eocallaghan/REFACTOR_AGESA | IDEAPAGE: Refactor AGESA for the long term]]<br />
<br />
<br />
== AGESA family table ==<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Model #<br />
! Family<br />
|-<br />
! K10 architecture (2011)<br />
| Llano || ? || f12<br />
|-<br />
! Bobcat architecture (2011)<br />
| Ontario || ? || f14<br />
|-<br />
|<br />
| Zacate || ? || f14<br />
|-<br />
|<br />
| Desna || ? || f14<br />
|-<br />
|<br />
| Hondo || ? || f14<br />
|-<br />
! Piledriver architecture (2012)<br />
| Orochi || 00h-0fh || f15<br />
|-<br />
|<br />
| Trinity || ? || f15tn<br />
|-<br />
|<br />
| Richland || ? || f15rl<br />
|-<br />
! Jaguar architecture (2013)<br />
| Kabini || ? || f16kb<br />
|-<br />
|<br />
| Temash || ? || ??<br />
|}<br />
<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! [http://en.wikipedia.org/wiki/List_of_AMD_CPU_microarchitectures AMD Architecture]<br />
! Model Name<br />
! Socket<br />
! Family / Model #<br />
! colspan="3" |Documentation<br />
|-<br />
! [http://en.wikipedia.org/wiki/K10_(microarchitecture) K10 architecture] (2011)<br />
||<br />
* Llano<br />
||<br />
* FM1<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2012h%22 <br> Family 12h]<br />
|| [http://support.amd.com/TechDocs/41131.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/44739_12h_Rev_Gd.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/50322_12h_AthlonII_PDS.pdf Athlon II Data Sheet]<br />
* [http://support.amd.com/TechDocs/50321_12h_Sempron_PDS.pdf Sempron Data Sheet]<br />
* [http://support.amd.com/TechDocs/49894_12h_A-Series_PDS.pdf A-Series Data Sheet]<br />
|-<br />
! [http://en.wikipedia.org/wiki/Bobcat_(microarchitecture) Bobcat architecture] (2011)<br />
||<br />
* Ontario<br />
* Zacate<br />
* Desna<br />
* Honda<br />
||<br />
* FT1 BGA<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2014h%20models%2000h-0fh%22 Family 14h <br> Models 00h-0fh]<br />
|| [http://support.amd.com/TechDocs/43170_14h_Mod_00h-0Fh_BKDG.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/47534_14h_Mod_00h-0Fh_Rev_Guide.pdf Revision Guide]<br />
|-<br />
! [http://en.wikipedia.org/wiki/Bulldozer_(microarchitecture) Bulldozer architecture] (2012)<br />
||<br />
* Orochi<br />
||<br />
* AM3+ (AM3r2)<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2015h%20models%2000h-0fh%22 Family 15h <br> Models 00h-0fh]<br />
|| [http://support.amd.com/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf BKDG ]<br />
|| [http://support.amd.com/TechDocs/48063_15h_Mod_00h-0Fh_Rev_Guide.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/49686_15h_Mod_00h-0Fh_FX-Series_PDS.pdf FX-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/49687_15h_Mod_00h-0Fh_Opteron_PDS.pdf Opteron Data Sheet]<br />
|-<br />
! [http://en.wikipedia.org/wiki/Piledriver_(microarchitecture) Piledriver architecture] (2012)<br />
||<br />
* Trinity<br />
* Richland<br />
||<br />
* AM3+<br />
* FM2<br />
* FS1r2<br />
* FP2 BGA<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2015h%20models%2010h-1fh%22 Family 15tn <br> Models 10h-1fh]<br />
|| [http://support.amd.com/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf BKDG ]<br />
|| [http://support.amd.com/TechDocs/48931_15h_Mod_10h-1Fh_Rev_Guide.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/50911_15h_Mod_10h-1Fh_A-Series_PDS.pdf A-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/51309.PDF R-Series Data Sheet]<br />
|-<br />
! [http://en.wikipedia.org/wiki/Jaguar_(microarchitecture) Jaguar architecture] (2013)<br />
||<br />
* Kabini<br />
* Temash<br />
|| <br />
* FT3 BGA /<br />
* AM1 (FS1b)<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2016h%20models%2000h-0fh%22 Family 16kb <br> Models 00h-0f]<br />
|| [http://support.amd.com/TechDocs/48751_16h_bkdg.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/51810_16h_00h-0Fh_Rev_Guide.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/53738_PDS_Athlon.pdf Athlon Data Sheet]<br />
* [http://support.amd.com/TechDocs/52259_KB_G-Series_Product_Data_Sheet.pdf G-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/52169_KB_A_Series_Mobile.pdf A-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/53102_Opteron_Product_Data_Sheet.pdf Opteron Data Sheet]<br />
|-<br />
! [http://en.wikipedia.org/wiki/Steamroller_(microarchitecture) Steamroller architecture] (2014)<br />
||<br />
* Kaveri - "Bald Eagle"<br />
|| <br />
* FM2+ (FM2b)<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2015h%20models%2030h-3fh%22 Family 15kv <br> Models 30h-3fh]<br />
|| [http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/51603_Rev_Guide_15h_Models_30h-3Fh.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/51590_15h_Models_30h-3Fh_A-Series_PDS.pdf A-Series Data Sheet]<br />
|-<br />
! [http://en.wikipedia.org/wiki/Puma_(microarchitecture) Puma architecture] (2014)<br />
|| <br />
* Mullins - "Steppe Eagle"<br />
* Beema - "Crowned Eagle"<br />
|| <br />
* AM1 (FS1b)<br />
* FT3b BGA<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2016h%20models%2030h-3fh%22 Family 16ml <br> Models 30h-3fh]<br />
|| [http://support.amd.com/TechDocs/52740_16h_Models_30h-3Fh_BKDG.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/53072_Rev_Guide_16h_Models_30h-3Fh.pdf Revision Guide]<br />
|-<br />
! [http://en.wikipedia.org/wiki/Excavator_(microarchitecture) Excavator architecture] (2015)<br />
|| <br />
* Carrizo<br />
||<br />
||<br />
||<br />
||<br />
|-<br />
! [http://en.wikipedia.org/wiki/AMD_K12 K12] [http://en.wikipedia.org/wiki/ARM-64#64-bit ARM-64 architecture] (2016)<br />
|| <br />
* <br />
||<br />
||<br />
||<br />
||<br />
|-<br />
|}<br />
<br />
[http://developer.amd.com/resources/documentation-articles/developer-guides-manuals/ AMD Developer Central: Developer Guides & Manuals]<br><br />
[http://search.amd.com/ Search developer.amd.com and support.amd.com]<br><br />
<br />
== Current Activities ==<br />
<br />
* Clean up superio support.<br />
* Fix DSDT/SSDT in AGESA<br />
<br />
=== AGESA - DSDT/SSDT ===<br />
<br />
Current list of issues below:<br />
<br />
==== Error 6126: syntax error, *** ====<br />
<br />
Notes:<br />
<br />
We may extract and decompile the first SSDT table in the following way:<br />
cat /sys/firmware/acpi/tables/SSDT1 > ssdt.dd ; iasl -d ssdt.dd<br />
<br />
A '''snip''' of the broken code fragment in question is given:<br />
<br />
If (LEqual (Local2, 0x07))<br />
{<br />
If (CondRefOf (\_SB.ALIC, Local6))<br />
{<br />
Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
\_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00, <br />
Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2, <br />
0x05))<br />
{<br />
Store (0x01, Local4)<br />
Store (0x00, Local2)<br />
A074 (Arg0, 0x02)<br />
}, If (LEqual (Local2, 0x00))<br />
{<br />
Store (0x01, A017) /* \_SB_.A017 */<br />
A029 ()<br />
Store (0x08, Local2)<br />
})<br />
}<br />
}<br />
<br />
<br />
Currently AGESA has pre-compiled a bunch of .esl files into:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h'''<br />
<br />
This array of pre-compiled SSDT bytecode is used to construct the SSDT table in:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c'''<br />
<br />
in the function:<br />
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { .. }<br />
<br />
The root of SSDT seems to be in the file: '''vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl'''<br />
<br />
We can work around the broken SSDT in mainboard support by maing the following changes to this line in '''acpi_tables.c''':<br />
<br />
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ // alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ alib = NULL;<br />
<br />
A full diagnostic report is given:<br />
<br />
Test 2 of 2: Disassemble and reassemble SSDT<br />
<br />
Checking ACPI table SSDT (#0)<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1151<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01148| If (CondRefOf (\_SB.ALIC, Local6))<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_SLEEP, expecting ',' or ')'<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
01153| 0x05))<br />
01154| {<br />
================================================================================<br />
:<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_CONTINUE, expecting ',' or ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1158<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01155| Store (0x01, Local4)<br />
01156| Store (0x00, Local2)<br />
01157| A074 (Arg0, 0x02)<br />
01158| }, If (LEqual (Local2, 0x00))<br />
| ^<br />
| Error 6126: syntax error, unexpected ','<br />
01159| {<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1163<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
01162| Store (0x08, Local2)<br />
01163| })<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01164| }<br />
01165| }<br />
01166| }<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] SyntaxCheckIASLCompilerAborted: Test 2, Compilation aborted early<br />
due to a parser detected syntax error.<br />
<br />
ADVICE: Some subsequent errors may not be detected because the compiler had to<br />
terminate prematurely. If the compiler did not abort early then potentially<br />
correct code may parse incorrectly producing some or many false positive errors.<br />
<br />
Table SSDT (0) reassembly: Found 5 errors, 0 warnings, 0 remarks.<br />
<br />
==== Remark 2089: Object is not referenced ====<br />
<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,0,CDW1)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,4,CDW2)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,8,CDW3)<br />
<br />
Checking ACPI table DSDT (#0)<br />
<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1793<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01790| Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
================================================================================<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1794<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
01797| /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,<br />
================================================================================<br />
Table DSDT (0) reassembly: Found 0 errors, 0 warnings, 2 remarks.<br />
<br />
<br />
== Resource allocator ==<br />
<br />
Key:<br />
<br />
= bus<br />
- device<br />
<br />
Structure:<br />
<br />
========= next =========<br />
|| bus ||--------------------------------->|| bus ||<br />
========= =========<br />
| | +-----------------+<br />
| | |<br />
| +-+ v children<br />
bus | | dev |<br />
^ v +---+----+<br />
| | +--- | Device |<br />
+--------+ bus | +--------+<br />
| Bridge |<-----+ |<br />
+--------+ | v children<br />
bus | +---+----+<br />
+--- | Device |<br />
+--------+</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:jetway/nf81-t56n-lf&diff=13759
Board:jetway/nf81-t56n-lf
2014-06-09T04:19:08Z
<p>Eocallaghan: /* Status */</p>
<hr />
<div></div>
Eocallaghan
https://www.coreboot.org/index.php?title=User_talk:Eocallaghan&diff=13756
User talk:Eocallaghan
2014-06-07T01:54:47Z
<p>Eocallaghan: /* AGESA family table */</p>
<hr />
<div>You can find me floating in #coreboot as ''funfunctor''<br />
<br />
== Sections deserving their own page ==<br />
* [[User_talk:Eocallaghan/Secure_RAM_API | IDEAPAGE: Mitigation ageist attack on encryption keys in memory after cold boot]]<br />
* [[User_talk:Eocallaghan/EOL_ROMCC_BOARDS | IDEAPAGE: List ROMCC dependant boards to possibly EOL]]<br />
* [[User_talk:Eocallaghan/REFACTOR_AGESA | IDEAPAGE: Refactor AGESA for the long term]]<br />
<br />
<br />
== AGESA family table ==<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Model #<br />
! Family<br />
|-<br />
! K10 architecture (2011)<br />
| Llano || ? || f12<br />
|-<br />
! Bobcat architecture (2011)<br />
| Ontario || ? || f14<br />
|-<br />
|<br />
| Zacate || ? || f14<br />
|-<br />
|<br />
| Desna || ? || f14<br />
|-<br />
|<br />
| Hondo || ? || f14<br />
|-<br />
! Piledriver architecture (2012)<br />
| Orochi || 00h-0fh || f15<br />
|-<br />
|<br />
| Trinity || ? || f15tn<br />
|-<br />
|<br />
| Richland || ? || f15rl<br />
|-<br />
! Jaguar architecture (2013)<br />
| Kabini || ? || f16kb<br />
|-<br />
|<br />
| Temash || ? || ??<br />
|}<br />
<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Family / Model #<br />
! colspan="3" |Documentation<br />
|-<br />
! K10 architecture (2011)<br />
| Llano<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2012h%22 <br> Family 12h]<br />
|| [http://support.amd.com/TechDocs/41131.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/44739_12h_Rev_Gd.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/50322_12h_AthlonII_PDS.pdf Athlon II Data Sheet]<br />
* [http://support.amd.com/TechDocs/50321_12h_Sempron_PDS.pdf Sempron Data Sheet]<br />
* [http://support.amd.com/TechDocs/49894_12h_A-Series_PDS.pdf A-Series Data Sheet]<br />
|-<br />
! Bobcat architecture (2011)<br />
| Ontario / Zacate / Desna / Honda<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2014h%20models%2000h-0fh%22 Family 14h <br> Models 00h-0fh]<br />
|| [http://support.amd.com/TechDocs/43170_14h_Mod_00h-0Fh_BKDG.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/47534_14h_Mod_00h-0Fh_Rev_Guide.pdf Revision Guide]<br />
|-<br />
! Piledriver architecture (2012)<br />
| Orochi<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2015h%20models%2000h-0fh%22 Family 15h <br> Models 00h-0fh]<br />
|| [http://support.amd.com/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf BKDG ]<br />
|| [http://support.amd.com/TechDocs/48063_15h_Mod_00h-0Fh_Rev_Guide.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/49686_15h_Mod_00h-0Fh_FX-Series_PDS.pdf FX-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/49687_15h_Mod_00h-0Fh_Opteron_PDS.pdf Opteron Data Sheet]<br />
|-<br />
|<br />
|| Trinity / Richland<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2015h%20models%2010h-1fh%22 Family 15tn <br> Models 10h-1fh]<br />
|| [http://support.amd.com/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf BKDG ]<br />
|| [http://support.amd.com/TechDocs/48931_15h_Mod_10h-1Fh_Rev_Guide.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/50911_15h_Mod_10h-1Fh_A-Series_PDS.pdf A-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/51309.PDF R-Series Data Sheet]<br />
|-<br />
! Jaguar architecture (2013)<br />
| Kabini / Temash<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2016h%20models%2000h-0fh%22 Family 16kb <br> Models 00h-0f]<br />
|| [http://support.amd.com/TechDocs/48751_16h_bkdg.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/51810_16h_00h-0Fh_Rev_Guide.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/53738_PDS_Athlon.pdf Athlon Data Sheet]<br />
* [http://support.amd.com/TechDocs/52259_KB_G-Series_Product_Data_Sheet.pdf G-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/52169_KB_A_Series_Mobile.pdf A-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/53102_Opteron_Product_Data_Sheet.pdf Opteron Data Sheet]<br />
|-<br />
! Steamroller architecture (2014)<br />
| Kaveri<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2015h%20models%2030h-3fh%22 Family 15kv <br> Models 30h-3fh]<br />
|| [http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/51603_Rev_Guide_15h_Models_30h-3Fh.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/51590_15h_Models_30h-3Fh_A-Series_PDS.pdf A-Series Data Sheet]<br />
|-<br />
! Puma architecture (2014)<br />
|| Mullins / Beema<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2016h%20models%2030h-3fh%22 Family 16ml <br> Models 30h-3fh]<br />
|| [http://support.amd.com/TechDocs/52740_16h_Models_30h-3Fh_BKDG.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/53072_Rev_Guide_16h_Models_30h-3Fh.pdf Revision Guide]<br />
|-<br />
<br />
|}<br />
<br />
[http://developer.amd.com/resources/documentation-articles/developer-guides-manuals/ AMD Developer Central: Developer Guides & Manuals]<br><br />
[http://search.amd.com/ Search developer.amd.com and support.amd.com]<br><br />
<br />
== Current Activities ==<br />
<br />
* Clean up superio support.<br />
* Fix DSDT/SSDT in AGESA<br />
<br />
=== AGESA - DSDT/SSDT ===<br />
<br />
Current list of issues below:<br />
<br />
==== Error 6126: syntax error, *** ====<br />
<br />
Notes:<br />
<br />
We may extract and decompile the first SSDT table in the following way:<br />
cat /sys/firmware/acpi/tables/SSDT1 > ssdt.dd ; iasl -d ssdt.dd<br />
<br />
A '''snip''' of the broken code fragment in question is given:<br />
<br />
If (LEqual (Local2, 0x07))<br />
{<br />
If (CondRefOf (\_SB.ALIC, Local6))<br />
{<br />
Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
\_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00, <br />
Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2, <br />
0x05))<br />
{<br />
Store (0x01, Local4)<br />
Store (0x00, Local2)<br />
A074 (Arg0, 0x02)<br />
}, If (LEqual (Local2, 0x00))<br />
{<br />
Store (0x01, A017) /* \_SB_.A017 */<br />
A029 ()<br />
Store (0x08, Local2)<br />
})<br />
}<br />
}<br />
<br />
<br />
Currently AGESA has pre-compiled a bunch of .esl files into:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h'''<br />
<br />
This array of pre-compiled SSDT bytecode is used to construct the SSDT table in:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c'''<br />
<br />
in the function:<br />
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { .. }<br />
<br />
The root of SSDT seems to be in the file: '''vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl'''<br />
<br />
We can work around the broken SSDT in mainboard support by maing the following changes to this line in '''acpi_tables.c''':<br />
<br />
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ // alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ alib = NULL;<br />
<br />
A full diagnostic report is given:<br />
<br />
Test 2 of 2: Disassemble and reassemble SSDT<br />
<br />
Checking ACPI table SSDT (#0)<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1151<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01148| If (CondRefOf (\_SB.ALIC, Local6))<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_SLEEP, expecting ',' or ')'<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
01153| 0x05))<br />
01154| {<br />
================================================================================<br />
:<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_CONTINUE, expecting ',' or ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1158<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01155| Store (0x01, Local4)<br />
01156| Store (0x00, Local2)<br />
01157| A074 (Arg0, 0x02)<br />
01158| }, If (LEqual (Local2, 0x00))<br />
| ^<br />
| Error 6126: syntax error, unexpected ','<br />
01159| {<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1163<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
01162| Store (0x08, Local2)<br />
01163| })<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01164| }<br />
01165| }<br />
01166| }<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] SyntaxCheckIASLCompilerAborted: Test 2, Compilation aborted early<br />
due to a parser detected syntax error.<br />
<br />
ADVICE: Some subsequent errors may not be detected because the compiler had to<br />
terminate prematurely. If the compiler did not abort early then potentially<br />
correct code may parse incorrectly producing some or many false positive errors.<br />
<br />
Table SSDT (0) reassembly: Found 5 errors, 0 warnings, 0 remarks.<br />
<br />
==== Remark 2089: Object is not referenced ====<br />
<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,0,CDW1)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,4,CDW2)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,8,CDW3)<br />
<br />
Checking ACPI table DSDT (#0)<br />
<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1793<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01790| Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
================================================================================<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1794<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
01797| /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,<br />
================================================================================<br />
Table DSDT (0) reassembly: Found 0 errors, 0 warnings, 2 remarks.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=User_talk:Eocallaghan&diff=13755
User talk:Eocallaghan
2014-06-07T01:49:03Z
<p>Eocallaghan: /* AGESA family table */</p>
<hr />
<div>You can find me floating in #coreboot as ''funfunctor''<br />
<br />
== Sections deserving their own page ==<br />
* [[User_talk:Eocallaghan/Secure_RAM_API | IDEAPAGE: Mitigation ageist attack on encryption keys in memory after cold boot]]<br />
* [[User_talk:Eocallaghan/EOL_ROMCC_BOARDS | IDEAPAGE: List ROMCC dependant boards to possibly EOL]]<br />
* [[User_talk:Eocallaghan/REFACTOR_AGESA | IDEAPAGE: Refactor AGESA for the long term]]<br />
<br />
<br />
== AGESA family table ==<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Model #<br />
! Family<br />
|-<br />
! K10 architecture (2011)<br />
| Llano || ? || f12<br />
|-<br />
! Bobcat architecture (2011)<br />
| Ontario || ? || f14<br />
|-<br />
|<br />
| Zacate || ? || f14<br />
|-<br />
|<br />
| Desna || ? || f14<br />
|-<br />
|<br />
| Hondo || ? || f14<br />
|-<br />
! Piledriver architecture (2012)<br />
| Orochi || 00h-0fh || f15<br />
|-<br />
|<br />
| Trinity || ? || f15tn<br />
|-<br />
|<br />
| Richland || ? || f15rl<br />
|-<br />
! Jaguar architecture (2013)<br />
| Kabini || ? || f16kb<br />
|-<br />
|<br />
| Temash || ? || ??<br />
|}<br />
<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Family / Model #<br />
! colspan="3" |Documentation<br />
|-<br />
! K10 architecture (2011)<br />
| Llano<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2012h%22 <br> Family 12h]<br />
|| [http://support.amd.com/TechDocs/41131.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/44739_12h_Rev_Gd.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/50322_12h_AthlonII_PDS.pdf Athlon II Data Sheet]<br />
* [http://support.amd.com/TechDocs/50321_12h_Sempron_PDS.pdf Sempron Data Sheet]<br />
* [http://support.amd.com/TechDocs/49894_12h_A-Series_PDS.pdf A-Series Data Sheet]<br />
|-<br />
! Bobcat architecture (2011)<br />
| Ontario / Zacate / Desna / Honda<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2014h%20models%2000h-0fh%22 Family 14h <br> Models 00h-0fh]<br />
|| [http://support.amd.com/TechDocs/43170_14h_Mod_00h-0Fh_BKDG.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/47534_14h_Mod_00h-0Fh_Rev_Guide.pdf Revision Guide]<br />
|-<br />
! Piledriver architecture (2012)<br />
| Orochi<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2015h%20models%2000h-0fh%22 Family 15h <br> Models 00h-0fh]<br />
|| [http://support.amd.com/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf BKDG ]<br />
|| [http://support.amd.com/TechDocs/48063_15h_Mod_00h-0Fh_Rev_Guide.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/49686_15h_Mod_00h-0Fh_FX-Series_PDS.pdf FX-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/49687_15h_Mod_00h-0Fh_Opteron_PDS.pdf Opteron Data Sheet]<br />
|-<br />
|<br />
|| Trinity / Richland<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2015h%20models%2010h-1fh%22 Family 15tn <br> Models 10h-1fh]<br />
|| [http://support.amd.com/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf BKDG ]<br />
|| [http://support.amd.com/TechDocs/48931_15h_Mod_10h-1Fh_Rev_Guide.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/50911_15h_Mod_10h-1Fh_A-Series_PDS.pdf A-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/51309.PDF R-Series Data Sheet]<br />
|-<br />
! Jaguar architecture (2013)<br />
| Kabini / Temash<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2016h%20models%2000h-0fh%22 Family 16kb <br> Models 00h-0f]<br />
|| [http://support.amd.com/TechDocs/48751_16h_bkdg.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/51810_16h_00h-0Fh_Rev_Guide.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/53738_PDS_Athlon.pdf Athlon Data Sheet]<br />
* [http://support.amd.com/TechDocs/52259_KB_G-Series_Product_Data_Sheet.pdf G-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/52169_KB_A_Series_Mobile.pdf A-Series Data Sheet]<br />
* [http://support.amd.com/TechDocs/53102_Opteron_Product_Data_Sheet.pdf Opteron Data Sheet]<br />
|-<br />
! Steamroller architecture (2014)<br />
| Kaveri<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2015h%20models%2030h-3fh%22 Family 15kv <br> Models 30h-3fh]<br />
|| [http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/51603_Rev_Guide_15h_Models_30h-3Fh.pdf Revision Guide]<br />
||<br />
* [http://support.amd.com/TechDocs/51590_15h_Models_30h-3Fh_A-Series_PDS.pdf A-Series Data Sheet]<br />
|-<br />
! Puma architecture (2014)<br />
|| Mullins / Beema<br />
|| [http://search.amd.com/en-us/Pages/results-all.aspx?k=%22family%2016h%20models%2030h-3fh%22 Family 16ml <br> Models 30h-3fh]<br />
|| [http://support.amd.com/TechDocs/52740_16h_Models_30h-3Fh_BKDG.pdf BKDG]<br />
|| [http://support.amd.com/TechDocs/53072_Rev_Guide_16h_Models_30h-3Fh.pdf Revision Guide]<br />
|-<br />
<br />
|}<br />
<br />
== Current Activities ==<br />
<br />
* Clean up superio support.<br />
* Fix DSDT/SSDT in AGESA<br />
<br />
=== AGESA - DSDT/SSDT ===<br />
<br />
Current list of issues below:<br />
<br />
==== Error 6126: syntax error, *** ====<br />
<br />
Notes:<br />
<br />
We may extract and decompile the first SSDT table in the following way:<br />
cat /sys/firmware/acpi/tables/SSDT1 > ssdt.dd ; iasl -d ssdt.dd<br />
<br />
A '''snip''' of the broken code fragment in question is given:<br />
<br />
If (LEqual (Local2, 0x07))<br />
{<br />
If (CondRefOf (\_SB.ALIC, Local6))<br />
{<br />
Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
\_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00, <br />
Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2, <br />
0x05))<br />
{<br />
Store (0x01, Local4)<br />
Store (0x00, Local2)<br />
A074 (Arg0, 0x02)<br />
}, If (LEqual (Local2, 0x00))<br />
{<br />
Store (0x01, A017) /* \_SB_.A017 */<br />
A029 ()<br />
Store (0x08, Local2)<br />
})<br />
}<br />
}<br />
<br />
<br />
Currently AGESA has pre-compiled a bunch of .esl files into:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h'''<br />
<br />
This array of pre-compiled SSDT bytecode is used to construct the SSDT table in:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c'''<br />
<br />
in the function:<br />
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { .. }<br />
<br />
The root of SSDT seems to be in the file: '''vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl'''<br />
<br />
We can work around the broken SSDT in mainboard support by maing the following changes to this line in '''acpi_tables.c''':<br />
<br />
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ // alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ alib = NULL;<br />
<br />
A full diagnostic report is given:<br />
<br />
Test 2 of 2: Disassemble and reassemble SSDT<br />
<br />
Checking ACPI table SSDT (#0)<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1151<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01148| If (CondRefOf (\_SB.ALIC, Local6))<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_SLEEP, expecting ',' or ')'<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
01153| 0x05))<br />
01154| {<br />
================================================================================<br />
:<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_CONTINUE, expecting ',' or ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1158<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01155| Store (0x01, Local4)<br />
01156| Store (0x00, Local2)<br />
01157| A074 (Arg0, 0x02)<br />
01158| }, If (LEqual (Local2, 0x00))<br />
| ^<br />
| Error 6126: syntax error, unexpected ','<br />
01159| {<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1163<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
01162| Store (0x08, Local2)<br />
01163| })<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01164| }<br />
01165| }<br />
01166| }<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] SyntaxCheckIASLCompilerAborted: Test 2, Compilation aborted early<br />
due to a parser detected syntax error.<br />
<br />
ADVICE: Some subsequent errors may not be detected because the compiler had to<br />
terminate prematurely. If the compiler did not abort early then potentially<br />
correct code may parse incorrectly producing some or many false positive errors.<br />
<br />
Table SSDT (0) reassembly: Found 5 errors, 0 warnings, 0 remarks.<br />
<br />
==== Remark 2089: Object is not referenced ====<br />
<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,0,CDW1)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,4,CDW2)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,8,CDW3)<br />
<br />
Checking ACPI table DSDT (#0)<br />
<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1793<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01790| Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
================================================================================<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1794<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
01797| /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,<br />
================================================================================<br />
Table DSDT (0) reassembly: Found 0 errors, 0 warnings, 2 remarks.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=User_talk:Eocallaghan&diff=13752
User talk:Eocallaghan
2014-06-05T23:12:05Z
<p>Eocallaghan: /* AGESA family table */</p>
<hr />
<div>You can find me floating in #coreboot as ''funfunctor''<br />
<br />
== Sections deserving their own page ==<br />
* [[User_talk:Eocallaghan/Secure_RAM_API | IDEAPAGE: Mitigation ageist attack on encryption keys in memory after cold boot]]<br />
* [[User_talk:Eocallaghan/EOL_ROMCC_BOARDS | IDEAPAGE: List ROMCC dependant boards to possibly EOL]]<br />
* [[User_talk:Eocallaghan/REFACTOR_AGESA | IDEAPAGE: Refactor AGESA for the long term]]<br />
<br />
<br />
== AGESA family table ==<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Model #<br />
! Family<br />
|-<br />
! K10 architecture (2011)<br />
| Llano || ? || f12<br />
|-<br />
! Bobcat architecture (2011)<br />
| Ontario || ? || f14<br />
|-<br />
|<br />
| Zacate || ? || f14<br />
|-<br />
|<br />
| Desna || ? || f14<br />
|-<br />
|<br />
| Hondo || ? || f14<br />
|-<br />
! Piledriver architecture (2012)<br />
| Orochi || 00h-0fh || f15<br />
|-<br />
|<br />
| Trinity || ? || f15tn<br />
|-<br />
|<br />
| Richland || ? || f15rl<br />
|-<br />
! Jaguar architecture (2013)<br />
| Kabini || ? || f16kb<br />
|-<br />
|<br />
| Temash || ? || ??<br />
|}<br />
<br />
== Current Activities ==<br />
<br />
* Clean up superio support.<br />
* Fix DSDT/SSDT in AGESA<br />
<br />
=== AGESA - DSDT/SSDT ===<br />
<br />
Current list of issues below:<br />
<br />
==== Error 6126: syntax error, *** ====<br />
<br />
Notes:<br />
<br />
We may extract and decompile the first SSDT table in the following way:<br />
cat /sys/firmware/acpi/tables/SSDT1 > ssdt.dd ; iasl -d ssdt.dd<br />
<br />
A '''snip''' of the broken code fragment in question is given:<br />
<br />
If (LEqual (Local2, 0x07))<br />
{<br />
If (CondRefOf (\_SB.ALIC, Local6))<br />
{<br />
Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
\_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00, <br />
Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2, <br />
0x05))<br />
{<br />
Store (0x01, Local4)<br />
Store (0x00, Local2)<br />
A074 (Arg0, 0x02)<br />
}, If (LEqual (Local2, 0x00))<br />
{<br />
Store (0x01, A017) /* \_SB_.A017 */<br />
A029 ()<br />
Store (0x08, Local2)<br />
})<br />
}<br />
}<br />
<br />
<br />
Currently AGESA has pre-compiled a bunch of .esl files into:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h'''<br />
<br />
This array of pre-compiled SSDT bytecode is used to construct the SSDT table in:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c'''<br />
<br />
in the function:<br />
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { .. }<br />
<br />
The root of SSDT seems to be in the file: '''vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl'''<br />
<br />
We can work around the broken SSDT in mainboard support by maing the following changes to this line in '''acpi_tables.c''':<br />
<br />
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ // alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ alib = NULL;<br />
<br />
A full diagnostic report is given:<br />
<br />
Test 2 of 2: Disassemble and reassemble SSDT<br />
<br />
Checking ACPI table SSDT (#0)<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1151<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01148| If (CondRefOf (\_SB.ALIC, Local6))<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_SLEEP, expecting ',' or ')'<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
01153| 0x05))<br />
01154| {<br />
================================================================================<br />
:<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_CONTINUE, expecting ',' or ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1158<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01155| Store (0x01, Local4)<br />
01156| Store (0x00, Local2)<br />
01157| A074 (Arg0, 0x02)<br />
01158| }, If (LEqual (Local2, 0x00))<br />
| ^<br />
| Error 6126: syntax error, unexpected ','<br />
01159| {<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1163<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
01162| Store (0x08, Local2)<br />
01163| })<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01164| }<br />
01165| }<br />
01166| }<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] SyntaxCheckIASLCompilerAborted: Test 2, Compilation aborted early<br />
due to a parser detected syntax error.<br />
<br />
ADVICE: Some subsequent errors may not be detected because the compiler had to<br />
terminate prematurely. If the compiler did not abort early then potentially<br />
correct code may parse incorrectly producing some or many false positive errors.<br />
<br />
Table SSDT (0) reassembly: Found 5 errors, 0 warnings, 0 remarks.<br />
<br />
==== Remark 2089: Object is not referenced ====<br />
<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,0,CDW1)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,4,CDW2)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,8,CDW3)<br />
<br />
Checking ACPI table DSDT (#0)<br />
<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1793<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01790| Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
================================================================================<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1794<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
01797| /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,<br />
================================================================================<br />
Table DSDT (0) reassembly: Found 0 errors, 0 warnings, 2 remarks.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=User_talk:Eocallaghan&diff=13751
User talk:Eocallaghan
2014-06-05T23:09:38Z
<p>Eocallaghan: /* AGESA family table */</p>
<hr />
<div>You can find me floating in #coreboot as ''funfunctor''<br />
<br />
== Sections deserving their own page ==<br />
* [[User_talk:Eocallaghan/Secure_RAM_API | IDEAPAGE: Mitigation ageist attack on encryption keys in memory after cold boot]]<br />
* [[User_talk:Eocallaghan/EOL_ROMCC_BOARDS | IDEAPAGE: List ROMCC dependant boards to possibly EOL]]<br />
* [[User_talk:Eocallaghan/REFACTOR_AGESA | IDEAPAGE: Refactor AGESA for the long term]]<br />
<br />
<br />
== AGESA family table ==<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Family<br />
|-<br />
! K10 architecture (2011)<br />
| Llano || f12<br />
|-<br />
! Bobcat architecture (2011)<br />
| Ontario || f14<br />
|-<br />
|<br />
| Zacate || f14<br />
|-<br />
|<br />
| Desna || f14<br />
|-<br />
|<br />
| Hondo || f14<br />
|-<br />
! Piledriver architecture (2012)<br />
| Orochi || f15<br />
|-<br />
|<br />
| Trinity || f15tn<br />
|-<br />
|<br />
| Richland || f15rl<br />
|-<br />
! Jaguar architecture (2013)<br />
| Kabini || f16kb<br />
|-<br />
|<br />
| Temash || ??<br />
|}<br />
<br />
* Family 15h Models 00h-0fh is Orochi<br />
<br />
== Current Activities ==<br />
<br />
* Clean up superio support.<br />
* Fix DSDT/SSDT in AGESA<br />
<br />
=== AGESA - DSDT/SSDT ===<br />
<br />
Current list of issues below:<br />
<br />
==== Error 6126: syntax error, *** ====<br />
<br />
Notes:<br />
<br />
We may extract and decompile the first SSDT table in the following way:<br />
cat /sys/firmware/acpi/tables/SSDT1 > ssdt.dd ; iasl -d ssdt.dd<br />
<br />
A '''snip''' of the broken code fragment in question is given:<br />
<br />
If (LEqual (Local2, 0x07))<br />
{<br />
If (CondRefOf (\_SB.ALIC, Local6))<br />
{<br />
Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
\_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00, <br />
Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2, <br />
0x05))<br />
{<br />
Store (0x01, Local4)<br />
Store (0x00, Local2)<br />
A074 (Arg0, 0x02)<br />
}, If (LEqual (Local2, 0x00))<br />
{<br />
Store (0x01, A017) /* \_SB_.A017 */<br />
A029 ()<br />
Store (0x08, Local2)<br />
})<br />
}<br />
}<br />
<br />
<br />
Currently AGESA has pre-compiled a bunch of .esl files into:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h'''<br />
<br />
This array of pre-compiled SSDT bytecode is used to construct the SSDT table in:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c'''<br />
<br />
in the function:<br />
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { .. }<br />
<br />
The root of SSDT seems to be in the file: '''vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl'''<br />
<br />
We can work around the broken SSDT in mainboard support by maing the following changes to this line in '''acpi_tables.c''':<br />
<br />
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ // alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ alib = NULL;<br />
<br />
A full diagnostic report is given:<br />
<br />
Test 2 of 2: Disassemble and reassemble SSDT<br />
<br />
Checking ACPI table SSDT (#0)<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1151<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01148| If (CondRefOf (\_SB.ALIC, Local6))<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_SLEEP, expecting ',' or ')'<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
01153| 0x05))<br />
01154| {<br />
================================================================================<br />
:<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_CONTINUE, expecting ',' or ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1158<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01155| Store (0x01, Local4)<br />
01156| Store (0x00, Local2)<br />
01157| A074 (Arg0, 0x02)<br />
01158| }, If (LEqual (Local2, 0x00))<br />
| ^<br />
| Error 6126: syntax error, unexpected ','<br />
01159| {<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1163<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
01162| Store (0x08, Local2)<br />
01163| })<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01164| }<br />
01165| }<br />
01166| }<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] SyntaxCheckIASLCompilerAborted: Test 2, Compilation aborted early<br />
due to a parser detected syntax error.<br />
<br />
ADVICE: Some subsequent errors may not be detected because the compiler had to<br />
terminate prematurely. If the compiler did not abort early then potentially<br />
correct code may parse incorrectly producing some or many false positive errors.<br />
<br />
Table SSDT (0) reassembly: Found 5 errors, 0 warnings, 0 remarks.<br />
<br />
==== Remark 2089: Object is not referenced ====<br />
<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,0,CDW1)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,4,CDW2)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,8,CDW3)<br />
<br />
Checking ACPI table DSDT (#0)<br />
<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1793<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01790| Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
================================================================================<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1794<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
01797| /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,<br />
================================================================================<br />
Table DSDT (0) reassembly: Found 0 errors, 0 warnings, 2 remarks.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=User_talk:Eocallaghan&diff=13727
User talk:Eocallaghan
2014-05-23T20:37:32Z
<p>Eocallaghan: /* AGESA family table */</p>
<hr />
<div>You can find me floating in #coreboot as ''funfunctor''<br />
<br />
== Sections deserving their own page ==<br />
* [[User_talk:Eocallaghan/Secure_RAM_API | IDEAPAGE: Mitigation ageist attack on encryption keys in memory after cold boot]]<br />
* [[User_talk:Eocallaghan/EOL_ROMCC_BOARDS | IDEAPAGE: List ROMCC dependant boards to possibly EOL]]<br />
* [[User_talk:Eocallaghan/REFACTOR_AGESA | IDEAPAGE: Refactor AGESA for the long term]]<br />
<br />
<br />
== AGESA family table ==<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Family<br />
|-<br />
! K10 architecture (2011)<br />
| Llano || f12<br />
|-<br />
! Bobcat architecture (2011)<br />
| Ontario || f14<br />
|-<br />
|<br />
| Zacate || f14<br />
|-<br />
|<br />
| Desna || f14<br />
|-<br />
|<br />
| Hondo || f14<br />
|-<br />
! Piledriver architecture (2012)<br />
| Trinity || f15tn<br />
|-<br />
|<br />
| Richland || f15rl<br />
|-<br />
! Jaguar architecture (2013)<br />
| Kabini || f16kb<br />
|-<br />
|<br />
| Temash || ??<br />
|}<br />
<br />
== Current Activities ==<br />
<br />
* Clean up superio support.<br />
* Fix DSDT/SSDT in AGESA<br />
<br />
=== AGESA - DSDT/SSDT ===<br />
<br />
Current list of issues below:<br />
<br />
==== Error 6126: syntax error, *** ====<br />
<br />
Notes:<br />
<br />
We may extract and decompile the first SSDT table in the following way:<br />
cat /sys/firmware/acpi/tables/SSDT1 > ssdt.dd ; iasl -d ssdt.dd<br />
<br />
A '''snip''' of the broken code fragment in question is given:<br />
<br />
If (LEqual (Local2, 0x07))<br />
{<br />
If (CondRefOf (\_SB.ALIC, Local6))<br />
{<br />
Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
\_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00, <br />
Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2, <br />
0x05))<br />
{<br />
Store (0x01, Local4)<br />
Store (0x00, Local2)<br />
A074 (Arg0, 0x02)<br />
}, If (LEqual (Local2, 0x00))<br />
{<br />
Store (0x01, A017) /* \_SB_.A017 */<br />
A029 ()<br />
Store (0x08, Local2)<br />
})<br />
}<br />
}<br />
<br />
<br />
Currently AGESA has pre-compiled a bunch of .esl files into:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h'''<br />
<br />
This array of pre-compiled SSDT bytecode is used to construct the SSDT table in:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c'''<br />
<br />
in the function:<br />
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { .. }<br />
<br />
The root of SSDT seems to be in the file: '''vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl'''<br />
<br />
We can work around the broken SSDT in mainboard support by maing the following changes to this line in '''acpi_tables.c''':<br />
<br />
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ // alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ alib = NULL;<br />
<br />
A full diagnostic report is given:<br />
<br />
Test 2 of 2: Disassemble and reassemble SSDT<br />
<br />
Checking ACPI table SSDT (#0)<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1151<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01148| If (CondRefOf (\_SB.ALIC, Local6))<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_SLEEP, expecting ',' or ')'<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
01153| 0x05))<br />
01154| {<br />
================================================================================<br />
:<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_CONTINUE, expecting ',' or ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1158<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01155| Store (0x01, Local4)<br />
01156| Store (0x00, Local2)<br />
01157| A074 (Arg0, 0x02)<br />
01158| }, If (LEqual (Local2, 0x00))<br />
| ^<br />
| Error 6126: syntax error, unexpected ','<br />
01159| {<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1163<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
01162| Store (0x08, Local2)<br />
01163| })<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01164| }<br />
01165| }<br />
01166| }<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] SyntaxCheckIASLCompilerAborted: Test 2, Compilation aborted early<br />
due to a parser detected syntax error.<br />
<br />
ADVICE: Some subsequent errors may not be detected because the compiler had to<br />
terminate prematurely. If the compiler did not abort early then potentially<br />
correct code may parse incorrectly producing some or many false positive errors.<br />
<br />
Table SSDT (0) reassembly: Found 5 errors, 0 warnings, 0 remarks.<br />
<br />
==== Remark 2089: Object is not referenced ====<br />
<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,0,CDW1)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,4,CDW2)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,8,CDW3)<br />
<br />
Checking ACPI table DSDT (#0)<br />
<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1793<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01790| Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
================================================================================<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1794<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
01797| /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,<br />
================================================================================<br />
Table DSDT (0) reassembly: Found 0 errors, 0 warnings, 2 remarks.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=User_talk:Eocallaghan&diff=13726
User talk:Eocallaghan
2014-05-23T20:35:41Z
<p>Eocallaghan: /* AGESA family table */</p>
<hr />
<div>You can find me floating in #coreboot as ''funfunctor''<br />
<br />
== Sections deserving their own page ==<br />
* [[User_talk:Eocallaghan/Secure_RAM_API | IDEAPAGE: Mitigation ageist attack on encryption keys in memory after cold boot]]<br />
* [[User_talk:Eocallaghan/EOL_ROMCC_BOARDS | IDEAPAGE: List ROMCC dependant boards to possibly EOL]]<br />
* [[User_talk:Eocallaghan/REFACTOR_AGESA | IDEAPAGE: Refactor AGESA for the long term]]<br />
<br />
<br />
== AGESA family table ==<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Family<br />
|-<br />
! K10 architecture (2011)<br />
| Llano || f12<br />
|-<br />
! Bobcat architecture (2011)<br />
| Ontario || f14<br />
|-<br />
|<br />
| Zacate || f14<br />
|-<br />
|<br />
| Desna || f14<br />
|-<br />
|<br />
| Hondo || f14<br />
|-<br />
! Piledriver architecture (2012)<br />
| Trinity || f15tn<br />
|-<br />
|<br />
| Richland || f15rl<br />
|-<br />
! Jaguar architecture (2013)<br />
| Kabini || f16<br />
|-<br />
|<br />
| Temash || f16<br />
|}<br />
<br />
== Current Activities ==<br />
<br />
* Clean up superio support.<br />
* Fix DSDT/SSDT in AGESA<br />
<br />
=== AGESA - DSDT/SSDT ===<br />
<br />
Current list of issues below:<br />
<br />
==== Error 6126: syntax error, *** ====<br />
<br />
Notes:<br />
<br />
We may extract and decompile the first SSDT table in the following way:<br />
cat /sys/firmware/acpi/tables/SSDT1 > ssdt.dd ; iasl -d ssdt.dd<br />
<br />
A '''snip''' of the broken code fragment in question is given:<br />
<br />
If (LEqual (Local2, 0x07))<br />
{<br />
If (CondRefOf (\_SB.ALIC, Local6))<br />
{<br />
Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
\_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00, <br />
Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2, <br />
0x05))<br />
{<br />
Store (0x01, Local4)<br />
Store (0x00, Local2)<br />
A074 (Arg0, 0x02)<br />
}, If (LEqual (Local2, 0x00))<br />
{<br />
Store (0x01, A017) /* \_SB_.A017 */<br />
A029 ()<br />
Store (0x08, Local2)<br />
})<br />
}<br />
}<br />
<br />
<br />
Currently AGESA has pre-compiled a bunch of .esl files into:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h'''<br />
<br />
This array of pre-compiled SSDT bytecode is used to construct the SSDT table in:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c'''<br />
<br />
in the function:<br />
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { .. }<br />
<br />
The root of SSDT seems to be in the file: '''vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl'''<br />
<br />
We can work around the broken SSDT in mainboard support by maing the following changes to this line in '''acpi_tables.c''':<br />
<br />
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ // alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ alib = NULL;<br />
<br />
A full diagnostic report is given:<br />
<br />
Test 2 of 2: Disassemble and reassemble SSDT<br />
<br />
Checking ACPI table SSDT (#0)<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1151<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01148| If (CondRefOf (\_SB.ALIC, Local6))<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_SLEEP, expecting ',' or ')'<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
01153| 0x05))<br />
01154| {<br />
================================================================================<br />
:<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_CONTINUE, expecting ',' or ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1158<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01155| Store (0x01, Local4)<br />
01156| Store (0x00, Local2)<br />
01157| A074 (Arg0, 0x02)<br />
01158| }, If (LEqual (Local2, 0x00))<br />
| ^<br />
| Error 6126: syntax error, unexpected ','<br />
01159| {<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1163<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
01162| Store (0x08, Local2)<br />
01163| })<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01164| }<br />
01165| }<br />
01166| }<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] SyntaxCheckIASLCompilerAborted: Test 2, Compilation aborted early<br />
due to a parser detected syntax error.<br />
<br />
ADVICE: Some subsequent errors may not be detected because the compiler had to<br />
terminate prematurely. If the compiler did not abort early then potentially<br />
correct code may parse incorrectly producing some or many false positive errors.<br />
<br />
Table SSDT (0) reassembly: Found 5 errors, 0 warnings, 0 remarks.<br />
<br />
==== Remark 2089: Object is not referenced ====<br />
<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,0,CDW1)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,4,CDW2)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,8,CDW3)<br />
<br />
Checking ACPI table DSDT (#0)<br />
<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1793<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01790| Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
================================================================================<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1794<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
01797| /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,<br />
================================================================================<br />
Table DSDT (0) reassembly: Found 0 errors, 0 warnings, 2 remarks.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=User_talk:Eocallaghan&diff=13725
User talk:Eocallaghan
2014-05-23T20:29:01Z
<p>Eocallaghan: /* AGESA family table */</p>
<hr />
<div>You can find me floating in #coreboot as ''funfunctor''<br />
<br />
== Sections deserving their own page ==<br />
* [[User_talk:Eocallaghan/Secure_RAM_API | IDEAPAGE: Mitigation ageist attack on encryption keys in memory after cold boot]]<br />
* [[User_talk:Eocallaghan/EOL_ROMCC_BOARDS | IDEAPAGE: List ROMCC dependant boards to possibly EOL]]<br />
* [[User_talk:Eocallaghan/REFACTOR_AGESA | IDEAPAGE: Refactor AGESA for the long term]]<br />
<br />
<br />
== AGESA family table ==<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Family<br />
|-<br />
! K10 architecture (2011)<br />
| Llano || ???<br />
|-<br />
! Bobcat architecture (2011)<br />
| Ontario || f14<br />
|-<br />
|<br />
| Zacate || f14<br />
|-<br />
|<br />
| Desna || f14<br />
|-<br />
|<br />
| Hondo || f14<br />
|-<br />
! Piledriver architecture (2012)<br />
| Trinity || f15tn<br />
|-<br />
|<br />
| Richland || f15rl<br />
|-<br />
! Jaguar architecture (2013)<br />
| Kabini || f16<br />
|-<br />
|<br />
| Temash || f16<br />
|}<br />
<br />
== Current Activities ==<br />
<br />
* Clean up superio support.<br />
* Fix DSDT/SSDT in AGESA<br />
<br />
=== AGESA - DSDT/SSDT ===<br />
<br />
Current list of issues below:<br />
<br />
==== Error 6126: syntax error, *** ====<br />
<br />
Notes:<br />
<br />
We may extract and decompile the first SSDT table in the following way:<br />
cat /sys/firmware/acpi/tables/SSDT1 > ssdt.dd ; iasl -d ssdt.dd<br />
<br />
A '''snip''' of the broken code fragment in question is given:<br />
<br />
If (LEqual (Local2, 0x07))<br />
{<br />
If (CondRefOf (\_SB.ALIC, Local6))<br />
{<br />
Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
\_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00, <br />
Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2, <br />
0x05))<br />
{<br />
Store (0x01, Local4)<br />
Store (0x00, Local2)<br />
A074 (Arg0, 0x02)<br />
}, If (LEqual (Local2, 0x00))<br />
{<br />
Store (0x01, A017) /* \_SB_.A017 */<br />
A029 ()<br />
Store (0x08, Local2)<br />
})<br />
}<br />
}<br />
<br />
<br />
Currently AGESA has pre-compiled a bunch of .esl files into:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h'''<br />
<br />
This array of pre-compiled SSDT bytecode is used to construct the SSDT table in:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c'''<br />
<br />
in the function:<br />
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { .. }<br />
<br />
The root of SSDT seems to be in the file: '''vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl'''<br />
<br />
We can work around the broken SSDT in mainboard support by maing the following changes to this line in '''acpi_tables.c''':<br />
<br />
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ // alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ alib = NULL;<br />
<br />
A full diagnostic report is given:<br />
<br />
Test 2 of 2: Disassemble and reassemble SSDT<br />
<br />
Checking ACPI table SSDT (#0)<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1151<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01148| If (CondRefOf (\_SB.ALIC, Local6))<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_SLEEP, expecting ',' or ')'<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
01153| 0x05))<br />
01154| {<br />
================================================================================<br />
:<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_CONTINUE, expecting ',' or ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1158<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01155| Store (0x01, Local4)<br />
01156| Store (0x00, Local2)<br />
01157| A074 (Arg0, 0x02)<br />
01158| }, If (LEqual (Local2, 0x00))<br />
| ^<br />
| Error 6126: syntax error, unexpected ','<br />
01159| {<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1163<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
01162| Store (0x08, Local2)<br />
01163| })<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01164| }<br />
01165| }<br />
01166| }<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] SyntaxCheckIASLCompilerAborted: Test 2, Compilation aborted early<br />
due to a parser detected syntax error.<br />
<br />
ADVICE: Some subsequent errors may not be detected because the compiler had to<br />
terminate prematurely. If the compiler did not abort early then potentially<br />
correct code may parse incorrectly producing some or many false positive errors.<br />
<br />
Table SSDT (0) reassembly: Found 5 errors, 0 warnings, 0 remarks.<br />
<br />
==== Remark 2089: Object is not referenced ====<br />
<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,0,CDW1)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,4,CDW2)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,8,CDW3)<br />
<br />
Checking ACPI table DSDT (#0)<br />
<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1793<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01790| Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
================================================================================<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1794<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
01797| /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,<br />
================================================================================<br />
Table DSDT (0) reassembly: Found 0 errors, 0 warnings, 2 remarks.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=User_talk:Eocallaghan&diff=13724
User talk:Eocallaghan
2014-05-23T20:23:21Z
<p>Eocallaghan: </p>
<hr />
<div>You can find me floating in #coreboot as ''funfunctor''<br />
<br />
== Sections deserving their own page ==<br />
* [[User_talk:Eocallaghan/Secure_RAM_API | IDEAPAGE: Mitigation ageist attack on encryption keys in memory after cold boot]]<br />
* [[User_talk:Eocallaghan/EOL_ROMCC_BOARDS | IDEAPAGE: List ROMCC dependant boards to possibly EOL]]<br />
* [[User_talk:Eocallaghan/REFACTOR_AGESA | IDEAPAGE: Refactor AGESA for the long term]]<br />
<br />
<br />
== AGESA family table ==<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Family<br />
|-<br />
| Bobcat architecture (2011)<br />
| Ontario || f14<br />
|-<br />
|<br />
| Zacate || f14<br />
|-<br />
|<br />
| Desna || f14<br />
|-<br />
|<br />
| Hondo || f14<br />
|-<br />
| Piledriver architecture (2012)<br />
| Trinity || f15tn<br />
|-<br />
|<br />
| Richland || f15rl<br />
|-<br />
|}<br />
<br />
== Current Activities ==<br />
<br />
* Clean up superio support.<br />
* Fix DSDT/SSDT in AGESA<br />
<br />
=== AGESA - DSDT/SSDT ===<br />
<br />
Current list of issues below:<br />
<br />
==== Error 6126: syntax error, *** ====<br />
<br />
Notes:<br />
<br />
We may extract and decompile the first SSDT table in the following way:<br />
cat /sys/firmware/acpi/tables/SSDT1 > ssdt.dd ; iasl -d ssdt.dd<br />
<br />
A '''snip''' of the broken code fragment in question is given:<br />
<br />
If (LEqual (Local2, 0x07))<br />
{<br />
If (CondRefOf (\_SB.ALIC, Local6))<br />
{<br />
Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
\_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00, <br />
Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2, <br />
0x05))<br />
{<br />
Store (0x01, Local4)<br />
Store (0x00, Local2)<br />
A074 (Arg0, 0x02)<br />
}, If (LEqual (Local2, 0x00))<br />
{<br />
Store (0x01, A017) /* \_SB_.A017 */<br />
A029 ()<br />
Store (0x08, Local2)<br />
})<br />
}<br />
}<br />
<br />
<br />
Currently AGESA has pre-compiled a bunch of .esl files into:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h'''<br />
<br />
This array of pre-compiled SSDT bytecode is used to construct the SSDT table in:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c'''<br />
<br />
in the function:<br />
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { .. }<br />
<br />
The root of SSDT seems to be in the file: '''vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl'''<br />
<br />
We can work around the broken SSDT in mainboard support by maing the following changes to this line in '''acpi_tables.c''':<br />
<br />
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ // alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ alib = NULL;<br />
<br />
A full diagnostic report is given:<br />
<br />
Test 2 of 2: Disassemble and reassemble SSDT<br />
<br />
Checking ACPI table SSDT (#0)<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1151<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01148| If (CondRefOf (\_SB.ALIC, Local6))<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_SLEEP, expecting ',' or ')'<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
01153| 0x05))<br />
01154| {<br />
================================================================================<br />
:<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_CONTINUE, expecting ',' or ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1158<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01155| Store (0x01, Local4)<br />
01156| Store (0x00, Local2)<br />
01157| A074 (Arg0, 0x02)<br />
01158| }, If (LEqual (Local2, 0x00))<br />
| ^<br />
| Error 6126: syntax error, unexpected ','<br />
01159| {<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1163<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
01162| Store (0x08, Local2)<br />
01163| })<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01164| }<br />
01165| }<br />
01166| }<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] SyntaxCheckIASLCompilerAborted: Test 2, Compilation aborted early<br />
due to a parser detected syntax error.<br />
<br />
ADVICE: Some subsequent errors may not be detected because the compiler had to<br />
terminate prematurely. If the compiler did not abort early then potentially<br />
correct code may parse incorrectly producing some or many false positive errors.<br />
<br />
Table SSDT (0) reassembly: Found 5 errors, 0 warnings, 0 remarks.<br />
<br />
==== Remark 2089: Object is not referenced ====<br />
<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,0,CDW1)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,4,CDW2)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,8,CDW3)<br />
<br />
Checking ACPI table DSDT (#0)<br />
<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1793<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01790| Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
================================================================================<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1794<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
01797| /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,<br />
================================================================================<br />
Table DSDT (0) reassembly: Found 0 errors, 0 warnings, 2 remarks.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=User_talk:Eocallaghan&diff=13723
User talk:Eocallaghan
2014-05-23T20:22:38Z
<p>Eocallaghan: /* AGESA family table */</p>
<hr />
<div>You can find me floating in #coreboot as ''funfunctor''<br />
<br />
== Sections deserving their own page ==<br />
* [[User_talk:Eocallaghan/Secure_RAM_API | IDEAPAGE: Mitigation ageist attack on encryption keys in memory after cold boot]]<br />
* [[User_talk:Eocallaghan/EOL_ROMCC_BOARDS | IDEAPAGE: List ROMCC dependant boards to possibly EOL]]<br />
* [[User_talk:Eocallaghan/REFACTOR_AGESA | IDEAPAGE: Refactor AGESA for the long term]]<br />
<br />
== Current Activities ==<br />
<br />
* Clean up superio support.<br />
* Fix DSDT/SSDT in AGESA<br />
<br />
=== AGESA - DSDT/SSDT ===<br />
<br />
Current list of issues below:<br />
<br />
==== Error 6126: syntax error, *** ====<br />
<br />
Notes:<br />
<br />
We may extract and decompile the first SSDT table in the following way:<br />
cat /sys/firmware/acpi/tables/SSDT1 > ssdt.dd ; iasl -d ssdt.dd<br />
<br />
A '''snip''' of the broken code fragment in question is given:<br />
<br />
If (LEqual (Local2, 0x07))<br />
{<br />
If (CondRefOf (\_SB.ALIC, Local6))<br />
{<br />
Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
\_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00, <br />
Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2, <br />
0x05))<br />
{<br />
Store (0x01, Local4)<br />
Store (0x00, Local2)<br />
A074 (Arg0, 0x02)<br />
}, If (LEqual (Local2, 0x00))<br />
{<br />
Store (0x01, A017) /* \_SB_.A017 */<br />
A029 ()<br />
Store (0x08, Local2)<br />
})<br />
}<br />
}<br />
<br />
<br />
Currently AGESA has pre-compiled a bunch of .esl files into:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h'''<br />
<br />
This array of pre-compiled SSDT bytecode is used to construct the SSDT table in:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c'''<br />
<br />
in the function:<br />
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { .. }<br />
<br />
The root of SSDT seems to be in the file: '''vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl'''<br />
<br />
We can work around the broken SSDT in mainboard support by maing the following changes to this line in '''acpi_tables.c''':<br />
<br />
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ // alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ alib = NULL;<br />
<br />
A full diagnostic report is given:<br />
<br />
Test 2 of 2: Disassemble and reassemble SSDT<br />
<br />
Checking ACPI table SSDT (#0)<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1151<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01148| If (CondRefOf (\_SB.ALIC, Local6))<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_SLEEP, expecting ',' or ')'<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
01153| 0x05))<br />
01154| {<br />
================================================================================<br />
:<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_CONTINUE, expecting ',' or ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1158<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01155| Store (0x01, Local4)<br />
01156| Store (0x00, Local2)<br />
01157| A074 (Arg0, 0x02)<br />
01158| }, If (LEqual (Local2, 0x00))<br />
| ^<br />
| Error 6126: syntax error, unexpected ','<br />
01159| {<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1163<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
01162| Store (0x08, Local2)<br />
01163| })<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01164| }<br />
01165| }<br />
01166| }<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] SyntaxCheckIASLCompilerAborted: Test 2, Compilation aborted early<br />
due to a parser detected syntax error.<br />
<br />
ADVICE: Some subsequent errors may not be detected because the compiler had to<br />
terminate prematurely. If the compiler did not abort early then potentially<br />
correct code may parse incorrectly producing some or many false positive errors.<br />
<br />
Table SSDT (0) reassembly: Found 5 errors, 0 warnings, 0 remarks.<br />
<br />
==== Remark 2089: Object is not referenced ====<br />
<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,0,CDW1)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,4,CDW2)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,8,CDW3)<br />
<br />
Checking ACPI table DSDT (#0)<br />
<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1793<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01790| Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
================================================================================<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1794<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
01797| /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,<br />
================================================================================<br />
Table DSDT (0) reassembly: Found 0 errors, 0 warnings, 2 remarks.<br />
<br />
== AGESA family table ==<br />
<br />
{| border="1" class="wikitable"<br />
|+ AMD AGESA map<br />
|-<br />
! Arch Name<br />
! Model Name<br />
! Family<br />
|-<br />
| Bobcat architecture (2011)<br />
| Ontario || f14<br />
|-<br />
|<br />
| Zacate || f14<br />
|-<br />
|<br />
| Desna || f14<br />
|-<br />
|<br />
| Hondo || f14<br />
|-<br />
| Piledriver architecture (2012)<br />
| Trinity || f15tn<br />
|-<br />
|<br />
| Richland || f15rl<br />
|-<br />
|}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=User_talk:Eocallaghan&diff=13722
User talk:Eocallaghan
2014-05-23T20:04:39Z
<p>Eocallaghan: /* AGESA family table */ new section</p>
<hr />
<div>You can find me floating in #coreboot as ''funfunctor''<br />
<br />
== Sections deserving their own page ==<br />
* [[User_talk:Eocallaghan/Secure_RAM_API | IDEAPAGE: Mitigation ageist attack on encryption keys in memory after cold boot]]<br />
* [[User_talk:Eocallaghan/EOL_ROMCC_BOARDS | IDEAPAGE: List ROMCC dependant boards to possibly EOL]]<br />
* [[User_talk:Eocallaghan/REFACTOR_AGESA | IDEAPAGE: Refactor AGESA for the long term]]<br />
<br />
== Current Activities ==<br />
<br />
* Clean up superio support.<br />
* Fix DSDT/SSDT in AGESA<br />
<br />
=== AGESA - DSDT/SSDT ===<br />
<br />
Current list of issues below:<br />
<br />
==== Error 6126: syntax error, *** ====<br />
<br />
Notes:<br />
<br />
We may extract and decompile the first SSDT table in the following way:<br />
cat /sys/firmware/acpi/tables/SSDT1 > ssdt.dd ; iasl -d ssdt.dd<br />
<br />
A '''snip''' of the broken code fragment in question is given:<br />
<br />
If (LEqual (Local2, 0x07))<br />
{<br />
If (CondRefOf (\_SB.ALIC, Local6))<br />
{<br />
Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
\_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00, <br />
Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2, <br />
0x05))<br />
{<br />
Store (0x01, Local4)<br />
Store (0x00, Local2)<br />
A074 (Arg0, 0x02)<br />
}, If (LEqual (Local2, 0x00))<br />
{<br />
Store (0x01, A017) /* \_SB_.A017 */<br />
A029 ()<br />
Store (0x08, Local2)<br />
})<br />
}<br />
}<br />
<br />
<br />
Currently AGESA has pre-compiled a bunch of .esl files into:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h'''<br />
<br />
This array of pre-compiled SSDT bytecode is used to construct the SSDT table in:<br />
<br />
'''src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c'''<br />
<br />
in the function:<br />
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { .. }<br />
<br />
The root of SSDT seems to be in the file: '''vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl'''<br />
<br />
We can work around the broken SSDT in mainboard support by maing the following changes to this line in '''acpi_tables.c''':<br />
<br />
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ // alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);<br />
+ alib = NULL;<br />
<br />
A full diagnostic report is given:<br />
<br />
Test 2 of 2: Disassemble and reassemble SSDT<br />
<br />
Checking ACPI table SSDT (#0)<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1151<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01148| If (CondRefOf (\_SB.ALIC, Local6))<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_SLEEP, expecting ',' or ')'<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
01153| 0x05))<br />
01154| {<br />
================================================================================<br />
:<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected PARSEOP_CONTINUE, expecting ',' or ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1152<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01149| {<br />
01150| Store (ShiftLeft (Add (Arg0, 0x02), 0x03), Local1)<br />
01151| \_SB.ALIC (Local1, 0x00, Sleep (0x02), \_SB.ALIC (Local1, 0x01, Store (0x00,<br />
01152| Local3), Store (0x01, Local2), Continue, Store (0x04, Local2)), If (LEqual (Local2,<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01153| 0x05))<br />
01154| {<br />
01155| Store (0x01, Local4)<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1158<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01155| Store (0x01, Local4)<br />
01156| Store (0x00, Local2)<br />
01157| A074 (Arg0, 0x02)<br />
01158| }, If (LEqual (Local2, 0x00))<br />
| ^<br />
| Error 6126: syntax error, unexpected ','<br />
01159| {<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] AMLAsmASL_MSG_SYNTAX: Test 2, Assembler error in line 1163<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01160| Store (0x01, A017) /* \_SB_.A017 */<br />
01161| A029 ()<br />
01162| Store (0x08, Local2)<br />
01163| })<br />
| ^<br />
| Error 6126: syntax error, unexpected ')'<br />
01164| }<br />
01165| }<br />
01166| }<br />
================================================================================<br />
<br />
ADVICE: (for Error #6126, ASL_MSG_SYNTAX): The disassembled code cannot be<br />
reassembled using the strict IASL compiler as it contains syntax errors.<br />
<br />
FAILED [HIGH] SyntaxCheckIASLCompilerAborted: Test 2, Compilation aborted early<br />
due to a parser detected syntax error.<br />
<br />
ADVICE: Some subsequent errors may not be detected because the compiler had to<br />
terminate prematurely. If the compiler did not abort early then potentially<br />
correct code may parse incorrectly producing some or many false positive errors.<br />
<br />
Table SSDT (0) reassembly: Found 5 errors, 0 warnings, 0 remarks.<br />
<br />
==== Remark 2089: Object is not referenced ====<br />
<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,0,CDW1)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,4,CDW2)<br />
./src/southbridge/amd/cimx/sb800/acpi/fch.asl: CreateDWordField(Arg3,8,CDW3)<br />
<br />
Checking ACPI table DSDT (#0)<br />
<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1793<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01790| Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
================================================================================<br />
FAILED [LOW] AMLAsmASL_MSG_NOT_REFERENCED: Test 1, Assembler remark in line 1794<br />
Line | AML source<br />
--------------------------------------------------------------------------------<br />
01791| {<br />
01792| CreateDWordField (Arg3, Zero, CDW1)<br />
01793| CreateDWordField (Arg3, 0x04, CDW2)<br />
01794| CreateDWordField (Arg3, 0x08, CDW3)<br />
| ^<br />
| Remark 2089: Object is not referenced (Name is within method [_OSC])<br />
01795| If (LEqual (Arg0, Buffer (0x10)<br />
01796| {<br />
01797| /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,<br />
================================================================================<br />
Table DSDT (0) reassembly: Found 0 errors, 0 warnings, 2 remarks.<br />
<br />
== AGESA family table ==<br />
<br />
{| border=1<br />
| Name<br />
| Family<br />
|-<br />
| Trinity<br />
| f15tn<br />
|-<br />
| Richland<br />
| f15rl<br />
|}</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Talk:Development_Guidelines&diff=13651
Talk:Development Guidelines
2014-05-01T19:06:29Z
<p>Eocallaghan: Proposed commit message policy</p>
<hr />
<div>Some other interesting commit rules can be found here:<br />
<br />
* http://www.freebsd.org/doc/en_US.ISO8859-1/articles/committers-guide/rules.html<br />
<br />
== Commit messages ==<br />
<br />
=== Short Summary ===<br />
<br />
Try to encapsulate what the changeset effects in the source tree at the begining of the commit message. For examples:<br />
<br />
mainboard/amd/foo: ..<br />
superio/bar: ..<br />
<br />
and so on. The short summary should be 50 chars or less.<br />
<br />
=== Body Text ===<br />
<br />
* Try to explain the reasoning behind your changeset, not how you did it or what tools you used.<br />
* Avoid putting URL's in commit messages. URL's do not last forever.<br />
* Do not put shell script in commit messages please.<br />
<br />
Additionally, putting executable shell script and URL's in commit messages makes it harder to match & parse useful information out of the commit message body with standard unix tools (awk,grep,sed,..).<br />
It is also not directly useful in figuring out what your changeset is actually about while looking back.<br />
<br />
To cross reference your changeset with a older changeset in git's history, use its short hash set to 7 chars like in the following example:<br />
<br />
Following the reasoning in,<br />
e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA<br />
<br />
This is good practice as one can use standard *nix tools to parse out this information depending on what they intend to do..<br />
Here are some examples to demonstrate the point of this rational:<br />
<br />
Make a patch since that referenced commit hash in the commit hash 'ac6b7ab',<br />
git format-patch $(git log -1 --pretty=format:%b ac6b7ab | grep -E "\b[0-9a-f]{7,40}\b" | awk '{ printf $1}')<br />
<br />
Or show its summary,<br />
git show --pretty=medium --summary --color=always $(git log -1 --pretty=format:%b ac6b7ab | grep -E "\b[0-9a-f]{7,40}\b" | awk '{ printf $1}')<br />
<br />
Or you can even pass it to git-bisect to bisect from the embedded reference.</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Development_Guidelines&diff=13648
Development Guidelines
2014-05-01T09:24:04Z
<p>Eocallaghan: /* Body Text */</p>
<hr />
<div>= Development Environment =<br />
<br />
== Required Toolchain ==<br />
<br />
The easiest way to get a working toolchain is to run <code>make crossgcc</code> in the toplevel directory of a coreboot checkout. Distributions usually modify their compilers in ways incompatible with coreboot. If in doubt, use our toolchain.<br />
<br />
The toolchain consists of:<br />
* GNU development environment:<br />
** [http://gcc.gnu.org/ GCC with G++]<br />
** [http://www.kernel.org/pub/linux/devel/binutils/ binutils]<br />
* libncurses*-dev<br />
* [http://www.acpica.org/downloads/ IASL], now part of the '''ACPICA''' download (package ''pmtools'' or ''iasl'' in many distributions)<br />
<br />
= Coding Guidelines =<br />
<br />
== General Guidelines ==<br />
<br />
* Encapsulate and isolate assembly language<br />
* Code shall not be "commented out"<br />
* No use of floating-point arithmetics<br />
* No hiding of identifiers defined in outer scopes<br />
* Typedefs are unique (device_t?)<br />
* Functions shall have prototype declarations<br />
* Local functions should be declared static<br />
* No definitions in header files<br />
* All variables are assigned before use<br />
* All objects should have fully qualified types (''unsigned int'' instead of ''unsigned'')<br />
* Types which indicate signedness and bitness should be used (''uint32_t'' or ''u32'' instead of ''unsigned int'')<br />
* We suggest trying to import more such rules, such as additional ones described in [http://www.misra.org.uk/index.htm MISRA-C 2012] (''Guidelines for the use of C in critical systems'')<br />
<br />
== Variable types ==<br />
<br />
Whenever possible, please use a variable type which is explicit about the size of data it can hold. For example, use '''uint32_t''' or '''u32''' instead of '''unsigned long''' when referencing a 32-bit wide register.<br />
<br />
=== short int names vs stdint names ===<br />
<br />
There is '''currently no hard rule''' on whether one should use short int types ('''u32'''), or stdint types ('''uint32_t'''). Whichever type you elect to use, please use common sense and stay consistent.<br />
<br />
== Comments ==<br />
<br />
=== References ===<br />
<br />
If you are referencing a data sheet or other documentation in the code, please add the name or document number in addition to the URL. Vendors just ''love'' to rearrange their websites (and some remove documentation on their old products altogether)! If we have the name/number (or even just the filename of the PDF) at least there's a chance to google for it again (either on the vendor's site or on some archive).<br />
<br />
== Coding Style ==<br />
<br />
* We use the coreboot [[Coding Style]] throughout the project.<br />
* You can use the 'indent' tool to fix the coding style like this:<br />
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]<br />
:Do not trust 'indent' blindly, though. It sometimes gets things wrong. Manual corrections may be required.<br />
<br />
== The 80 character limit ==<br />
<br />
Lines larger than 80 columns should be broken down into readable pieces. This includes not only source files, but also Makefiles, Kconfig files, and any file meant to be edited by a human. We recommend setting your editor to show the 80th character limit.<br />
This limit is not a relic from long forgotten times, but a very practical and efficient way to organize code and increase productivity. Several files can be edited on the same monitor, without the need to side-scroll. Side-scrolling source files is inefficient, time-consuming, and uncomfortable. On average, 95% of source lines are shorter than 80 characters, so limiting the line length is this manner is not only _not_ an impediment, it also gets you to think on how to best organize the code.<br />
<br />
== Commit messages ==<br />
<br />
=== Short Summary ===<br />
<br />
Try to encapsulate what the changeset effects in the source tree at the begining of the commit message. For examples:<br />
<br />
mainboard/amd/foo: ..<br />
superio/bar: ..<br />
<br />
and so on. The short summary should be 50 chars or less.<br />
<br />
=== Body Text ===<br />
<br />
* Try to explain the reasoning behind your changeset, not how you did it or what tools you used.<br />
* Avoid putting URL's in commit messages. URL's do not last forever.<br />
* Do not put shell script in commit messages please.<br />
<br />
Additionally, putting executable shell script and URL's in commit messages makes it harder to match & parse useful information out of the commit message body with standard unix tools (awk,grep,sed,..).<br />
It is also not directly useful in figuring out what your changeset is actually about while looking back.<br />
<br />
To cross reference your changeset with a older changeset in git's history, use its short hash set to 7 chars like in the following example:<br />
<br />
Following the reasoning in,<br />
e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA<br />
<br />
This is good practice as one can use standard *nix tools to parse out this information depending on what they intend to do..<br />
Here are some examples to demonstrate the point of this rational:<br />
<br />
Make a patch since that referenced commit hash in the commit hash 'ac6b7ab',<br />
git format-patch $(git log -1 --pretty=format:%b ac6b7ab | grep -E "\b[0-9a-f]{7,40}\b" | awk '{ printf $1}')<br />
<br />
Or show its summary,<br />
git show --pretty=medium --summary --color=always $(git log -1 --pretty=format:%b ac6b7ab | grep -E "\b[0-9a-f]{7,40}\b" | awk '{ printf $1}')<br />
<br />
Or you can even pass it to git-bisect to bisect from the embedded reference.<br />
<br />
= Documentation Guidelines =<br />
<br />
== General Guidelines and Tips ==<br />
<br />
* Documentation should be put into the wiki and/or in the code as Doxygen comments<br />
* Avoid using different styles and looks of documentation<br />
* Document ''why'' and ''what'', not ''how'' (No comments like ''/* add one to i */'')<br />
* Document assumptions, stipulations etc...<br />
* Document design and concepts!<br />
* Not lots of documentation but good documentation<br />
* Structured documentation<br />
* Focus: Whom are you addressing in your documentation? Write documentation for users, developers, vendors, ...<br />
<br />
== Automatic documentation ==<br />
<br />
* Doxygen-generated API- and code documentation is available at http://qa.coreboot.org/docs/. This documentation is updated on every 10th checkin.<br />
* To create a Doxygen comment, write<br />
/**<br />
* Sample comment.<br />
*/<br />
:or<br />
/** Sample comment. */<br />
* There are a few commands that describe what kind of comment you are adding:<br />
::@param &mdash; input parameters of a function<br />
::@return &mdash; return value of a function<br />
* A list of all commands is available at http://www.stack.nl/~dimitri/doxygen/commands.html<br />
<br />
Full example:<br />
<br />
/**<br />
* Calculate the length of a string.<br />
*<br />
* @param str The input string.<br />
* @return The length of the string, not including the final NUL character.<br />
*/<br />
static inline size_t strlen(const char *str)<br />
{<br />
/* ... */<br />
}<br />
<br />
= Testing =<br />
<br />
Every commit will be processed by the autobuild and autotest system available at http://qa.coreboot.org/. In addition please run autobuild yourself before submitting patches.<br />
<br />
== autobuild ==<br />
<br />
Autobuild can be found at [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=util/abuild;hb=HEAD coreboot/util/abuild]. <br />
<br />
Please run ''abuild'' '''before''' you commit.<br />
<br />
Autobuild is also running on every check-in to the repository. The results of this build are also available at http://qa.coreboot.org/.<br />
<br />
== autotest ==<br />
<br />
We can also run automatic tests on boards, if we find contributors willing to have a board automatically managed by our QA system. This requires a permanent connection to the net, a host system and some special circuitry. If interested, please contact us using the [[Mailinglist|mailing list]].<br />
<br />
= How to contribute =<br />
<br />
== Creating Patches ==<br />
<br />
* We use gerrit for change management, using the instance on http://review.coreboot.org/<br />
* While not necessary with gerrit, '''make sure that your change is against current master'''. Patches that fail on merge (after some developer looked at it and approved it) might linger around until '''you''' update it.<br />
* Rebase, if necessary, '''then test''' again. You might be the only contributor with that specific mainboard.<br />
* Make sure all new and modified files contain the [[Development Guidelines#Common_License_Header|proper license headers]] (see below).<br />
* Make sure all added files are actually within the commit.<br />
* Make one commit per logical change.<br />
* For more details on using gerrit, see our [[Git]] documentation. Things are somewhat different (eg. it's normal to rebase changes that were already pushed).<br />
* Double-check that your changes are correct, and that the commit only contains what you think it contains.<br />
<br />
== Sign-off Procedure ==<br />
<br />
We employ a similar sign-off procedure for coreboot <br />
[http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html as the Linux kernel developers] do.<br />
Please add a note such as<br />
Signed-off-by: Random J Developer <random@developer.example.org><br />
to your email/patch if you agree with the following Developer's Certificate of Origin 1.1.<br />
<br />
Patches without a Signed-off-by cannot be pushed to gerrit!<br />
<br />
<span style="color:red">You have to use your real name in the Signed-off-by line and in any copyright notices you add.</span> Patches without an associated real name cannot be committed!<br />
<br />
'''Developer's Certificate of Origin 1.1:'''<br />
<br />
By making a contribution to this project, I certify that:<br /><br />
(a) The contribution was created in whole or in part by me and I have<br />
the right to submit it under the open source license indicated in the file; or<br /><br />
(b) The contribution is based upon previous work that, to the best of my<br />
knowledge, is covered under an appropriate open source license and I have the<br />
right under that license to submit that work with modifications, whether created<br />
in whole or in part by me, under the same open source license (unless I am<br />
permitted to submit under a different license), as indicated in the file; or<br /><br />
(c) The contribution was provided directly to me by some other person who<br />
certified (a), (b) or (c) and I have not modified it; and<br /><br />
(d) In the case of each of (a), (b), or (c), I understand and agree that<br />
this project and the contribution are public and that a record of the contribution<br />
(including all personal information I submit with it, including my sign-off) is<br />
maintained indefinitely and may be redistributed consistent with this project or the<br />
open source license indicated in the file.<br />
<br />
<small>Note: The [http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html Developer's Certificate of Origin 1.1] is licensed under the terms of the [http://creativecommons.org/licenses/by-sa/2.5/ Creative Commons Attribution-ShareAlike 2.5 License].</small><br />
<br />
== Reviews ==<br />
<br />
* Send your patch to [[Git|gerrit]] for review.<br />
** Provide useful commit messages. Explain what the change does and why. Our short intro to [[Git|git]] explains the format in more detail.<br />
** Add a single line containing your "[[Development Guidelines#Sign-off_Procedure|sign-off]]" after the description of the patch (<code>git commit -s</code> helps, but make sure you understand and comply with the DCO).<br />
*** Example: ''Signed-off-by: John Doe <john@example.com>''<br />
* The developers will review and/or test your change and send comments or suggestions. Please push updated patches as described in "[[Git#Evolving_patches|evolving patches]]".<br />
* If the change looks ok to one or more developers, they will approve and submit it to the master branch.<br />
<br />
= Bug-Tracker =<br />
<br />
'''note: the bug tracker is dead. more or less.'''<br />
<br />
= License Issues =<br />
<br />
* Contributed code must be GPL'd (preferrably 'GPLv2 or any later version', but 'GPLv2' is fine, too). At the very minimum the code must have a GPL-compatible license.<br />
<br />
== Common License Header ==<br />
<br />
Please quote the full GPL license header text in every file, as shown below. It should contain:<br />
<br />
* The '''year(s)''' when the code was written or modified and a '''copyright note''' of you (or your company, if you are contributing as part of your employment, and thus the copyright belongs to your company). Also, please provide an '''email address''' so that you can be contacted if questions arise.<br />
** Example:<br />
::''Copyright (C) 2006 John Doe <john@example.com>''<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
* An extra line which lists the '''author of the code, if the copyright holder is not the same as the author''' (e.g. if you work for a company and the company owns the copyright).<br />
** Example:<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
::''(Written by Janet Doe <janet@example.com> for Company, Inc.)''<br />
* The full '''GPL header''' as shown below.<br />
<br />
'''Complete example for *.c and *.h files:'''<br />
<br />
/*<br />
* This file is part of the coreboot project.<br />
*<br />
* Copyright (C) 2003-2005 John Doe <john@example.com><br />
* Copyright (C) 2005 Jane Doe <jane@example.com><br />
* Copyright (C) 2006 Company, Inc.<br />
* (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
* Copyright (C) 2007 Joe Doe <joe@example.com><br />
*<br />
* This program is free software; you can redistribute it and/or modify<br />
* it under the terms of the GNU General Public License as published by<br />
* the Free Software Foundation; either version 2 of the License, or<br />
* (at your option) any later version.<br />
*<br />
* This program is distributed in the hope that it will be useful,<br />
* but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
* GNU General Public License for more details.<br />
*<br />
* You should have received a copy of the GNU General Public License<br />
* along with this program; if not, write to the Free Software<br />
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
*/<br />
<br />
'''Complete example for Makefiles, config files, Python files, shell scripts etc.:'''<br />
<br />
##<br />
## This file is part of the coreboot project.<br />
##<br />
## Copyright (C) 2003-2005 John Doe <john@example.com><br />
## Copyright (C) 2005 Jane Doe <jane@example.com><br />
## Copyright (C) 2006 Company, Inc.<br />
## (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
## Copyright (C) 2007 Joe Doe <joe@example.com><br />
##<br />
## This program is free software; you can redistribute it and/or modify<br />
## it under the terms of the GNU General Public License as published by<br />
## the Free Software Foundation; either version 2 of the License, or<br />
## (at your option) any later version.<br />
##<br />
## This program is distributed in the hope that it will be useful,<br />
## but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
## GNU General Public License for more details.<br />
##<br />
## You should have received a copy of the GNU General Public License<br />
## along with this program; if not, write to the Free Software<br />
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
##</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Development_Guidelines&diff=13647
Development Guidelines
2014-05-01T09:23:32Z
<p>Eocallaghan: Proposed commit message policy - open to argument if any?</p>
<hr />
<div>= Development Environment =<br />
<br />
== Required Toolchain ==<br />
<br />
The easiest way to get a working toolchain is to run <code>make crossgcc</code> in the toplevel directory of a coreboot checkout. Distributions usually modify their compilers in ways incompatible with coreboot. If in doubt, use our toolchain.<br />
<br />
The toolchain consists of:<br />
* GNU development environment:<br />
** [http://gcc.gnu.org/ GCC with G++]<br />
** [http://www.kernel.org/pub/linux/devel/binutils/ binutils]<br />
* libncurses*-dev<br />
* [http://www.acpica.org/downloads/ IASL], now part of the '''ACPICA''' download (package ''pmtools'' or ''iasl'' in many distributions)<br />
<br />
= Coding Guidelines =<br />
<br />
== General Guidelines ==<br />
<br />
* Encapsulate and isolate assembly language<br />
* Code shall not be "commented out"<br />
* No use of floating-point arithmetics<br />
* No hiding of identifiers defined in outer scopes<br />
* Typedefs are unique (device_t?)<br />
* Functions shall have prototype declarations<br />
* Local functions should be declared static<br />
* No definitions in header files<br />
* All variables are assigned before use<br />
* All objects should have fully qualified types (''unsigned int'' instead of ''unsigned'')<br />
* Types which indicate signedness and bitness should be used (''uint32_t'' or ''u32'' instead of ''unsigned int'')<br />
* We suggest trying to import more such rules, such as additional ones described in [http://www.misra.org.uk/index.htm MISRA-C 2012] (''Guidelines for the use of C in critical systems'')<br />
<br />
== Variable types ==<br />
<br />
Whenever possible, please use a variable type which is explicit about the size of data it can hold. For example, use '''uint32_t''' or '''u32''' instead of '''unsigned long''' when referencing a 32-bit wide register.<br />
<br />
=== short int names vs stdint names ===<br />
<br />
There is '''currently no hard rule''' on whether one should use short int types ('''u32'''), or stdint types ('''uint32_t'''). Whichever type you elect to use, please use common sense and stay consistent.<br />
<br />
== Comments ==<br />
<br />
=== References ===<br />
<br />
If you are referencing a data sheet or other documentation in the code, please add the name or document number in addition to the URL. Vendors just ''love'' to rearrange their websites (and some remove documentation on their old products altogether)! If we have the name/number (or even just the filename of the PDF) at least there's a chance to google for it again (either on the vendor's site or on some archive).<br />
<br />
== Coding Style ==<br />
<br />
* We use the coreboot [[Coding Style]] throughout the project.<br />
* You can use the 'indent' tool to fix the coding style like this:<br />
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]<br />
:Do not trust 'indent' blindly, though. It sometimes gets things wrong. Manual corrections may be required.<br />
<br />
== The 80 character limit ==<br />
<br />
Lines larger than 80 columns should be broken down into readable pieces. This includes not only source files, but also Makefiles, Kconfig files, and any file meant to be edited by a human. We recommend setting your editor to show the 80th character limit.<br />
This limit is not a relic from long forgotten times, but a very practical and efficient way to organize code and increase productivity. Several files can be edited on the same monitor, without the need to side-scroll. Side-scrolling source files is inefficient, time-consuming, and uncomfortable. On average, 95% of source lines are shorter than 80 characters, so limiting the line length is this manner is not only _not_ an impediment, it also gets you to think on how to best organize the code.<br />
<br />
== Commit messages ==<br />
<br />
=== Short Summary ===<br />
<br />
Try to encapsulate what the changeset effects in the source tree at the begining of the commit message. For examples:<br />
<br />
mainboard/amd/foo: ..<br />
superio/bar: ..<br />
<br />
and so on. The short summary should be 50 chars or less.<br />
<br />
=== Body Text ===<br />
<br />
* Try to explain the reasoning behind your changeset, not how you did it or what tools you used.<br />
* Avoid putting URL's in commit messages. URL's do not last forever.<br />
* Do not put shell script in commit messages please.<br />
<br />
Additionally, putting executable shell script and URL's in commit messages makes it harder to match & parse useful information out of the commit message body with standard unix tools (awk,grep,sed,..).<br />
It is also not directly useful in figuring out what your changeset is actually about while looking back.<br />
<br />
To cross reference your changeset with a older changeset in git's history, use its short hash set to 7 chars like in the following example:<br />
<br />
Following the reasoning in,<br />
e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA<br />
<br />
This is good practice as one can use standard *nix tools to parse out this information depending on what they intend to do..<br />
Here are some examples to demonstrate the point of this rational:<br />
<br />
Make a patch since that referenced commit hash in the commit hash 'ac6b7ab',<br />
git format-patch $(git log -1 --pretty=format:%b ac6b7ab | grep -E "\b[0-9a-f]{7,40}\b" | awk '{ printf $1}')<br />
<br />
Or show its summary,<br />
git show --pretty=medium --summary --color=always $(git log -1 --pretty=format:%b ac6b7ab | grep -E "\b[0-9a-f]{7,40}\b" | awk '{ printf $1}')<br />
<br />
Or you can even pass it to git-bisect to bisect from the embedded reference.<br />
<br />
= Documentation Guidelines =<br />
<br />
== General Guidelines and Tips ==<br />
<br />
* Documentation should be put into the wiki and/or in the code as Doxygen comments<br />
* Avoid using different styles and looks of documentation<br />
* Document ''why'' and ''what'', not ''how'' (No comments like ''/* add one to i */'')<br />
* Document assumptions, stipulations etc...<br />
* Document design and concepts!<br />
* Not lots of documentation but good documentation<br />
* Structured documentation<br />
* Focus: Whom are you addressing in your documentation? Write documentation for users, developers, vendors, ...<br />
<br />
== Automatic documentation ==<br />
<br />
* Doxygen-generated API- and code documentation is available at http://qa.coreboot.org/docs/. This documentation is updated on every 10th checkin.<br />
* To create a Doxygen comment, write<br />
/**<br />
* Sample comment.<br />
*/<br />
:or<br />
/** Sample comment. */<br />
* There are a few commands that describe what kind of comment you are adding:<br />
::@param &mdash; input parameters of a function<br />
::@return &mdash; return value of a function<br />
* A list of all commands is available at http://www.stack.nl/~dimitri/doxygen/commands.html<br />
<br />
Full example:<br />
<br />
/**<br />
* Calculate the length of a string.<br />
*<br />
* @param str The input string.<br />
* @return The length of the string, not including the final NUL character.<br />
*/<br />
static inline size_t strlen(const char *str)<br />
{<br />
/* ... */<br />
}<br />
<br />
= Testing =<br />
<br />
Every commit will be processed by the autobuild and autotest system available at http://qa.coreboot.org/. In addition please run autobuild yourself before submitting patches.<br />
<br />
== autobuild ==<br />
<br />
Autobuild can be found at [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=util/abuild;hb=HEAD coreboot/util/abuild]. <br />
<br />
Please run ''abuild'' '''before''' you commit.<br />
<br />
Autobuild is also running on every check-in to the repository. The results of this build are also available at http://qa.coreboot.org/.<br />
<br />
== autotest ==<br />
<br />
We can also run automatic tests on boards, if we find contributors willing to have a board automatically managed by our QA system. This requires a permanent connection to the net, a host system and some special circuitry. If interested, please contact us using the [[Mailinglist|mailing list]].<br />
<br />
= How to contribute =<br />
<br />
== Creating Patches ==<br />
<br />
* We use gerrit for change management, using the instance on http://review.coreboot.org/<br />
* While not necessary with gerrit, '''make sure that your change is against current master'''. Patches that fail on merge (after some developer looked at it and approved it) might linger around until '''you''' update it.<br />
* Rebase, if necessary, '''then test''' again. You might be the only contributor with that specific mainboard.<br />
* Make sure all new and modified files contain the [[Development Guidelines#Common_License_Header|proper license headers]] (see below).<br />
* Make sure all added files are actually within the commit.<br />
* Make one commit per logical change.<br />
* For more details on using gerrit, see our [[Git]] documentation. Things are somewhat different (eg. it's normal to rebase changes that were already pushed).<br />
* Double-check that your changes are correct, and that the commit only contains what you think it contains.<br />
<br />
== Sign-off Procedure ==<br />
<br />
We employ a similar sign-off procedure for coreboot <br />
[http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html as the Linux kernel developers] do.<br />
Please add a note such as<br />
Signed-off-by: Random J Developer <random@developer.example.org><br />
to your email/patch if you agree with the following Developer's Certificate of Origin 1.1.<br />
<br />
Patches without a Signed-off-by cannot be pushed to gerrit!<br />
<br />
<span style="color:red">You have to use your real name in the Signed-off-by line and in any copyright notices you add.</span> Patches without an associated real name cannot be committed!<br />
<br />
'''Developer's Certificate of Origin 1.1:'''<br />
<br />
By making a contribution to this project, I certify that:<br /><br />
(a) The contribution was created in whole or in part by me and I have<br />
the right to submit it under the open source license indicated in the file; or<br /><br />
(b) The contribution is based upon previous work that, to the best of my<br />
knowledge, is covered under an appropriate open source license and I have the<br />
right under that license to submit that work with modifications, whether created<br />
in whole or in part by me, under the same open source license (unless I am<br />
permitted to submit under a different license), as indicated in the file; or<br /><br />
(c) The contribution was provided directly to me by some other person who<br />
certified (a), (b) or (c) and I have not modified it; and<br /><br />
(d) In the case of each of (a), (b), or (c), I understand and agree that<br />
this project and the contribution are public and that a record of the contribution<br />
(including all personal information I submit with it, including my sign-off) is<br />
maintained indefinitely and may be redistributed consistent with this project or the<br />
open source license indicated in the file.<br />
<br />
<small>Note: The [http://web.archive.org/web/20070306195036/http://osdlab.org/newsroom/press_releases/2004/2004_05_24_dco.html Developer's Certificate of Origin 1.1] is licensed under the terms of the [http://creativecommons.org/licenses/by-sa/2.5/ Creative Commons Attribution-ShareAlike 2.5 License].</small><br />
<br />
== Reviews ==<br />
<br />
* Send your patch to [[Git|gerrit]] for review.<br />
** Provide useful commit messages. Explain what the change does and why. Our short intro to [[Git|git]] explains the format in more detail.<br />
** Add a single line containing your "[[Development Guidelines#Sign-off_Procedure|sign-off]]" after the description of the patch (<code>git commit -s</code> helps, but make sure you understand and comply with the DCO).<br />
*** Example: ''Signed-off-by: John Doe <john@example.com>''<br />
* The developers will review and/or test your change and send comments or suggestions. Please push updated patches as described in "[[Git#Evolving_patches|evolving patches]]".<br />
* If the change looks ok to one or more developers, they will approve and submit it to the master branch.<br />
<br />
= Bug-Tracker =<br />
<br />
'''note: the bug tracker is dead. more or less.'''<br />
<br />
= License Issues =<br />
<br />
* Contributed code must be GPL'd (preferrably 'GPLv2 or any later version', but 'GPLv2' is fine, too). At the very minimum the code must have a GPL-compatible license.<br />
<br />
== Common License Header ==<br />
<br />
Please quote the full GPL license header text in every file, as shown below. It should contain:<br />
<br />
* The '''year(s)''' when the code was written or modified and a '''copyright note''' of you (or your company, if you are contributing as part of your employment, and thus the copyright belongs to your company). Also, please provide an '''email address''' so that you can be contacted if questions arise.<br />
** Example:<br />
::''Copyright (C) 2006 John Doe <john@example.com>''<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
* An extra line which lists the '''author of the code, if the copyright holder is not the same as the author''' (e.g. if you work for a company and the company owns the copyright).<br />
** Example:<br />
::''Copyright (C) 2004-2006 Company, Inc.''<br />
::''(Written by Janet Doe <janet@example.com> for Company, Inc.)''<br />
* The full '''GPL header''' as shown below.<br />
<br />
'''Complete example for *.c and *.h files:'''<br />
<br />
/*<br />
* This file is part of the coreboot project.<br />
*<br />
* Copyright (C) 2003-2005 John Doe <john@example.com><br />
* Copyright (C) 2005 Jane Doe <jane@example.com><br />
* Copyright (C) 2006 Company, Inc.<br />
* (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
* Copyright (C) 2007 Joe Doe <joe@example.com><br />
*<br />
* This program is free software; you can redistribute it and/or modify<br />
* it under the terms of the GNU General Public License as published by<br />
* the Free Software Foundation; either version 2 of the License, or<br />
* (at your option) any later version.<br />
*<br />
* This program is distributed in the hope that it will be useful,<br />
* but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
* GNU General Public License for more details.<br />
*<br />
* You should have received a copy of the GNU General Public License<br />
* along with this program; if not, write to the Free Software<br />
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
*/<br />
<br />
'''Complete example for Makefiles, config files, Python files, shell scripts etc.:'''<br />
<br />
##<br />
## This file is part of the coreboot project.<br />
##<br />
## Copyright (C) 2003-2005 John Doe <john@example.com><br />
## Copyright (C) 2005 Jane Doe <jane@example.com><br />
## Copyright (C) 2006 Company, Inc.<br />
## (Written by Janet Doe <janet@example.com> for Company, Inc.)<br />
## Copyright (C) 2007 Joe Doe <joe@example.com><br />
##<br />
## This program is free software; you can redistribute it and/or modify<br />
## it under the terms of the GNU General Public License as published by<br />
## the Free Software Foundation; either version 2 of the License, or<br />
## (at your option) any later version.<br />
##<br />
## This program is distributed in the hope that it will be useful,<br />
## but WITHOUT ANY WARRANTY; without even the implied warranty of<br />
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br />
## GNU General Public License for more details.<br />
##<br />
## You should have received a copy of the GNU General Public License<br />
## along with this program; if not, write to the Free Software<br />
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br />
##</div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:jetway/nf81-t56n-lf&diff=13642
Board:jetway/nf81-t56n-lf
2014-04-23T15:35:31Z
<p>Eocallaghan: </p>
<hr />
<div></div>
Eocallaghan
https://www.coreboot.org/index.php?title=Board:asus/m5a99fx-pro-r2&diff=13637
Board:asus/m5a99fx-pro-r2
2014-04-21T05:34:57Z
<p>Eocallaghan: initial version.</p>
<hr />
<div>This page describes how to use coreboot on the '''[https://www.asus.com/Motherboards/M5A99FX_PRO_R20 Asus M5A99FX-PRO-R2]''' mainboard.<br />
<br />
This page is a work in progress.<br />
<br />
== Known Issues ==<br />
<br />
* ??<br />
<br />
== Overview ==<br />
<br />
=== Hardware ===<br />
<br />
* '''Supports AM3+ 32 nm CPU''' CPU Support<br />
* '''AMD 990FX/SB950''' Southbridge<br />
* '''IT8721F''' ITE IT8721F Super I/O<br />
* '''RTL8111F''' Realtek RTL8111F network controllers<br />
* '''ALC892''' 6-Channel HD Audio (via Realtek ALC892), AC97 AD/DA<br />
<br />
=== Details ===<br />
<br />
2 x PCIe 2.0 x16 (dual x16)<br />
2 x PCIe 2.0 x16 (x4 mode, black)<br />
1 x PCIe 2.0 x1<br />
1 x PCI <br />
<br />
=== super io ===<br />
<br />
$ sudo superiotool -d<br />
superiotool r4.0-5814-g0a57e99<br />
Found ITE IT8721F (id=0x8721, rev=0x1) at 0x2e<br />
No dump available for this Super I/O<br />
<br />
=== lspci-tvnn ===<br />
<br />
-[0000:00]-+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (external gfx0 port B) [1002:5a14]<br />
+-02.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] Bonaire [1002:6658]<br />
| \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] Device [1002:aac0]<br />
+-04.0-[02]--<br />
+-0b.0-[03]--<br />
+-0d.0-[04]--<br />
+-11.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391]<br />
+-12.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397]<br />
+-12.2 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396]<br />
+-13.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397]<br />
+-13.2 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396]<br />
+-14.0 Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller [1002:4385]<br />
+-14.2 Advanced Micro Devices, Inc. [AMD/ATI] SBx00 Azalia (Intel HDA) [1002:4383]<br />
+-14.3 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d]<br />
+-14.4-[05]--<br />
+-14.5 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI2 Controller [1002:4399]<br />
+-15.0-[06]----00.0 ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:0612]<br />
+-15.1-[07]----00.0 ASMedia Technology Inc. Device [1b21:1142]<br />
+-15.2-[08]----00.0 ASMedia Technology Inc. Device [1b21:1142]<br />
+-15.3-[09]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168]<br />
+-16.0 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397]<br />
+-16.2 Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396]<br />
+-18.0 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 0 [1022:1600]<br />
+-18.1 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 1 [1022:1601]<br />
+-18.2 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 2 [1022:1602]<br />
+-18.3 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 3 [1022:1603]<br />
+-18.4 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 4 [1022:1604]<br />
\-18.5 Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 5 [1022:1605]<br />
<br />
<br />
=== lspci-vvv ===<br />
<br />
00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (external gfx0 port B) (rev 02)<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (external gfx0 port B)<br />
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-<br />
Capabilities: <access denied><br />
<br />
00:02.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (PCI express gpp port B) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0<br />
I/O behind bridge: 0000e000-0000efff<br />
Memory behind bridge: fea00000-feafffff<br />
Prefetchable memory behind bridge: 00000000c0000000-00000000d07fffff<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:04.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (PCI express gpp port D) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=02, subordinate=02, sec-latency=0<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:0b.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (NB-SB link) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=03, subordinate=03, sec-latency=0<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:0d.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (external gfx1 port B) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=04, subordinate=04, sec-latency=0<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:11.0 SATA controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) (prog-if 01 [AHCI 1.0])<br />
Subsystem: ASUSTeK Computer Inc. Device 84dd<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32<br />
Interrupt: pin A routed to IRQ 19<br />
Region 0: I/O ports at f040 [size=8]<br />
Region 1: I/O ports at f030 [size=4]<br />
Region 2: I/O ports at f020 [size=8]<br />
Region 3: I/O ports at f010 [size=4]<br />
Region 4: I/O ports at f000 [size=16]<br />
Region 5: Memory at feb0b000 (32-bit, non-prefetchable) [size=1K]<br />
Capabilities: <access denied><br />
Kernel driver in use: ahci<br />
Kernel modules: ahci<br />
<br />
00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller (prog-if 10 [OHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 18<br />
Region 0: Memory at feb0a000 (32-bit, non-prefetchable) [size=4K]<br />
Kernel driver in use: ohci-pci<br />
Kernel modules: ohci_pci<br />
<br />
00:12.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller (prog-if 20 [EHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin B routed to IRQ 17<br />
Region 0: Memory at feb09000 (32-bit, non-prefetchable) [size=256]<br />
Capabilities: <access denied><br />
Kernel driver in use: ehci-pci<br />
Kernel modules: ehci_pci<br />
<br />
00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller (prog-if 10 [OHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 20<br />
Region 0: Memory at feb08000 (32-bit, non-prefetchable) [size=4K]<br />
Kernel driver in use: ohci-pci<br />
Kernel modules: ohci_pci<br />
<br />
00:13.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller (prog-if 20 [EHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin B routed to IRQ 21<br />
Region 0: Memory at feb07000 (32-bit, non-prefetchable) [size=256]<br />
Capabilities: <access denied><br />
Kernel driver in use: ehci-pci<br />
Kernel modules: ehci_pci<br />
<br />
00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller (rev 42)<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller<br />
Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Kernel driver in use: piix4_smbus<br />
Kernel modules: i2c_piix4, sp5100_tco<br />
<br />
00:14.2 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 Azalia (Intel HDA) (rev 40)<br />
Subsystem: ASUSTeK Computer Inc. Device 84fb<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 16<br />
Region 0: Memory at feb00000 (64-bit, non-prefetchable) [size=16K]<br />
Capabilities: <access denied><br />
Kernel driver in use: snd_hda_intel<br />
Kernel modules: snd_hda_intel<br />
<br />
00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 LPC host controller (rev 40)<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 LPC host controller<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0<br />
<br />
00:14.4 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 PCI to PCI Bridge (rev 40) (prog-if 01 [Subtractive decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop+ ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 64<br />
Bus: primary=00, secondary=05, subordinate=05, sec-latency=64<br />
Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
<br />
00:14.5 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI2 Controller (prog-if 10 [OHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI2 Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin C routed to IRQ 18<br />
Region 0: Memory at feb06000 (32-bit, non-prefetchable) [size=4K]<br />
Kernel driver in use: ohci-pci<br />
Kernel modules: ohci_pci<br />
<br />
00:15.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB700/SB800/SB900 PCI to PCI bridge (PCIE port 0) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=06, subordinate=06, sec-latency=0<br />
I/O behind bridge: 0000d000-0000dfff<br />
Memory behind bridge: fe900000-fe9fffff<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:15.1 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB700/SB800/SB900 PCI to PCI bridge (PCIE port 1) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=07, subordinate=07, sec-latency=0<br />
Memory behind bridge: fe800000-fe8fffff<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:15.2 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB900 PCI to PCI bridge (PCIE port 2) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=08, subordinate=08, sec-latency=0<br />
Memory behind bridge: fe700000-fe7fffff<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:15.3 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB900 PCI to PCI bridge (PCIE port 3) (prog-if 00 [Normal decode])<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Bus: primary=00, secondary=09, subordinate=09, sec-latency=0<br />
I/O behind bridge: 0000c000-0000cfff<br />
Prefetchable memory behind bridge: 00000000d0900000-00000000d09fffff<br />
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-<br />
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-<br />
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-<br />
Capabilities: <access denied><br />
Kernel driver in use: pcieport<br />
Kernel modules: shpchp<br />
<br />
00:16.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller (prog-if 10 [OHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 22<br />
Region 0: Memory at feb05000 (32-bit, non-prefetchable) [size=4K]<br />
Kernel driver in use: ohci-pci<br />
Kernel modules: ohci_pci<br />
<br />
00:16.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller (prog-if 20 [EHCI])<br />
Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 32, Cache Line Size: 64 bytes<br />
Interrupt: pin B routed to IRQ 23<br />
Region 0: Memory at feb04000 (32-bit, non-prefetchable) [size=256]<br />
Capabilities: <access denied><br />
Kernel driver in use: ehci-pci<br />
Kernel modules: ehci_pci<br />
<br />
00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 0<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Capabilities: <access denied><br />
<br />
00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 1<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
<br />
00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 2<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Kernel modules: amd64_edac_mod<br />
<br />
00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 3<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Capabilities: <access denied><br />
Kernel driver in use: k10temp<br />
Kernel modules: k10temp<br />
<br />
00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 4<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Kernel driver in use: fam15h_power<br />
Kernel modules: fam15h_power<br />
<br />
00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 5<br />
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-<br />
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
<br />
01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Bonaire (prog-if 00 [VGA controller])<br />
Subsystem: ASUSTeK Computer Inc. Device 048f<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 91<br />
Region 0: Memory at c0000000 (64-bit, prefetchable) [size=256M]<br />
Region 2: Memory at d0000000 (64-bit, prefetchable) [size=8M]<br />
Region 4: I/O ports at e000 [size=256]<br />
Region 5: Memory at fea00000 (32-bit, non-prefetchable) [size=256K]<br />
Expansion ROM at fea40000 [disabled] [size=128K]<br />
Capabilities: <access denied><br />
Kernel driver in use: radeon<br />
Kernel modules: radeon<br />
<br />
01:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device aac0<br />
Subsystem: ASUSTeK Computer Inc. Device aac0<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin B routed to IRQ 90<br />
Region 0: Memory at fea60000 (64-bit, non-prefetchable) [size=16K]<br />
Capabilities: <access denied><br />
Kernel driver in use: snd_hda_intel<br />
Kernel modules: snd_hda_intel<br />
<br />
06:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) (prog-if 01 [AHCI 1.0])<br />
Subsystem: ASUSTeK Computer Inc. Device 84b7<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 88<br />
Region 0: I/O ports at d050 [size=8]<br />
Region 1: I/O ports at d040 [size=4]<br />
Region 2: I/O ports at d030 [size=8]<br />
Region 3: I/O ports at d020 [size=4]<br />
Region 4: I/O ports at d000 [size=32]<br />
Region 5: Memory at fe900000 (32-bit, non-prefetchable) [size=512]<br />
Capabilities: <access denied><br />
Kernel driver in use: ahci<br />
Kernel modules: ahci<br />
<br />
07:00.0 USB controller: ASMedia Technology Inc. Device 1142 (prog-if 30 [XHCI])<br />
Subsystem: ASUSTeK Computer Inc. Device 85bf<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 21<br />
Region 0: Memory at fe800000 (64-bit, non-prefetchable) [size=32K]<br />
Capabilities: <access denied><br />
Kernel driver in use: xhci_hcd<br />
Kernel modules: xhci_hcd<br />
<br />
08:00.0 USB controller: ASMedia Technology Inc. Device 1142 (prog-if 30 [XHCI])<br />
Subsystem: ASUSTeK Computer Inc. Device 85bf<br />
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 22<br />
Region 0: Memory at fe700000 (64-bit, non-prefetchable) [size=32K]<br />
Capabilities: <access denied><br />
Kernel driver in use: xhci_hcd<br />
Kernel modules: xhci_hcd<br />
<br />
09:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 09)<br />
Subsystem: ASUSTeK Computer Inc. P8H77-I Motherboard<br />
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+<br />
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-<br />
Latency: 0, Cache Line Size: 64 bytes<br />
Interrupt: pin A routed to IRQ 89<br />
Region 0: I/O ports at c000 [size=256]<br />
Region 2: Memory at d0904000 (64-bit, prefetchable) [size=4K]<br />
Region 4: Memory at d0900000 (64-bit, prefetchable) [size=16K]<br />
Capabilities: <access denied><br />
Kernel driver in use: r8169<br />
Kernel modules: r8169<br />
<br />
=== Building a coreboot image ===<br />
<br />
Make a fresh clone of Coreboot into a empty directory and run:<br />
make crossgcc-i386<br />
Make a cup of tea.. Then run:<br />
make menuconfig<br />
and select Asus/M5A99FX-PRO-R2 under "Mainboard -> Mainboard vendor/model" leaving<br />
everything else as defaults. Then finally do,<br />
make<br />
<br />
To flash the board with '''flashrom''' run:<br />
flashrom -p ft2232_spi:type=2232H,port=A -c "MX25L1605A/MX25L1606E" -w build/coreboot.rom<br />
''assuming'' you have a SPI flasher setup.<br />
<br />
== Status ==<br />
<br />
TODO<br />
<br />
== Issue Analysis ==<br />
<br />
???<br />
<br />
=== Coreboot boot log ===<br />
<br />
See [http://www.coreboot.org/Supported_Motherboards#asus.m5a99fx-pro-r2] for a recent log.<br />
<br />
{{PD-self}}</div>
Eocallaghan