https://www.coreboot.org/api.php?action=feedcontributions&user=Fchmmr&feedformat=atomcoreboot - User contributions [en]2024-03-28T14:15:35ZUser contributionsMediaWiki 1.40.0https://www.coreboot.org/index.php?title=Build_HOWTO&diff=17699Build HOWTO2016-01-10T23:00:53Z<p>Fchmmr: more cleanup</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++ (gcc-multilib is ideal, makes building payloads a lot easier)<br />
* make<br />
* cmake (if using clang/llvm)<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
Most beginners want to use the default [[SeaBIOS]] payload. It runs Option ROMs, is able to discover boot devices and provides a very simple boot menu.<br />
<br />
There's no need to build SeaBIOS by hand, it is done by coreboot.<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
OR<br />
<br />
$ '''make nconfig''' (easier to navigate, uses ncurses)<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of <code>flashrom</code> command)<br />
<br />
More detailed example (generic) configuration (tweak accordingly):<br />
(note that this assumes presence of native graphics initialization on the given board, which is not universally available in coreboot)<br />
<br />
General setup / Expert mode = enable<br />
General / Use CMOS for configuration values = enable<br />
Mainboard / Mainboard vendor = Name of manufacturer<br />
Mainboard / Mainboard model = Model name<br />
Mainboard / ROM chip size = size of flash chip<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates (NOTE: you probably want to enable it on some systems)<br />
Devices / Use native graphics initialization = enable (NOTE: not available on all systems)<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Generic Drivers / USB 2.0 EHCI debug dongle support = Enable<br />
Generic Drivers / Enable early (pre-RAM) usbdebug = Enable<br />
Generic Drivers / Type of dongle = Net20DC or compatible<br />
Generic Drivers / Digitizer = Present<br />
Console / USB dongle console output = enable<br />
Payload / Add a payload = An ELF executable payload (change if you want a different payload)<br />
Payload / Payload path and filename = grub.elf (assumes building GRUB manually. Change this if you want a different payload)<br />
<br />
Now go back into Devices (only do this if you didn't enable native graphics initialization; NOTE: instructions for adding a vbios option rom are not mentioned in the above instructions):<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
<br />
<br />
=== Intel boards ===<br />
For Intel boards you have to provide files coreboot can't generate by itself:<br />
* [[Intel Flash Descriptor region]]<br />
* [[Intel Gigabit Ethernet firmware]]<br />
* [[Intel Management Engine]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
* Enter the '''Chipset''' menu<br />
** Do the following based on which blobs you have:<br />
** Untick '''Build with a fake IFD''' (descriptor.bin)<br />
** Tick '''Add gigabit ethernet firmware''' (gbe.bin)<br />
** Tick '''Add Intel Management Engine firmware''' (me.bin)<br />
<br />
=== AMD boards ===<br />
For AMD boards you have to provide files coreboot can't generate by itself:<br />
* [[NIC firmware]]<br />
* [[AMD IMC]]<br />
* [[AMD XHCI]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
=== Choose the payload ===<br />
Here's the full list of supported [[Payloads]].<br />
<br />
By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process.<br />
<br />
If you want to use another payload (ELF for example):<br />
<br />
* Enter the '''Payload''' menu.<br />
** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
=== VGA support ===<br />
In order to see something on your screen the graphic card has to be initialized by the [[VGA BIOS]] which is actually an [[Option ROM]].<br />
<br />
[[VGA support]] is required for payloads such as GRUB or elf-memtest86+-5.01.<br />
<br />
It isn't required for operating systems such as GNU/Linux as it initializes the graphic card by itself.<br />
<br />
On some platforms there's support for [[native gfx init]]. A VGA BIOS isn't required.<br />
<br />
=== Compiling ===<br />
<br />
You also need to build crossgcc (highly recommended because distributions patch gcc in ways that introduce bugs when building coreboot):<br />
<br />
$ '''make crossgcc'''<br />
<br />
Or alternatively to build with more than one thread, invoke the cross compiler build script directly (in this example eight threads):<br />
<br />
$ '''util/crossgcc/buildgcc -j 8'''<br />
<br />
In case something fails, try to search for the relevant log (<code>find . -name '*.log' | xargs grep Error</code>) and examine last few lines of it.<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
We have been working on building coreboot with clang/llvm and it basically works.<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
The default and recommended flow is still to use crossgcc.<br />
<br />
== Known issues ==<br />
<br />
Make sure you really have all the requirements installed!<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can [[flashing coreboot|flash]] the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Build_HOWTO&diff=17698Build HOWTO2016-01-10T22:59:36Z<p>Fchmmr: s/libreboot/coreboot - sorry, forgot to replace when adapting this from the libreboot site</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++ (gcc-multilib is ideal, makes building payloads a lot easier)<br />
* make<br />
* cmake (if using clang/llvm)<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
Most beginners want to use the default [[SeaBIOS]] payload. It runs Option ROMs, is able to discover boot devices and provides a very simple boot menu.<br />
<br />
There's no need to build SeaBIOS by hand, it is done by coreboot.<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
OR<br />
<br />
$ '''make nconfig''' (easier to navigate, uses ncurses)<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of <code>flashrom</code> command)<br />
<br />
More detailed example (generic) configuration (tweak accordingly):<br />
(note that this assumes presence of native graphics initialization on the given board, which is not universally available in coreboot)<br />
<br />
General setup / Expert mode = enable<br />
General / Use CMOS for configuration values = enable<br />
Mainboard / Mainboard vendor = Name of manufacturer<br />
Mainboard / Mainboard model = Model name<br />
Mainboard / ROM chip size = size of flash chip<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates (NOTE: you probably want to enable it on some systems)<br />
Devices / Use native graphics initialization = enable (NOTE: not available on all systems)<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Coreboot usually provides this with text-mode enabled by default, but it automatically patches a copy of the config at build time to enable coreboot framebuffer for a separate set of ROM images, in each system.<br />
Generic Drivers / USB 2.0 EHCI debug dongle support = Enable<br />
Generic Drivers / Enable early (pre-RAM) usbdebug = Enable<br />
Generic Drivers / Type of dongle = Net20DC or compatible<br />
Generic Drivers / Digitizer = Present<br />
Console / USB dongle console output = enable<br />
Payload / Add a payload = An ELF executable payload (change if you want a different payload)<br />
Payload / Payload path and filename = grub.elf (assumes building GRUB manually. Change this if you want a different payload)<br />
<br />
Now go back into Devices (only do this if you didn't enable native graphics initialization; NOTE: instructions for adding a vbios option rom are not mentioned in the above instructions):<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
<br />
<br />
=== Intel boards ===<br />
For Intel boards you have to provide files coreboot can't generate by itself:<br />
* [[Intel Flash Descriptor region]]<br />
* [[Intel Gigabit Ethernet firmware]]<br />
* [[Intel Management Engine]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
* Enter the '''Chipset''' menu<br />
** Do the following based on which blobs you have:<br />
** Untick '''Build with a fake IFD''' (descriptor.bin)<br />
** Tick '''Add gigabit ethernet firmware''' (gbe.bin)<br />
** Tick '''Add Intel Management Engine firmware''' (me.bin)<br />
<br />
=== AMD boards ===<br />
For AMD boards you have to provide files coreboot can't generate by itself:<br />
* [[NIC firmware]]<br />
* [[AMD IMC]]<br />
* [[AMD XHCI]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
=== Choose the payload ===<br />
Here's the full list of supported [[Payloads]].<br />
<br />
By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process.<br />
<br />
If you want to use another payload (ELF for example):<br />
<br />
* Enter the '''Payload''' menu.<br />
** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
=== VGA support ===<br />
In order to see something on your screen the graphic card has to be initialized by the [[VGA BIOS]] which is actually an [[Option ROM]].<br />
<br />
[[VGA support]] is required for payloads such as GRUB or elf-memtest86+-5.01.<br />
<br />
It isn't required for operating systems such as GNU/Linux as it initializes the graphic card by itself.<br />
<br />
On some platforms there's support for [[native gfx init]]. A VGA BIOS isn't required.<br />
<br />
=== Compiling ===<br />
<br />
You also need to build crossgcc (highly recommended because distributions patch gcc in ways that introduce bugs when building coreboot):<br />
<br />
$ '''make crossgcc'''<br />
<br />
Or alternatively to build with more than one thread, invoke the cross compiler build script directly (in this example eight threads):<br />
<br />
$ '''util/crossgcc/buildgcc -j 8'''<br />
<br />
In case something fails, try to search for the relevant log (<code>find . -name '*.log' | xargs grep Error</code>) and examine last few lines of it.<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
We have been working on building coreboot with clang/llvm and it basically works.<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
The default and recommended flow is still to use crossgcc.<br />
<br />
== Known issues ==<br />
<br />
Make sure you really have all the requirements installed!<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can [[flashing coreboot|flash]] the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Build_HOWTO&diff=17697Build HOWTO2016-01-10T22:58:17Z<p>Fchmmr: </p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++ (gcc-multilib is ideal, makes building payloads a lot easier)<br />
* make<br />
* cmake (if using clang/llvm)<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
Most beginners want to use the default [[SeaBIOS]] payload. It runs Option ROMs, is able to discover boot devices and provides a very simple boot menu.<br />
<br />
There's no need to build SeaBIOS by hand, it is done by coreboot.<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
OR<br />
<br />
$ '''make nconfig''' (easier to navigate, uses ncurses)<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of <code>flashrom</code> command)<br />
<br />
More detailed example (generic) configuration (tweak accordingly):<br />
(note that this assumes presence of native graphics initialization on the given board, which is not universally available in coreboot)<br />
<br />
General setup / Expert mode = enable<br />
General / Use CMOS for configuration values = enable<br />
Mainboard / Mainboard vendor = Name of manufacturer<br />
Mainboard / Mainboard model = Model name<br />
Mainboard / ROM chip size = size of flash chip<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates (NOTE: you probably want to enable it on some systems)<br />
Devices / Use native graphics initialization = enable (NOTE: not available on all systems)<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Libreboot provides this with text-mode enabled by default, but it automatically patches a copy of the config at build time to enable coreboot framebuffer for a separate set of ROM images, in each system.<br />
Generic Drivers / USB 2.0 EHCI debug dongle support = Enable<br />
Generic Drivers / Enable early (pre-RAM) usbdebug = Enable<br />
Generic Drivers / Type of dongle = Net20DC or compatible<br />
Generic Drivers / Digitizer = Present<br />
Console / USB dongle console output = enable<br />
Payload / Add a payload = An ELF executable payload (change if you want a different payload)<br />
Payload / Payload path and filename = grub.elf (assumes building GRUB manually. Change this if you want a different payload)<br />
<br />
Now go back into Devices (only do this if you didn't enable native graphics initialization; NOTE: instructions for adding a vbios option rom are not mentioned in the above instructions):<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
<br />
<br />
=== Intel boards ===<br />
For Intel boards you have to provide files coreboot can't generate by itself:<br />
* [[Intel Flash Descriptor region]]<br />
* [[Intel Gigabit Ethernet firmware]]<br />
* [[Intel Management Engine]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
* Enter the '''Chipset''' menu<br />
** Do the following based on which blobs you have:<br />
** Untick '''Build with a fake IFD''' (descriptor.bin)<br />
** Tick '''Add gigabit ethernet firmware''' (gbe.bin)<br />
** Tick '''Add Intel Management Engine firmware''' (me.bin)<br />
<br />
=== AMD boards ===<br />
For AMD boards you have to provide files coreboot can't generate by itself:<br />
* [[NIC firmware]]<br />
* [[AMD IMC]]<br />
* [[AMD XHCI]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
=== Choose the payload ===<br />
Here's the full list of supported [[Payloads]].<br />
<br />
By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process.<br />
<br />
If you want to use another payload (ELF for example):<br />
<br />
* Enter the '''Payload''' menu.<br />
** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
=== VGA support ===<br />
In order to see something on your screen the graphic card has to be initialized by the [[VGA BIOS]] which is actually an [[Option ROM]].<br />
<br />
[[VGA support]] is required for payloads such as GRUB or elf-memtest86+-5.01.<br />
<br />
It isn't required for operating systems such as GNU/Linux as it initializes the graphic card by itself.<br />
<br />
On some platforms there's support for [[native gfx init]]. A VGA BIOS isn't required.<br />
<br />
=== Compiling ===<br />
<br />
You also need to build crossgcc (highly recommended because distributions patch gcc in ways that introduce bugs when building coreboot):<br />
<br />
$ '''make crossgcc'''<br />
<br />
Or alternatively to build with more than one thread, invoke the cross compiler build script directly (in this example eight threads):<br />
<br />
$ '''util/crossgcc/buildgcc -j 8'''<br />
<br />
In case something fails, try to search for the relevant log (<code>find . -name '*.log' | xargs grep Error</code>) and examine last few lines of it.<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
We have been working on building coreboot with clang/llvm and it basically works.<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
The default and recommended flow is still to use crossgcc.<br />
<br />
== Known issues ==<br />
<br />
Make sure you really have all the requirements installed!<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can [[flashing coreboot|flash]] the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Build_HOWTO&diff=17696Build HOWTO2016-01-10T22:57:08Z<p>Fchmmr: </p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++ (gcc-multilib is ideal, makes building payloads a lot easier)<br />
* make<br />
* cmake (if using clang/llvm)<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
Most beginners want to use the default [[SeaBIOS]] payload. It runs Option ROMs, is able to discover boot devices and provides a very simple boot menu.<br />
<br />
There's no need to build SeaBIOS by hand, it is done by coreboot.<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
OR<br />
<br />
$ '''make nconfig''' (easier to navigate, uses ncurses)<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of <code>flashrom</code> command)<br />
<br />
More detailed example (generic) configuration (tweak accordingly):<br />
(note that this assumes presence of native graphics initialization on the given board, which is not universally available in coreboot)<br />
<br />
General setup / Expert mode = enable<br />
General / Use CMOS for configuration values = enable<br />
Mainboard / Mainboard vendor = Name of manufacturer<br />
Mainboard / Mainboard model = Model name<br />
Mainboard / ROM chip size = size of flash chip<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates (NOTE: you probably want to enable it on some systems)<br />
Devices / Use native graphics initialization = enable (NOTE: not available on all systems)<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Libreboot provides this with text-mode enabled by default, but it automatically patches a copy of the config at build time to enable coreboot framebuffer for a separate set of ROM images, in each system.<br />
Generic Drivers / USB 2.0 EHCI debug dongle support = Enable<br />
Generic Drivers / Enable early (pre-RAM) usbdebug = Enable<br />
Generic Drivers / Type of dongle = Net20DC or compatible<br />
Generic Drivers / Digitizer = Present<br />
Console / USB dongle console output = enable<br />
Payload / Add a payload = An ELF executable payload<br />
Payload / Payload path and filename = grub.elf<br />
<br />
Now go back into Devices (only do this if you didn't enable native graphics initialization; NOTE: instructions for adding a vbios option rom are not mentioned in the above instructions):<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
<br />
<br />
=== Intel boards ===<br />
For Intel boards you have to provide files coreboot can't generate by itself:<br />
* [[Intel Flash Descriptor region]]<br />
* [[Intel Gigabit Ethernet firmware]]<br />
* [[Intel Management Engine]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
* Enter the '''Chipset''' menu<br />
** Do the following based on which blobs you have:<br />
** Untick '''Build with a fake IFD''' (descriptor.bin)<br />
** Tick '''Add gigabit ethernet firmware''' (gbe.bin)<br />
** Tick '''Add Intel Management Engine firmware''' (me.bin)<br />
<br />
=== AMD boards ===<br />
For AMD boards you have to provide files coreboot can't generate by itself:<br />
* [[NIC firmware]]<br />
* [[AMD IMC]]<br />
* [[AMD XHCI]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
=== Choose the payload ===<br />
Here's the full list of supported [[Payloads]].<br />
<br />
By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process.<br />
<br />
If you want to use another payload (ELF for example):<br />
<br />
* Enter the '''Payload''' menu.<br />
** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
=== VGA support ===<br />
In order to see something on your screen the graphic card has to be initialized by the [[VGA BIOS]] which is actually an [[Option ROM]].<br />
<br />
[[VGA support]] is required for payloads such as GRUB or elf-memtest86+-5.01.<br />
<br />
It isn't required for operating systems such as GNU/Linux as it initializes the graphic card by itself.<br />
<br />
On some platforms there's support for [[native gfx init]]. A VGA BIOS isn't required.<br />
<br />
=== Compiling ===<br />
<br />
You also need to build crossgcc (highly recommended because distributions patch gcc in ways that introduce bugs when building coreboot):<br />
<br />
$ '''make crossgcc'''<br />
<br />
Or alternatively to build with more than one thread, invoke the cross compiler build script directly (in this example eight threads):<br />
<br />
$ '''util/crossgcc/buildgcc -j 8'''<br />
<br />
In case something fails, try to search for the relevant log (<code>find . -name '*.log' | xargs grep Error</code>) and examine last few lines of it.<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
We have been working on building coreboot with clang/llvm and it basically works.<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
The default and recommended flow is still to use crossgcc.<br />
<br />
== Known issues ==<br />
<br />
Make sure you really have all the requirements installed!<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can [[flashing coreboot|flash]] the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Build_HOWTO&diff=17695Build HOWTO2016-01-10T22:55:44Z<p>Fchmmr: more detailed generic config</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++ (gcc-multilib is ideal, makes building payloads a lot easier)<br />
* make<br />
* cmake (if using clang/llvm)<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
Most beginners want to use the default [[SeaBIOS]] payload. It runs Option ROMs, is able to discover boot devices and provides a very simple boot menu.<br />
<br />
There's no need to build SeaBIOS by hand, it is done by coreboot.<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
OR<br />
<br />
$ '''make nconfig''' (easier to navigate, uses ncurses)<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of <code>flashrom</code> command)<br />
<br />
More detailed example (generic) configuration (tweak accordingly):<br />
(note that this assumes presence of native graphics initialization on the given board, which is not universally available in coreboot)<br />
<br />
General setup / Expert mode = enable<br />
General / Use CMOS for configuration values = enable<br />
Mainboard / Mainboard vendor = Name of manufacturer<br />
Mainboard / Mainboard model = Model name<br />
Mainboard / ROM chip size = size of flash chip<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates<br />
Devices / Use native graphics initialization = enable<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Libreboot provides this with text-mode enabled by default, but it automatically patches a copy of the config at build time to enable coreboot framebuffer for a separate set of ROM images, in each system.<br />
Generic Drivers / USB 2.0 EHCI debug dongle support = Enable<br />
Generic Drivers / Enable early (pre-RAM) usbdebug = Enable<br />
Generic Drivers / Type of dongle = Net20DC or compatible<br />
Generic Drivers / Digitizer = Present<br />
Console / USB dongle console output = enable<br />
Payload / Add a payload = An ELF executable payload<br />
Payload / Payload path and filename = grub.elf<br />
<br />
Now go back into Devices:<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
<br />
<br />
=== Intel boards ===<br />
For Intel boards you have to provide files coreboot can't generate by itself:<br />
* [[Intel Flash Descriptor region]]<br />
* [[Intel Gigabit Ethernet firmware]]<br />
* [[Intel Management Engine]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
* Enter the '''Chipset''' menu<br />
** Do the following based on which blobs you have:<br />
** Untick '''Build with a fake IFD''' (descriptor.bin)<br />
** Tick '''Add gigabit ethernet firmware''' (gbe.bin)<br />
** Tick '''Add Intel Management Engine firmware''' (me.bin)<br />
<br />
=== AMD boards ===<br />
For AMD boards you have to provide files coreboot can't generate by itself:<br />
* [[NIC firmware]]<br />
* [[AMD IMC]]<br />
* [[AMD XHCI]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
=== Choose the payload ===<br />
Here's the full list of supported [[Payloads]].<br />
<br />
By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process.<br />
<br />
If you want to use another payload (ELF for example):<br />
<br />
* Enter the '''Payload''' menu.<br />
** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
=== VGA support ===<br />
In order to see something on your screen the graphic card has to be initialized by the [[VGA BIOS]] which is actually an [[Option ROM]].<br />
<br />
[[VGA support]] is required for payloads such as GRUB or elf-memtest86+-5.01.<br />
<br />
It isn't required for operating systems such as GNU/Linux as it initializes the graphic card by itself.<br />
<br />
On some platforms there's support for [[native gfx init]]. A VGA BIOS isn't required.<br />
<br />
=== Compiling ===<br />
<br />
You also need to build crossgcc (highly recommended because distributions patch gcc in ways that introduce bugs when building coreboot):<br />
<br />
$ '''make crossgcc'''<br />
<br />
Or alternatively to build with more than one thread, invoke the cross compiler build script directly (in this example eight threads):<br />
<br />
$ '''util/crossgcc/buildgcc -j 8'''<br />
<br />
In case something fails, try to search for the relevant log (<code>find . -name '*.log' | xargs grep Error</code>) and examine last few lines of it.<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
We have been working on building coreboot with clang/llvm and it basically works.<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
The default and recommended flow is still to use crossgcc.<br />
<br />
== Known issues ==<br />
<br />
Make sure you really have all the requirements installed!<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can [[flashing coreboot|flash]] the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Motherboard_Porting_Guide&diff=16739Motherboard Porting Guide2015-08-23T23:31:37Z<p>Fchmmr: get more info from ectool</p>
<hr />
<div><br />
== Motherboard Porting Guide ==<br />
<br />
Please note that this is WIP work.<br />
<br />
== HOWTO to find a way ==<br />
<br />
* find a model and manufacturer of your mobo<br />
* download these tools:<br />
# git clone http://review.coreboot.org/p/coreboot<br />
# superiotool ( cd coreboot/util/superiotool ; make ; sudo make install )<br />
# inteltool ( cd coreboot/util/inteltool ; make ; sudo make install )<br />
# ectool ( cd coreboot/util/ectool ; make ; sudo make install )<br />
# dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )<br />
# msrtool ( cd coreboot/util/msrtool ; ./configure ; make ; sudo make install )<br />
# nvramtool ( cd coreboot/util/nvramtool ; make ; sudo make install )<br />
# flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )<br />
* make and install them (make; sudo make install) - you need at least libpci/pciutils<br />
* check that your distro have this tools and install them:<br />
# lspci<br />
# dmesg<br />
# acpitool<br />
# lspnp <-- where do you actually get this? I couldn't find it anywhere.<br />
# lsusb<br />
# acpidump<br />
* # modprobe msr<br />
(this is for one of the steps below) <br />
* Do this commands '''as root''' (# remove for the easy copypasting):<br />
lspci -nnvvvxxxx > lspci.log 2>lspci.err.log<br />
lspnp -vv > lspnp.log 2>lspnp.err.log<br />
lsusb -vvv > lsusb.log 2>lsusb.err.log<br />
superiotool -deV > superiotool.log 2> superiotool.err.log<br />
inteltool -a > inteltool.log 2> inteltool.err.log<br />
ectool -i > ectool.log 2>ectool.err.log<br />
msrtool > msrtool.log 2>msrtool.err.log<br />
dmidecode > dmidecode.log 2>dmidecode.err.log<br />
biosdecode > biosdecode.log 2>biosdecode.err.log<br />
nvramtool -x > nvramtool.log 2>nvramtool.err.log<br />
dmesg > dmesg.log 2>dmesg.err.log<br />
flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log 2>flashrom_info.err.log # this won't work on some vendor firmware<br />
flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log 2>flashrom_read.err.log # this won't work on some vendor firmware<br />
acpidump > acpidump.log 2>acpidump.err.log<br />
for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" > pin_"$(basename "$x")"; done<br />
for x in /proc/asound/card0/codec#*; do cat "$x" > "$(basename "$x")"; done<br />
cat /proc/cpuinfo > cpuinfo.log 2>cpuinfo.err.log<br />
cat /proc/ioports > ioports.log 2>ioports.err.log<br />
cat /sys/class/input/input*/id/bustype > input_bustypes.log<br />
* Save all logs in safe place, and also rom.bin file. <br />
* Find what chip does your mobo use. The name of the chip is present in flashrom_info.log but is not always exact as some chips have several packaging variants (e.g. SOIC-16, SOIC-8 and TSOP). Consult [[http://flashrom.org/Technology]] for more info on possible chip formats. If possible make a high-resolution (600dpi or higher) scan of motherboard. Make a scan, not a photo as cameras typically don't have enough resolution to identify individual chips.<br />
* try to find information - what EC (if on laptop) or Super I/O chip (if any) is used in your mobo (may be some info in Service Manuals or Disassembly guides)<br />
* try to find your Super I/O / EC chip datasheet<br />
For laptop, additionally:<br />
* if you see that ectool return some fake stuff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support<br />
* if you see that ectool return looks like 'right' output - you have a big chances for support<br />
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop<br />
<br />
=== Preparing recovery method ===<br />
<br />
Inevitably when you develop coreboot there will be unbootable builds and so you need a way to unbrick your machine after a failed image. There are several ways to do so. Main ones are:<br />
* In-system Programming. For more info consult [[http://flashrom.org/ISP]]<br />
* Hotswap. Consult [[http://flashrom.org/Technology]]<br />
In any case you have to locate the flash chip. Note the chipname from flashrom output. Teardown your system and find that chip. For how it usually looks like consult [[http://flashrom.org/Technology]]. If you have a scanner, do a high-resolution scan of your board, it may be useful later.<br />
<br />
=== Selecting Similar Board ===<br />
<br />
Most important criteria for finding similar board is chipset. Look at northbridge (device 0:0.0) and southbridge (LPC controller) in the lspci output. grep through coreboot tree to find how those chipsets are named, then grep for chipset name (case-insensitive) to find a board which uses it. If there are several of them, try to match (in order of decreasing importance) system type (desktop/laptop), SuperI/O and manufacturer.<br />
<br />
<br />
=== Adding a new board ===<br />
<br />
This is a two step process. If you mainboard already exists, skip to next section.<br />
<br />
==== Adding a new vendor to tree ====<br />
<br />
Create a directory in src/mainboard with the same name as vendor name. Add to src/mainboard/Kconfig<br />
new vendor entry, the rest of this example uses "foo" vendor.<br />
<br />
config VENDOR_FOO<br />
bool "Foo"<br />
<br />
Add also a include for new Kconfig file which holds the vendor motherboards in the vendor directory<br />
<br />
source "src/mainboard/foo/Kconfig"<br />
<br />
Create a src/mainboard/foo/Kconfig, copy from other vendor, and change the vendor name. Delete all mainboards. <br />
<br />
==== Adding a new motherboard to tree ====<br />
<br />
Asume that vendor name is foo and board type is bar. Add new configuration item in src/mainboard/foo/Kconfig<br />
<br />
config BOARD_FOO_BAR<br />
bool "BAR"<br />
<br />
Add include for board specific config:<br />
<br />
source "src/mainboard/foo/bar/Kconfig"<br />
<br />
==== Adjusting contents of new board directory ====<br />
<br />
Now copy your similar board and start adjusting. Your first stop is the Kconfig.<br />
<br />
* You need to change the condition in the first line to match your board:<br />
<br />
-if BOARD_VENDOR_BAR<br />
+if BOARD_VENDOR_BAZ<br />
<br />
* Change MAINBOARD_DIR and names<br />
* Change device options to match your config<br />
* Next stop go to mainboard.c and adjust GPIO config based on inteltool dump above.<br />
* Now you can flash the image and see what fails. <br />
* Later adjust hda_verb.h to get sound working properly (use initial pin dumps for reference)<br />
<br />
Look through the options and adjust <br />
<br />
Adjust Kconfig to fit the new vendor/model name and dont forget to change MAINBOARD_DIR and MAINBOARD_PART_NUMBER.</div>Fchmmrhttps://www.coreboot.org/index.php?title=User:Fchmmr&diff=16718User:Fchmmr2015-08-17T23:45:11Z<p>Fchmmr: </p>
<hr />
<div>I am the maintainer for the [http://libreboot.org/ libreboot project]<br />
<br />
You can contact me on freenode IRC, with my handle 'francis7'.<br />
(previously 'fchmmr')</div>Fchmmrhttps://www.coreboot.org/index.php?title=Build_HOWTO&diff=16506Build HOWTO2015-06-15T23:33:24Z<p>Fchmmr: I thought this was needed for GCC, but turns out only needed for clang. the build system was just buggy, making me install something I didn't need. Fuck Apple - and therefore, fuck clang.</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of <code>flashrom</code> command)<br />
* Enter the '''Payload''' menu.<br />
** By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process. If you want to use another payload:<br />
*** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
*** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
You also need to build crossgcc (highly recommended because distributions patch gcc in ways that introduce bugs when building coreboot):<br />
<br />
$ '''make crossgcc'''<br />
<br />
In case something fails, try to search for the relevant log (<code>find . -name '*.log' | xargs grep Error</code>) and examine last few lines of it.<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
We have been working on building coreboot with clang/llvm and it basically works.<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
The default and recommended flow is still to use crossgcc.<br />
<br />
== Known issues ==<br />
<br />
Make sure you really have all the requirements installed!<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Build_HOWTO&diff=16505Build HOWTO2015-06-15T23:32:29Z<p>Fchmmr: /* Requirements */</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* cmake (if using clang/llvm)<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of <code>flashrom</code> command)<br />
* Enter the '''Payload''' menu.<br />
** By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process. If you want to use another payload:<br />
*** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
*** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
You also need to build crossgcc (highly recommended because distributions patch gcc in ways that introduce bugs when building coreboot):<br />
<br />
$ '''make crossgcc'''<br />
<br />
In case something fails, try to search for the relevant log (<code>find . -name '*.log' | xargs grep Error</code>) and examine last few lines of it.<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
We have been working on building coreboot with clang/llvm and it basically works.<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
The default and recommended flow is still to use crossgcc.<br />
<br />
== Known issues ==<br />
<br />
Make sure you really have all the requirements installed!<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Build_HOWTO&diff=16504Build HOWTO2015-06-15T23:12:30Z<p>Fchmmr: /* Requirements */</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* cmake (for '''make crossgcc''')<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of <code>flashrom</code> command)<br />
* Enter the '''Payload''' menu.<br />
** By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process. If you want to use another payload:<br />
*** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
*** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
You also need to build crossgcc (highly recommended because distributions patch gcc in ways that introduce bugs when building coreboot):<br />
<br />
$ '''make crossgcc'''<br />
<br />
In case something fails, try to search for the relevant log (<code>find . -name '*.log' | xargs grep Error</code>) and examine last few lines of it.<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
We have been working on building coreboot with clang/llvm and it basically works.<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
The default and recommended flow is still to use crossgcc.<br />
<br />
== Known issues ==<br />
<br />
Make sure you really have all the requirements installed!<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Build_HOWTO&diff=16503Build HOWTO2015-06-15T22:54:29Z<p>Fchmmr: cmake</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* cmake<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of <code>flashrom</code> command)<br />
* Enter the '''Payload''' menu.<br />
** By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process. If you want to use another payload:<br />
*** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
*** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
You also need to build crossgcc (highly recommended because distributions patch gcc in ways that introduce bugs when building coreboot):<br />
<br />
$ '''make crossgcc'''<br />
<br />
In case something fails, try to search for the relevant log (<code>find . -name '*.log' | xargs grep Error</code>) and examine last few lines of it.<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
We have been working on building coreboot with clang/llvm and it basically works.<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
The default and recommended flow is still to use crossgcc.<br />
<br />
== Known issues ==<br />
<br />
Make sure you really have all the requirements installed!<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Motherboard_Porting_Guide&diff=16478Motherboard Porting Guide2015-05-28T12:39:00Z<p>Fchmmr: you must be root</p>
<hr />
<div><br />
== Motherboard Porting Guide ==<br />
<br />
Please note that this is WIP work.<br />
<br />
== HOWTO to find a way ==<br />
<br />
* find a model and manufacturer of your mobo<br />
* download these tools:<br />
# git clone http://review.coreboot.org/p/coreboot<br />
# superiotool ( cd coreboot/util/superiotool ; make ; sudo make install )<br />
# inteltool ( cd coreboot/util/inteltool ; make ; sudo make install )<br />
# ectool ( cd coreboot/util/ectool ; make ; sudo make install )<br />
# dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )<br />
# msrtool ( cd coreboot/util/msrtool ; ./configure ; make ; sudo make install )<br />
# nvramtool ( cd coreboot/util/nvramtool ; make ; sudo make install )<br />
# flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )<br />
* make and install them (make; sudo make install) - you need at least libpci/pciutils<br />
* check that your distro have this tools and install them:<br />
# lspci<br />
# dmesg<br />
# acpitool<br />
# lspnp <-- where do you actually get this? I couldn't find it anywhere.<br />
# lsusb<br />
# acpidump<br />
* # modprobe msr<br />
(this is for one of the steps below) <br />
* Do this commands '''as root''' (# remove for the easy copypasting):<br />
lspci -nnvvvxxxx > lspci.log 2>lspci.err.log<br />
lspnp -vv > lspnp.log 2>lspnp.err.log<br />
lsusb -vvv > lsusb.log 2>lsusb.err.log<br />
superiotool -deV > superiotool.log 2> superiotool.err.log<br />
inteltool -a > inteltool.log 2> inteltool.err.log<br />
ectool > ectool.log 2>ectool.err.log<br />
msrtool > msrtool.log 2>msrtool.err.log<br />
dmidecode > dmidecode.log 2>dmidecode.err.log<br />
biosdecode > biosdecode.log 2>biosdecode.err.log<br />
nvramtool -x > nvramtool.log 2>nvramtool.err.log<br />
dmesg > dmesg.log 2>dmesg.err.log<br />
flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log 2>flashrom_info.err.log # this won't work on some vendor firmware<br />
flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log 2>flashrom_read.err.log # this won't work on some vendor firmware<br />
acpidump > acpidump.log 2>acpidump.err.log<br />
for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" > pin_"$(basename "$x")"; done<br />
for x in /proc/asound/card0/codec#*; do cat "$x" > "$(basename "$x")"; done<br />
cat /proc/cpuinfo > cpuinfo.log 2>cpuinfo.err.log<br />
cat /proc/ioports > ioports.log 2>ioports.err.log<br />
* Save all logs in safe place, and also rom.bin file. <br />
* Find what chip does your mobo use. The name of the chip is present in flashrom_info.log but is not always exact as some chips have several packaging variants (e.g. SOIC-16, SOIC-8 and TSOP). Consult [[http://flashrom.org/Technology]] for more info on possible chip formats. If possible make a high-resolution (600dpi or higher) scan of motherboard. Make a scan, not a photo as cameras typically don't have enough resolution to identify individual chips.<br />
* try to find information - what EC (if on laptop) or Super I/O chip (if any) is used in your mobo (may be some info in Service Manuals or Disassembly guides)<br />
* try to find your Super I/O / EC chip datasheet<br />
For laptop, additionally:<br />
* if you see that ectool return some fake stuff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support<br />
* if you see that ectool return looks like 'right' output - you have a big chances for support<br />
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop<br />
<br />
=== Preparing recovery method ===<br />
<br />
Inevitably when you develop coreboot there will be unbootable builds and so you need a way to unbrick your machine after a failed image. There are several ways to do so. Main ones are:<br />
* In-system Programming. For more info consult [[http://flashrom.org/ISP]]<br />
* Hotswap. Consult [[http://flashrom.org/Technology]]<br />
In any case you have to locate the flash chip. Note the chipname from flashrom output. Teardown your system and find that chip. For how it usually looks like consult [[http://flashrom.org/Technology]]. If you have a scanner, do a high-resolution scan of your board, it may be useful later.<br />
<br />
=== Selecting Similar Board ===<br />
<br />
Most important criteria for finding similar board is chipset. Look at northbridge (device 0:0.0) and southbridge (LPC controller) in the lspci output. grep through coreboot tree to find how those chipsets are named, then grep for chipset name (case-insensitive) to find a board which uses it. If there are several of them, try to match (in order of decreasing importance) system type (desktop/laptop), SuperI/O and manufacturer.<br />
<br />
<br />
=== Adding a new board ===<br />
<br />
This is a two step process. If you mainboard already exists, skip to next section.<br />
<br />
==== Adding a new vendor to tree ====<br />
<br />
Create a directory in src/mainboard with the same name as vendor name. Add to src/mainboard/Kconfig<br />
new vendor entry, the rest of this example uses "foo" vendor.<br />
<br />
config VENDOR_FOO<br />
bool "Foo"<br />
<br />
Add also a include for new Kconfig file which holds the vendor motherboards in the vendor directory<br />
<br />
source "src/mainboard/foo/Kconfig"<br />
<br />
Create a src/mainboard/foo/Kconfig, copy from other vendor, and change the vendor name. Delete all mainboards. <br />
<br />
==== Adding a new motherboard to tree ====<br />
<br />
Asume that vendor name is foo and board type is bar. Add new configuration item in src/mainboard/foo/Kconfig<br />
<br />
config BOARD_FOO_BAR<br />
bool "BAR"<br />
<br />
Add include for board specific config:<br />
<br />
source "src/mainboard/foo/bar/Kconfig"<br />
<br />
==== Adjusting contents of new board directory ====<br />
<br />
Now copy your similar board and start adjusting. Your first stop is the Kconfig.<br />
<br />
* You need to change the condition in the first line to match your board:<br />
<br />
-if BOARD_VENDOR_BAR<br />
+if BOARD_VENDOR_BAZ<br />
<br />
* Change MAINBOARD_DIR and names<br />
* Change device options to match your config<br />
* Next stop go to mainboard.c and adjust GPIO config based on inteltool dump above.<br />
* Now you can flash the image and see what fails. <br />
* Later adjust hda_verb.h to get sound working properly (use initial pin dumps for reference)<br />
<br />
Look through the options and adjust <br />
<br />
Adjust Kconfig to fit the new vendor/model name and dont forget to change MAINBOARD_DIR and MAINBOARD_PART_NUMBER.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Motherboard_Porting_Guide&diff=16474Motherboard Porting Guide2015-05-28T08:01:02Z<p>Fchmmr: </p>
<hr />
<div><br />
== Motherboard Porting Guide ==<br />
<br />
Please note that this is WIP work.<br />
<br />
== HOWTO to find a way ==<br />
<br />
* find a model and manufacturer of your mobo<br />
* download these tools:<br />
# git clone http://review.coreboot.org/p/coreboot<br />
# superiotool ( cd coreboot/util/superiotool ; make ; sudo make install )<br />
# inteltool ( cd coreboot/util/inteltool ; make ; sudo make install )<br />
# ectool ( cd coreboot/util/ectool ; make ; sudo make install )<br />
# dmidecode ( cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode co dmidecode )<br />
# msrtool ( cd coreboot/util/msrtool ; ./configure ; make ; sudo make install )<br />
# nvramtool ( cd coreboot/util/nvramtool ; make ; sudo make install )<br />
# flashrom ( svn co svn://coreboot.org/flashrom/trunk flashrom )<br />
* make and install them (make; sudo make install) - you need at least libpci/pciutils<br />
* check that your distro have this tools and install them:<br />
# lspci<br />
# dmesg<br />
# acpitool<br />
# lspnp <-- where do you actually get this? I couldn't find it anywhere.<br />
# lsusb<br />
# acpidump<br />
* # modprobe msr<br />
(this is for one of the steps below) <br />
* Do this commands (# remove for the easy copypasting):<br />
lspci -nnvvvxxxx > lspci.log 2>&1<br />
lspnp -vv > lspnp.log 2>&1<br />
lsusb -vvv > lsusb.log 2>&1<br />
superiotool -deV > superiotool.log 2>&1<br />
inteltool -a > inteltool.log 2>&1<br />
ectool > ectool.log 2>&1<br />
msrtool > msrtool.log 2>&1<br />
dmidecode > dmidecode.log 2>&1<br />
biosdecode > biosdecode.log 2>&1<br />
nvramtool -x > nvramtool.log 2>&1<br />
dmesg > dmesg.log 2>&1<br />
flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log 2>&1 # this won't work on some vendor firmware<br />
flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log 2>&1 # this won't work on some vendor firmware<br />
acpidump > acpidump.log 2>&1<br />
for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" > pin_"$(basename "$x")" 2>&1; done<br />
for x in /proc/asound/card0/codec#*; do cat "$x" > "$(basename "$x")" 2>&1; done<br />
cat /proc/cpuinfo > cpuinfo.log 2>&1<br />
cat /proc/ioports > ioports.log 2>&1<br />
* Save all logs in safe place, and also rom.bin file. <br />
* Find what chip does your mobo use. The name of the chip is present in flashrom_info.log but is not always exact as some chips have several packaging variants (e.g. SOIC-16, SOIC-8 and TSOP). Consult [[http://flashrom.org/Technology]] for more info on possible chip formats. If possible make a high-resolution (600dpi or higher) scan of motherboard. Make a scan, not a photo as cameras typically don't have enough resolution to identify individual chips.<br />
* try to find information - what EC (if on laptop) or Super I/O chip (if any) is used in your mobo (may be some info in Service Manuals or Disassembly guides)<br />
* try to find your Super I/O / EC chip datasheet<br />
For laptop, additionally:<br />
* if you see that ectool return some fake stuff - like only 'FF' or '00' - so you have custom EC configuration, it's a hard work for support<br />
* if you see that ectool return looks like 'right' output - you have a big chances for support<br />
* you need to find from thease outputs Super I/O / EC chip name, or if not see this - disassembly your laptop<br />
<br />
=== Preparing recovery method ===<br />
<br />
Inevitably when you develop coreboot there will be unbootable builds and so you need a way to unbrick your machine after a failed image. There are several ways to do so. Main ones are:<br />
* In-system Programming. For more info consult [[http://flashrom.org/ISP]]<br />
* Hotswap. Consult [[http://flashrom.org/Technology]]<br />
In any case you have to locate the flash chip. Note the chipname from flashrom output. Teardown your system and find that chip. For how it usually looks like consult [[http://flashrom.org/Technology]]. If you have a scanner, do a high-resolution scan of your board, it may be useful later.<br />
<br />
=== Selecting Similar Board ===<br />
<br />
Most important criteria for finding similar board is chipset. Look at northbridge (device 0:0.0) and southbridge (LPC controller) in the lspci output. grep through coreboot tree to find how those chipsets are named, then grep for chipset name (case-insensitive) to find a board which uses it. If there are several of them, try to match (in order of decreasing importance) system type (desktop/laptop), SuperI/O and manufacturer.<br />
<br />
<br />
=== Adding a new board ===<br />
<br />
This is a two step process. If you mainboard already exists, skip to next section.<br />
<br />
==== Adding a new vendor to tree ====<br />
<br />
Create a directory in src/mainboard with the same name as vendor name. Add to src/mainboard/Kconfig<br />
new vendor entry, the rest of this example uses "foo" vendor.<br />
<br />
config VENDOR_FOO<br />
bool "Foo"<br />
<br />
Add also a include for new Kconfig file which holds the vendor motherboards in the vendor directory<br />
<br />
source "src/mainboard/foo/Kconfig"<br />
<br />
Create a src/mainboard/foo/Kconfig, copy from other vendor, and change the vendor name. Delete all mainboards. <br />
<br />
==== Adding a new motherboard to tree ====<br />
<br />
Asume that vendor name is foo and board type is bar. Add new configuration item in src/mainboard/foo/Kconfig<br />
<br />
config BOARD_FOO_BAR<br />
bool "BAR"<br />
<br />
Add include for board specific config:<br />
<br />
source "src/mainboard/foo/bar/Kconfig"<br />
<br />
==== Adjusting contents of new board directory ====<br />
<br />
Now copy your similar board and start adjusting. Your first stop is the Kconfig.<br />
<br />
* You need to change the condition in the first line to match your board:<br />
<br />
-if BOARD_VENDOR_BAR<br />
+if BOARD_VENDOR_BAZ<br />
<br />
* Change MAINBOARD_DIR and names<br />
* Change device options to match your config<br />
* Next stop go to mainboard.c and adjust GPIO config based on inteltool dump above.<br />
* Now you can flash the image and see what fails. <br />
* Later adjust hda_verb.h to get sound working properly (use initial pin dumps for reference)<br />
<br />
Look through the options and adjust <br />
<br />
Adjust Kconfig to fit the new vendor/model name and dont forget to change MAINBOARD_DIR and MAINBOARD_PART_NUMBER.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:biostar/am1ml&diff=16063Board:biostar/am1ml2015-04-11T13:23:53Z<p>Fchmmr: Created page with "."</p>
<hr />
<div>.</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16053Board:lenovo/x60/Installation2015-04-10T03:04:18Z<p>Fchmmr: </p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You will most likely need to swap the screen and/or swap the motherboard, in mast cases. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed. Other T60 laptops are also compatible, with the same configuration in coreboot.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to create a backup of the vendor BIOS firmware; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to create a backup of the original firmware, creating a new file containing the data called {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
For those systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn | grep VGA''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# You'll see a lot of error output, but relax: this is normal. It will look something like this:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|SeaBIOS will not display anything without a proprietary VGABIOS blob (Intel or ATI GPU) or (Intel GPU only) the free SeaVGABIOS ("coreboot linear framebuffer" in SeaBIOS menuconfig) option ROM in SeaBIOS combined with native graphics initialization, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16052Board:lenovo/x60/Installation2015-04-10T02:56:19Z<p>Fchmmr: /* Back up the original proprietary firmware */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You will most likely need to swap the screen and/or swap the motherboard, in mast cases. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to create a backup of the vendor BIOS firmware; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to create a backup of the original firmware, creating a new file containing the data called {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
For those systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn | grep VGA''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# You'll see a lot of error output, but relax: this is normal. It will look something like this:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|SeaBIOS will not display anything without a proprietary VGABIOS blob (Intel or ATI GPU) or (Intel GPU only) the free SeaVGABIOS ("coreboot linear framebuffer" in SeaBIOS menuconfig) option ROM in SeaBIOS combined with native graphics initialization, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16051Board:lenovo/x60/Installation2015-04-10T02:52:46Z<p>Fchmmr: /* Install Coreboot (First Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You will most likely need to swap the screen and/or swap the motherboard, in mast cases. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to create a backup of the original firmware, creating a new file containing the data called {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
For those systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn | grep VGA''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# You'll see a lot of error output, but relax: this is normal. It will look something like this:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|SeaBIOS will not display anything without a proprietary VGABIOS blob (Intel or ATI GPU) or (Intel GPU only) the free SeaVGABIOS ("coreboot linear framebuffer" in SeaBIOS menuconfig) option ROM in SeaBIOS combined with native graphics initialization, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16050Board:lenovo/x60/Installation2015-04-10T02:50:18Z<p>Fchmmr: /* Video BIOS (VGA option ROM) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You will most likely need to swap the screen and/or swap the motherboard, in mast cases. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to create a backup of the original firmware, creating a new file containing the data called {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
For those systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn | grep VGA''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# You'll see a lot of error output, but relax: this is normal. It will look something like this:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|SeaBIOS will not display anything without a proprietary VGABIOS blob (Intel or ATI GPU) or (Intel GPU only) the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS combined with native graphics initialization, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16049Board:lenovo/x60/Installation2015-04-10T02:48:45Z<p>Fchmmr: /* Video BIOS (VGA option ROM) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You will most likely need to swap the screen and/or swap the motherboard, in mast cases. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to create a backup of the original firmware, creating a new file containing the data called {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn | grep VGA''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# You'll see a lot of error output, but relax: this is normal. It will look something like this:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|SeaBIOS will not display anything without a proprietary VGABIOS blob (Intel or ATI GPU) or (Intel GPU only) the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS combined with native graphics initialization, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16048Board:lenovo/x60/Installation2015-04-10T02:43:57Z<p>Fchmmr: /* Back up the original proprietary firmware */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You will most likely need to swap the screen and/or swap the motherboard, in mast cases. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to create a backup of the original firmware, creating a new file containing the data called {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# You'll see a lot of error output, but relax: this is normal. It will look something like this:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|SeaBIOS will not display anything without a proprietary VGABIOS blob (Intel or ATI GPU) or (Intel GPU only) the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS combined with native graphics initialization, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16047Board:lenovo/x60/Installation2015-04-10T02:41:16Z<p>Fchmmr: All X60 compatible; why mention this? It's irrelevant if there are no issues, so save some vertical screen real estate in the users browser window.</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You will most likely need to swap the screen and/or swap the motherboard, in mast cases. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# You'll see a lot of error output, but relax: this is normal. It will look something like this:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|SeaBIOS will not display anything without a proprietary VGABIOS blob (Intel or ATI GPU) or (Intel GPU only) the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS combined with native graphics initialization, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16046Board:lenovo/x60/Installation2015-04-10T02:38:00Z<p>Fchmmr: </p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All '''ThinkPad X60 Series''' laptops work out of the box with '''Coreboot or Libreboot''', no modifications necessary.}}<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You will most likely need to swap the screen and/or swap the motherboard, in mast cases. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# You'll see a lot of error output, but relax: this is normal. It will look something like this:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|SeaBIOS will not display anything without a proprietary VGABIOS blob (Intel or ATI GPU) or (Intel GPU only) the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS combined with native graphics initialization, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16045Board:lenovo/x60/Installation2015-04-10T02:32:06Z<p>Fchmmr: /* VBIOS replacement (native graphics) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All '''ThinkPad X60 Series''' laptops work out of the box with '''Coreboot or Libreboot''', no modifications necessary.}}<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You are guaranteed to require either a screen swap or motherboard swap. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# You'll see a lot of error output, but relax: this is normal. It will look something like this:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|SeaBIOS will not display anything without a proprietary VGABIOS blob (Intel or ATI GPU) or (Intel GPU only) the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS combined with native graphics initialization, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16044Board:lenovo/x60/Installation2015-04-10T02:31:31Z<p>Fchmmr: /* Install Coreboot (First Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All '''ThinkPad X60 Series''' laptops work out of the box with '''Coreboot or Libreboot''', no modifications necessary.}}<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You are guaranteed to require either a screen swap or motherboard swap. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# You'll see a lot of error output, but relax: this is normal. It will look something like this:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|SeaBIOS will not display anything without a proprietary VGABIOS blob (Intel or ATI GPU) or (Intel GPU only) the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS combined with native graphics initialization, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16043Board:lenovo/x60/Installation2015-04-10T02:29:51Z<p>Fchmmr: /* Install Coreboot (First Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All '''ThinkPad X60 Series''' laptops work out of the box with '''Coreboot or Libreboot''', no modifications necessary.}}<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You are guaranteed to require either a screen swap or motherboard swap. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# You'll see a lot of error output, but relax: this is normal. It will look something like this:<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16042Board:lenovo/x60/Installation2015-04-10T02:28:47Z<p>Fchmmr: /* Install Coreboot (First Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All '''ThinkPad X60 Series''' laptops work out of the box with '''Coreboot or Libreboot''', no modifications necessary.}}<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You are guaranteed to require either a screen swap or motherboard swap. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/ - apply the lenovobios patches from libreboot src - resources/flashrom/patch/lenovobios_* - there are 2 patches, for different chips. Build 2 executables, each with one of the patches (but not the other)<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16041Board:lenovo/x60/Installation2015-04-10T02:27:29Z<p>Fchmmr: /* Install Coreboot (First Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All '''ThinkPad X60 Series''' laptops work out of the box with '''Coreboot or Libreboot''', no modifications necessary.}}<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You are guaranteed to require either a screen swap or motherboard swap. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
The initial flash will write coreboot to the flash chip, but with the final 64KiB boot block from lenovobios (which is write-protected) intact. bucts will be used to make the system boot from the lower 64KiB boot block (before the final one) where you previously copied it to using dd.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16040Board:lenovo/x60/Installation2015-04-10T02:24:27Z<p>Fchmmr: /* Install Coreboot (First Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All '''ThinkPad X60 Series''' laptops work out of the box with '''Coreboot or Libreboot''', no modifications necessary.}}<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You are guaranteed to require either a screen swap or motherboard swap. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60 (dd modification for bucts already applied on all ROM images), if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16039Board:lenovo/x60/Installation2015-04-10T02:16:26Z<p>Fchmmr: //or</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All '''ThinkPad X60 Series''' laptops work out of the box with '''Coreboot or Libreboot''', no modifications necessary.}}<br />
<br />
{{Warning|The '''ThinkPad T60'''/T60p Series must be reconfigured to work with '''Libreboot'''. If you have a 1024x768 or 1280x800 resolution screen, ''you must replace it'' with a [http://libreboot.org/docs/hcl/index.html#supported_t60_list 1400x1050 or 1600x1200 screen.] If you have an ATI GPU, ''you must replace it'' [http://libreboot.org/docs/hcl/index.html#t60_ati_intel with an Intel motherboard.] You are guaranteed to require either a screen swap or motherboard swap. [http://support.lenovo.com/us/en/docs/migr-62733 Follow the steps in the Lenovo HMM] to replace them.}}<br />
<br />
{{Note|ThinkPad T60/T60p systems with a 1024x768 or 1280x800 resolution screen or an ATI GPU are compatible with '''Coreboot''' ''as long as proprietary VGABIOS blobs are extracted and installed.'' See [https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p this guide] for more information.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16035Board:lenovo/x60/Installation2015-04-09T21:00:25Z<p>Fchmmr: /* Back up the original proprietary firmware */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download and extract the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16034Board:lenovo/x60/Installation2015-04-09T20:15:02Z<p>Fchmmr: /* Recovery with a Hardware Firmware Flasher */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16033Board:lenovo/x60/Installation2015-04-09T20:09:48Z<p>Fchmmr: </p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]<br />
<br />
= OLD INFO =<br />
<br />
The status and installation pages used to be one in the same.<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60&diff=16032Board:lenovo/x602015-04-09T20:09:10Z<p>Fchmmr: </p>
<hr />
<div>Coreboot supports all variants of the ThinkPad X60 Series. (X60, X60s, X60 Tablet). <br />
<br />
Aside from pre-sales configuration (display, processor speed, optional components) it looks like every X60 variant uses the same motherboard schematic.<br />
<br />
== Status ==<br />
<br />
* Some ACPI issues with Windows needs to be fixed.<br />
* Works well with GNU/Linux.<br />
* The Wacom Digitizer now works on the X60 Tablet.<br />
<br />
==Installation and Flashing==<br />
<br />
Follow the tutorial below to install Coreboot on the ThinkPad X60 Series.<br />
<br />
[[Board:lenovo/x60/Installation]]<br />
<br />
== Wifi chipsets ==<br />
<br />
Lenovo BIOS has a whitelist of approved PCI ID's for wifi cards. Coreboot does not, so you are free to use any wifi chipset of your choosing once coreboot is installed.<br />
<br />
The [http://libreboot.org/ Libreboot] distribution [http://libreboot.org/docs/hcl/index.html#recommended_wifi lists Wifi chipsets not needing proprietary software to work].<br />
<br />
== Status ==<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = Core Duo Mobile (L2300), PBGA479<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_virt_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = OK<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_VGA_status = OK<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = [[Intel_82573_Ethernet_controller|Intel 82573L]]<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = Untested<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_PCMCIA_status = OK<br />
|Onboard_PCMCIA_comments = Ricoh rl5c476<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_CF_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM1_comments = located in Ultrabase X6<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = WIP<br />
|IR_comments = [http://review.coreboot.org/#/c/5242/ Submited for review]<br />
|Speaker_status = N/A<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Watchdog_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = OK<br />
|LEDs_comments = LEDs are controlled by Embedded Controller (EC). Working without special support.<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|Flashrom_status = OK<br />
|Flashrom_comments = See [[Lenovo_x60x]]<br />
}}<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
|- bgcolor="#6699ff"<br />
| colspan ="9" | '''Laptop specific'''<br />
{{Statusitem|Name=Tablet Touchscreen|Status={{{COM5_status|OK}}}|Comments={{{COM5_comments|x60 tablet wacom "penabled"}}}}}<br />
{{Statusitem|Name=thinkpad_acpi module compatibility|Status={{{thinkpad_acpi_status|OK}}}|Comments={{{thinkpad_acpi_comments|modprobe thinkpad_acpi works}}}}}<br />
|}<includeonly>[[Category:Tutorials]]</includeonly><noinclude><br />
<br />
== proprietary components status ==<br />
* CPU Microcode (optional?) - works fine without. See [http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf]<br />
* VGA option rom (optional): Native graphics initialization (free replacement) is also available and merged in the master repo. Note that the replacement doesn't work yet with seabios but works with grub(as a payload) or libpayload based payloads. SeaBIOS can be used with SeaVGABIOS (coreboot linear framebuffer option in seabios menuconfig) but the native graphics implementation currently lacks INT 10H and VBT.<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Building the ROM without proprietary blobs ==<br />
<br />
This basically means:<br />
* No microcode updates<br />
* Native graphics (replacement for the proprietary Video BIOS / VGA Option ROM)<br />
* GRUB2 payload<br />
<br />
In this configuration, only GNU/Linux is known to work. If you plan to use other operating systems, you might be out of luck.<br />
<br />
Download coreboot like usual:<br />
<pre><br />
git clone http://review.coreboot.org/coreboot<br />
cd coreboot<br />
</pre><br />
At the time of writing for (for these instructions), the following git revision was used:<br />
<pre><br />
git reset --hard 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e<br />
</pre><br />
Install all of the coreboot build dependencies listed at [http://www.coreboot.org/Build_HOWTO Build_HOWTO] and then build the crossgcc toolchain:<br />
<pre><br />
make crossgcc-i386<br />
</pre><br />
Apply the following patches in this order:<br />
<pre><br />
# Text mode patch for X60 native graphics (main patch already merged in coreboot. See 6723 on coreboot gerrit)<br />
git fetch http://review.coreboot.org/coreboot refs/changes/25/6725/3 && git cherry-pick FETCH_HEAD<br />
<br />
# Permanently enable wlan/wwan/bluetooth/trackpoint<br />
git fetch http://review.coreboot.org/coreboot refs/changes/58/7058/3 && git cherry-pick FETCH_HEAD<br />
<br />
# If you want legacy brightness controls (if using this, make sure not to include the ACPI brightness patch below):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/48/7048/4 && git cherry-pick FETCH_HEAD<br />
<br />
# OR if you want ACPI brightness controls (if using this, make sure not to include the legacy brightness patch above):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/31/6731/7 && git cherry-pick FETCH_HEAD<br />
# Fix uneven backlight levels (for ACPI brightness controls):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/49/7049/1 && git cherry-pick FETCH_HEAD<br />
<br />
# ACPI brightness patches above were abandoned due to Windows incompatibility. If you only want to use GNU/Linux, then it should work fine.<br />
</pre><br />
<br />
Now you will want this basic configuration for X60/X60s (in '''make menuconfig'''):<br />
<pre><br />
General setup / Expert mode = enable<br />
General setup / Local version string = 7BETC7WW (2.08 )<br />
Mainboard / Mainboard vendor = Lenovo<br />
Mainboard / Mainboard model = ThinkPad X60 / X60s / X60t<br />
Mainboard / ROM chip size = 2048 KB (2 MB)<br />
Mainboard / SMBIOS Serial Number = L3BH242<br />
Mainboard / SMBIOS Version Number = ThinkPad X60s<br />
Mainboard / SMBIOS Manufacturer = LENOVO<br />
Mainboard / SMBIOS Product name = 1702L8G<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates<br />
Devices / Use native graphics initialization = enable<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Generic Drivers / Digitizer = Autodetect<br />
Console / Send console output to a CBMEM buffer = enable<br />
Payload / Add a payload = An ELF executable payload<br />
Payload / Payload path and filename = grub.elf<br />
<br />
Now go back into Devices:<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
</pre><br />
<br />
Alternatively for X60 Tablet; it's the same as above, but with these differences:<br />
<pre><br />
General setup / Local version string = 7JET23WW (1.08 )<br />
Mainboard / SMBIOS Serial Number = L3B8281<br />
Mainboard / SMBIOS Version Number = ThinkPad X60 Tablet<br />
Mainboard / SMBIOS Product name = 6364WJ1<br />
Generic Drivers / Digitizer = Present<br />
</pre><br />
<br />
SMBIOS values were taken by running '''dmidecode''' with the factory BIOS.<br />
<br />
Note, the above assumes that you already built your grub.elf from source along with everything that you need. Building GRUB is not covered here.<br />
<br />
Put your grub.elf in the coreboot directory and then run '''make'''. Alternatively, you could go back into menuconfig and select coreboot's own GRUB payload config, which will automatically download and build the GRUB payload. Building it yourself can be more flexible, though, since you get to choose what modules you want and you can use your own configs.<br />
<br />
== TODO ==<br />
=== Non-free components replacements ===<br />
* <s>Replace the non-free VGA option rom by making native graphics init work.</s> (native graphics available in master)<br />
* Create a Native graphics<->VGA option rom. '''SeaVGABIOS (part of SeaBIOS) might be the answer. INT 10H and VBT are missing in native graphics.'''<br />
* <s>Make backlight work without the non-free option rom.</s> See [http://www.coreboot.org/Board:lenovo/x60#Building_without_proprietary_blobs]<br />
<br />
=== Windows currently doesn't boot (STOP A5 error) ===<br />
<br />
Windows 7 was tested and fails to boot at the moment.<br />
<br />
The native graphics implementation lacks INT 10H and VBT, and GRUB cannot boot it. Booting with SeaBIOS+SeaVGABIOS results in graphical corruption (and no boot).<br />
<br />
Booting with SeaBIOS and the VGA ROM (vbios) can be used to boot it, but booting ends with the message outlined here: [http://paste.debian.net/plain/122557 STOP A5]<br />
<br />
More information can be found [http://www.coreboot.org/ACPI#STOP_0xa5 here]<br />
<br />
===high pitched noise from the board during low power states===<br />
<br />
During low power state (cstate 3), a high-pitched "humming" noise eminates from the board. Some discussion has been made about this; suggestions include "using an oscilliscope in clever ways" (to detect where the noise is coming from to debug the issue). There are some workarounds:<br />
<br />
Use "idle=halt" (higher power consumption) or "processor.max_cstate=2" (higher power consumption, but not as bad) kernel parameter in GRUB. These increase heat and power consumption.<br />
<br />
Another option (for increased battery life and lower temperatures) is to use '''powertop --auto-tune''', or set 'Tunables' in powertop (without any parameters).<br />
<br />
== Other things ==<br />
* Add support for more batteries in ACPI.<br />
* Make the wifi card and/or the laptop produce less heat.<br />
* Sometimes some dock USB port aren't initialized => fix that<br />
* Fix that warning: <br />
[ 14.566817] ACPI Warning: 0x00000400-0x0000041f SystemIO conflicts with Region \_SB_.PCI0.SBUS.SMBI 1 (20130117/utaddress-251)<br />
By using that advise:<br />
<phcoder> GNUtoo-x60: in this case it looks like same range is declared twice in DSDT/SSDT<br />
<br />
== Documentation ==<br />
* The touchscreen serial port is on irq 5 at port 0x0200. [http://forum.bongofish.co.uk/index.php?topic=2307.0 Some additional info from a x61t wacom]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60&diff=16031Board:lenovo/x602015-04-09T20:04:17Z<p>Fchmmr: </p>
<hr />
<div>Coreboot supports all variants of the ThinkPad X60 Series. (X60, X60s, X60 Tablet). <br />
<br />
Aside from pre-sales configuration (display, processor speed, optional components) it looks like every X60 variant uses the same motherboard schematic.<br />
<br />
== Status ==<br />
<br />
* Some ACPI issues with Windows needs to be fixed.<br />
* Works well with GNU/Linux.<br />
* The Wacom Digitizer now works on the X60 Tablet.<br />
<br />
==Installation and Flashing==<br />
<br />
Follow the tutorial below to install Coreboot on the ThinkPad X60 Series.<br />
<br />
[[Board:lenovo/x60/Installation]]<br />
<br />
== Wifi chipsets ==<br />
<br />
Lenovo BIOS has a whitelist of approved PCI ID's for wifi cards. Coreboot does not, so you are free to use any wifi chipset of your choosing once coreboot is installed.<br />
<br />
The [http://libreboot.org/ Libreboot] distribution [http://libreboot.org/docs/hcl/index.html#recommended_wifi lists Wifi chipsets not needing proprietary software to work].<br />
<br />
== Status ==<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = Core Duo Mobile (L2300), PBGA479<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_virt_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = OK<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_VGA_status = OK<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = [[Intel_82573_Ethernet_controller|Intel 82573L]]<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = Untested<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_PCMCIA_status = OK<br />
|Onboard_PCMCIA_comments = Ricoh rl5c476<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_CF_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM1_comments = located in Ultrabase X6<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = WIP<br />
|IR_comments = [http://review.coreboot.org/#/c/5242/ Submited for review]<br />
|Speaker_status = N/A<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Watchdog_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = OK<br />
|LEDs_comments = LEDs are controlled by Embedded Controller (EC). Working without special support.<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|Flashrom_status = OK<br />
|Flashrom_comments = See [[Lenovo_x60x]]<br />
}}<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
|- bgcolor="#6699ff"<br />
| colspan ="9" | '''Laptop specific'''<br />
{{Statusitem|Name=Tablet Touchscreen|Status={{{COM5_status|OK}}}|Comments={{{COM5_comments|x60 tablet wacom "penabled"}}}}}<br />
{{Statusitem|Name=thinkpad_acpi module compatibility|Status={{{thinkpad_acpi_status|OK}}}|Comments={{{thinkpad_acpi_comments|modprobe thinkpad_acpi works}}}}}<br />
|}<includeonly>[[Category:Tutorials]]</includeonly><noinclude><br />
<br />
== proprietary components status ==<br />
* CPU Microcode (optional?) - works fine without. See [http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf]<br />
* VGA option rom (optional): Native graphics initialization (free replacement) is also available and merged in the master repo. Note that the replacement doesn't work yet with seabios but works with grub(as a payload) or libpayload based payloads. SeaBIOS can be used with SeaVGABIOS (coreboot linear framebuffer option in seabios menuconfig) but the native graphics implementation currently lacks INT 10H and VBT.<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Building the ROM without proprietary blobs ==<br />
<br />
This basically means:<br />
* No microcode updates<br />
* Native graphics (replacement for the proprietary Video BIOS / VGA Option ROM)<br />
* GRUB2 payload<br />
<br />
In this configuration, only GNU/Linux is known to work. If you plan to use other operating systems, you might be out of luck.<br />
<br />
Download coreboot like usual:<br />
<pre><br />
git clone http://review.coreboot.org/coreboot<br />
cd coreboot<br />
</pre><br />
At the time of writing for (for these instructions), the following git revision was used:<br />
<pre><br />
git reset --hard 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e<br />
</pre><br />
Install all of the coreboot build dependencies listed at [http://www.coreboot.org/Build_HOWTO Build_HOWTO] and then build the crossgcc toolchain:<br />
<pre><br />
make crossgcc-i386<br />
</pre><br />
Apply the following patches in this order:<br />
<pre><br />
# Text mode patch for X60 native graphics (main patch already merged in coreboot. See 6723 on coreboot gerrit)<br />
git fetch http://review.coreboot.org/coreboot refs/changes/25/6725/3 && git cherry-pick FETCH_HEAD<br />
<br />
# Permanently enable wlan/wwan/bluetooth/trackpoint<br />
git fetch http://review.coreboot.org/coreboot refs/changes/58/7058/3 && git cherry-pick FETCH_HEAD<br />
<br />
# If you want legacy brightness controls (if using this, make sure not to include the ACPI brightness patch below):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/48/7048/4 && git cherry-pick FETCH_HEAD<br />
<br />
# OR if you want ACPI brightness controls (if using this, make sure not to include the legacy brightness patch above):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/31/6731/7 && git cherry-pick FETCH_HEAD<br />
# Fix uneven backlight levels (for ACPI brightness controls):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/49/7049/1 && git cherry-pick FETCH_HEAD<br />
<br />
# ACPI brightness patches above were abandoned due to Windows incompatibility. If you only want to use GNU/Linux, then it should work fine.<br />
</pre><br />
<br />
Now you will want this basic configuration for X60/X60s (in '''make menuconfig'''):<br />
<pre><br />
General setup / Expert mode = enable<br />
General setup / Local version string = 7BETC7WW (2.08 )<br />
Mainboard / Mainboard vendor = Lenovo<br />
Mainboard / Mainboard model = ThinkPad X60 / X60s / X60t<br />
Mainboard / ROM chip size = 2048 KB (2 MB)<br />
Mainboard / SMBIOS Serial Number = L3BH242<br />
Mainboard / SMBIOS Version Number = ThinkPad X60s<br />
Mainboard / SMBIOS Manufacturer = LENOVO<br />
Mainboard / SMBIOS Product name = 1702L8G<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates<br />
Devices / Use native graphics initialization = enable<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Generic Drivers / Digitizer = Autodetect<br />
Console / Send console output to a CBMEM buffer = enable<br />
Payload / Add a payload = An ELF executable payload<br />
Payload / Payload path and filename = grub.elf<br />
<br />
Now go back into Devices:<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
</pre><br />
<br />
Alternatively for X60 Tablet; it's the same as above, but with these differences:<br />
<pre><br />
General setup / Local version string = 7JET23WW (1.08 )<br />
Mainboard / SMBIOS Serial Number = L3B8281<br />
Mainboard / SMBIOS Version Number = ThinkPad X60 Tablet<br />
Mainboard / SMBIOS Product name = 6364WJ1<br />
Generic Drivers / Digitizer = Present<br />
</pre><br />
<br />
SMBIOS values were taken by running '''dmidecode''' with the factory BIOS.<br />
<br />
Note, the above assumes that you already built your grub.elf from source along with everything that you need. Building GRUB is not covered here.<br />
<br />
Put your grub.elf in the coreboot directory and then run '''make'''. Alternatively, you could go back into menuconfig and select coreboot's own GRUB payload config, which will automatically download and build the GRUB payload. Building it yourself can be more flexible, though, since you get to choose what modules you want and you can use your own configs.<br />
<br />
== TODO ==<br />
=== Non-free components replacements ===<br />
* <s>Replace the non-free VGA option rom by making native graphics init work.</s> (native graphics available in master)<br />
* Create a Native graphics<->VGA option rom. '''SeaVGABIOS (part of SeaBIOS) might be the answer. INT 10H and VBT are missing in native graphics.'''<br />
* <s>Make backlight work without the non-free option rom.</s> See [http://www.coreboot.org/Board:lenovo/x60#Building_without_proprietary_blobs]<br />
<br />
=== Windows currently doesn't boot (STOP A5 error) ===<br />
<br />
Windows 7 was tested and fails to boot at the moment.<br />
<br />
The native graphics implementation lacks INT 10H and VBT, and GRUB cannot boot it. Booting with SeaBIOS+SeaVGABIOS results in graphical corruption (and no boot).<br />
<br />
Booting with SeaBIOS and the VGA ROM (vbios) can be used to boot it, but booting ends with the message outlined here: [http://paste.debian.net/plain/122557 STOP A5]<br />
<br />
More information can be found [http://www.coreboot.org/ACPI#STOP_0xa5 here]<br />
<br />
===high pitched noise from the board during low power states===<br />
<br />
During low power state (cstate 3), a high-pitched "humming" noise eminates from the board. Some discussion has been made about this; suggestions include "using an oscilliscope in clever ways" (to detect where the noise is coming from to debug the issue). There are some workarounds:<br />
<br />
Use "idle=halt" (higher power consumption) or "processor.max_cstate=2" (higher power consumption, but not as bad) kernel parameter in GRUB. These increase heat and power consumption.<br />
<br />
Another option (for increased battery life and lower temperatures) is to use '''powertop --auto-tune''', or set 'Tunables' in powertop (without any parameters).<br />
<br />
== Other things ==<br />
* Add support for more batteries in ACPI.<br />
* Make the wifi card and/or the laptop produce less heat.<br />
* Sometimes some dock USB port aren't initialized => fix that<br />
* Fix that warning: <br />
[ 14.566817] ACPI Warning: 0x00000400-0x0000041f SystemIO conflicts with Region \_SB_.PCI0.SBUS.SMBI 1 (20130117/utaddress-251)<br />
By using that advise:<br />
<phcoder> GNUtoo-x60: in this case it looks like same range is declared twice in DSDT/SSDT<br />
<br />
== Documentation ==<br />
* The touchscreen serial port is on irq 5 at port 0x0200. [http://forum.bongofish.co.uk/index.php?topic=2307.0 Some additional info from a x61t wacom]<br />
<br />
<br />
<br />
<br />
= OLD INFO =<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60&diff=16030Board:lenovo/x602015-04-09T20:03:34Z<p>Fchmmr: </p>
<hr />
<div>Coreboot supports all variants of the ThinkPad X60 Series. (X60, X60s, X60 Tablet). <br />
<br />
Aside from pre-sales configuration (display, processor speed, optional components) it looks like every X60 variant uses the same motherboard schematic.<br />
<br />
== Status ==<br />
<br />
* Some ACPI issues with Windows needs to be fixed.<br />
* Works well with GNU/Linux.<br />
* The Wacom Digitizer now works on the X60 Tablet.<br />
<br />
==Installation and Flashing==<br />
<br />
Follow the tutorial below to install Coreboot on the ThinkPad X60 Series.<br />
<br />
[[Board:lenovo/x60/Installation]]<br />
<br />
== Wifi chipsets ==<br />
<br />
Lenovo BIOS has a whitelist of approved PCI ID's for wifi cards. Coreboot does not, so you are free to use any wifi chipset of your choosing once coreboot is installed.<br />
<br />
The [http://libreboot.org/ Libreboot] distribution [http://libreboot.org/docs/hcl/index.html#recommended_wifi lists Wifi chipsets not needing proprietary software to work].<br />
<br />
== Status ==<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = Core Duo Mobile (L2300), PBGA479<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_virt_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = OK<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_VGA_status = OK<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = [[Intel_82573_Ethernet_controller|Intel 82573L]]<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = Untested<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_PCMCIA_status = OK<br />
|Onboard_PCMCIA_comments = Ricoh rl5c476<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_CF_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM1_comments = located in Ultrabase X6<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = WIP<br />
|IR_comments = [http://review.coreboot.org/#/c/5242/ Submited for review]<br />
|Speaker_status = N/A<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Watchdog_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = OK<br />
|LEDs_comments = LEDs are controlled by Embedded Controller (EC). Working without special support.<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|Flashrom_status = OK<br />
|Flashrom_comments = See [[Lenovo_x60x]]<br />
}}<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
|- bgcolor="#6699ff"<br />
| colspan ="9" | '''Laptop specific'''<br />
{{Statusitem|Name=Tablet Touchscreen|Status={{{COM5_status|OK}}}|Comments={{{COM5_comments|x60 tablet wacom "penabled"}}}}}<br />
{{Statusitem|Name=thinkpad_acpi module compatibility|Status={{{thinkpad_acpi_status|OK}}}|Comments={{{thinkpad_acpi_comments|modprobe thinkpad_acpi works}}}}}<br />
|}<includeonly>[[Category:Tutorials]]</includeonly><noinclude><br />
<br />
== proprietary components status ==<br />
* CPU Microcode (optional?) - works fine without. See [http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf]<br />
* VGA option rom (optional): Native graphics initialization (free replacement) is also available and merged in the master repo. Note that the replacement doesn't work yet with seabios but works with grub(as a payload) or libpayload based payloads. SeaBIOS can be used with SeaVGABIOS (coreboot linear framebuffer option in seabios menuconfig) but the native graphics implementation currently lacks INT 10H and VBT.<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Building the ROM without proprietary blobs ==<br />
<br />
This basically means:<br />
* No microcode updates<br />
* Native graphics (replacement for the proprietary Video BIOS / VGA Option ROM)<br />
* GRUB2 payload<br />
<br />
In this configuration, only GNU/Linux is known to work. If you plan to use other operating systems, you might be out of luck.<br />
<br />
Download coreboot like usual:<br />
<pre><br />
git clone http://review.coreboot.org/coreboot<br />
cd coreboot<br />
</pre><br />
At the time of writing for (for these instructions), the following git revision was used:<br />
<pre><br />
git reset --hard 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e<br />
</pre><br />
Install all of the coreboot build dependencies listed at [http://www.coreboot.org/Build_HOWTO Build_HOWTO] and then build the crossgcc toolchain:<br />
<pre><br />
make crossgcc-i386<br />
</pre><br />
Apply the following patches in this order:<br />
<pre><br />
# Text mode patch for X60 native graphics (main patch already merged in coreboot. See 6723 on coreboot gerrit)<br />
git fetch http://review.coreboot.org/coreboot refs/changes/25/6725/3 && git cherry-pick FETCH_HEAD<br />
<br />
# Permanently enable wlan/wwan/bluetooth/trackpoint<br />
git fetch http://review.coreboot.org/coreboot refs/changes/58/7058/3 && git cherry-pick FETCH_HEAD<br />
<br />
# If you want legacy brightness controls (if using this, make sure not to include the ACPI brightness patch below):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/48/7048/4 && git cherry-pick FETCH_HEAD<br />
<br />
# OR if you want ACPI brightness controls (if using this, make sure not to include the legacy brightness patch above):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/31/6731/7 && git cherry-pick FETCH_HEAD<br />
# Fix uneven backlight levels (for ACPI brightness controls):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/49/7049/1 && git cherry-pick FETCH_HEAD<br />
<br />
# ACPI brightness patches above were abandoned due to Windows incompatibility. If you only want to use GNU/Linux, then it should work fine.<br />
</pre><br />
<br />
Now you will want this basic configuration for X60/X60s (in '''make menuconfig'''):<br />
<pre><br />
General setup / Expert mode = enable<br />
General setup / Local version string = 7BETC7WW (2.08 )<br />
Mainboard / Mainboard vendor = Lenovo<br />
Mainboard / Mainboard model = ThinkPad X60 / X60s / X60t<br />
Mainboard / ROM chip size = 2048 KB (2 MB)<br />
Mainboard / SMBIOS Serial Number = L3BH242<br />
Mainboard / SMBIOS Version Number = ThinkPad X60s<br />
Mainboard / SMBIOS Manufacturer = LENOVO<br />
Mainboard / SMBIOS Product name = 1702L8G<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates<br />
Devices / Use native graphics initialization = enable<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Generic Drivers / Digitizer = Autodetect<br />
Console / Send console output to a CBMEM buffer = enable<br />
Payload / Add a payload = An ELF executable payload<br />
Payload / Payload path and filename = grub.elf<br />
<br />
Now go back into Devices:<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
</pre><br />
<br />
Alternatively for X60 Tablet; it's the same as above, but with these differences:<br />
<pre><br />
General setup / Local version string = 7JET23WW (1.08 )<br />
Mainboard / SMBIOS Serial Number = L3B8281<br />
Mainboard / SMBIOS Version Number = ThinkPad X60 Tablet<br />
Mainboard / SMBIOS Product name = 6364WJ1<br />
Generic Drivers / Digitizer = Present<br />
</pre><br />
<br />
SMBIOS values were taken by running '''dmidecode''' with the factory BIOS.<br />
<br />
Note, the above assumes that you already built your grub.elf from source along with everything that you need. Building GRUB is not covered here.<br />
<br />
Put your grub.elf in the coreboot directory and then run '''make'''. Alternatively, you could go back into menuconfig and select coreboot's own GRUB payload config, which will automatically download and build the GRUB payload. Building it yourself can be more flexible, though, since you get to choose what modules you want and you can use your own configs.<br />
<br />
== TODO ==<br />
=== Non-free components replacements ===<br />
* <s>Replace the non-free VGA option rom by making native graphics init work.</s> (native graphics available in master)<br />
* Create a Native graphics<->VGA option rom. '''SeaVGABIOS (part of SeaBIOS) might be the answer. INT 10H and VBT are missing in native graphics.'''<br />
* <s>Make backlight work without the non-free option rom.</s> See [http://www.coreboot.org/Board:lenovo/x60#Building_without_proprietary_blobs]<br />
<br />
=== Windows currently doesn't boot (STOP A5 error) ===<br />
<br />
Windows 7 was tested and fails to boot at the moment.<br />
<br />
The native graphics implementation lacks INT 10H and VBT, and GRUB cannot boot it. Booting with SeaBIOS+SeaVGABIOS results in graphical corruption (and no boot).<br />
<br />
Booting with SeaBIOS and the VGA ROM (vbios) can be used to boot it, but booting ends with the message outlined here: [http://paste.debian.net/plain/122557 STOP A5]<br />
<br />
More information can be found [http://www.coreboot.org/ACPI#STOP_0xa5 here]<br />
<br />
===high pitched noise from the board during low power states===<br />
<br />
During low power state (cstate 3), a high-pitched "humming" noise eminates from the board. Some discussion has been made about this; suggestions include "using an oscilliscope in clever ways" (to detect where the noise is coming from to debug the issue). There are some workarounds:<br />
<br />
Use "idle=halt" (higher power consumption) or "processor.max_cstate=2" (higher power consumption, but not as bad) kernel parameter in GRUB. These increase heat and power consumption.<br />
<br />
Another option (for increased battery life and lower temperatures) is to use '''powertop --auto-tune''', or set 'Tunables' in powertop (without any parameters).<br />
<br />
== Other things ==<br />
* Add support for more batteries in ACPI.<br />
* Make the wifi card and/or the laptop produce less heat.<br />
* Sometimes some dock USB port aren't initialized => fix that<br />
* Fix that warning: <br />
[ 14.566817] ACPI Warning: 0x00000400-0x0000041f SystemIO conflicts with Region \_SB_.PCI0.SBUS.SMBI 1 (20130117/utaddress-251)<br />
By using that advise:<br />
<phcoder> GNUtoo-x60: in this case it looks like same range is declared twice in DSDT/SSDT<br />
<br />
== Documentation ==<br />
* The touchscreen serial port is on irq 5 at port 0x0200. [http://forum.bongofish.co.uk/index.php?topic=2307.0 Some additional info from a x61t wacom]<br />
<br />
<br />
<br />
<br />
# OLD INFO<br />
<br />
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:<br />
<br />
== Flashing on the laptop instructions. ==<br />
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions.<br />
<br />
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.<br />
<br />
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.<br />
<br />
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility].<br />
<br />
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.<br />
#* Find the definition of your flash chip in flashrom's flashchips.c<br />
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>).<br />
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID)<br />
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>)<br />
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>)<br />
# Run <code>flashrom -p internal -r factory.bin</code><br />
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.<br />
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code><br />
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code><br />
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output:<br />
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code><br />
#: <code>*</code><br />
#: <code>0010000</code><br />
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code><br />
# Run <code>bucts 1</code><br />
# Run <code>flashrom -p internal -w coreboot.rom</code><br />
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic.<br />
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot<br />
# Revert all changes made to flashrom (maybe backup the binary for later experiments)<br />
# Run <code>flashrom -p internal -w coreboot.rom</code>.<br />
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.<br />
# Run <code>bucts 0</code><br />
<br />
<br />
<br />
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575<br />
<br />
== Recovery ==<br />
If you had a bad flash you will need a recovery method.<br />
<br />
If you only set bucts, then rebooted without doing any flash writes, things might be easier:<br />
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted).<br />
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.<br />
<br />
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.<br />
=== Required/advised hardware and informations ===<br />
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop<br />
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance.<br />
* An external flashrom programmer<br />
<br />
=== Howto ===<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the BIOS chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
== Coreboot standard configuration ==<br />
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:<br />
[ ] Run VGA Option ROMs<br />
in make menuconfig.<br />
Note that you still need to include the option rom in coreboot:<br />
[*] Add a VGA BIOS image<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).<br />
<br />
From the #coreboot IRC Channel on FreeNode servers: <br />
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels<br />
[...]<br />
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that<br />
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)<br />
<br />
== Last tested revision on the X60 ==<br />
4bd7b0cbadabb45f9131da03121a6ca284f24f35<br />
<br />
== Status ==<br />
* [[Thinkpad_X60s|Thinkpad X60s Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60&diff=16029Board:lenovo/x602015-04-09T20:01:58Z<p>Fchmmr: /* Wifi chipsets */</p>
<hr />
<div>Coreboot supports all variants of the ThinkPad X60 Series. (X60, X60s, X60 Tablet). <br />
<br />
Aside from pre-sales configuration (display, processor speed, optional components) it looks like every X60 variant uses the same motherboard schematic.<br />
<br />
== Status ==<br />
<br />
* Some ACPI issues with Windows needs to be fixed.<br />
* Works well with GNU/Linux.<br />
* The Wacom Digitizer now works on the X60 Tablet.<br />
<br />
==Installation and Flashing==<br />
<br />
Follow the tutorial below to install Coreboot on the ThinkPad X60 Series.<br />
<br />
[[Board:lenovo/x60/Installation]]<br />
<br />
== Wifi chipsets ==<br />
<br />
Lenovo BIOS has a whitelist of approved PCI ID's for wifi cards. Coreboot does not, so you are free to use any wifi chipset of your choosing once coreboot is installed.<br />
<br />
The [http://libreboot.org/ Libreboot] distribution [http://libreboot.org/docs/hcl/index.html#recommended_wifi lists Wifi chipsets not needing proprietary software to work].<br />
<br />
== Status ==<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = Core Duo Mobile (L2300), PBGA479<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_virt_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = OK<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_VGA_status = OK<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = [[Intel_82573_Ethernet_controller|Intel 82573L]]<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = Untested<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_PCMCIA_status = OK<br />
|Onboard_PCMCIA_comments = Ricoh rl5c476<br />
|Onboard_SCSI_status = N/A<br />
|Onboard_CF_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM1_comments = located in Ultrabase X6<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = WIP<br />
|IR_comments = [http://review.coreboot.org/#/c/5242/ Submited for review]<br />
|Speaker_status = N/A<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Watchdog_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = OK<br />
|LEDs_comments = LEDs are controlled by Embedded Controller (EC). Working without special support.<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|Flashrom_status = OK<br />
|Flashrom_comments = See [[Lenovo_x60x]]<br />
}}<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
|- bgcolor="#6699ff"<br />
| colspan ="9" | '''Laptop specific'''<br />
{{Statusitem|Name=Tablet Touchscreen|Status={{{COM5_status|OK}}}|Comments={{{COM5_comments|x60 tablet wacom "penabled"}}}}}<br />
{{Statusitem|Name=thinkpad_acpi module compatibility|Status={{{thinkpad_acpi_status|OK}}}|Comments={{{thinkpad_acpi_comments|modprobe thinkpad_acpi works}}}}}<br />
|}<includeonly>[[Category:Tutorials]]</includeonly><noinclude><br />
<br />
== proprietary components status ==<br />
* CPU Microcode (optional?) - works fine without. See [http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf]<br />
* VGA option rom (optional): Native graphics initialization (free replacement) is also available and merged in the master repo. Note that the replacement doesn't work yet with seabios but works with grub(as a payload) or libpayload based payloads. SeaBIOS can be used with SeaVGABIOS (coreboot linear framebuffer option in seabios menuconfig) but the native graphics implementation currently lacks INT 10H and VBT.<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Building the ROM without proprietary blobs ==<br />
<br />
This basically means:<br />
* No microcode updates<br />
* Native graphics (replacement for the proprietary Video BIOS / VGA Option ROM)<br />
* GRUB2 payload<br />
<br />
In this configuration, only GNU/Linux is known to work. If you plan to use other operating systems, you might be out of luck.<br />
<br />
Download coreboot like usual:<br />
<pre><br />
git clone http://review.coreboot.org/coreboot<br />
cd coreboot<br />
</pre><br />
At the time of writing for (for these instructions), the following git revision was used:<br />
<pre><br />
git reset --hard 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e<br />
</pre><br />
Install all of the coreboot build dependencies listed at [http://www.coreboot.org/Build_HOWTO Build_HOWTO] and then build the crossgcc toolchain:<br />
<pre><br />
make crossgcc-i386<br />
</pre><br />
Apply the following patches in this order:<br />
<pre><br />
# Text mode patch for X60 native graphics (main patch already merged in coreboot. See 6723 on coreboot gerrit)<br />
git fetch http://review.coreboot.org/coreboot refs/changes/25/6725/3 && git cherry-pick FETCH_HEAD<br />
<br />
# Permanently enable wlan/wwan/bluetooth/trackpoint<br />
git fetch http://review.coreboot.org/coreboot refs/changes/58/7058/3 && git cherry-pick FETCH_HEAD<br />
<br />
# If you want legacy brightness controls (if using this, make sure not to include the ACPI brightness patch below):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/48/7048/4 && git cherry-pick FETCH_HEAD<br />
<br />
# OR if you want ACPI brightness controls (if using this, make sure not to include the legacy brightness patch above):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/31/6731/7 && git cherry-pick FETCH_HEAD<br />
# Fix uneven backlight levels (for ACPI brightness controls):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/49/7049/1 && git cherry-pick FETCH_HEAD<br />
<br />
# ACPI brightness patches above were abandoned due to Windows incompatibility. If you only want to use GNU/Linux, then it should work fine.<br />
</pre><br />
<br />
Now you will want this basic configuration for X60/X60s (in '''make menuconfig'''):<br />
<pre><br />
General setup / Expert mode = enable<br />
General setup / Local version string = 7BETC7WW (2.08 )<br />
Mainboard / Mainboard vendor = Lenovo<br />
Mainboard / Mainboard model = ThinkPad X60 / X60s / X60t<br />
Mainboard / ROM chip size = 2048 KB (2 MB)<br />
Mainboard / SMBIOS Serial Number = L3BH242<br />
Mainboard / SMBIOS Version Number = ThinkPad X60s<br />
Mainboard / SMBIOS Manufacturer = LENOVO<br />
Mainboard / SMBIOS Product name = 1702L8G<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates<br />
Devices / Use native graphics initialization = enable<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Generic Drivers / Digitizer = Autodetect<br />
Console / Send console output to a CBMEM buffer = enable<br />
Payload / Add a payload = An ELF executable payload<br />
Payload / Payload path and filename = grub.elf<br />
<br />
Now go back into Devices:<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
</pre><br />
<br />
Alternatively for X60 Tablet; it's the same as above, but with these differences:<br />
<pre><br />
General setup / Local version string = 7JET23WW (1.08 )<br />
Mainboard / SMBIOS Serial Number = L3B8281<br />
Mainboard / SMBIOS Version Number = ThinkPad X60 Tablet<br />
Mainboard / SMBIOS Product name = 6364WJ1<br />
Generic Drivers / Digitizer = Present<br />
</pre><br />
<br />
SMBIOS values were taken by running '''dmidecode''' with the factory BIOS.<br />
<br />
Note, the above assumes that you already built your grub.elf from source along with everything that you need. Building GRUB is not covered here.<br />
<br />
Put your grub.elf in the coreboot directory and then run '''make'''. Alternatively, you could go back into menuconfig and select coreboot's own GRUB payload config, which will automatically download and build the GRUB payload. Building it yourself can be more flexible, though, since you get to choose what modules you want and you can use your own configs.<br />
<br />
== TODO ==<br />
=== Non-free components replacements ===<br />
* <s>Replace the non-free VGA option rom by making native graphics init work.</s> (native graphics available in master)<br />
* Create a Native graphics<->VGA option rom. '''SeaVGABIOS (part of SeaBIOS) might be the answer. INT 10H and VBT are missing in native graphics.'''<br />
* <s>Make backlight work without the non-free option rom.</s> See [http://www.coreboot.org/Board:lenovo/x60#Building_without_proprietary_blobs]<br />
<br />
=== Windows currently doesn't boot (STOP A5 error) ===<br />
<br />
Windows 7 was tested and fails to boot at the moment.<br />
<br />
The native graphics implementation lacks INT 10H and VBT, and GRUB cannot boot it. Booting with SeaBIOS+SeaVGABIOS results in graphical corruption (and no boot).<br />
<br />
Booting with SeaBIOS and the VGA ROM (vbios) can be used to boot it, but booting ends with the message outlined here: [http://paste.debian.net/plain/122557 STOP A5]<br />
<br />
More information can be found [http://www.coreboot.org/ACPI#STOP_0xa5 here]<br />
<br />
===high pitched noise from the board during low power states===<br />
<br />
During low power state (cstate 3), a high-pitched "humming" noise eminates from the board. Some discussion has been made about this; suggestions include "using an oscilliscope in clever ways" (to detect where the noise is coming from to debug the issue). There are some workarounds:<br />
<br />
Use "idle=halt" (higher power consumption) or "processor.max_cstate=2" (higher power consumption, but not as bad) kernel parameter in GRUB. These increase heat and power consumption.<br />
<br />
Another option (for increased battery life and lower temperatures) is to use '''powertop --auto-tune''', or set 'Tunables' in powertop (without any parameters).<br />
<br />
== Other things ==<br />
* Add support for more batteries in ACPI.<br />
* Make the wifi card and/or the laptop produce less heat.<br />
* Sometimes some dock USB port aren't initialized => fix that<br />
* Fix that warning: <br />
[ 14.566817] ACPI Warning: 0x00000400-0x0000041f SystemIO conflicts with Region \_SB_.PCI0.SBUS.SMBI 1 (20130117/utaddress-251)<br />
By using that advise:<br />
<phcoder> GNUtoo-x60: in this case it looks like same range is declared twice in DSDT/SSDT<br />
<br />
== Documentation ==<br />
* The touchscreen serial port is on irq 5 at port 0x0200. [http://forum.bongofish.co.uk/index.php?topic=2307.0 Some additional info from a x61t wacom]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16027Board:lenovo/x60/Installation2015-04-09T19:52:16Z<p>Fchmmr: /* Install Coreboot (First Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16026Board:lenovo/x60/Installation2015-04-09T19:35:03Z<p>Fchmmr: /* Back up the original proprietary firmware */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} or {{ic|libreboot_util/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16025Board:lenovo/x60/Installation2015-04-09T19:34:13Z<p>Fchmmr: /* Install Coreboot (Second Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the original boot block. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16024Board:lenovo/x60/Installation2015-04-09T19:33:50Z<p>Fchmmr: /* Install Coreboot (Second Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the vendor BIOS. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal (only if the step above worked):<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16023Board:lenovo/x60/Installation2015-04-09T19:33:27Z<p>Fchmmr: /* Install Coreboot (Second Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the vendor BIOS. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
## It should say '''Verifying flash... VERIFIED''' at the end of the output. If not, get help.<br />
# Reset bucts back to normal:<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16022Board:lenovo/x60/Installation2015-04-09T19:32:05Z<p>Fchmmr: /* Install Coreboot (First Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" widescreen T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the vendor BIOS. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
# Reset bucts back to normal:<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16021Board:lenovo/x60/Installation2015-04-09T19:31:48Z<p>Fchmmr: /* Install Coreboot (First Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics; also, the 15.4" T60 laptops are untested in libreboot):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the vendor BIOS. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
# Reset bucts back to normal:<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16020Board:lenovo/x60/Installation2015-04-09T19:30:32Z<p>Fchmmr: /* Install Coreboot (Second Flash) */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the vendor BIOS. This time, you can (and should) used an unpatched version of flashrom. Libreboot also comes with this, or (once again) you can also use upstream if you like.<br />
<br />
# Run {{ic|su}} to become root, and change to the libreboot_bin or libreboot_util directory.<br />
## Run {{ic|./flashrom/i686/flashrom -p internal -w coreboot.rom}} <br />
# Reset bucts back to normal:<br />
## Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16019Board:lenovo/x60/Installation2015-04-09T19:28:27Z<p>Fchmmr: /* Patch the coreboot ROM image for bucts */</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the vendor BIOS.<br />
<br />
# Run {{ic|su}} to become root.<br />
# Enter the {{ic|flashrom}} directory.<br />
# Run {{ic|./flashrom -p internal -w coreboot.rom}} <br />
#: This will successfully overwrite the entire flash chip with no errors, including the last 64k that were write protected with the factory BIOS.<br />
#: If it complains about 3 different flashchips (in the case of macronix chip), do this instead:<br />
#: Run {{ic|./flashrom -p internal -w coreboot.rom -c "MX25L1605D/MX25L1608D/MX25L1673E"}} <br />
# Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16018Board:lenovo/x60/Installation2015-04-09T19:27:43Z<p>Fchmmr: /* Patch the coreboot ROM image for bucts */ Remove more crap</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Copy the built {{ic|coreboot.rom</code> to the <code>flashrom}} source code directory.<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the vendor BIOS.<br />
<br />
# Run {{ic|su}} to become root.<br />
# Enter the {{ic|flashrom}} directory.<br />
# Run {{ic|./flashrom -p internal -w coreboot.rom}} <br />
#: This will successfully overwrite the entire flash chip with no errors, including the last 64k that were write protected with the factory BIOS.<br />
#: If it complains about 3 different flashchips (in the case of macronix chip), do this instead:<br />
#: Run {{ic|./flashrom -p internal -w coreboot.rom -c "MX25L1605D/MX25L1608D/MX25L1673E"}} <br />
# Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/x60/Installation&diff=16017Board:lenovo/x60/Installation2015-04-09T19:26:52Z<p>Fchmmr: remove all the crap. tidy it up. The instructions were conflicting, contradictory and confusing. Not to mention, wrong.</p>
<hr />
<div>These Coreboot/Libreboot flashing instructions are designed for the [[Board:lenovo/x60|'''Lenovo X60''', '''X60s''', '''X60 tablet''',]] [[Board:lenovo/t60|'''T60''' and '''T60p''']].<br />
<br />
{{Note|All ThinkPad X60 Series laptops work out of the box with Coreboot and Libreboot, no modifications necessary.}}<br />
<br />
=== Back up the original proprietary firmware ===<br />
<br />
{{Warning|It is ''STRONGLY RECOMMENDED'' to back up the vendor BIOS; each vendor BIOS image has a unique, unrecoverable ID. Do not use another laptop's vendor BIOS image.}}<br />
<br />
# Download, extract, and build the latest [http://www.libreboot.org/download/ Libreboot binaries].<br />
# From the {{ic|libreboot_bin/}} directory:<br />
# Run ''both'' of these commands to backup the BIOS to {{ic|factory.bin}} (don't panic, nothing is being installed): <br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_sst -p internal -r factory.bin}}<br />
#: {{ic|sudo ./flashrom/i686/flashrom_lenovobios_macronix -p internal -r factory.bin}}<br />
# This will have created a file called "factory.bin", which is the contents of the flash chip while it had the original "BIOS" firmware. Back this up to a safe place (it can be useful for potential reverse engineering work, or for other testing).<br />
# The source code for this version of flashrom can also be found on the libreboot website. It is a patched flashrom executable, to work around security restrictions in the original Lenovo BIOS (it will also be used for flashing, later on in this guide); the patches for it in libreboot can be found under resources/flashrom/patch/.<br />
# There are two flash chips for the X60/T60. The instructions above simply used flashrom executables for both; one failed, and one should have succeeded. This is much easier than finding out what flash chip you have before hand (which involved elaborate hacks in flashrom, reading output, or taking apart the laptop and physically looking at the chip).<br />
<br />
== Video BIOS (VGA option ROM) ==<br />
<br />
On systems with Intel graphics, native graphics initialization code exists in coreboot. However, if you want to use the Intel (proprietary) Video BIOS, you should extract this from the factory.bin dump that you created earlier. If your system has ATI graphics (common on the T60), this is '''required'''.<br />
<br />
[http://www.coreboot.org/VGA_support#RECOMMENDED:_Extracting_from_your_vendor_bios_image VGA support] page on the coreboot wiki tells you how to extract it.<br />
<br />
Place this inside the coreboot/ directory, and in menuconfig enable it under '''Devices''' if you are using payloads other than SeaBIOS (for SeaBIOS, you should configure SeaBIOS to run it. Coreboot's default SeaBIOS configuration will use it). In either scenario, you will want to include it in the ROM image, so make sure to specify the path "vgabios.bin" (or whatever the path to your VBIOS image is) in menuconfig, making sure to enter the correct numbers for the PCI ID (get this using '''lspci -nn''').<br />
<br />
== Patch the coreboot ROM image for bucts ==<br />
<br />
Failure to follow this will result in a bricked laptop.<br />
<br />
=== Method 1: One-line Patcher===<br />
<br />
# Place the {{ic|coreboot.rom}} file in the current directory.<br />
# Run this one-liner to patch the ROM in one command:<br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k; dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump; dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
<br />
<br />
=== BUC.TS ===<br />
<br />
'''B'''ack'''u'''p '''C'''ontrol '''T'''op '''S'''wap.<br />
<br />
# Copy the built {{ic|coreboot.rom</code> to the <code>flashrom}} source code directory.<br />
# Run the {{ic|dd}} command below to shift the first 64K of data from <code>coreboot.rom</code><br />
#: {{ic|<nowiki>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</nowiki>}}<br />
# Run the dd command below to display the first 64k of {{ic|coreboot.rom}}<br />
#: {{ic|<nowiki>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</nowiki>}}<br />
# Verify that the complete range is filled with {{ic|ff}} bytes before proceeding.<br />
#: The output of the {{ic|dd}} command above must EXACTLY match the text below. If not, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.<br />
#:: {{ic|0000000 ffff ffff ffff ffff ffff ffff ffff ffff *0010000}} <br />
# Run the {{ic|dd}} command below:<br />
#: {{ic|<nowiki>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s<br />
coreboot.rom) - 0x20000] count=64k conv=notrunc</nowiki>}}<br />
<br />
What this did was copy the upper 64KiB section of the ROM image, into the section below. This is the boot block; lenovobios prevents writing to the upper 64KiB block (by default, it prevents all other regions but a patched flashrom binary can flash those regions in software). A utility called '''bucts''' will be used later on to set the system up so that it boots from the before-final 64KiB block during the initial installation of coreboot.<br />
<br />
* Source: [http://comments.gmane.org/gmane.linux.bios/69354 gmane.linux.bios Mailing List - LinuxBIOS on T60] - Peter Stuge's Method of installing Coreboot on the X60.<br />
<br />
== Install Coreboot (First Flash) ==<br />
<br />
First, install Coreboot alongside the vendor BIOS.<br />
<br />
As before, you will be using the patched version of flashrom distributed in libreboot. The binary releases of libreboot come with both bucts and flashrom already compiled (you can also build them from source, if you like). You can also get bucts and flashrom from upstream (optional):<br />
* http://git.stuge.se/?p=bucts.git<br />
* http://flashrom.org/<br />
<br />
The libreboot project also distributes ROM images already compiled for the X60/T60, if you prefer (for T60, please avoid these if you have either a 1024x768 screen and/or ATI graphics):<br />
<br />
# Run {{ic|su}} to become root.<br />
# You '''must''' run bucts, flipping the register so that the value is high (1) (as explained before):<br />
# Run {{ic|./bucts/i686/bucts 1}} <br />
## It should have said '''Updated BUC.TS=1''' for the above command. If not, please do NOT continue; get help.<br />
# Flash Coreboot (run both of these commands, whichever works first):<br />
#: {{ic|sudo ./flashrom_lenovobios_sst -p internal -w coreboot.rom}} <br />
#: {{ic|sudo ./flashrom_lenovobios_macronix -p internal -w coreboot.rom}} <br />
#* This will take a while, and will spit out a few errors (since the upper 64KiB region of the flash is write-protected). <br />
# Check to make sure that the errors match the following (example):<br />
<br />
{{bc| Reading old flash chip contents... done.<br />
Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_block_erase_52 failed during command execution at address 0x0<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
Transaction error!<br />
spi_block_erase_d8 failed during command execution at address 0x1f0000<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_60 failed during command execution<br />
Reading current flash chip contents... done. Looking for another erase function.<br />
spi_chip_erase_c7 failed during command execution<br />
Looking for another erase function.<br />
No usable erase functions left.<br />
FAILED!<br />
Uh oh. Erase/write failed. Checking if anything has changed.<br />
Reading current flash chip contents... done.<br />
Apparently at least some data has changed.<br />
Your flash chip is in an unknown state.}}<br />
<br />
# If the errors are like that then, contrary to the error output, the image was flashed successfully.<br />
#* If they don't match, '''DO NOT TURN OFF YOUR LAPTOP'''; get help instead.<br />
# Shut down the laptop (fully shut it down, as in, turn it off), and then boot it again in a few seconds. Your laptop will boot into Coreboot.<br />
<br />
{{Note|If you're using an Intel GPU, SeaBIOS will not display anything without a proprietary VGABIOS blob, or without the free SeaVGABIOS ("coreboot linear framebuffer" in menuconfig) option ROM in SeaBIOS, but GNU/Linux should work fine in any case.}}<br />
<br />
* Sources: [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] - [http://thread.gmane.org/gmane.linux.bios/69354 Mailing List Thread 1] - [http://thread.gmane.org/gmane.linux.bios.flashrom/575 Mailing List Thread 2]<br />
<br />
== Install Coreboot (Second Flash) ==<br />
<br />
Next, flash Coreboot a second time to overwrite the vendor BIOS.<br />
<br />
# Run {{ic|su}} to become root.<br />
# Enter the {{ic|flashrom}} directory.<br />
# Run {{ic|./flashrom -p internal -w coreboot.rom}} <br />
#: This will successfully overwrite the entire flash chip with no errors, including the last 64k that were write protected with the factory BIOS.<br />
#: If it complains about 3 different flashchips (in the case of macronix chip), do this instead:<br />
#: Run {{ic|./flashrom -p internal -w coreboot.rom -c "MX25L1605D/MX25L1608D/MX25L1673E"}} <br />
# Run {{ic|bucts 0}} <br />
# Reboot the laptop. Coreboot has been successfully installed.<br />
<br />
== Recovery with a Hardware Firmware Flasher ==<br />
<br />
If you had a bad flash you will need to use a hardware flasher to reflash the BIOS.<br />
<br />
If you want something that's easy to follow, the libreboot project shows how to flash externally using a BeagleBone Black<br />
* [http://libreboot.org/docs/install/x60_unbrick.html Unbricking the X60]<br />
* [http://libreboot.org/docs/install/x60tablet_unbrick.html Unbricking the X60 Tablet]<br />
* [http://libreboot.org/docs/install/t60_unbrick.html Unbricking the T60]<br />
* [http://libreboot.org/docs/install/bbb_setup.html How to flash using the BBB]<br />
<br />
=== Howto (old) ===<br />
<br />
0. wire the pomona clip to a programmer that way:<br />
<br />
From the #coreboot IRC Channel on FreeNode servers:<br />
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins<br />
[...]<br />
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6<br />
[...]<br />
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip<br />
[...]<br />
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected<br />
[...]<br />
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break<br />
[...]<br />
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside<br />
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside<br />
[...]<br />
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens<br />
[...]<br />
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer<br />
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip<br />
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...<br />
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...<br />
# connect the pomona clip to the flash chip<br />
# flash coreboot or the BIOS<br />
# remount the laptop<br />
<br />
See also [http://flashrom.org/ISP In-System Programming]<br />
<br />
== Coreboot standard configuration ==<br />
* It's now the default that when running SeaBios, that it (instead of coreboot) runs the VGA option rom.<br />
See [[VGA_support]] for details on how to include the VGA BIOS image.<br />
<br />
== VBIOS replacement (native graphics) ==<br />
The VGA option ROM (see above) is proprietary. Under devices in menuconfig, disable loading option ROM,s and enable 'Native graphics initialization'. '''Use the GRUB payload'''.<br />
<br />
TODO: add notes here for how to patch coreboot for T60 native graphics (it's in libreboot already, or on 5345 on coreboot gerrit).<br />
<br />
== Recently tested revisions on the X60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/x60;hb=HEAD the most recent board-status submissions]<br />
<br />
[[Supported_Motherboards#2014W08 | 970ad7076388b3ef98988121170df86196d493b4 coreboot-4.0-5534-g970ad70 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 8496c4dbec41b3a9284fc29b0dcd97fc8946223b coreboot-4.0-5045-g9bf05de ]]<br />
<br />
== Recently tested revisions on the T60 ==<br />
<br />
See [http://review.coreboot.org/gitweb?p=board-status.git;a=tree;f=lenovo/t60;hb=HEAD the most recent board-status submisssions]<br />
<br />
[[Supported_Motherboards#2014W10 | a172ea546992c3f6f6a99b4dbaabbdae4c959707 4.0-5611-ga172ea5 ]]<br />
<br />
[[Supported_Motherboards#2013W50 | 9bf05de5ab2842fc83cea8da5e9058417fc4bc24 4.0-5045-g9bf05de ]]<br />
<br />
== Status ==<br />
* [[Board:lenovo/x60|Thinkpad X60 Status]]<br />
* [[Board:lenovo/t60|Thinkpad T60 Status]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=VGA_support&diff=16016VGA support2015-04-09T19:01:51Z<p>Fchmmr: /* RECOMMENDED: Extracting from your vendor bios image */</p>
<hr />
<div>== VGA initialization in coreboot ==<br />
<br />
Since coreboot v4 you can configure VGA initialization in Kconfig. For older versions of coreboot check the history of this page.<br />
<br />
First do:<br />
<br />
<source lang="bash"><br />
$ make menuconfig<br />
</source><br />
<br />
Then go<br />
Chipset ---><br />
[*] Setup bridges on path to VGA adapter <br />
[*] Run VGA option ROMs<br />
Option ROM execution type (Native mode) ---><br />
<br />
Alternatively you can choose the "Secure mode" to run the VGA option rom in a contained environment.<br />
<br />
If you have no on-board graphics, you are done configuring coreboot at this point. You may exit configuration, and run make to get your VGA enabled coreboot image.<br />
<br />
=== On-board Video Devices ===<br />
<br />
If you run coreboot on a system with on-board graphics, you have to embed a VGA on the top level, enter the file name of your option rom and the PCI ID of the associated graphics device in the form <vendor_id>,<device_id>:<br />
<br />
VGA BIOS ---><br />
[*] Add a VGA BIOS image<br />
(oprom-0.rom) VGA BIOS path and filename<br />
(8086,27a2) VGA device PCI IDs<br />
<br />
That's it, exit configuration, and run make to get your VGA enabled coreboot image.<br />
<br />
== How to retrieve a good video bios ==<br />
<br />
There are various ways to get hold of the video bios blob and not all work equally good for all boards (rather the opposite).<br />
<br />
The best way is to extract it from the vendor firmware.<br />
In the case of a traditional x86 BIOS this is rather easy and very reliable.<br />
On UEFI systems there does not seem to be a unified way of success but sometimes the steps below work.<br />
<br />
Another category is downloading the blobs directly.<br />
Some vendors offer them in graphics driver packages etc. and you might even find them on enthusiasts website dedicated to firmware modding etc.<br />
<br />
The most delicate ways are by dumping the blob from a running system.<br />
This might sound like the most reasonable way but the image present after boot might not be the same as it is (to be) stored in flash (e.g. if it is self modifying).<br />
However, in some cases this is the only way and then it is quite comfortable.<br />
<br />
=== RECOMMENDED: Extracting from your vendor bios image ===<br />
<br />
The recommended method is to take your mainboard vendor's BIOS image (if there is one) and extract the VGA BIOS using a tool called [[bios_extract]].<br />
<br />
$ git clone http://review.coreboot.org/p/bios_extract.git<br />
<br />
This is the most reliable way:<br />
* You are guaranteed to get an image that fits to your onboard VGA<br />
* Even if your VGA BIOS uses self-modifying code you get a correct image<br />
<br />
Decompress your rom image with:<br />
$ ./bios_extract hdmag217.rom<br />
<br />
If bios_decode fails with a message like<br />
Using file "hdmag217.rom" (513kB)<br />
Found Phoenix BIOS "Phoenix ServerBIOS 3 Release 6.0 "<br />
Version "DEVEL4E0", created on 03/20/06 at 14:37:39.<br />
Error: Invalid module signature at 0x80581<br />
<br />
then you have to cut the flash chip description off the image. In this case the BIOS image is 512KB, so you do<br />
$ dd if=hdmag217.rom of=hdma.rom bs=512k count=1<br />
1+0 records in<br />
1+0 records out<br />
524288 bytes transferred in 0.000883 secs (593688784 bytes/sec)<br />
<br />
<br />
You will get an output similar to this:<br />
<br />
Using file "hdma.rom" (512kB)<br />
Found Phoenix BIOS "Phoenix ServerBIOS 3 Release 6.0 "<br />
Version "DEVEL4E0", created on 03/20/06 at 14:37:39.<br />
0x715FC ( 27134 bytes) -> romexec_0.rom<br />
0x6E1CB ( 13338 bytes) -> strings_0.rom (29401 bytes)<br />
0x6D65D ( 2899 bytes) -> display_0.rom (4128 bytes)<br />
0x6B62E ( 8208 bytes) -> update_0.rom<br />
0x6B1E3 ( 1072 bytes) -> decompcode_0.rom [0x5000:0xB6D0]<br />
0x6564F ( 23421 bytes) -> oprom_0.rom (36864 bytes)<br />
0x65608 ( 44 bytes) -> tcpa_H_0.rom (32 bytes)<br />
0x65592 ( 91 bytes) -> acpi_1.rom (116 bytes)<br />
0x65519 ( 94 bytes) -> acpi_2.rom (244 bytes)<br />
0x654ED ( 13 bytes) -> tcpa_*_0.rom<br />
0x64D4F ( 1927 bytes) -> bioscode_0.rom (31382 bytes) [0xF000:0x856A]<br />
0x60020 ( 19728 bytes) -> romexec_1.rom<br />
0x570D9 ( 36656 bytes) -> oprom_1.rom (61440 bytes)<br />
0x4DB9D ( 38177 bytes) -> oprom_2.rom (63488 bytes)<br />
0x46493 ( 30447 bytes) -> oprom_3.rom (65536 bytes)<br />
0x41DAB ( 18125 bytes) -> logo_0.rom (310162 bytes)<br />
0x39CA5 ( 25439 bytes) -> oprom_4.rom (51200 bytes)<br />
0x36005 ( 15493 bytes) -> setup_0.rom (37682 bytes)<br />
0x325D7 ( 14867 bytes) -> template_0.rom (37728 bytes)<br />
0x2FA36 ( 11142 bytes) -> miser_0.rom (16208 bytes)<br />
0x2E63C ( 5087 bytes) -> tcpa_Q_0.rom (16096 bytes)<br />
0x2D7C3 ( 3678 bytes) -> acpi_0.rom (10464 bytes)<br />
0x1FA2A ( 41023 bytes) -> bioscode_1.rom (56080 bytes) [0xE000:0x40F0]<br />
0x14FE0 ( 43567 bytes) -> bioscode_2.rom (62416 bytes) [0x6000:0xCC30]<br />
0x0EB4C ( 25721 bytes) -> bioscode_3.rom (36976 bytes) [0x6000:0x3BC0]<br />
0x0D0A0 ( 6801 bytes) -> bioscode_4.rom (31856 bytes) [0x5000:0xBF50]<br />
<br />
Now you can check the option roms (oprom_?.rom) with the tool romheaders which is part of the [http://www.openfirmware.info/FCODE_suite FCode Suite] (in debian-based distros, you can get it by installing the '''fcode-utils''' package):<br />
<br />
$ romheaders oprom_0.rom <br />
<br />
Image 1:<br />
PCI Expansion ROM Header:<br />
Signature: 0x55aa (Ok)<br />
CPU unique data: 0x48 0xeb 0x7b 0x01 0x76 0x00 0x00 0x00<br />
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00<br />
Pointer to PCI Data Structure: 0x017c<br />
<br />
PCI Data Structure:<br />
Signature: 0x50434952 'PCIR' (Ok)<br />
Vendor ID: 0x1002<br />
Device ID: 0x4752<br />
Vital Product Data: 0x0000<br />
PCI Data Structure Length: 0x0018 (24 bytes)<br />
PCI Data Structure Revision: 0x00<br />
Class Code: 0x030000 (VGA Display controller)<br />
Image Length: 0x0048 blocks (36864 bytes)<br />
Revision Level of Code/Data: 0x0421<br />
Code Type: 0x00 (Intel x86)<br />
Last-Image Flag: 0x80 (last image in rom)<br />
Reserved: 0x0000<br />
<br />
Platform specific data for x86 compliant option rom:<br />
Initialization Size: 0x48 (36864 bytes)<br />
Entry point for INIT function: 0x80<br />
<br />
Congratulations, that's your option rom (compare PCI IDs and Class Code to find it among the option roms).<br />
<br />
=== UEFI Method ===<br />
<br />
UEFI's format is more structured than that of a traditional flat binary BIOS. In order to extract the VBIOS Option ROM you will need<br />
to parse out the UEFI Volumes and sub-Volumes out the UEFI filesystem using the [https://github.com/LongSoft/UEFITool UEFITool].<br />
<br />
* Look for the " CSMCORE " DXE Driver ? usually having the hash 'a062cf1f-8473-4aa3-8793-600bc4ffe9a8'? and extract the RAW Section to a file.<br />
* Search for text "VGA Compatible BIOS" '''uncheck unicode''' and "extract Body"<br />
* Search for text "PCIR" and '''uncheck unicode''' and "extract Body"<br />
<br />
=== Downloading ===<br />
<br />
There are sites that have video BIOS ROMs on their website (with all implications of retrieving a binary from an unknown source and executing it...).<br />
<br />
For Intel onboard graphics you can download the vbios (vga bios) from Intel's download section. The vbios is included with some versions of the graphics driver. The summary will say something like "NOTE:These materials are intended for use by developers.Includes VBIOS". The actual vbios file is the *.dat file included with the graphics driver.<br />
<br />
=== Retrieval via Linux kernel ===<br />
Some Linux drivers (e.g. <tt>radeon</tt> for AMD) make option ROMs like the video blob available to user space via sysfs.<br />
To use that to get the blob you need to enable it first.<br />
To that end you need to determine the path within <tt>/sys</tt> corresponding to your graphics chip.<br />
It looks like this: <tt>/sys/devices/pci<domain>:<bus>/<domain>:<bus>:<slot>.<function>/rom</tt>.<br />
<br />
You can get the respective information with <tt>lspci</tt>, for example:<br />
# lspci -tv<br />
-[0000:00]-+-00.0 Advanced Micro Devices, Inc. [AMD] Family 16h Processor Root Complex<br />
+-01.0 Advanced Micro Devices, Inc. [AMD/ATI] Kabini [Radeon HD 8210]<br />
...<br />
<br />
Here the the needed bits (for the ROM of the Kabini device) are:<br />
* PCI domain: (almost always) 0000<br />
* PCI bus: (also very commonly) 00<br />
* PCI slot: 01 (logical slot; different from any physical slots)<br />
* PCI function: 0 (a PCI device might have multiple functions... shouldn't matter here)<br />
<br />
To enable reading of the ROM you need to write 1 to the respective file, e.g.:<br />
<br />
echo 1 > /sys/devices/pci0000:00/0000:00:01.0/rom<br />
<br />
The same file should then contain the video blob and it should be possible to simply copy it, e.g.:<br />
<br />
cp /sys/devices/pci0000:00/0000:00:01.0/rom vgabios.bin<br />
<br />
<tt>romheaders</tt> should print reasonable output for this file.<br />
<br />
=== Extraction from mapped memory (if everything else fails) ===<br />
<br />
However you might be able to retrieve your on-board video BIOS with Linux as well.<br />
<br />
* Boot up a machine with a commercial BIOS (not coreboot) with the video card you wish to work under coreboot.<br />
* You can see where and how much your card's bios is using by doing a <br />
<source lang="bash">grep 'Video ROM' /proc/iomem</source><br />
* From the command line enter:<br /><source lang="bash">dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768</source> This assumes you card's BIOS is cached at 0xc0000, and is 64K long.<br />
<br /><source lang="bash">dd if=/dev/mem of=video.bios.bin.4 bs=65536 count=1 skip=12</source><br />
This works for many of the VIA Epia boards.<br><br />
Alternatively you can automatically generate it using this nice script from Peter Stuge:<br /><br />
<source lang="bash"><br />
cat /proc/iomem | grep 'Video ROM' | (read m; m=${m/ :*}; s=${m/-*}; e=${m/*-}; \<br />
dd if=/dev/mem of=vgabios.bin bs=1c skip=$[0x$s] count=$[$[0x$e]-$[0x$s]+1])<br />
</source><br />
* You (might) have a video BIOS image now. Check it at least with romheaders (as described above).<br />
<br />
== YABEL ==<br />
* Yabel can be used to trace the VGA option rom. <br />
* However its ability to prevent the option rom to do nasty things is limited: Often the GPU offers a way (e.g. trough an IO BAR) to access arbitrary locations in RAM, so limiting access of the GPU's PCI device to the option rom wouldn't contain it completely.<br />
<br />
See [[Coreboot Options]] for more information about the option.<br />
<br />
[[Category:Blobs]]</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/t60&diff=16015Board:lenovo/t602015-04-09T18:02:26Z<p>Fchmmr: /* Wifi chipsets */ <-- fix broken link.</p>
<hr />
<div>Coreboot supports all ThinkPad T60/T60p Series laptops.<br />
<br />
==Installation and Flashing==<br />
[[Board:lenovo/x60/Installation| Instructions on Installation and flashing the x60 or t60 ]]<br />
<br />
== Wifi chipsets ==<br />
<br />
Lenovo BIOS has a whitelist of approved PCI ID's for wifi cards. Coreboot does not, so you are free to use any wifi chipset of your choosing once coreboot is installed.<br />
<br />
The [http://libreboot.org/ Libreboot] distribution [http://libreboot.org/docs/hcl/index.html#recommended_wifi lists Wifi chipsets not needing proprietary software to work].<br />
<br />
== Status ==<br />
This table needs review. I copied the x60 table and ran through it from memory, expresscard comes to mind...<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_virt_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = OK<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_VGA_status = OK<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Intel 82573L<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = Untested<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_PCMCIA_status = OK<br />
|Onboard_PCMCIA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|Onboard_CF_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM1_comments = located in docking station<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = N/A<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Watchdog_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = OK<br />
|LEDs_comments = LEDs are controlled by Embedded Controller (EC). Working without special support.<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|Flashrom_status = OK<br />
|Flashrom_comments = See [[Board:lenovo/x60/Installation]]<br />
}}<br />
<br />
<br />
== proprietary components status ==<br />
* CPU Microcode (optional?) - works fine without. See [http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf]<br />
* VGA option rom (optional): Native graphics initialization (free replacement) is also available with [http://review.coreboot.org/#/c/5345 this patch] that is under review. (libreboot merges this patch, along with patches enabling text-mode and backlight controls)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Building the ROM without proprietary blobs ==<br />
<br />
TODO: these instructions should still work, but they are outdated. Bring them up to date, using the latest coreboot revision.<br />
<br />
This basically means:<br />
* No microcode updates<br />
* Native graphics (replacement for the proprietary Video BIOS / VGA Option ROM)<br />
* GRUB2 payload<br />
<br />
In this configuration, only GNU/Linux is known to work. If you plan to use other operating systems, you might be out of luck.<br />
<br />
* Note, not all T60 lcd panels work with this configuration. (the code to enable native graphics on T60 is still under review), check [http://libreboot.org/docs/hcl/index.html#supported_t60_list compatibility list]<br />
* Note, if your LCD panel is unsupported, you can still use this configuration; you won't see any graphics on the screen, but an external monitor will work (using VGA output, or DVI if you have the docking station). For GRUB console, you can use serial output or EHCI debug. Recommended docking station: Advanced Mini Dock.<br />
* Note, replacing the LCD panel is relatively easy. The libreboot project has some guides in it's documentation, along with info about what LCD panels are known to work.<br />
* Note, this configuration only works for T60's with the Intel GMA950 video chipset. ATI GPU won't work, because they lack native graphics support.<br />
<br />
Download coreboot like usual:<br />
<pre><br />
git clone http://review.coreboot.org/coreboot<br />
cd coreboot<br />
</pre><br />
At the time of writing for (for these instructions), the following git revision was used:<br />
<pre><br />
git reset --hard 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e<br />
</pre><br />
Install all of the coreboot build dependencies listed at [http://www.coreboot.org/Build_HOWTO Build_HOWTO] and then build the crossgcc toolchain:<br />
<pre><br />
make crossgcc-i386<br />
</pre><br />
Apply the following patches in this order:<br />
<pre><br />
# Enable T60 native graphics<br />
git fetch http://review.coreboot.org/coreboot refs/changes/45/5345/9 && git cherry-pick FETCH_HEAD<br />
# Enable text-mode graphics for T60<br />
git fetch http://review.coreboot.org/coreboot refs/changes/50/7050/2 && git cherry-pick FETCH_HEAD<br />
<br />
# Permanently enable wlan/wwan/bluetooth/trackpoint/touchpad<br />
git fetch http://review.coreboot.org/coreboot refs/changes/58/7058/3 && git cherry-pick FETCH_HEAD<br />
<br />
# If you want legacy brightness controls (if using this, make sure not to include the ACPI brightness patch below)<br />
git fetch http://review.coreboot.org/coreboot refs/changes/51/7051/1 && git cherry-pick FETCH_HEAD<br />
<br />
# OR if you want ACPI brightness controls (if using this, make sure not to include the legacy brightness patch above):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/31/6731/7 && git cherry-pick FETCH_HEAD<br />
# Fix uneven backlight levels (for ACPI brightness controls):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/49/7049/1 && git cherry-pick FETCH_HEAD<br />
# Apply this patch to fix compilation:<br />
wget http://paste.debian.net/plain/125769<br />
git apply 125769<br />
rm -rf 125769<br />
<br />
# ACPI brightness patches above were abandoned due to Windows incompatibility. If you only want to use GNU/Linux, then it should work fine.<br />
</pre><br />
<br />
Now you will want this basic configuration for X60/X60s (in '''make menuconfig'''):<br />
<pre><br />
General setup / Expert mode = enable<br />
General setup / Local version string = 79ETE7WW (2.27 )<br />
Mainboard / Mainboard vendor = Lenovo<br />
Mainboard / Mainboard model = ThinkPad T60 / T60p<br />
Mainboard / ROM chip size = 2048 KB (2 MB)<br />
Mainboard / SMBIOS Serial Number = L3DKE06<br />
Mainboard / SMBIOS Version Number = ThinkPad T60<br />
Mainboard / SMBIOS Manufacturer = LENOVO<br />
Mainboard / SMBIOS Product name = 1951FEG<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates<br />
Devices / Use native graphics initialization = enable<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Console / Send console output to a CBMEM buffer = enable<br />
Payload / Add a payload = An ELF executable payload<br />
Payload / Payload path and filename = grub.elf<br />
<br />
Go back into Devices:<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
</pre><br />
<br />
<br />
SMBIOS values were taken by running '''dmidecode''' with the factory BIOS.<br />
<br />
Note, the above assumes that you already built your grub.elf from source along with everything that you need. Building GRUB is not covered here.<br />
<br />
Put your grub.elf in the coreboot directory and then run '''make'''. Alternatively, you could go back into menuconfig and select coreboot's own GRUB payload config, which will automatically download and build the GRUB payload. Building it yourself can be more flexible, though, since you get to choose what modules you want and you can use your own configs.<br />
<br />
== TODO ==<br />
=== Non-free components replacements ===<br />
* <s>Replace the non-free VGA option rom by making native graphics init work.</s> See [http://www.coreboot.org/Board:lenovo/t60#Make_backlight_.28Fn_keys.29_control_work_with_native_gpu_init] (under review on 5345 changeset, review.coreboot.org]<br />
* Create a Native graphics<->VGA option rom. '''SeaVGABIOS (part of SeaBIOS) might be the answer. INT 10H and VBT are missing in native graphics.'''<br />
* <s>Make backlight work without the non-free option rom.</s> See 6731 on review.coreboot.org<br />
=== Windows currently doesn't boot (STOP A5 error) ===<br />
<br />
Windows 7 was tested and fails to boot at the moment.<br />
<br />
The native graphics implementation lacks INT 10H and VBT, and GRUB cannot boot it. Booting with SeaBIOS+SeaVGABIOS results in graphical corruption (and no boot).<br />
<br />
Booting with SeaBIOS and the VGA ROM (vbios) can be used to boot it, but booting ends with the message outlined here: [http://paste.debian.net/plain/122557 STOP A5]<br />
<br />
More information can be found [http://www.coreboot.org/ACPI#STOP_0xa5 here]<br />
<br />
===high pitched noise from the board during low power states===<br />
<br />
During low power state (cstate 3), a high-pitched "humming" noise eminates from the board. Some discussion has been made about this; suggestions include "using an oscilliscope in clever ways" (to detect where the noise is coming from to debug the issue). There are some workarounds:<br />
<br />
Use "idle=halt" (higher power consumption) or "processor.max_cstate=2" (higher power consumption, but not as bad) kernel parameter in GRUB. These increase heat and power consumption.<br />
<br />
Another option (for increased battery life and lower temperatures) is to use '''powertop --auto-tune''', or set 'Tunables' in powertop (without any parameters).<br />
<br />
=== Other things ===<br />
* Add support for more batteries in ACPI.<br />
* Make the wifi card and/or the laptop produce less heat.<br />
* Finish and merge support for thinkpad_acpi linux kernel module<br />
* Sometimes some dock USB port aren't initialized => fix that</div>Fchmmrhttps://www.coreboot.org/index.php?title=Board:lenovo/t60&diff=16013Board:lenovo/t602015-04-09T18:01:35Z<p>Fchmmr: </p>
<hr />
<div>Coreboot supports all ThinkPad T60/T60p Series laptops.<br />
<br />
==Installation and Flashing==<br />
[[Board:lenovo/x60/Installation| Instructions on Installation and flashing the x60 or t60 ]]<br />
<br />
== Wifi chipsets ==<br />
<br />
Lenovo BIOS has a whitelist of approved PCI ID's for wifi cards. Coreboot does not, so you are free to use any wifi chipset of your choosing once coreboot is installed.<br />
<br />
The [http://libreboot.org/ Libreboot] distribution [http://libreboot.org/docs/index.html#recommended_wifi lists Wifi chipsets not needing proprietary software to work].<br />
<br />
== Status ==<br />
This table needs review. I copied the x60 table and ran through it from memory, expresscard comes to mind...<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_virt_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_multiple_status = N/A<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = OK<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = OK<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_VGA_status = OK<br />
|Onboard_ethernet_status = OK<br />
|Onboard_ethernet_comments = Intel 82573L<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = Untested<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_PCMCIA_status = OK<br />
|Onboard_PCMCIA_comments = <br />
|Onboard_SCSI_status = N/A<br />
|Onboard_CF_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = OK<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM1_comments = located in docking station<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = N/A<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Watchdog_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|Powersave_status = OK<br />
|ACPI_status = OK<br />
|SMBus_status = OK<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = OK<br />
|LEDs_status = OK<br />
|LEDs_comments = LEDs are controlled by Embedded Controller (EC). Working without special support.<br />
|HPET_status = OK<br />
|RNG_status = N/A<br />
|Flashrom_status = OK<br />
|Flashrom_comments = See [[Board:lenovo/x60/Installation]]<br />
}}<br />
<br />
<br />
== proprietary components status ==<br />
* CPU Microcode (optional?) - works fine without. See [http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf]<br />
* VGA option rom (optional): Native graphics initialization (free replacement) is also available with [http://review.coreboot.org/#/c/5345 this patch] that is under review. (libreboot merges this patch, along with patches enabling text-mode and backlight controls)<br />
* EC(Embedded Controller) => you do not have to touch it(just leave it where it is)<br />
<br />
== Building the ROM without proprietary blobs ==<br />
<br />
TODO: these instructions should still work, but they are outdated. Bring them up to date, using the latest coreboot revision.<br />
<br />
This basically means:<br />
* No microcode updates<br />
* Native graphics (replacement for the proprietary Video BIOS / VGA Option ROM)<br />
* GRUB2 payload<br />
<br />
In this configuration, only GNU/Linux is known to work. If you plan to use other operating systems, you might be out of luck.<br />
<br />
* Note, not all T60 lcd panels work with this configuration. (the code to enable native graphics on T60 is still under review), check [http://libreboot.org/docs/hcl/index.html#supported_t60_list compatibility list]<br />
* Note, if your LCD panel is unsupported, you can still use this configuration; you won't see any graphics on the screen, but an external monitor will work (using VGA output, or DVI if you have the docking station). For GRUB console, you can use serial output or EHCI debug. Recommended docking station: Advanced Mini Dock.<br />
* Note, replacing the LCD panel is relatively easy. The libreboot project has some guides in it's documentation, along with info about what LCD panels are known to work.<br />
* Note, this configuration only works for T60's with the Intel GMA950 video chipset. ATI GPU won't work, because they lack native graphics support.<br />
<br />
Download coreboot like usual:<br />
<pre><br />
git clone http://review.coreboot.org/coreboot<br />
cd coreboot<br />
</pre><br />
At the time of writing for (for these instructions), the following git revision was used:<br />
<pre><br />
git reset --hard 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e<br />
</pre><br />
Install all of the coreboot build dependencies listed at [http://www.coreboot.org/Build_HOWTO Build_HOWTO] and then build the crossgcc toolchain:<br />
<pre><br />
make crossgcc-i386<br />
</pre><br />
Apply the following patches in this order:<br />
<pre><br />
# Enable T60 native graphics<br />
git fetch http://review.coreboot.org/coreboot refs/changes/45/5345/9 && git cherry-pick FETCH_HEAD<br />
# Enable text-mode graphics for T60<br />
git fetch http://review.coreboot.org/coreboot refs/changes/50/7050/2 && git cherry-pick FETCH_HEAD<br />
<br />
# Permanently enable wlan/wwan/bluetooth/trackpoint/touchpad<br />
git fetch http://review.coreboot.org/coreboot refs/changes/58/7058/3 && git cherry-pick FETCH_HEAD<br />
<br />
# If you want legacy brightness controls (if using this, make sure not to include the ACPI brightness patch below)<br />
git fetch http://review.coreboot.org/coreboot refs/changes/51/7051/1 && git cherry-pick FETCH_HEAD<br />
<br />
# OR if you want ACPI brightness controls (if using this, make sure not to include the legacy brightness patch above):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/31/6731/7 && git cherry-pick FETCH_HEAD<br />
# Fix uneven backlight levels (for ACPI brightness controls):<br />
git fetch http://review.coreboot.org/coreboot refs/changes/49/7049/1 && git cherry-pick FETCH_HEAD<br />
# Apply this patch to fix compilation:<br />
wget http://paste.debian.net/plain/125769<br />
git apply 125769<br />
rm -rf 125769<br />
<br />
# ACPI brightness patches above were abandoned due to Windows incompatibility. If you only want to use GNU/Linux, then it should work fine.<br />
</pre><br />
<br />
Now you will want this basic configuration for X60/X60s (in '''make menuconfig'''):<br />
<pre><br />
General setup / Expert mode = enable<br />
General setup / Local version string = 79ETE7WW (2.27 )<br />
Mainboard / Mainboard vendor = Lenovo<br />
Mainboard / Mainboard model = ThinkPad T60 / T60p<br />
Mainboard / ROM chip size = 2048 KB (2 MB)<br />
Mainboard / SMBIOS Serial Number = L3DKE06<br />
Mainboard / SMBIOS Version Number = ThinkPad T60<br />
Mainboard / SMBIOS Manufacturer = LENOVO<br />
Mainboard / SMBIOS Product name = 1951FEG<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates<br />
Devices / Use native graphics initialization = enable<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Console / Send console output to a CBMEM buffer = enable<br />
Payload / Add a payload = An ELF executable payload<br />
Payload / Payload path and filename = grub.elf<br />
<br />
Go back into Devices:<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
</pre><br />
<br />
<br />
SMBIOS values were taken by running '''dmidecode''' with the factory BIOS.<br />
<br />
Note, the above assumes that you already built your grub.elf from source along with everything that you need. Building GRUB is not covered here.<br />
<br />
Put your grub.elf in the coreboot directory and then run '''make'''. Alternatively, you could go back into menuconfig and select coreboot's own GRUB payload config, which will automatically download and build the GRUB payload. Building it yourself can be more flexible, though, since you get to choose what modules you want and you can use your own configs.<br />
<br />
== TODO ==<br />
=== Non-free components replacements ===<br />
* <s>Replace the non-free VGA option rom by making native graphics init work.</s> See [http://www.coreboot.org/Board:lenovo/t60#Make_backlight_.28Fn_keys.29_control_work_with_native_gpu_init] (under review on 5345 changeset, review.coreboot.org]<br />
* Create a Native graphics<->VGA option rom. '''SeaVGABIOS (part of SeaBIOS) might be the answer. INT 10H and VBT are missing in native graphics.'''<br />
* <s>Make backlight work without the non-free option rom.</s> See 6731 on review.coreboot.org<br />
=== Windows currently doesn't boot (STOP A5 error) ===<br />
<br />
Windows 7 was tested and fails to boot at the moment.<br />
<br />
The native graphics implementation lacks INT 10H and VBT, and GRUB cannot boot it. Booting with SeaBIOS+SeaVGABIOS results in graphical corruption (and no boot).<br />
<br />
Booting with SeaBIOS and the VGA ROM (vbios) can be used to boot it, but booting ends with the message outlined here: [http://paste.debian.net/plain/122557 STOP A5]<br />
<br />
More information can be found [http://www.coreboot.org/ACPI#STOP_0xa5 here]<br />
<br />
===high pitched noise from the board during low power states===<br />
<br />
During low power state (cstate 3), a high-pitched "humming" noise eminates from the board. Some discussion has been made about this; suggestions include "using an oscilliscope in clever ways" (to detect where the noise is coming from to debug the issue). There are some workarounds:<br />
<br />
Use "idle=halt" (higher power consumption) or "processor.max_cstate=2" (higher power consumption, but not as bad) kernel parameter in GRUB. These increase heat and power consumption.<br />
<br />
Another option (for increased battery life and lower temperatures) is to use '''powertop --auto-tune''', or set 'Tunables' in powertop (without any parameters).<br />
<br />
=== Other things ===<br />
* Add support for more batteries in ACPI.<br />
* Make the wifi card and/or the laptop produce less heat.<br />
* Finish and merge support for thinkpad_acpi linux kernel module<br />
* Sometimes some dock USB port aren't initialized => fix that</div>Fchmmr