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2024-03-28T13:29:27Z
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https://www.coreboot.org/index.php?title=Nvidia_MCP55_Porting_Notes&diff=16629
Nvidia MCP55 Porting Notes
2015-07-14T12:51:31Z
<p>Jakllsch: /* Interrupt Routing Registers */</p>
<hr />
<div>== Interrupt Routing Registers ==<br />
Please note that this is valid for the [[Nvidia_CK804_Porting_Notes|CK804]] too.<br />
<br />
'''Values for routing IRQ's:'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Value<br />
! align="left" | APIC Pin (hex.)<br />
! align="left" | APIC Pin (dec.)<br />
|- bgcolor="#eeeeee"<br />
|0x01 || 0x17 || 23<br />
|- bgcolor="#dddddd"<br />
|0x02 || 0x16 || 22<br />
|- bgcolor="#eeeeee"<br />
|0x03 || 0x10 || 16<br />
|- bgcolor="#dddddd"<br />
|0x04 || 0x11 || 17<br />
|- bgcolor="#eeeeee"<br />
|0x05 || 0x05 || 5<br />
|- bgcolor="#dddddd"<br />
|0x06 || 0x12 || 18<br />
|- bgcolor="#eeeeee"<br />
|0x07 || 0x7 || 7<br />
|- bgcolor="#dddddd"<br />
|0x08 || 0x14 || 20<br />
|- bgcolor="#eeeeee"<br />
|0x09 || 0x09 || 9<br />
|- bgcolor="#dddddd"<br />
|0x0A || 0x0a || 10<br />
|- bgcolor="#eeeeee"<br />
|0x0B || 0x0b || 11<br />
|- bgcolor="#dddddd"<br />
|0x0C || 0x13 || 19<br />
|- bgcolor="#eeeeee"<br />
|0x0D || 0x15 || 21<br />
|- bgcolor="#dddddd"<br />
|0x0E || 0x0E || 14<br />
|- bgcolor="#eeeeee"<br />
|0x0F || 0x0F || 15<br />
|}<br />
<br />
== Registers on M57SLI ==<br />
Each line is 4 bits.<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | 0x7c<br />
! align="left" | 0x80<br />
! align="left" | 0x84<br />
|- bgcolor="#eeeeee"<br />
|INTA || SCII || INTG<br />
|- bgcolor="#dddddd"<br />
|INTB || TCOI || INTH<br />
|- bgcolor="#eeeeee"<br />
|INTC || INTF || INTJ<br />
|- bgcolor="#dddddd"<br />
|INTD || INTQ || INTK<br />
|- bgcolor="#eeeeee"<br />
|PCEA || INTU || INTL<br />
|- bgcolor="#dddddd"<br />
|PCEB || INTS || INTM<br />
|- bgcolor="#eeeeee"<br />
|PCEC || IS0P || INTN<br />
|- bgcolor="#dddddd"<br />
|PCED || ITID || ISA2<br />
|}<br />
<br />
== Wiring on M57SLI-S4 ==<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Device/Pin<br />
! align="left" | Routed to Pin<br />
! align="left" | Description<br />
|- bgcolor="#eeeeee"<br />
| 1/INTA || INTF || ISALPC<br />
|- bgcolor="#eeeeee"<br />
| 1/INTB || INTS || SMBus<br />
|- bgcolor="#dddddd"<br />
| 2/INTA || INTG || Usb0<br />
|- bgcolor="#dddddd"<br />
| 2/INTB || INTQ || Usb1<br />
|- bgcolor="#eeeeee"<br />
| 4/INTA || INTN || IDE<br />
|- bgcolor="#dddddd"<br />
| 5/INTA || ITID || Sata1<br />
|- bgcolor="#dddddd"<br />
| 5/INTB || IS0P || Sata2<br />
|- bgcolor="#dddddd"<br />
| 5/INTC || ISA2 || Sata3<br />
|- bgcolor="#eeeeee"<br />
| 6/INTA || INTU || Bridge to Bus 1<br />
|- bgcolor="#eeeeee"<br />
| 6/INTB || INTK || Audio<br />
|- bgcolor="#dddddd"<br />
| 8/INTA || INTJ || Ethernet<br />
|}<br />
Bridges to the PCI-E Slots & Devices<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Device/Pin<br />
! align="left" | Routed to Pin<br />
! align="left" | Description<br />
|- bgcolor="#eeeeee"<br />
| F/INTA || PCEB || Bridge to Bus 7 - PCIE 16x (black)<br />
|- bgcolor="#eeeeee"<br />
| F/INTB || PCEC ||<br />
|- bgcolor="#eeeeee"<br />
| F/INTC || PCED ||<br />
|- bgcolor="#eeeeee"<br />
| F/INTD || PCEA ||<br />
|- bgcolor="#dddddd"<br />
| E/INTA || PCEC || Bridge to Bus 6<br />
|- bgcolor="#dddddd"<br />
| E/INTB || PCED ||<br />
|- bgcolor="#dddddd"<br />
| E/INTC || PCEA ||<br />
|- bgcolor="#dddddd"<br />
| E/INTD || PCEB ||<br />
|- bgcolor="#eeeeee"<br />
| D/INTA || PCED || Bridge to Bus 5<br />
|- bgcolor="#eeeeee"<br />
| D/INTB || PCEA ||<br />
|- bgcolor="#eeeeee"<br />
| D/INTC || PCEB ||<br />
|- bgcolor="#eeeeee"<br />
| D/INTD || PCEC ||<br />
|- bgcolor="#dddddd"<br />
| C/INTA || PCEA || Bridge to Bus 4<br />
|- bgcolor="#dddddd"<br />
| C/INTB || PCEB ||<br />
|- bgcolor="#dddddd"<br />
| C/INTC || PCEC ||<br />
|- bgcolor="#dddddd"<br />
| C/INTD || PCED ||<br />
|- bgcolor="#eeeeee"<br />
| B/INTA || PCEB || Bridge to Bus 3<br />
|- bgcolor="#eeeeee"<br />
| B/INTB || PCEC ||<br />
|- bgcolor="#eeeeee"<br />
| B/INTC || PCED ||<br />
|- bgcolor="#eeeeee"<br />
| B/INTD || PCEA ||<br />
|- bgcolor="#dddddd"<br />
| A/INTA || PCEC || Bridge to Bus 2 - PCIE 16x (blue)<br />
|- bgcolor="#dddddd"<br />
| A/INTB || PCED ||<br />
|- bgcolor="#dddddd"<br />
| A/INTC || PCEA ||<br />
|- bgcolor="#dddddd"<br />
| A/INTD || PCEB ||<br />
|}<br />
<br />
Bus 1 behind bridge from device 6<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Device/Pin<br />
! align="left" | Routed to Pin<br />
! align="left" | Description<br />
|- bgcolor="#eeeeee"<br />
| 6/INTA || INTC ||<br />
|- bgcolor="#eeeeee"<br />
| 6/INTB || INTD ||<br />
|- bgcolor="#eeeeee"<br />
| 6/INTC || INTA ||<br />
|- bgcolor="#eeeeee"<br />
| 6/INTD || INTB ||<br />
|- bgcolor="#dddddd"<br />
| 7/INTA || INTD || PCI Slot 1<br />
|- bgcolor="#dddddd"<br />
| 7/INTB || INTA ||<br />
|- bgcolor="#dddddd"<br />
| 7/INTC || INTB ||<br />
|- bgcolor="#dddddd"<br />
| 7/INTD || INTC ||<br />
|- bgcolor="#eeeeee"<br />
| 8/INTA || INTA || PCI Slot 2<br />
|- bgcolor="#eeeeee"<br />
| 8/INTB || INTB ||<br />
|- bgcolor="#eeeeee"<br />
| 8/INTC || INTC ||<br />
|- bgcolor="#eeeeee"<br />
| 8/INTD || INTD ||<br />
|- bgcolor="#dddddd"<br />
| 9/INTA || INTB ||<br />
|- bgcolor="#dddddd"<br />
| 9/INTB || INTC ||<br />
|- bgcolor="#dddddd"<br />
| 9/INTC || INTD ||<br />
|- bgcolor="#dddddd"<br />
| 9/INTD || INTA ||<br />
|- bgcolor="#eeeeee"<br />
| A/INTA || INTC ||<br />
|- bgcolor="#eeeeee"<br />
| A/INTB || INTD ||<br />
|- bgcolor="#eeeeee"<br />
| A/INTC || INTA ||<br />
|- bgcolor="#eeeeee"<br />
| A/INTD || INTB ||<br />
|}<br />
== Example Code for MPtable == <br />
This source is to do a propper mptable setup on M57SLI.<br />
<br />
'''Setup the registers 0x7c-0x84 with the IRQ Values you want to have:'''<br />
/*I/O APICs: APIC ID Version State Address*/<br />
{<br />
device_t dev;<br />
struct resource *res;<br />
uint32_t dword;<br />
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));<br />
if (dev) {<br />
res = find_resource(dev, PCI_BASE_ADDRESS_1);<br />
if (res) {<br />
smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);<br />
}<br />
dword = 0xc643c643;<br />
pci_write_config32(dev, 0x7c, dword);<br />
dword = 0x8da01009;<br />
pci_write_config32(dev, 0x80, dword);<br />
dword = 0x200018d2;<br />
pci_write_config32(dev, 0x84, dword);<br />
}<br />
}<br />
'''According to the Registers 0x7c-0x84 do the IRQ setup:'''<br />
#define PCI_INT(bus, dev, fn, pin) \<br />
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\<br />
bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))<br />
<br />
PCI_INT(0,sbdn+1,1, 10); /* SMBus */<br />
PCI_INT(0,sbdn+2,0, 22); /* USB */<br />
PCI_INT(0,sbdn+2,1, 23); /* USB */<br />
PCI_INT(0,sbdn+4,0, 21); /* IDE */<br />
PCI_INT(0,sbdn+5,0, 20); /* SATA */<br />
PCI_INT(0,sbdn+5,1, 21); /* SATA */<br />
PCI_INT(0,sbdn+5,2, 22); /* SATA */<br />
PCI_INT(0,sbdn+6,1, 23); /* HD Audio */<br />
PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */<br />
PCI_INT(1,0x0a,0, 18); /* Firewire */<br />
<br />
/* The PCIe slots, each on its own bus */<br />
k = 1;<br />
for(i=0; i<=3; i++){<br />
for(j=7; j>=2; j--){<br />
if(k>3) k=0;<br />
PCI_INT(j,0,i, 16+k);<br />
k++;<br />
}<br />
k--;<br />
}<br />
<br />
/* On bus 1: the PCI bus slots... */<br />
k=2;<br />
for(i=0; i<=3; i++){<br />
for(j=6; j<=10; j++){<br />
if(k>3) k=0;<br />
PCI_INT(1,j,i, 16+k);<br />
k++;<br />
}<br />
}<br />
<br />
== Example ACPI static IRQ routing ==<br />
For this the registers 0x7c-0x84 need to be set so that this static routing will work.<br />
/* PCI Routing Table */<br />
Name (_PRT, Package () {<br />
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0A }, /* 0x1 - 00:01.1 - IRQ 10 - SMBus */<br />
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x16 }, /* 0x2 - 00:02.0 - IRQ 22 - USB */<br />
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x17 }, /* 0x2 - 00:01.1 - IRQ 23 - USB */<br />
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x15 }, /* 0x4 - 00:04.0 - IRQ 21 - IDE */<br />
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 }, /* 0x5 - 00:05.0 - IRQ 20 - SATA */<br />
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x15 }, /* 0x5 - 00:05.1 - IRQ 21 - SATA */<br />
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, /* 0x5 - 00:05.2 - IRQ 22 - SATA */<br />
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x17 }, /* 0x6 - 00:06.1 - IRQ 23 - HD Audio */<br />
Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, /* 0x8 - 00:08.0 - IRQ 20 - GBit Ethernet */<br />
})<br />
<br />
Device (PEBA) /* PCI-E Bridge A */<br />
{<br />
Name (_ADR, 0x000A0000)<br />
Name (_UID, 0x00)<br />
Name (_BBN, 0x02)<br />
Name (_Prt, Package () {<br />
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },<br />
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },<br />
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },<br />
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },<br />
})<br />
}<br />
<br />
Bridge B-F needs also to get a routing setting, but not listed here.<br />
Device (PCID) /* PCI Device */<br />
{<br />
Name (_ADR, 0x00060000)<br />
Name (_UID, 0x00)<br />
Name (_BBN, 0x01)<br />
Name (_PRT, Package () {<br />
Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 },<br />
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x13 },<br />
Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 },<br />
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x11 },<br />
Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x13 },<br />
Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x10 },<br />
Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x11 },<br />
Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x12 },<br />
Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x10 },<br />
Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x11 },<br />
Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x12 },<br />
Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x13 },<br />
Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x11 },<br />
Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x12 },<br />
Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x13 },<br />
Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x10 },<br />
Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x12 }, /* FireWire */<br />
Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x13 },<br />
Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x10 },<br />
Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x11 },<br />
})<br />
}<br />
== Thanks ... ==<br />
... go to Rudolf Marek who figured the informations out from the M57SLI's vendor dsdt.asl, and while he was doing this on a train his wallet was stolen.<br />
So please keep that informations careful, it's valuable. :)</div>
Jakllsch
https://www.coreboot.org/index.php?title=Board:sunw/ultra40m2&diff=16589
Board:sunw/ultra40m2
2015-07-01T16:18:07Z
<p>Jakllsch: dual core works</p>
<hr />
<div>This page describes the [http://docs.oracle.com/cd/E19127-01/ultra40m2.ws/819-7565-16/index.html Sun Ultra 40 M2]. <br />
<br />
It is maintained by [[User:jakllsch|jakllsch]] and [[User:Cseait|seait]].<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = WIP<br />
|CPU_comments = Dual-core K8 CPUs only running at 1Ghz. Possible issue booting Linux when setting FID/VID.<br />
|CPU_L1_status = Untested<br />
|CPU_L2_status = Untested<br />
|CPU_L3_status = Untested<br />
|CPU_multiple_status = OK<br />
|CPU_multicore_status = OK<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = WIP<br />
|RAM_DDR2_comments = Possible issues addressing memory above 4GB. ECC needs tested.<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = OK<br />
|RAM_dualchannel_comments = Seems to be working.<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = Untested<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = SATA on MCP55b (IO-55) unknown - needs tested.<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = Untested<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = No<br />
|Onboard_firewire_comments = Firewire is on stuck PCI Bus (00:06.0)<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = No<br />
|PCI_cards_comments = 00:06.0 stuck PCI Bus. Firewire and PCI slot affected.<br />
|AGP_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x16_comments = Slot on board with label "PCIE3" tested with video card - works. Others need tested but probably working.<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM1_comments = Using LCP47B397 superio code. superio/smscsuperio possibly broken.<br />
|COM2_status = N/A<br />
|PP_status = N/A<br />
|PP_comments = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = Unknown<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = WIP<br />
|Sensors_comments = jakllsch has figured some of this out and put in place a short term solution for managing fan speed. More work needed.<br />
|Watchdog_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = Untested<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = No ACPI implementation yet.<br />
|Reboot_status = Untested<br />
|Poweroff_status = No<br />
|LEDs_status = Untested<br />
|HPET_status = No<br />
|HPET_comments = Present but not enabled.<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Board Information ==<br />
<br />
'''CPU:''' Dual Socket F with ''Node 1'' connected to ''HT Link 0'' on ''Node 0''<br />
<br />
'''Chipset:''' Two southbridges - nForce Pro 3600 (MCP55) connected to ''HT Link 1'' on ''Node 0'' and nForce Pro 3050 (IO-55) connected to ''HT Link 2'' on ''Node 0''.<br />
<br />
'''SuperIO:''' SMSC DME1737<br />
<br />
'''Fan Controller:''' Chassis and Memory are on the DME1737 HW monitor (accessible via i2c.)<br />
<br />
'''CPU Fan Controller:''' SMSC EMC6D103 (LM85 Linux driver)<br />
<br />
== Supported CPUs ==<br />
<br />
Currently supports Socket F dual-core processors (K8.) Planned support for Fam10.<br />
<br />
{{GPL}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=Board:asrock/e350m1&diff=11210
Board:asrock/e350m1
2012-09-23T15:09:39Z
<p>Jakllsch: remove references to inappropriate content</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = <br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = OK<br />
|CPU_multicore_comments = Both cores seem to be detected.<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = OK<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
|RAM_ecc_comments = <br />
<br />
|Onboard_SCSI_status = N/A<br />
|IDE_status = N/A<br />
|IDE_comments = <br />
|IDE_25_status = N/A<br />
|IDE_CF_status = Untested<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|USB_comments = <br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = You must add a VGA BIOS image. Use the nomodeset kernel command line option if you get garbled output immediately after starting the Linux kernel.<br />
|Onboard_ethernet_status = WIP<br />
|Onboard_ethernet_comments = After reset the ethernet adapter might not be initialized properly, so OS won't be able to detect it. Unplugging power supply for a few seconds appears to get it back to life.<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|PCIE_x1_status = Untested<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = ?<br />
|PCIE_x16_comments = <br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = Untested<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|PP_comments =<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = ?<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments = The CPU temperature seems to be displayed properly by lm-sensors.<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = OK<br />
|CPUfreq_comments = The ondemand governor works by default.<br />
|Powersave_status = OK<br />
|Powersave_comments = By default the CPU fan rotates at maximum speed. See the fancontrol attachment below on how to get it adjust automatically depending on CPU temperature.<br />
|ACPI_status = ?<br />
|ACPI_comments = <br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Suspend_status = NO<br />
|Suspend_comments = The machine suspends but it fails to resume from suspend.<br />
|LEDs_status = N/A<br />
|HPET_status = Unknown<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
Dumps of information gathered by various commands while running the proprietary BIOS are available here: [[File:ASRock_E350M1_info_dump.tar.bz2]]<br />
<br />
Fancontrol configuration file for adjusting the CPU fan speed dynamically: [[File:Fancontrol.gz]]</div>
Jakllsch
https://www.coreboot.org/index.php?title=Board:msi/ms7135&diff=10916
Board:msi/ms7135
2011-11-06T16:18:38Z
<p>Jakllsch: use class="wikitable"</p>
<hr />
<div></div>
Jakllsch
https://www.coreboot.org/index.php?title=Superiotool&diff=10884
Superiotool
2011-08-01T14:14:48Z
<p>Jakllsch: /* Installation */ note that superiotool is now in the coreboot git repo</p>
<hr />
<div>'''Superiotool''' is a GPL'd user-space helper tool for coreboot development purposes (but may also be useful for other things). It allows you to detect which [[wikipedia:Super I/O|Super I/O]] you have on your mainboard, and it can provide detailed information about the register contents of the Super I/O.<br />
<br />
This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.<br />
<br />
<gallery><br />
Image:Ite it8705f.jpg|<small>ITE IT8705F</small><br />
Image:Winbond w83977ef.jpg|<small>Winbond W83977EF</small><br />
</gallery><br />
<br />
== Support of various devices ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M1535/M1535D/M1535+/M1535D+<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/048024.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5105<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5107<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5109<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5113<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5119<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M512x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513x<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513xB<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513xF<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M514x<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-September/024916.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-July/050471.html 2], [http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html 3]<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71862FG / F71863FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71889<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71872F/FG / F71806F/FG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71882FG/F71883FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040016.html 1], [http://www.flashrom.org/pipermail/flashrom/2010-August/004390.html 2]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-November/026831.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F8000<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C711<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C712<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C721<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C735<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8228E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8502E/F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8510E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8511E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8512E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8661F/IT8770F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://article.gmane.org/gmane.linux.bios/42100/ 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F/IT8687R<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2010-May/058010.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT86793<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8702F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8703F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8705F/AF / IT8700F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026913.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8706R<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8708F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024879.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8710F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8711F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 2]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024884.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8720F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8721F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8722F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8726F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8761E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8780F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| HMC<br />
| HMC83755<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Holtek<br />
| HT6552IR<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS307<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS308<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS309<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS317<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS338<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS351<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97307<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/047843.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87309<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87360<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026991.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87351<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87364<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87365<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87363<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87366<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87382<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8739x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/043447.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87591x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8741x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87372<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8374L<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071014/19fe07aa/attachment-0001.htm 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87427<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87373<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| WPCE775x / NPCE781x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| WPCM450<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| NCT6776F (B)<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| NCT6776F (C)<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xFR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N971<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-July/003832.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N972<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N252<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-June/050276.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M172<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xAPM<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C67x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B80x/FDC37M707<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N958FR<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027036.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B77x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B78x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M602<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M60x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B72x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M81x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B27x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027245.html 1]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027248.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B37x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47U33x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B34x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S42x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M10x/112/13x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025451.html 1] <br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B357<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M14x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M15x/192/997<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-December/028269.html 1]<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-February/030897.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S45x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M292<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B387<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B397<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M182<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M584<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| MEC1308<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| DME1737<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5504<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N217<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5514D-NS<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3112<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3114<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3116<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5317<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5027<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH4307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669FR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N237<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N769<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024883.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N3869/FDC37N869<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N227<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025846.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SIO10N268<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C665GT/IR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C666GT<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SIS6801<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SIS950<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686A/VT82C686B<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977CTF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977EF/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040507.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83527HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627SF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697HF/F/HG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-August/004443.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83L517D/D-F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83637HF/HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627THF/THG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment.txt 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025599.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-August/037685.html 3], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 4]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment-0001.txt 1]<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627DHG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-January/029517.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627DHG-P/-PT<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627UHG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83667HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977F-A/G-A/AF-A/AG-A<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977AF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977TF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627HF/F/HG/G<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025453.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025592.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697SF/UF/UG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025914.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627EHF/EF/EHG/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024887.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025284.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-January/029416.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877AF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-February/002119.html]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877TF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| WPCD376I<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-October/053894.html 1]<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM82C862<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8663BF<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8669<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8670<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|}<br />
<br />
|}<br />
<br />
'''Extended dumps (EC, HWM) available for:'''<br />
<br />
Use the '''--extra-dump''' option to see the contents of these registers.<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 1]<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond<br />
| W83627THF/THG HWM<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMSC<br />
| LPC47N227 runtime register block<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
<br />
<small><br />
<sup>1</sup> Previosly National Semiconductor, now bought by Winbond.<br /><br />
<sup>2</sup> Register dump output from a running coreboot system (vs. proprietary BIOS).<br /><br />
</small><br />
<br />
== Installation ==<br />
<br />
'''Manual installation'''<br />
<br />
$ git clone http://review.coreboot.org/p/coreboot<br />
$ cd coreboot/util/superiotool<br />
$ make<br />
$ sudo make install<br />
<br />
'''Debian / Ubuntu'''<br />
<br />
$ apt-get install superiotool<br />
<br />
'''Fedora'''<br />
<br />
$ yum install superiotool<br />
<br />
== Usage ==<br />
<br />
Probe/detect the Super I/O in your mainboard:<br />
<br />
$ superiotool<br />
<br />
Register dump as table of hex-values (if the Super I/O is detected):<br />
<br />
$ superiotool -d<br />
<br />
Please see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool/README README] for further information.<br />
<br />
{{GPL}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=SeaBIOS&diff=10573
SeaBIOS
2011-02-18T19:33:32Z
<p>Jakllsch: Update git:// URL of SeaBIOS per http://www.seabios.org/pipermail/seabios/2011-February/001533.html. (Is gitweb moving too?)</p>
<hr />
<div>[http://www.seabios.org '''SeaBIOS'''] is an open-source legacy BIOS implementation which can be used as a coreboot [[Payloads|payload]]. It implements the standard BIOS calling interfaces that a typical x86 proprietary BIOS implements.<br />
<br />
This page describes using SeaBIOS with coreboot. SeaBIOS can also run natively in [[QEMU]] and bochs &mdash; see the [http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=README;hb=HEAD SeaBIOS README] file for information on non-coreboot uses.<br />
<br />
= Use cases =<br />
<br />
Any software requiring 16-bit BIOS services benefits from SeaBIOS (eg, Windows and DOS). SeaBIOS also enables booting Linux out of the box (using standard boot-loaders like GRUB and Syslinux).<br />
<br />
SeaBIOS supports booting from ATA hard drives, ATAPI CDROMs, USB hard drives, USB CDROMs, payloads in flash, and from [http://en.wikipedia.org/wiki/Option_ROM Option ROMs] (eg, SCSI or network cards). SeaBIOS can initialize and use a PS/2 keyboard or USB keyboard.<br />
<br />
== Windows ==<br />
<br />
SeaBIOS has been tested with Windows XP, Windows Vista (64/32 bit), and Windows 7 Beta (64 bit).<br />
<br />
However, Windows has a very strict ACPI interpreter, and many coreboot boards do not have a complete [[ACPI in coreboot|ACPI definition]]. As a result, many coreboot boards will fail during Windows boot (eg, it may fail with a '''STOP 0xA5''' code).<br />
<br />
So far [[ASUS M2V-MX SE]] and [[GIGABYTE GA-M57SLI-S4]] have known good working ACPI and are able to boot XP/Vista/Windows 7. Please ask on the [[Mailinglist|mailing list]] for the status of other boards/chipsets.<br />
<br />
== Linux ==<br />
<br />
SeaBIOS has been tested with GRUB, LILO, and Syslinux. Linux booting works well.<br />
<br />
== Other ==<br />
<br />
SeaBIOS has also been tested with FreeDOS, NetBSD, and OpenBSD.<br />
<br />
Because SeaBIOS implements the standard x86 BIOS interfaces, it is expected many other operating systems and boot-loaders will work.<br />
<br />
= Building =<br />
<br />
== Building via coreboot's menuconfig ==<br />
<br />
Probably the easiest way to use SeaBIOS as coreboot payload is to simply use the coreboot build process, which downloads and builds SeaBIOS as payload by default nowadays. You just have to run the following in your coreboot checkout:<br />
<br />
<source lang="bash"><br />
$ make menuconfig<br />
$ make<br />
</source><br />
<br />
Both SeaBIOS and coreboot will be built, and SeaBIOS will be added as payload to the '''coreboot.rom''' image that is being built.<br />
<br />
== Manual build ==<br />
<br />
One can download the latest version of SeaBIOS through a git repository:<br />
<br />
<source lang="bash"><br />
$ git clone git://git.seabios.org/seabios.git seabios<br />
$ cd seabios<br />
</source><br />
<br />
There's also a [http://git.linuxtogo.org/?p=kevin/seabios.git;a=summary gitweb] facility to browse the latest source code online.<br />
<br />
Edit '''src/config.h''' and set the following values:<br />
<br />
<source lang="C"><br />
#define CONFIG_COREBOOT 1<br />
#define CONFIG_DEBUG_SERIAL 1<br />
#define CONFIG_VGAHOOKS 1<br />
</source><br />
<br />
Then:<br />
<br />
<source lang="bash"><br />
$ make<br />
</source><br />
<br />
The final SeaBIOS payload file is '''out/bios.bin.elf'''.<br />
<br />
=== Compiled SeaBIOS images ===<br />
<br />
It is also possible to download a compiled SeaBIOS image. The latest released version compiled for coreboot is: http://www.linuxtogo.org/~kevin/SeaBIOS/bios.bin.elf-0.6.1<br />
<br />
Other versions are also available at: http://www.linuxtogo.org/~kevin/SeaBIOS/<br />
<br />
== coreboot ==<br />
<br />
For best results, configure coreboot with CONFIG_WRITE_HIGH_TABLES and CONFIG_VGA_BRIDGE_SETUP both enabled, and CONFIG_VGA_ROM_RUN and CONFIG_PCI_ROM_RUN both disabled.<br />
<br />
Finally, configure the SeaBIOS '''out/bios.bin.elf''' file as the coreboot payload and build coreboot. The resulting '''coreboot.rom''' file will contain both SeaBIOS and coreboot, and it can be flashed to a ROM chip.<br />
<br />
= SeaBIOS and CBFS =<br />
<br />
SeaBIOS can read the coreboot flash filesystem and extract files.<br />
<br />
When SeaBIOS scans the target machine's PCI devices, it will recognize option ROMs in CBFS that have the form '''pciVVVV,DDDD.rom'''. It will also run any file in the directory '''vgaroms/''' as a VGA option ROM not specific to a device and files in '''genroms/''' as a generic option ROM not specific to a device. In the above cases, SeaBIOS will recognize files with a '''.lzma''' suffix, and automatically decompress them (eg, '''pci1106,3344.rom.lzma''' and '''vgaroms/sgabios.bin.lzma''').<br />
<br />
SeaBIOS can also load a graphical bootsplash image from '''bootsplash.jpg''', payloads found in the CBFS directory '''img/''', and floppy images found in the '''floppyimg/''' directory.<br />
<br />
Further, SeaBIOS can obtain configuration information from CBFS. A file '''bootorder''' determines the order of devices and methods to attempt to boot the system from.<br />
<br />
The examples below show some common uses of these features.<br />
<br />
== Adding a VGA option ROM ==<br />
<br />
It is frequently necessary to add a VGA option ROM to CBFS in order to use a VGA adapter that is built-in to a motherboard. Note, VGA adapters on external cards (PCI, AGP, PCIe) do not require this step as SeaBIOS will automatically extract the VGA BIOS directly from the card. For machines without a VGA adapter, please follow the [[#Adding sgabios support|sgabios instructions]] below.<br />
<br />
The first step is to find the vendor and device ID of the built-in VGA adapter. This information can be found from '''lspci''':<br />
<br />
<source lang="bash"><br />
$ lspci -vnn<br />
...<br />
01:00.0 VGA compatible controller [0300]: VIA Technologies, Inc. UniChrome Pro IGP ['''1106:3344'''] (rev 01) (prog-if 00 [VGA controller])<br />
</source><br />
<br />
In the above example, the VGA vendor/device ID is '''1106:3344'''. [[VGA support#How_to_retrieve_a_good_video_bios|Obtain the VGA ROM]] (eg, '''vgabios.bin''') and add it to the ROM with:<br />
<br />
<source lang="bash"><br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add /path/to/vgabios.bin pci1106,3344.rom raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
Alternatively, SeaBIOS supports LZMA compressed option ROMs. Use the following to add a compressed option ROM instead:<br />
<br />
<source lang="bash"><br />
$ lzma -zc /path/to/vgabios.bin > vgabios.bin.lzma<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add vgabios.bin.lzma pci1106,3344.rom.lzma raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
After the above is done, one can write the '''coreboot.rom''' file to flash. SeaBIOS will extract the VGA ROM and run it during boot.<br />
<br />
== Adding gpxe support ==<br />
<br />
A [[GPXE|gpxe]] option ROM can nicely complement SeaBIOS and coreboot by adding network boot support. Adding gpxe is similar to [[#Adding a VGA option ROM]]. The first step is to find the Ethernet vendor/device ID. For example:<br />
<br />
<source lang="bash"><br />
$ lspci -vnn<br />
...<br />
00:09.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8110SC/8169SC Gigabit Ethernet ['''10ec:8167'''] (rev 10)<br />
</source><br />
<br />
Then one can build a gpxe option ROM. For example:<br />
<br />
<source lang="bash"><br />
$ cd /path/to/gpxe/src/<br />
$ make bin/10ec8167.rom<br />
</source><br />
<br />
And add it to the coreboot image. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add /path/to/gpxe/src/bin/10ec8167.rom pci10ec,8167.rom raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
As with VGA option ROMs, the gpxe option ROM may be compressed with LZMA. However, compression won't significantly reduce gpxe's size as it implements its own compression.<br />
<br />
In addition to gpxe, other option ROMs can be added in the same manner.<br />
<br />
== Adding sgabios support ==<br />
<br />
An [http://code.google.com/p/sgabios/ sgabios] option ROM can forward many VGA BIOS requests and keyboard events over a serial port. One can deploy it in addition to the primary VGA BIOS or by itself.<br />
<br />
If the target machine does not have a VGA adapter, then one should install sgabios. Most bootloaders (eg, GRUB) require a VGA BIOS in order to function properly &mdash; the sgabios ROM can fill this requirement.<br />
<br />
Place the sgabios ROM file in the '''vgaroms/''' directory of CBFS. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add /path/to/sgabios.bin vgaroms/sgabios.bin raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
When using sgabios, all the characters that SeaBIOS writes to the screen will be seen twice &mdash; once from SeaBIOS sending the character to the serial port and once from sgabios forwarding the character. To prevent the duplicates one can edit the SeaBIOS '''src/config.h''' file and set the following:<br />
<br />
<source lang="C"><br />
#define CONFIG_SCREEN_AND_DEBUG 0<br />
</source><br />
<br />
== Adding a graphical "bootsplash" image ==<br />
<br />
SeaBIOS can show a custom [http://en.wikipedia.org/wiki/JPEG JPEG] image during bootup. To enable this, add the JPEG file to flash with the name '''bootsplash.jpg'''. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add /path/to/image.jpg bootsplash.jpg raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
The size of the JPEG image determines the video mode to use for showing the image. Make sure the dimensions of the image exactly correspond to an available video mode (eg, 640x480, or 1024x768), otherwise it will not be displayed.<br />
<br />
SeaBIOS will show the image during the wait for the boot menu (if the boot menu has been disabled, users will not see the image). The image should probably have "Press F12 for boot menu" embedded in it so users know they can enter the normal SeaBIOS boot menu. By default, the boot menu prompt (and thus graphical image) is shown for 2.5 seconds. This can be customized by modifying SeaBIOS' '''src/config.h''' file and changing the '''CONFIG_BOOTMENU_WAIT''' setting.<br />
<br />
The JPEG viewer in SeaBIOS uses a simplified decoding algorithm. It supports most common JPEGs, but does not support all possible formats. Please see the [[#Trouble reporting]] section if a valid image isn't displayed properly.<br />
<br />
== Adding payloads ==<br />
<br />
Most [[Payloads|payloads]] can also be launched from SeaBIOS. To add a payload, build the corresponding .elf file and then add it to the '''coreboot.rom''' file in the '''img/''' directory. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add-payload /path/to/payload.elf img/MyPayload l<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
During boot, one can press the '''F12''' key to get a boot menu. SeaBIOS will show all files in the '''img/''' directory, and one can instruct SeaBIOS to run them.<br />
<br />
SeaBIOS supports both uncompressed and LZMA compressed payloads.<br />
<br />
== Adding a floppy image ==<br />
<br />
It is possible to embed an image of a floppy in flash. SeaBIOS can then boot from and redirect floppy BIOS calls to the flash image. This is mainly useful for legacy software (such as DOS utilities). To use this feature, place a floppy image into the CBFS directory '''floppyimg/'''. For example:<br />
<br />
<source lang="bash"><br />
$ lzma -zc /path/to/myfloppy.img > myfloppy.img.lzma<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add myfloppy.img.lzma floppyimg/MyFloppy.lzma raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
Both uncompressed and LZMA compressed images are supported. Several floppy formats are available: 360K, 1.2MB, 720K, 1.44MB, 2.88MB, 160K, 180K, 320K.<br />
<br />
The floppy image will appear as writable to the system, however all writes are discarded on reboot.<br />
<br />
When using this system, SeaBIOS reserves high-memory to store the floppy. The reserved memory is then no longer available for OS use, so this feature should only be used when needed.<br />
<br />
== Configuring boot order ==<br />
<br />
'''This feature is only available in SeaBIOS git versions after 20110104.'''<br />
<br />
Place a file in CBFS with the name '''bootorder''' to configure the boot up order. The file should be ASCII text and contain one line per boot method. The description of each boot method follows an Open Firmware device path format. SeaBIOS will attempt to boot from each item in the file - first line of the file first.<br />
<br />
The easiest way to find the available boot methods is to look for "Searching bootorder for" in the SeaBIOS serial output. For example, one may see lines similar to:<br />
<br />
Searching bootorder for: /pci@i0cf8/*@f/drive@1/disk@0<br />
Searching bootorder for: /pci@i0cf8/*@f,1/drive@2/disk@1<br />
Searching bootorder for: /pci@i0cf8/usb@10,4/*@2<br />
<br />
The above represents the patterns SeaBIOS will search for in the bootorder file. However, it's safe to just copy and paste the pattern into bootorder. For example, the file:<br />
<br />
/pci@i0cf8/usb@10,4/*@2<br />
/pci@i0cf8/*@f/drive@1/disk@0<br />
<br />
will instruct SeaBIOS to attempt to boot from the given USB drive first and then attempt the given ATA harddrive second.<br />
<br />
Once a file has been created, add it to CBFS with the name '''bootorder'''. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add mybootlist.txt bootorder raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
= Trouble reporting =<br />
<br />
If you are experiencing problems with SeaBIOS, it's useful to increase the debugging level. This is done by editing the '''src/config.h''' file and setting the debug level to a higher number (for example '''8'''):<br />
<br />
<source lang="C"><br />
#define CONFIG_DEBUG_LEVEL 8<br />
</source><br />
<br />
A debug level of 8 will show a lot of diagnostic information without flooding the serial port (levels above 8 will frequently cause too much data).<br />
<br />
To report an issue, please collect the serial boot log with SeaBIOS set to a debug level of 8 and forward the full log along with a description of the problem to the coreboot [[Mailinglist|mailing list]].</div>
Jakllsch
https://www.coreboot.org/index.php?title=ACPI&diff=9922
ACPI
2010-09-18T13:35:35Z
<p>Jakllsch: s/APCI/ACPI/g</p>
<hr />
<div></div>
Jakllsch
https://www.coreboot.org/index.php?title=SeaBIOS&diff=9921
SeaBIOS
2010-09-17T15:30:50Z
<p>Jakllsch: link to seabios.org</p>
<hr />
<div>[http://www.seabios.org '''SeaBIOS'''] is an open-source legacy BIOS implementation which can be used as a coreboot [[Payloads|payload]]. It implements the standard BIOS calling interfaces that a typical x86 proprietary BIOS implements.<br />
<br />
This page describes using SeaBIOS with coreboot. SeaBIOS can also run natively in qemu and bochs - see the SeaBIOS README file for information on non-coreboot uses.<br />
<br />
= Use cases =<br />
<br />
Any software requiring 16-bit BIOS services benefits from SeaBIOS (eg, Windows and DOS). SeaBIOS also enables booting Linux out of the box (using standard boot-loaders like GRUB and Syslinux).<br />
<br />
SeaBIOS supports booting from ATA hard drives, ATAPI cdroms, USB hard drives, USB cdroms, payloads in flash, and from [http://en.wikipedia.org/wiki/Option_ROM Option ROMs] (eg, SCSI or network cards). SeaBIOS can initialize and use a ps2 keyboard or USB keyboard.<br />
<br />
== Windows ==<br />
<br />
SeaBIOS has been tested with Windows XP, Windows Vista (64/32 bit), and Windows 7 Beta (64 bit).<br />
<br />
However, Windows has a very strict ACPI interpreter, and many coreboot boards do not have a complete [[ACPI in coreboot|ACPI definition]]. As a result, many coreboot boards will fail during Windows boot (eg, it may fail with a STOP 0xA5 code).<br />
<br />
So far [[ASUS M2V-MX SE]] and [[GIGABYTE GA-M57SLI-S4]] have known good working ACPI and are able to boot XP/Vista/Windows 7. Please ask on the [[Mailinglist|mailing list]] for the status of other boards/chipsets.<br />
<br />
== Linux ==<br />
<br />
SeaBIOS has been tested with GRUB, LILO, and Syslinux. Linux booting works well.<br />
<br />
== Other ==<br />
<br />
SeaBIOS has also been tested with FreeDOS and NetBSD.<br />
<br />
Because SeaBIOS implements the standard x86 BIOS interfaces, it is expected many other operating systems and boot-loaders will work.<br />
<br />
= Building =<br />
<br />
== SeaBIOS ==<br />
<br />
One can download the latest version of SeaBIOS through a git repository:<br />
<br />
<source lang="bash"><br />
$ git clone git://git.linuxtogo.org/home/kevin/seabios.git seabios<br />
$ cd seabios<br />
</source><br />
<br />
There's also a [http://git.linuxtogo.org/?p=kevin/seabios.git;a=summary gitweb] facility to browse the latest source code online.<br />
<br />
Edit '''src/config.h''' and set the following values:<br />
<br />
<source lang="C"><br />
#define CONFIG_COREBOOT 1<br />
#define CONFIG_DEBUG_SERIAL 1<br />
#define CONFIG_VGAHOOKS 1<br />
</source><br />
<br />
Then:<br />
<br />
<source lang="bash"><br />
$ make<br />
</source><br />
<br />
The final SeaBIOS payload file is '''out/bios.bin.elf'''.<br />
<br />
=== Compiled SeaBIOS images ===<br />
<br />
It is also possible to download a compiled SeaBIOS image. The latest released version compiled for coreboot is: http://linuxtogo.org/~kevin/SeaBIOS/bios.bin.elf-0.6.0<br />
<br />
Other versions are also available at: http://linuxtogo.org/~kevin/SeaBIOS/<br />
<br />
== coreboot ==<br />
<br />
For best results, configure coreboot with CONFIG_WRITE_HIGH_TABLES and CONFIG_VGA_BRIDGE_SETUP both enabled, and CONFIG_VGA_ROM_RUN and CONFIG_PCI_ROM_RUN both disabled.<br />
<br />
Finally, configure the SeaBIOS '''/out/bios.bin.elf''' file as the coreboot payload and build coreboot. The resulting '''coreboot.rom''' file will contain both SeaBIOS and coreboot, and it can be flashed to a rom.<br />
<br />
= SeaBIOS and CBFS =<br />
<br />
SeaBIOS can read the coreboot flash filesystem and extract files.<br />
<br />
When SeaBIOS scans the target machine's PCI devices, it will recognize option ROMs in CBFS that have the form '''pciVVVV,DDDD.rom'''. It will also run any file in the directory '''vgaroms/''' as a vga option ROM not specific to a device and files in '''genroms/''' as a generic option ROM not specific to a device. In the above cases, SeaBIOS will recognize files with a '''.lzma''' suffix, and automatically decompress them (eg, '''pci1106,3344.rom.lzma''' and '''vgaroms/sgabios.bin.lzma''').<br />
<br />
SeaBIOS can also load a graphical bootsplash image from '''bootsplash.jpg''', payloads found in the CBFS directory '''img/''', and floppy images found in the '''floppyimg/''' directory.<br />
<br />
The examples below show some common uses of this feature.<br />
<br />
== Adding a VGA option ROM ==<br />
<br />
It is frequently necessary to add a VGA option ROM to CBFS in order to use a VGA adapter that is built-in to a motherboard. Note, VGA adapters on external cards do not require this step as SeaBIOS will automatically extract the VGA bios directly from the card. For machines without a VGA adapter, please follow the [[#Adding sgabios support|sgabios instructions]] below.<br />
<br />
The first step is to find the vendor and device ID of the built-in VGA adapter. This information can be found from '''lspci''':<br />
<br />
<source lang="bash"><br />
$ lspci -vnn<br />
...<br />
01:00.0 VGA compatible controller [0300]: VIA Technologies, Inc. UniChrome Pro IGP [1106:3344] (rev 01) (prog-if 00 [VGA controller])<br />
</source><br />
<br />
In the above example, the VGA vendor/device ID is '''1106:3344'''. [[VGA support#How_to_retrieve_a_good_video_bios|Obtain the VGA ROM]] (eg, '''vgabios.bin''') and add it to the ROM with:<br />
<br />
<source lang="bash"><br />
$ ./cbfs/cbfstool coreboot.rom add /path/to/vgabios.bin pci1106,3344.rom raw<br />
$ ./cbfs/cbfstool coreboot.rom print<br />
</source><br />
<br />
Alternatively, SeaBIOS supports LZMA compressed option ROMs. Use the following to add a compressed option ROM instead:<br />
<br />
<source lang="bash"><br />
$ lzma -zc /path/to/vgabios.bin > vgabios.bin.lzma<br />
$ ./cbfs/cbfstool coreboot.rom add vgabios.bin.lzma pci1106,3344.rom.lzma raw<br />
$ ./cbfs/cbfstool coreboot.rom print<br />
</source><br />
<br />
After the above is done, one can write the coreboot.rom file to flash. SeaBIOS will extract the VGA ROM and run it during boot.<br />
<br />
== Adding gpxe support ==<br />
<br />
A [[GPXE|gpxe]] option ROM can nicely complement SeaBIOS and coreboot by adding network boot support. Adding gpxe is similar to [[#Adding a VGA option ROM]]. The first step is to find the Ethernet vendor/device ID. For example:<br />
<br />
<source lang="bash"><br />
$ lspci -vnn<br />
...<br />
00:09.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8110SC/8169SC Gigabit Ethernet [10ec:8167] (rev 10)<br />
</source><br />
<br />
Then one can build a gpxe option ROM. For example:<br />
<br />
<source lang="bash"><br />
$ cd /path/to/gpxe/src/<br />
$ make bin/10ec8167.rom<br />
</source><br />
<br />
And add it to the coreboot image. For example:<br />
<br />
<source lang="bash"><br />
$ ./cbfs/cbfstool coreboot.rom add /path/to/gpxe/src/bin/10ec8167.rom pci10ec,8167.rom raw<br />
$ ./cbfs/cbfstool coreboot.rom print<br />
</source><br />
<br />
As with VGA option ROMs, the gpxe option ROM may be compressed with LZMA. However, compression won't significantly reduce gpxe's size as it implements its own compression.<br />
<br />
In addition to gpxe, other option ROMs can be added in the same manner.<br />
<br />
== Adding sgabios support ==<br />
<br />
An [http://code.google.com/p/sgabios/ sgabios] option ROM can forward many VGA BIOS requests and keyboard events over a serial port. One can deploy it in addition to the primary VGA BIOS or by itself.<br />
<br />
If the target machine does not have a VGA adapter, then one should install sgabios. Most bootloaders (eg, grub) require a VGA BIOS in order to function properly - the sgabios rom can fill this requirement.<br />
<br />
The current version of sgabios (as of 20090617) does not implement a proper checksum. As a work around, a tool from the seabios source repo can fix the checksum:<br />
<source lang="bash"><br />
$ /path/to/seabios/tools/buildrom.py /path/to/sgabios.bin sgabios-fixed.bin<br />
</source><br />
<br />
Once the above is done, place the ROM file in the '''vgaroms/''' directory of CBFS. For example:<br />
<br />
<source lang="bash"><br />
$ ./cbfs/cbfstool coreboot.rom add sgabios-fixed.bin vgaroms/sgabios.bin raw<br />
$ ./cbfs/cbfstool coreboot.rom print<br />
</source><br />
<br />
When using sgabios, all the characters that SeaBIOS writes to the screen will be seen twice - once from SeaBIOS sending the character to the serial port and once from sgabios forwarding the character. To prevent the duplicates one can edit the SeaBIOS '''src/config.h''' file and set the following:<br />
<br />
<source lang="C"><br />
#define CONFIG_SCREEN_AND_DEBUG 0<br />
</source><br />
<br />
== Adding a graphical "bootsplash" image ==<br />
<br />
SeaBIOS can show a custom [http://en.wikipedia.org/wiki/JPEG JPEG] image during bootup. To enable this, add the jpeg file to flash with the name '''bootsplash.jpg'''. For example:<br />
<br />
<source lang="bash"><br />
$ ./cbfs/cbfstool coreboot.rom add /path/to/image.jpg bootsplash.jpg raw<br />
$ ./cbfs/cbfstool coreboot.rom print<br />
</source><br />
<br />
The size of the jpeg image determines the video mode to use for showing the image. Make sure the dimensions of the image exactly correspond to an available video mode (eg, 640x480, 1024x768).<br />
<br />
SeaBIOS will show the image during the wait for the boot menu. (If the boot menu has been disabled, users will not see the image.) The image should probably have "Press F12 for boot menu" embedded in it so users know they can enter the normal SeaBIOS boot menu. By default, the boot menu prompt (and thus graphical image) is shown for 2.5 seconds. This can be customized by modifying SeaBIOS' '''src/config.h''' file and changing the '''CONFIG_BOOTMENU_WAIT''' setting.<br />
<br />
The jpeg viewer in SeaBIOS uses a simplified decoding algorithm. It supports most common jpegs, but does not support all possible formats. Please see the [[#Trouble reporting]] section if a valid image isn't displayed properly.<br />
<br />
== Adding payloads ==<br />
<br />
Most [[Payloads|payloads]] can also be launched from SeaBIOS. To add a payload, build the corresponding .elf file and then add it to the '''coreboot.rom''' file in the '''img/''' directory. For example:<br />
<br />
<source lang="bash"><br />
$ ./cbfs/cbfstool coreboot.rom add-payload /path/to/payload.elf img/MyPayload l<br />
$ ./cbfs/cbfstool coreboot.rom print<br />
</source><br />
<br />
During boot, one can press the '''F12''' key to get a boot menu. SeaBIOS will show all files in the '''img/''' directory, and one can instruct SeaBIOS to run them.<br />
<br />
SeaBIOS supports both uncompressed and LZMA compressed payloads.<br />
<br />
== Adding a floppy image ==<br />
<br />
It is possible to embed an image of a floppy in flash. SeaBIOS can then boot from and redirect floppy BIOS calls to the flash image. This is mainly useful for legacy software (such as DOS utilities). To use this feature, place a floppy image into the CBFS directory '''floppyimg/'''. For example:<br />
<br />
<source lang="bash"><br />
$ lzma -zc /path/to/myfloppy.img > myfloppy.img.lzma<br />
$ ./cbfs/cbfstool coreboot.rom add myfloppy.img.lzma floppyimg/MyFloppy.lzma raw<br />
$ ./cbfs/cbfstool coreboot.rom print<br />
</source><br />
<br />
Both uncompressed and lzma compressed images are supported. Several floppy formats are available: 360K, 1.2MB, 720K, 1.44MB, 2.88MB, 160K, 180K, 320K.<br />
<br />
The floppy image will appear as writable to the system, however all writes are discarded on reboot.<br />
<br />
When using this system, SeaBIOS reserves high-memory to store the floppy. The reserved memory is then no longer available for OS use, so this feature should only be used when needed.<br />
<br />
= Trouble reporting =<br />
<br />
If you are experiencing problems with SeaBIOS, it's useful to increase the debugging level. This is done by editing the '''src/config.h''' file and setting the debug level to a higher number (for example 8):<br />
<br />
<source lang="C"><br />
#define CONFIG_DEBUG_LEVEL 8<br />
</source><br />
<br />
A debug level of 8 will show a lot of diagnostic information without flooding the serial port (levels above 8 will frequently cause too much data).<br />
<br />
To report an issue, please collect the serial boot log with SeaBIOS set to a debug level of 8 and forward the full log along with a description of the problem to the coreboot [[Mailinglist|mailing list]].</div>
Jakllsch
https://www.coreboot.org/index.php?title=Board:msi/ms7135&diff=9317
Board:msi/ms7135
2010-02-14T23:06:16Z
<p>Jakllsch: status update, a little info on MS-6 power controller chip</p>
<hr />
<div></div>
Jakllsch
https://www.coreboot.org/index.php?title=NetBSD&diff=9313
NetBSD
2010-02-09T17:48:08Z
<p>Jakllsch: drop old instructions for coreboot v2 and v3, replace with more-currently-applicable v4 instructions</p>
<hr />
<div>This page documents coreboot usage with NetBSD. It is probably terser than it could be, as it mostly just describes differences from the more-commonly-documented Linux procedures.<br />
<br />
== building coreboot on NetBSD ==<br />
GNU make is required to build coreboot, install it from pkgsrc/devel/gmake.<br />
<br />
=== coreboot v4 ===<br />
Use coreboot/util/crossgcc, you may have to work around a issue with the path to the GCC sources.<br />
== building [[SeaBIOS]] on NetBSD ==<br />
Build SeaBIOS with the previously mentioned crossgcc. You may need to (temporarily) use pkgsrc/shells/bash as your shell.<br />
<br />
== using NetBSD/x86 with coreboot ==<br />
=== interrupt routing ===<br />
<br />
Legacy interrupt routing (the PCI interrupt line register) is traditionally not<br />
implemented by coreboot on many mainboards. MPBIOS or ACPI will be required otherwise.<br />
<br />
NetBSD does not (without patching) search for a MPBIOS floating pointer at the location<br />
coreboot usually places it. SeaBIOS does relocate this pointer structure however.<br />
<br />
=== BIOS calls ===<br />
(This section is probably only relevant when not loading via SeaBIOS.)<br />
<br />
NetBSD/i386 GENERIC still makes some BIOS calls after boot(8):<br />
* isapnp(4)<br />
* mca(4)<br />
<br />
Removal of these subsystems from your kernel config(5) file removes these calls.<br />
<br />
Due to the nature of x86_64, BIOS calls on NetBSD/amd64 are not a problem, as they cannot be made from long-mode.<br />
<br />
=== coreboot-related utilities ===<br />
<br />
Both [[nvramtool]] and [[flashrom]] are in [http://pkgsrc-wip.sourceforge.net pkgsrc-wip].<br />
<br />
{{PD-self}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=File:Coreboot_menuconfig.png&diff=9312
File:Coreboot menuconfig.png
2010-02-09T17:27:45Z
<p>Jakllsch: uploaded a new version of "File:Coreboot menuconfig.png":&#32;update for Coreboot 4.0</p>
<hr />
<div>New kconfig ("make menuconfig") system for build- and configuration system.</div>
Jakllsch
https://www.coreboot.org/index.php?title=Supported_Chipsets_and_Devices&diff=6739
Supported Chipsets and Devices
2008-07-31T04:22:01Z
<p>Jakllsch: restore footnote 5 about some superio chips in v2</p>
<hr />
<div>Note: If a device is not supported by coreboot v2, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] for support. Do '''not''' attempt to use coreboot v3 &mdash; this is an early development version which is not ready for production use, yet.<br />
<br />
See also [[Supported Motherboards]].<br />
<br />
== Devices supported in coreboot v3 ==<br />
<br />
<div style="color: #ff0000">coreboot v3 is an alpha-stage development version of coreboot and is not meant for production use, yet!</div><br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;LX<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Generic<br />
| i586<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| Geode LX<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
|}<br />
<br />
== Devices supported in coreboot v2 ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam10<br />
| style="background:lime" | OK<sup>16</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX1<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX&nbsp;(GX2)<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| LX<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC710<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC925<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7520<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7525<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82810<br />
| style="background:yellow" | WIP<sup>9</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:yellow" | WIP<sup>11</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82855PM<br />
| style="background:red" | WIP<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SiS<br />
| SiS761GX<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623 (CLE266)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8T890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8M890<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:lime" | OK<sup>14</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8111<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8131<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8132<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8151<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5530/CS5530A<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5535<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background: lime " | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5780<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5785<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 6300ESB (ESB6300)<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:yellow" | WIP<sup>6</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801AA/AB&nbsp;(ICH/ICH0)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801BA/BAM&nbsp;(ICH2/ICH2-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA/CAM&nbsp;(ICH3-S/ICH3-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB/DBL/DBM<br/>(ICH4/ICH4-L/ICH4-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801EB/ER&nbsp;(ICH5/ICH5R)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PXHD<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| CK804<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Ricoh<br />
| RL5C476<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966(L)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237A<br />
| style="background:red" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8237S<br />
| style="background:red" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | <sup>12</sup>, <sup>13</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8661F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8705F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK <sup>8</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK <sup>15</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC8374<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:yellow" | OK <sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87360<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87366<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87417<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87427<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307 <br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M70x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B80x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B78x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B72x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B81x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M60x<br />
| style="background:lime" | OK<sup>3</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B27x<br />
| style="background:lime" | OK<sup>7</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M10x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M112<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M13x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M15x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M192<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B397<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| DME1737<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| SCH5307<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47N217<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686(A/B)<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627EHG/EHF<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THF<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977TF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:lime" | OK<sup>4</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| MPC74xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC4xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC7xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC970<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Emulated<br />
| QEMU<br />
| style="background:lime" | OK<br />
|}<br />
<br />
'''SOCs'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | SOC<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Elan SC520<br />
| style="background: lime" | OK<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> Serial output should work for all ITE Super I/Os (but is only tested on the IT8671F and IT8712F). The rest ''could'' work, but is completely untested.<br /><br />
<sup>2</sup> Work in progress.<br /><br />
<sup>3</sup> Serial output on serial port 1 is tested and works, the rest probably not yet (tested on FDC37M602).<br /><br />
<sup>4</sup> The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least).<br /><br />
<sup>5</sup> Pre-RAM serial output works fine, but nothing else, yet.<br /><br />
<sup>6</sup> IDE support is available and tested. SMBus support may work, but is untested. USB support is on our TODO list.<br /><br />
<sup>7</sup> Pre-RAM serial output [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021247.html works fine], everything else is untested.<br /><br />
<sup>8</sup> [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021623.html Works fine] mostly, but support for more obscure features (floppy, game port, MIDI, IR) might need more work.<br /><br />
<sup>9</sup> Works mostly, but currently there are some limitations as to which RAM DIMMs can be used.<br /><br />
<sup>10</sup> These southbridges should all be supported by the (experimental) new code in src/southbridge/intel/i82801xx/ now. Please test this code and use this code for all new ICH* based boards. There's still some old code for the southbridges, but that should not be used anymore.<br /><br />
<sup>11</sup> Sort of works, but the settings are hardcoded for the Tyan S1846. This will be fixed soonish.<br /><br />
<sup>12</sup> All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though.<br /><br />
<sup>13</sup> The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737.<br /><br />
<sup>14</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
<sup>15</sup> The Intel 3100 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far.<br /><br />
<sup>16</sup> Barcelona B0-B3 supported.<br />
</small><br />
<br />
== Devices supported in coreboot v1 ==<br />
<br />
Not all devices have been ported from coreboot v1 to coreboot v2, yet (check "v2?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
! align="left" | v2?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1631<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Alpha<br />
| Tsunami<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD76x<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 430TX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440BX<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>3</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440GX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82815EP<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82860<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7500<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7505<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Micron<br />
| 21PAD<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC/AMD<br />
| GX1<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT694<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | v2?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1543<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD766<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD768<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PIIX4E<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC/AMD<br />
| CS5530<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
! align="left" | v2?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:lime" | OK<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 950<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B72X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B78X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B807<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C669<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C67X<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37N769<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83877TF<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<sup>1</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''North-/Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | North/South<br />
! align="left" | Status<br />
! align="left" | v2?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 540<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 550<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 630<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 635<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 730<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 735<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ST<br />
| STPC<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
! align="left" | v2?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Alpha<br />
| EV6<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| ?<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> The W83977EF works fine with the W83977TF code in coreboot v2 (the pre-RAM serial part at least).<br /><br />
<sup>2</sup> Pre-RAM serial output works in coreboot v2, but the rest is not supported, yet.<br /><br />
<sup>3</sup> Work in progress.<br /><br />
</small><br />
<br />
__FORCETOC__</div>
Jakllsch
https://www.coreboot.org/index.php?title=EHCI_Debug_Port&diff=6714
EHCI Debug Port
2008-07-07T16:44:29Z
<p>Jakllsch: /* Controllers verified to lack the Debug port capability */ add SiS EHCI to the 'without' list</p>
<hr />
<div>Serial ports have been the primary means of early debugging of new coreboot ports. New hardware doesn't always have a serial port and another method for early debugging is needed.<br />
<br />
The '''EHCI Debug Port''' is an optional capability of EHCI controllers. All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.<br />
<br />
== Debug Class Device ==<br />
While the Debug Class functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.<br />
<br />
== Considerations in coreboot ==<br />
We'll use Mode 1 since a full USB stack and EHCI driver isn't running when we're using the debug port. We get early two-way communication from PCI memory write accesses. printf() should transmit also to the debug port on any (all?) EHCI controllers sporting the capability. Linux already supports this and we could probably copy code or headers from the kernel.<br />
<br />
== Hardware capability ==<br />
The Debug Port is optional, please check if EHCI controllers near you support it:<br />
<br />
# lspci -vs $(lspci|grep EHCI|cut -f1 -d' ')<br />
00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])<br />
Subsystem: IBM Unknown device 0566<br />
Flags: bus master, medium devsel, latency 0, IRQ 5<br />
Memory at b0000000 (32-bit, non-prefetchable) [size=1K]<br />
Capabilities: [50] Power Management version 2<br />
Capabilities: [58] Debug port<br />
<br />
Look for a line like the last one above.<br />
<br />
Please include the PCI device id too:<br />
<br />
# lspci -ns $(lspci|grep EHCI|cut -f1 -d' ')<br />
00:1d.7 0c03: 8086:265c (rev 03)<br />
<br />
If your controller isn't already listed below then please add it or send an email to the [[Mailinglist]] if you don't have a wiki account yet and want one, or want us to add your controller to the page.<br />
<br />
=== Controllers verified to have the Debug port capability ===<br />
<br />
* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)<br />
* 8086:24cd Intel ICH4/ICH4-M<br />
* 8086:24dd Intel ICH5<br />
* 8086:265c Intel ICH6<br />
* 8086:268c Intel 631xESB/632xESB/3100 Chipset (rev 09) (in Dell PE 1950)<br />
* 8086:27cc Intel ICH7<br />
* 8086:2836 Intel ICH8<br />
* 8086:283a Intel ICH8<br />
* 10de:0088 NVIDIA MCP2A (rev a2)<br />
* 10de:005b NVIDIA CK804 (rev a3)<br />
* 10de:026e NVIDIA MCP51 (rev a3)<br />
* 10de:036d NVIDIA MCP55 (rev a2)<br />
* 10de:03f2 NVIDIA MCP61 (rev a3)<br />
* 1002:4386 ATI/AMD SB600<br />
* 1106:3104 VIA VX800 (rev 90)<br />
<br />
=== Controllers verified to lack the Debug port capability ===<br />
<br />
* 1033:00e0 NEC Corporation EHCI (rev 02) (Compaq part)<br />
* 1106:3104 VIA Technologies EHCI (rev 82, rev 63, rev 86)<br />
* 1002:4373 ATI Technologies Inc IXP SB400 USB2 Host Controller (rev 80)<br />
* 1022:2095 Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)<br />
* 8086:24cd Intel Corporation 82801DB/DBM (ICH4/ICH4-M) EHCI (rev 01)<br />
* 1039:7002 SiS EHCI (rev 00)<br />
<br />
== Where to buy ==<br />
<br />
Currently there seems to be only one device which can use the EHCI Debug Port, the '''NET20DC'''.<br />
<br />
* http://www.plxtech.com/products/NET2000/NET20DC/default.asp<br />
* http://www.semiconductorstore.com/cart/pc/viewPrd.asp?idproduct=12083<br />
* http://www.semiconductorstore.com/pages/asp/supplier.asp?pl=0121<br />
* http://www.ajaystech.com/resources.htm<br />
<br />
== More information ==<br />
<br />
* [http://www.intel.com/technology/usb/download/ehci-r10.pdf EHCI 1.0 spec] (PDF) &mdash; The Debug Port is described in Appendix C.<br />
* [http://developer.intel.com/technology/usb/download/DebugDeviceSpec_R090.pdf Debug Class functional spec] (PDF) &mdash; This is what has to be connected to the EHCI controller.<br />
* [http://www.intel.com/technology/magazine/computing/it09021.pdf Intel Developer UPDATE Magazine on USB debugging] (PDF)<br />
* [http://tracker.coreboot.org/trac/coreboot/ticket/57 libusb host program for PLX NET20DC debug device]<br />
* [http://lkml.org/lkml/2006/12/4/3 Linux x86_64 early USB Debug Port support]<br />
* http://coreboot.org/pipermail/coreboot/2006-December/thread.html#17480<br />
* http://lkml.org/lkml/2006/12/1/214<br />
* http://www.usb.org/developers/presentations/pres0602/john_keys.pdf</div>
Jakllsch
https://www.coreboot.org/index.php?title=NetBSD&diff=6713
NetBSD
2008-07-04T18:39:09Z
<p>Jakllsch: s/LegacyBIOS/SeaBIOS/g and some slight rewording and additional details</p>
<hr />
<div>This page documents coreboot usage with NetBSD. It is probably terser than it could be, as it mostly just describes differences from the more-commonly-documented Linux procedures.<br />
<br />
== building coreboot on NetBSD ==<br />
GNU make is required to build coreboot, install it from pkgsrc/devel/gmake.<br />
=== coreboot v2 ===<br />
As of revision 3363 only one change needs to be made.<br />
<br />
<source lang="text"><br />
Index: src/config/Config.lb<br />
===================================================================<br />
--- src/config/Config.lb (revision 3389)<br />
+++ src/config/Config.lb (working copy)<br />
@@ -5,7 +5,7 @@<br />
<br />
makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E<br />
makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)<br />
-makedefine GCC_INC_DIR := $(shell LC_ALL=C $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")<br />
+makedefine GCC_INC_DIR := /usr/include<br />
<br />
makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)<br />
makedefine CFLAGS := $(CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -fno-builtin -Wall<br />
</source><br />
<br />
<br />
=== coreboot v3 ===<br />
<source lang="text"><br />
Index: Makefile<br />
===================================================================<br />
--- Makefile (revision 690)<br />
+++ Makefile (working copy)<br />
@@ -106,7 +106,7 @@<br />
# Note: This _must_ come after 'CC' is set for the second time in this<br />
# Makefile (see above), otherwise the build would break if 'gcc' isn't<br />
# the compiler actually used for the build (e.g. on cross compiler setups).<br />
-CFLAGS += -nostdinc -isystem `$(CC) -print-file-name=include`<br />
+CFLAGS += -nostdinc -isystem /usr/include<br />
<br />
include lib/Makefile<br />
include device/Makefile<br />
</source><br />
<br />
On NetBSD libintl is required to build kconfig.<br />
<source lang="bash"><br />
gmake INTLLIBS=-lintl menuconfig<br />
</source><br />
<br />
== building [[SeaBIOS]] on NetBSD ==<br />
A change is required to '''seabios/Makefile''', then gmake can be used to build SeaBIOS in the normal way.<br />
<source lang="text"><br />
-$(Q)/bin/echo -e '$(foreach i,$2,#include "../$i"\n)' > $3.tmp.c<br />
+$(Q)echo -e '$(foreach i,$2,#include "../$i"\n)' > $3.tmp.c<br />
</source><br />
<br />
== using NetBSD/x86 with coreboot ==<br />
=== interrupt routing ===<br />
<br />
Legacy interrupt routing (the PCI interrupt line register) is traditionally not<br />
implemented by coreboot on many mainboards. MPBIOS or ACPI will be required otherwise.<br />
<br />
NetBSD does not (without patching) search for a MPBIOS floating pointer at the location<br />
coreboot usually places it. SeaBIOS does relocate this pointer structure however.<br />
<br />
=== BIOS calls ===<br />
(This section is probably only relevant when not loading via SeaBIOS.)<br />
<br />
NetBSD/i386 GENERIC still makes some BIOS calls after boot(8):<br />
* isapnp(4)<br />
* mca(4)<br />
<br />
Removal of these subsystems from your kernel config(5) file removes these calls.<br />
<br />
Due to the nature of x86_64, BIOS calls on NetBSD/amd64 are not a problem, as they cannot be made from long-mode.<br />
<br />
=== coreboot-related utilities ===<br />
<br />
Both [[nvramtool]] and [[flashrom]] are in [http://pkgsrc-wip.sourceforge.net pkgsrc-wip].<br />
<br />
{{PD-self}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=Payloads&diff=6712
Payloads
2008-07-04T18:32:59Z
<p>Jakllsch: /* NetBSD */ s/LegacyBIOS/SeaBIOS/g</p>
<hr />
<div>coreboot in itself is "only" minimal code for initializing a mainboard with peripherals. After the initialization, it jumps to a '''payload'''.<br />
<br />
== Payloads ==<br />
<br />
=== Bootloaders ===<br />
<br />
==== GRUB2 ====<br />
<br />
[[GRUB2]] is the standard bootloader for Linux and other Unix-like operating systems.<br />
<br />
You can use GRUB2 as a coreboot payload, too, in order to boot and operating system from a hard drive, for instance.<br />
<br />
==== FILO ====<br />
<br />
[[FILO]] is a simple bootloader with filesystem support.<br />
<br />
It will be deprecated in favor of [[GRUB2]] soon.<br />
<br />
==== Etherboot ====<br />
<br />
[[Etherboot]] is a network bootloader. It provides a direct replacement for proprietary PXE ROMs, with many extra features such as DNS, HTTP, iSCSI, etc.<br />
<br />
Older versions of Etherboot included parts of [[FILO]], and thus supported SATA and USB booting.<br />
<br />
The new [[GPXE]] is not yet supported, various code changes are required before it can work with coreboot.<br />
<br />
==== Open Firmware ====<br />
<br />
Mitch Bradley's [http://www.openbios.org/Open_Firmware Open Firmware], an IEEE1275-1994 Open Firmware implementation, can also be used as coreboot payload.<br />
<br />
==== OpenBIOS ====<br />
<br />
[[OpenBIOS]] &mdash; IEEE1275-1994 Open Firmware.<br />
<br />
=== Operating systems ===<br />
<br />
==== Linux ====<br />
<br />
Coreboot can use a [http://www.kernel.org Linux] kernel as payload directly. That is, the kernel is included in the ROM chip where coreboot resides.<br />
<br />
Alternatively, you can also boot a Linux kernel from your hard drive using either the [[FILO]] or [[GRUB2]] payloads, of course.<br />
<br />
==== FreeBSD ====<br />
<br />
[[Booting FreeBSD using coreboot|FreeBSD]] can be booted via coreboot with the help of [[ADLO]].<br />
<br />
==== OpenBSD ====<br />
<br />
[http://openbsd.org/ OpenBSD] can also be booted via coreboot with the help of [[ADLO]].<br />
<br />
This use-case is not well-tested yet, though.<br />
<br />
==== NetBSD ====<br />
<br />
[http://www.netbsd.org/ NetBSD]/x86 boot code is known to work with [[SeaBIOS]].<br />
<br />
[[User:Jakllsch|jakllsch]] has worked on a partially-complete port of the x86 boot code to the role of native payload. However, with the advent of [[SeaBIOS]], this is likely to become less of a priority. Consult [[Coreboot and NetBSD]] for further information.<br />
<br />
==== Windows ====<br />
<br />
[[Booting Windows using coreboot|Windows]] can be booted with the help of [[ADLO]].<br />
<br />
This use-case is not well-tested yet, though.<br />
<br />
==== OpenSolaris ====<br />
<br />
[[OpenSolaris]] has multiboot compliant kernels, and so it is possible to boot it with GRUB2 (pending some bug fixes).<br />
Some Sun engineers even worked on it, see http://bugs.opensolaris.org/bugdatabase/view_bug.do?bug_id=6475349 for information.<br />
<br />
Currently, GRUB2 refuses to load the kernel due to a small bug in the multiboot header of the kernel, but the kernel still refuses to<br />
work if that is worked around. Maybe they reintroduced some BIOS calls again?<br />
<br />
See also [http://blogs.sun.com/szhou/entry/booting_solaris_from_linuxbios this blog entry].<br />
<br />
=== Other ===<br />
<br />
==== Memtest86 / Memtest86+ ====<br />
<br />
[[Image:Qemu memtest.png|160px|right]]<br />
<br />
[[Memtest86]] is a program which checks your RAM modules.<br />
<br />
It can be run from within GRUB, but also as a coreboot payload (i.e. included in your ROM chip).<br />
<br />
<br clear="all" /><br />
<br />
==== ADLO ====<br />
<br />
[[ADLO]] &mdash; Glue layer to 16-bit Bochs BIOS. Allows [[Booting Windows using coreboot|booting Windows]] and [http://openbsd.org/ OpenBSD].<br />
<br />
==== SeaBIOS ====<br />
<br />
[[SeaBIOS]] (previously known as '''LegacyBIOS''') is an open-source implementation of a legacy BIOS which can also be used as coreboot payload.<br />
<br />
==== Libpayload ====<br />
<br />
[[Libpayload]] is a helper-library for payload-writers.<br />
<br />
==== Coreinfo ====<br />
<br />
[[Image:Coreinfo_pci.png|160px|right]]<br />
[[coreinfo]] is a coreboot payload which can display various system information.<br />
<br clear="all" /><br />
<br />
==== Bayou ====<br />
<br />
[[Image:Bayou-screenshot-menu.jpg|160px|right]]<br />
[[Bayou]] is the working name for a coreboot payload that can choose, load and run other payloads from a LAR archive on the ROM.<br />
<br clear="all" /><br />
<br />
=== Games ===<br />
<br />
==== GRUB invaders ====<br />
<br />
[[Image:Coreboot invaders.png|160px|right]]<br />
<br />
[[GRUB invaders]] multi-boot compliant ''space invaders'' game.<br />
<br />
It can either be started from within GRUB (as a "kernel"), or it can be used as a coreboot payload.<br />
<br />
<br clear="all" /><br />
<br />
==== TINT ====<br />
<br />
[[Image:Coreboot libpayload tint.png|160px|right]]<br />
[[tint]] is a falling blocks game.<br />
<br clear="all" /><br />
<br />
== Possible future payloads ==<br />
<br />
The following payloads might or might not work (with more or less changes required) with coreboot &mdash; their usage hasn't been tested or documented so far.<br />
<br />
* CodeGen's [http://www.openbios.org/SmartFirmware SmartFirmware] &mdash; IEEE1275-1994 Open Firmware <br />
* [http://www.gnu.org/software/gnufi/ GNUFI] (UEFI)<br />
* [[Plan 9]] &mdash; A distributed operating system.<br />
* [[RedBoot]] / eCos &mdash; Real-time OS for embedded systems; initial port to ELF completed but no longer available.<br />
* GPXE &mdash; Needs some code changes<br />
* HelenOS<br />
* ReactOS<br />
* FreeDOS<br />
* DragonflyBSD<br />
* MirBSD<br />
* MidnightBSD<br />
* OpenSolaris / BeleniX<br />
* FreeRTOS<br />
* QNX<br />
* Windows CE<br />
* Haiku<br />
* NanoVM (small JVM)<br />
* uip / lwip (small TCP/IP stacks)<br />
* MenuetOS<br />
* Minix<br />
<br />
== History ==<br />
<br />
The payload was originally intended to be a Linux kernel stored in flash. Flash ROM growth rate was anticipated optimistically however, today there are not many mainboards that actually have enough flash ROM room for a kernel. 512KB can be seen here-and-there and a few boards come with 1MB. Recent kernels really want that MB, and then<br />
you'll only have room for 300-400 KB of initial ramdisk, which could be too small too, depending on the application. During testing, a payload may also be downloaded via X-Modem from the serial debug console, saving flashing time.<br />
<br />
So, other payloads are used; the two major ones are [[FILO]] (soon to be deprecated in favor of [[GRUB2]]) and [[Etherboot]] (soon to be deprecated in favor of [[GPXE]]). FILO loads a kernel from a filesystem on an IDE device and Etherboot loads a kernel from the network or from a filesystem on an IDE device.<br />
<br />
If you're using FILO there is no Linux kernel until FILO loads it, and the kernel loaded by FILO (or Etherboot) can absolutely be the one you want to run in your system. Just set it up with the correct root and init commandline so that it can start init.</div>
Jakllsch
https://www.coreboot.org/index.php?title=NetBSD&diff=6688
NetBSD
2008-07-02T15:26:31Z
<p>Jakllsch: note utilities in pkgsrc-wip</p>
<hr />
<div>This page documents coreboot usage with NetBSD. It is probably terser than it could be, as it mostly just describes differences from the more-commonly-documented Linux procedures.<br />
<br />
== building coreboot on NetBSD ==<br />
GNU make is required to build coreboot, install it from pkgsrc/devel/gmake.<br />
=== coreboot v2 ===<br />
As of revision 3363 only one change needs to be made.<br />
<br />
<source lang="text"><br />
Index: src/config/Config.lb<br />
===================================================================<br />
--- src/config/Config.lb (revision 3389)<br />
+++ src/config/Config.lb (working copy)<br />
@@ -5,7 +5,7 @@<br />
<br />
makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E<br />
makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)<br />
-makedefine GCC_INC_DIR := $(shell LC_ALL=C $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")<br />
+makedefine GCC_INC_DIR := /usr/include<br />
<br />
makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)<br />
makedefine CFLAGS := $(CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -fno-builtin -Wall<br />
</source><br />
<br />
<br />
=== coreboot v3 ===<br />
<source lang="text"><br />
Index: Makefile<br />
===================================================================<br />
--- Makefile (revision 690)<br />
+++ Makefile (working copy)<br />
@@ -106,7 +106,7 @@<br />
# Note: This _must_ come after 'CC' is set for the second time in this<br />
# Makefile (see above), otherwise the build would break if 'gcc' isn't<br />
# the compiler actually used for the build (e.g. on cross compiler setups).<br />
-CFLAGS += -nostdinc -isystem `$(CC) -print-file-name=include`<br />
+CFLAGS += -nostdinc -isystem /usr/include<br />
<br />
include lib/Makefile<br />
include device/Makefile<br />
</source><br />
<br />
On NetBSD libintl is required to build kconfig.<br />
<source lang="bash"><br />
gmake INTLLIBS=-lintl menuconfig<br />
</source><br />
<br />
== building [[LegacyBIOS]] on NetBSD ==<br />
A change is required to '''legacybios/Makefile''', then gmake can be used to build LegacyBIOS in the normal way.<br />
<source lang="text"><br />
-$(Q)/bin/echo -e '$(foreach i,$2,#include "../$i"\n)' > $3.tmp.c<br />
+$(Q)echo -e '$(foreach i,$2,#include "../$i"\n)' > $3.tmp.c<br />
</source><br />
<br />
== using NetBSD/x86 with coreboot ==<br />
=== interrupt routing ===<br />
<br />
Legacy interrupt routing (the PCI interrupt line register) is traditionally not<br />
implemented on many mainboards under coreboot. MPBIOS or ACPI will be required.<br />
<br />
NetBSD does not (without patching) search for a MPBIOS floating pointer at the location<br />
coreboot usually places it. LegacyBIOS does relocate this pointer structure however.<br />
<br />
=== BIOS calls ===<br />
NetBSD/i386 GENERIC still makes some BIOS calls after boot(8):<br />
* isapnp(4)<br />
* mca(4)<br />
<br />
Removal of these subsystems from your kernel config(5) file removes these calls.<br />
<br />
Due to the nature of x86_64, BIOS calls on NetBSD/amd64 are not a problem, as they cannot be made from long-mode.<br />
<br />
=== coreboot-related utilities ===<br />
<br />
Both [[nvramtool]] and [[flashrom]] are in [http://pkgsrc-wip.sourceforge.net pkgsrc-wip].<br />
<br />
{{PD-self}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=Payloads&diff=6687
Payloads
2008-07-02T15:21:33Z
<p>Jakllsch: /* NetBSD */ add a link to Coreboot and NetBSD‎</p>
<hr />
<div>coreboot in itself is "only" minimal code for initializing a mainboard with peripherals. After the initialization, it jumps to a '''payload'''.<br />
<br />
== Payloads ==<br />
<br />
=== Bootloaders ===<br />
<br />
==== GRUB2 ====<br />
<br />
[[GRUB2]] is the standard bootloader for Linux and other Unix-like operating systems.<br />
<br />
You can use GRUB2 as a coreboot payload, too, in order to boot and operating system from a hard drive, for instance.<br />
<br />
==== FILO ====<br />
<br />
[[FILO]] is a simple bootloader with filesystem support.<br />
<br />
It will be deprecated in favor of [[GRUB2]] soon.<br />
<br />
==== Etherboot ====<br />
<br />
[[Etherboot]] is a network bootloader. It provides a direct replacement for proprietary PXE ROMs, with many extra features such as DNS, HTTP, iSCSI, etc.<br />
<br />
Older versions of Etherboot included parts of [[FILO]], and thus supported SATA and USB booting.<br />
<br />
The new [[GPXE]] is not yet supported, various code changes are required before it can work with coreboot.<br />
<br />
==== Open Firmware ====<br />
<br />
Mitch Bradley's [http://www.openbios.org/Open_Firmware Open Firmware], an IEEE1275-1994 Open Firmware implementation, can also be used as coreboot payload.<br />
<br />
==== OpenBIOS ====<br />
<br />
[[OpenBIOS]] &mdash; IEEE1275-1994 Open Firmware.<br />
<br />
=== Operating systems ===<br />
<br />
==== Linux ====<br />
<br />
Coreboot can use a [http://www.kernel.org Linux] kernel as payload directly. That is, the kernel is included in the ROM chip where coreboot resides.<br />
<br />
Alternatively, you can also boot a Linux kernel from your hard drive using either the [[FILO]] or [[GRUB2]] payloads, of course.<br />
<br />
==== FreeBSD ====<br />
<br />
[[Booting FreeBSD using coreboot|FreeBSD]] can be booted via coreboot with the help of [[ADLO]].<br />
<br />
==== OpenBSD ====<br />
<br />
[http://openbsd.org/ OpenBSD] can also be booted via coreboot with the help of [[ADLO]].<br />
<br />
This use-case is not well-tested yet, though.<br />
<br />
==== [http://www.netbsd.org/ NetBSD] ====<br />
<br />
NetBSD/x86 boot code is known to work with [[LegacyBIOS]].<br />
<br />
[[User:Jakllsch|jakllsch]] has worked on a partially-complete port of the x86 boot code<br />
to the role of native payload. However, with the advent of LegacyBIOS, this is likely<br />
to become less of a priority.<br />
<br />
Consult [[Coreboot and NetBSD?]] for further information.<br />
<br />
==== Windows ====<br />
<br />
[[Booting Windows using coreboot|Windows]] can be booted with the help of [[ADLO]].<br />
<br />
This use-case is not well-tested yet, though.<br />
<br />
==== OpenSolaris ====<br />
<br />
[[OpenSolaris]] has multiboot compliant kernels, and so it is possible to boot it with GRUB2 (pending some bug fixes).<br />
Some Sun engineers even worked on it, see http://bugs.opensolaris.org/bugdatabase/view_bug.do?bug_id=6475349 for information.<br />
<br />
Currently, GRUB2 refuses to load the kernel due to a small bug in the multiboot header of the kernel, but the kernel still refuses to<br />
work if that is worked around. Maybe they reintroduced some BIOS calls again?<br />
<br />
See also [http://blogs.sun.com/szhou/entry/booting_solaris_from_linuxbios this blog entry].<br />
<br />
=== Other ===<br />
<br />
==== Memtest86 / Memtest86+ ====<br />
<br />
[[Image:Qemu memtest.png|160px|right]]<br />
<br />
[[Memtest86]] is a program which checks your RAM modules.<br />
<br />
It can be run from within GRUB, but also as a coreboot payload (i.e. included in your ROM chip).<br />
<br />
<br clear="all" /><br />
<br />
==== ADLO ====<br />
<br />
[[ADLO]] &mdash; Glue layer to 16-bit Bochs BIOS. Allows [[Booting Windows using coreboot|booting Windows]] and [http://openbsd.org/ OpenBSD].<br />
<br />
==== LegacyBIOS ====<br />
<br />
[[LegacyBIOS]] is an open-source implementation of a legacy BIOS which can also be used as coreboot payload.<br />
<br />
==== Libpayload ====<br />
<br />
[[Libpayload]] is a helper-library for payload-writers.<br />
<br />
==== Coreinfo ====<br />
<br />
[[Image:Coreinfo_pci.png|160px|right]]<br />
[[coreinfo]] is a coreboot payload which can display various system information.<br />
<br clear="all" /><br />
<br />
=== Games ===<br />
<br />
==== GRUB invaders ====<br />
<br />
[[Image:Coreboot invaders.png|160px|right]]<br />
<br />
[[GRUB invaders]] multi-boot compliant ''space invaders'' game.<br />
<br />
It can either be started from within GRUB (as a "kernel"), or it can be used as a coreboot payload.<br />
<br />
<br clear="all" /><br />
<br />
==== TINT ====<br />
<br />
[[Image:Coreboot libpayload tint.png|160px|right]]<br />
[[tint]] is a falling blocks game.<br />
<br clear="all" /><br />
<br />
== Possible future payloads ==<br />
<br />
The following payloads might or might not work (with more or less changes required) with coreboot &mdash; their usage hasn't been tested or documented so far.<br />
<br />
* CodeGen's [http://www.openbios.org/SmartFirmware SmartFirmware] &mdash; IEEE1275-1994 Open Firmware <br />
* [http://www.gnu.org/software/gnufi/ GNUFI] (UEFI)<br />
* [[Plan 9]] &mdash; A distributed operating system.<br />
* [[RedBoot]] / eCos &mdash; Real-time OS for embedded systems; initial port to ELF completed but no longer available.<br />
* GPXE &mdash; Needs some code changes<br />
* HelenOS<br />
* ReactOS<br />
* FreeDOS<br />
* DragonflyBSD<br />
* MirBSD<br />
* MidnightBSD<br />
* OpenSolaris / BeleniX<br />
* FreeRTOS<br />
* QNX<br />
* Windows CE<br />
* Haiku<br />
* NanoVM (small JVM)<br />
* uip / lwip (small TCP/IP stacks)<br />
* MenuetOS<br />
* Minix<br />
<br />
== History ==<br />
<br />
The payload was originally intended to be a Linux kernel stored in flash. Flash ROM growth rate was anticipated optimistically however, today there are not many mainboards that actually have enough flash ROM room for a kernel. 512KB can be seen here-and-there and a few boards come with 1MB. Recent kernels really want that MB, and then<br />
you'll only have room for 300-400 KB of initial ramdisk, which could be too small too, depending on the application. During testing, a payload may also be downloaded via X-Modem from the serial debug console, saving flashing time.<br />
<br />
So, other payloads are used; the two major ones are [[FILO]] (soon to be deprecated in favor of [[GRUB2]]) and [[Etherboot]] (soon to be deprecated in favor of [[GPXE]]). FILO loads a kernel from a filesystem on an IDE device and Etherboot loads a kernel from the network or from a filesystem on an IDE device.<br />
<br />
If you're using FILO there is no Linux kernel until FILO loads it, and the kernel loaded by FILO (or Etherboot) can absolutely be the one you want to run in your system. Just set it up with the correct root and init commandline so that it can start init.</div>
Jakllsch
https://www.coreboot.org/index.php?title=NetBSD&diff=6686
NetBSD
2008-07-02T15:16:11Z
<p>Jakllsch: some notes on coreboot in combination with NetBSD</p>
<hr />
<div>This page documents coreboot usage with NetBSD. It is probably terser than it could be, as it mostly just describes differences from the more-commonly-documented Linux procedures.<br />
<br />
== building coreboot on NetBSD ==<br />
GNU make is required to build coreboot, install it from pkgsrc/devel/gmake.<br />
=== coreboot v2 ===<br />
As of revision 3363 only one change needs to be made.<br />
<br />
<source lang="text"><br />
Index: src/config/Config.lb<br />
===================================================================<br />
--- src/config/Config.lb (revision 3389)<br />
+++ src/config/Config.lb (working copy)<br />
@@ -5,7 +5,7 @@<br />
<br />
makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E<br />
makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)<br />
-makedefine GCC_INC_DIR := $(shell LC_ALL=C $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")<br />
+makedefine GCC_INC_DIR := /usr/include<br />
<br />
makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)<br />
makedefine CFLAGS := $(CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -fno-builtin -Wall<br />
</source><br />
<br />
<br />
=== coreboot v3 ===<br />
<source lang="text"><br />
Index: Makefile<br />
===================================================================<br />
--- Makefile (revision 690)<br />
+++ Makefile (working copy)<br />
@@ -106,7 +106,7 @@<br />
# Note: This _must_ come after 'CC' is set for the second time in this<br />
# Makefile (see above), otherwise the build would break if 'gcc' isn't<br />
# the compiler actually used for the build (e.g. on cross compiler setups).<br />
-CFLAGS += -nostdinc -isystem `$(CC) -print-file-name=include`<br />
+CFLAGS += -nostdinc -isystem /usr/include<br />
<br />
include lib/Makefile<br />
include device/Makefile<br />
</source><br />
<br />
On NetBSD libintl is required to build kconfig.<br />
<source lang="bash"><br />
gmake INTLLIBS=-lintl menuconfig<br />
</source><br />
<br />
== building [[LegacyBIOS]] on NetBSD ==<br />
A change is required to '''legacybios/Makefile''', then gmake can be used to build LegacyBIOS in the normal way.<br />
<source lang="text"><br />
-$(Q)/bin/echo -e '$(foreach i,$2,#include "../$i"\n)' > $3.tmp.c<br />
+$(Q)echo -e '$(foreach i,$2,#include "../$i"\n)' > $3.tmp.c<br />
</source><br />
<br />
== booting NetBSD/x86 with coreboot ==<br />
=== interrupt routing ===<br />
<br />
Legacy interrupt routing (the PCI interrupt line register) is traditionally not<br />
implemented on many mainboards under coreboot. MPBIOS or ACPI will be required.<br />
<br />
NetBSD does not (without patching) search for a MPBIOS floating pointer at the location<br />
coreboot usually places it. LegacyBIOS does relocate this pointer structure however.<br />
<br />
=== BIOS calls ===<br />
NetBSD/i386 GENERIC still makes some BIOS calls after boot(8):<br />
* isapnp(4)<br />
* mca(4)<br />
<br />
Removal of these subsystems from your kernel config(5) file removes these calls.<br />
<br />
Due to the nature of x86_64, BIOS calls on NetBSD/amd64 are not a problem, as they cannot be made from long-mode.<br />
<br />
<br />
{{PD-self}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=Payloads&diff=6685
Payloads
2008-07-02T14:22:56Z
<p>Jakllsch: add NetBSD entry</p>
<hr />
<div>coreboot in itself is "only" minimal code for initializing a mainboard with peripherals. After the initialization, it jumps to a '''payload'''.<br />
<br />
== Payloads ==<br />
<br />
=== Bootloaders ===<br />
<br />
==== GRUB2 ====<br />
<br />
[[GRUB2]] is the standard bootloader for Linux and other Unix-like operating systems.<br />
<br />
You can use GRUB2 as a coreboot payload, too, in order to boot and operating system from a hard drive, for instance.<br />
<br />
==== FILO ====<br />
<br />
[[FILO]] is a simple bootloader with filesystem support.<br />
<br />
It will be deprecated in favor of [[GRUB2]] soon.<br />
<br />
==== Etherboot ====<br />
<br />
[[Etherboot]] is a network bootloader. It provides a direct replacement for proprietary PXE ROMs, with many extra features such as DNS, HTTP, iSCSI, etc.<br />
<br />
Older versions of Etherboot included parts of [[FILO]], and thus supported SATA and USB booting.<br />
<br />
The new [[GPXE]] is not yet supported, various code changes are required before it can work with coreboot.<br />
<br />
==== Open Firmware ====<br />
<br />
Mitch Bradley's [http://www.openbios.org/Open_Firmware Open Firmware], an IEEE1275-1994 Open Firmware implementation, can also be used as coreboot payload.<br />
<br />
==== OpenBIOS ====<br />
<br />
[[OpenBIOS]] &mdash; IEEE1275-1994 Open Firmware.<br />
<br />
=== Operating systems ===<br />
<br />
==== Linux ====<br />
<br />
Coreboot can use a [http://www.kernel.org Linux] kernel as payload directly. That is, the kernel is included in the ROM chip where coreboot resides.<br />
<br />
Alternatively, you can also boot a Linux kernel from your hard drive using either the [[FILO]] or [[GRUB2]] payloads, of course.<br />
<br />
==== FreeBSD ====<br />
<br />
[[Booting FreeBSD using coreboot|FreeBSD]] can be booted via coreboot with the help of [[ADLO]].<br />
<br />
==== OpenBSD ====<br />
<br />
[http://openbsd.org/ OpenBSD] can also be booted via coreboot with the help of [[ADLO]].<br />
<br />
This use-case is not well-tested yet, though.<br />
<br />
==== [http://www.netbsd.org/ NetBSD] ====<br />
<br />
NetBSD/x86 boot code is known to work with [[LegacyBIOS]].<br />
<br />
[[User:Jakllsch|jakllsch]] has worked on a partially-complete port of the x86 boot code<br />
to the role of native payload. However, with the advent of LegacyBIOS, this is likely<br />
to become less of a priority.<br />
<br />
==== Windows ====<br />
<br />
[[Booting Windows using coreboot|Windows]] can be booted with the help of [[ADLO]].<br />
<br />
This use-case is not well-tested yet, though.<br />
<br />
==== OpenSolaris ====<br />
<br />
[[OpenSolaris]] has multiboot compliant kernels, and so it is possible to boot it with GRUB2 (pending some bug fixes).<br />
Some Sun engineers even worked on it, see http://bugs.opensolaris.org/bugdatabase/view_bug.do?bug_id=6475349 for information.<br />
<br />
Currently, GRUB2 refuses to load the kernel due to a small bug in the multiboot header of the kernel, but the kernel still refuses to<br />
work if that is worked around. Maybe they reintroduced some BIOS calls again?<br />
<br />
See also [http://blogs.sun.com/szhou/entry/booting_solaris_from_linuxbios this blog entry].<br />
<br />
=== Other ===<br />
<br />
==== Memtest86 / Memtest86+ ====<br />
<br />
[[Image:Qemu memtest.png|160px|right]]<br />
<br />
[[Memtest86]] is a program which checks your RAM modules.<br />
<br />
It can be run from within GRUB, but also as a coreboot payload (i.e. included in your ROM chip).<br />
<br />
<br clear="all" /><br />
<br />
==== ADLO ====<br />
<br />
[[ADLO]] &mdash; Glue layer to 16-bit Bochs BIOS. Allows [[Booting Windows using coreboot|booting Windows]] and [http://openbsd.org/ OpenBSD].<br />
<br />
==== LegacyBIOS ====<br />
<br />
[[LegacyBIOS]] is an open-source implementation of a legacy BIOS which can also be used as coreboot payload.<br />
<br />
==== Libpayload ====<br />
<br />
[[Libpayload]] is a helper-library for payload-writers.<br />
<br />
==== Coreinfo ====<br />
<br />
[[Image:Coreinfo_pci.png|160px|right]]<br />
[[coreinfo]] is a coreboot payload which can display various system information.<br />
<br clear="all" /><br />
<br />
=== Games ===<br />
<br />
==== GRUB invaders ====<br />
<br />
[[Image:Coreboot invaders.png|160px|right]]<br />
<br />
[[GRUB invaders]] multi-boot compliant ''space invaders'' game.<br />
<br />
It can either be started from within GRUB (as a "kernel"), or it can be used as a coreboot payload.<br />
<br />
<br clear="all" /><br />
<br />
==== TINT ====<br />
<br />
[[Image:Coreboot libpayload tint.png|160px|right]]<br />
[[tint]] is a falling blocks game.<br />
<br clear="all" /><br />
<br />
== Possible future payloads ==<br />
<br />
The following payloads might or might not work (with more or less changes required) with coreboot &mdash; their usage hasn't been tested or documented so far.<br />
<br />
* CodeGen's [http://www.openbios.org/SmartFirmware SmartFirmware] &mdash; IEEE1275-1994 Open Firmware <br />
* [http://www.gnu.org/software/gnufi/ GNUFI] (UEFI)<br />
* [[Plan 9]] &mdash; A distributed operating system.<br />
* [[RedBoot]] / eCos &mdash; Real-time OS for embedded systems; initial port to ELF completed but no longer available.<br />
* GPXE &mdash; Needs some code changes<br />
* HelenOS<br />
* ReactOS<br />
* FreeDOS<br />
* DragonflyBSD<br />
* MirBSD<br />
* MidnightBSD<br />
* OpenSolaris / BeleniX<br />
* FreeRTOS<br />
* QNX<br />
* Windows CE<br />
* Haiku<br />
* NanoVM (small JVM)<br />
* uip / lwip (small TCP/IP stacks)<br />
* MenuetOS<br />
* Minix<br />
<br />
== History ==<br />
<br />
The payload was originally intended to be a Linux kernel stored in flash. Flash ROM growth rate was anticipated optimistically however, today there are not many mainboards that actually have enough flash ROM room for a kernel. 512KB can be seen here-and-there and a few boards come with 1MB. Recent kernels really want that MB, and then<br />
you'll only have room for 300-400 KB of initial ramdisk, which could be too small too, depending on the application. During testing, a payload may also be downloaded via X-Modem from the serial debug console, saving flashing time.<br />
<br />
So, other payloads are used; the two major ones are [[FILO]] (soon to be deprecated in favor of [[GRUB2]]) and [[Etherboot]] (soon to be deprecated in favor of [[GPXE]]). FILO loads a kernel from a filesystem on an IDE device and Etherboot loads a kernel from the network or from a filesystem on an IDE device.<br />
<br />
If you're using FILO there is no Linux kernel until FILO loads it, and the kernel loaded by FILO (or Etherboot) can absolutely be the one you want to run in your system. Just set it up with the correct root and init commandline so that it can start init.</div>
Jakllsch
https://www.coreboot.org/index.php?title=Board:msi/ms7135&diff=6681
Board:msi/ms7135
2008-07-02T00:30:40Z
<p>Jakllsch: /* The Mainboard */ sensors work now</p>
<hr />
<div>Coreboot on the K8N Neo3 (MS-7135).<br />
<br />
There are two versions of this board.<br />
The K8N Neo3 H has a solder-on PLCC flash and brown AGR slot.<br />
The K8N Neo3 F has a yellow AGR slot and a socketed flash.<br />
<br />
In addition to the stock 512KiB LPC flash (such as Windbond W39V040A), 1MiB LPC flashes (SST 49VF080A) are usable.<br />
<br />
== The Mainboard ==<br />
<br />
{{Status|<br />
|CPU_status = OK<br />
|CPU_comments = cpu0: AMD Athlon(tm) 64 Processor 3200+, 2210.29 MHz<br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = cpu0: I-cache 64 KB 64B/line 2-way, D-cache 64 KB 64B/line 2-way<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = cpu0: L2 cache 512 KB 64B/line 16-way<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = OK<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = No<br />
|RAM_ecc_comments = Using ECC RAM causes machine to fail to get very far out of CAR.<br />
<br />
|IDE_status = OK<br />
|IDE_CF_status = OK<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|AGP_cards_comments = AGR slot, it's really legacy PCI. Interrupts untested.<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = Untested<br />
|PP_comments = lpt0 at isa0 port 0x378-0x37b irq 7<br />
|PS2_keyboard_status = OK<br />
|PS2_keyboard_comments = Occasionally driver will not successfully attach, may be cold/warm boot related.<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Watchdog_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = No<br />
|CPUfreq_comments = reboots when FID is changed<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board.<br />
|Reboot_status = OK<br />
|Poweroff_status = No<br />
|Poweroff_comments = may need ACPI to work<br />
|LEDs_status = N/A<br />
|HPET_status = Unknown<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = needs board enable: "-m msi:k8n-neo3"<br />
}}<br />
<br />
{{Cc-by-2.5}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=Supported_Chipsets_and_Devices&diff=6609
Supported Chipsets and Devices
2008-06-21T01:10:19Z
<p>Jakllsch: /* Devices supported in coreboot v2 */ correct EBS6300 to 6300ESB and hint that coreboot calls it ESB6300</p>
<hr />
<div>Note: If a device is not supported by coreboot v2, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] for support. Do '''not''' attempt to use coreboot v3 &mdash; this is an early development version which is not ready for production use, yet.<br />
<br />
See also [[Supported Motherboards]].<br />
<br />
== Devices supported in coreboot v3 ==<br />
<br />
<div style="color: #ff0000">coreboot v3 is an alpha-stage development version of coreboot and is not meant for production use, yet!</div><br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;LX<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Generic<br />
| i586<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| Geode LX<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
|}<br />
<br />
== Devices supported in coreboot v2 ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX1<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX&nbsp;(GX2)<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| LX<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC710<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| IBM<br />
| CPC925<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7520<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| E7525<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82810<br />
| style="background:yellow" | WIP<sup>9</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:yellow" | WIP<sup>11</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82855PM<br />
| style="background:red" | WIP<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SiS<br />
| SiS761GX<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8T890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8M890<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:lime" | OK<sup>14</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8111<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8131<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8132<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8151<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5530/CS5530A<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5535<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background: lime " | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5780<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5785<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 6300ESB (ESB6300)<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:yellow" | WIP<sup>6</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801AA/AB&nbsp;(ICH/ICH0)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801BA/BAM&nbsp;(ICH2/ICH2-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA/CAM&nbsp;(ICH3-S/ICH3-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB/DBL/DBM<br/>(ICH4/ICH4-L/ICH4-M)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801EB/ER&nbsp;(ICH5/ICH5R)<br />
| style="background:lime" | OK<sup>10</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PXHD<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| CK804<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Ricoh<br />
| RL5C476<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966(L)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237A<br />
| style="background:red" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | <sup>12</sup>, <sup>13</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8661F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8705F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK <sup>8</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK <sup>15</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC8374<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:yellow" | OK <sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87360<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87366<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87417<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87427<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307 <br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M70x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B80x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B78x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B72x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B81x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M60x<br />
| style="background:lime" | OK<sup>3</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B27x<br />
| style="background:lime" | OK<sup>7</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M10x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M112<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M13x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M15x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M192<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B397<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| DME1737<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| SCH5307<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47N217<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686(A/B)<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627EHG/EHF<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THF<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977TF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:lime" | OK<sup>4</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| MPC74xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC4xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC7xx<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| PPC970<br />
| style="background:#dddddd" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Emulated<br />
| QEMU<br />
| style="background:lime" | OK<br />
|}<br />
<br />
'''SOCs'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | SOC<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Elan SC520<br />
| style="background: lime" | OK<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> Serial output should work for all ITE Super I/Os (but is only tested on the IT8671F and IT8712F). The rest ''could'' work, but is completely untested.<br /><br />
<sup>2</sup> Work in progress.<br /><br />
<sup>3</sup> Serial output on serial port 1 is tested and works, the rest probably not yet (tested on FDC37M602).<br /><br />
<sup>4</sup> The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least).<br /><br />
<sup>6</sup> IDE support is available and tested. SMBus support may work, but is untested. USB support is on our TODO list.<br /><br />
<sup>7</sup> Pre-RAM serial output [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021247.html works fine], everything else is untested.<br /><br />
<sup>8</sup> [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021623.html Works fine] mostly, but support for more obscure features (floppy, game port, MIDI, IR) might need more work.<br /><br />
<sup>9</sup> Works mostly, but currently there are some limitations as to which RAM DIMMs can be used.<br /><br />
<sup>10</sup> These southbridges should all be supported by the (experimental) new code in src/southbridge/intel/i82801xx/ now. Please test this code and use this code for all new ICH* based boards. There's still some old code for the southbridges, but that should not be used anymore.<br /><br />
<sup>11</sup> Sort of works, but the settings are hardcoded for the Tyan S1846. This will be fixed soonish.<br /><br />
<sup>12</sup> All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though.<br /><br />
<sup>13</sup> The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737.<br /><br />
<sup>14</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
<sup>15</sup> The Intel 3100 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far.<br /><br />
</small><br />
<br />
== Devices supported in coreboot v1 ==<br />
<br />
Not all devices have been ported from coreboot v1 to coreboot v2, yet (check "v2?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
! align="left" | v2?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1631<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Alpha<br />
| Tsunami<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD76x<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 430TX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440BX<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>3</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440GX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82815EP<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82860<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7500<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7505<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Micron<br />
| 21PAD<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC/AMD<br />
| GX1<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT694<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | v2?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1543<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD766<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD768<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PIIX4E<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC/AMD<br />
| CS5530<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
! align="left" | v2?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:lime" | OK<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 950<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B72X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B78X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B807<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C669<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C67X<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37N769<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83877TF<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<sup>1</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''North-/Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | North/South<br />
! align="left" | Status<br />
! align="left" | v2?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 540<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 550<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 630<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 635<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 730<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 735<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ST<br />
| STPC<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
! align="left" | v2?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Alpha<br />
| ?<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| ?<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| EV6 (?)<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> The W83977EF works fine with the W83977TF code in coreboot v2 (the pre-RAM serial part at least).<br /><br />
<sup>2</sup> Pre-RAM serial output works in coreboot v2, but the rest is not supported, yet.<br /><br />
<sup>3</sup> Work in progress.<br /><br />
</small><br />
<br />
__FORCETOC__</div>
Jakllsch
https://www.coreboot.org/index.php?title=Board:msi/ms7135&diff=6568
Board:msi/ms7135
2008-06-05T20:38:39Z
<p>Jakllsch: some updates based on further testing and research</p>
<hr />
<div>Coreboot on the K8N Neo3 (MS-7135).<br />
<br />
There are two versions of this board.<br />
The K8N Neo3 H has a solder-on PLCC flash and brown AGR slot.<br />
The K8N Neo3 F has a yellow AGR slot and a socketed flash.<br />
<br />
In addition to the stock 512KiB LPC flash (such as Windbond W39V040A), 1MiB LPC flashes (SST 49VF080A) are usable.<br />
<br />
== The Mainboard ==<br />
<br />
{{Status|<br />
|CPU_status = OK<br />
|CPU_comments = cpu0: AMD Athlon(tm) 64 Processor 3200+, 2210.29 MHz<br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = cpu0: I-cache 64 KB 64B/line 2-way, D-cache 64 KB 64B/line 2-way<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = cpu0: L2 cache 512 KB 64B/line 16-way<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = OK<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = No<br />
|RAM_ecc_comments = Using ECC RAM causes machine to fail to get very far out of CAR.<br />
<br />
|IDE_status = OK<br />
|IDE_CF_status = OK<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|AGP_cards_comments = AGR slot, it's really legacy PCI. Interrupts untested.<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = Untested<br />
|PP_comments = lpt0 at isa0 port 0x378-0x37b irq 7<br />
|PS2_keyboard_status = OK<br />
|PS2_keyboard_comments = Occasionally driver will not successfully attach, may be cold/warm boot related.<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = No<br />
|Watchdog_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = No<br />
|CPUfreq_comments = reboots when FID is changed<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board.<br />
|Reboot_status = OK<br />
|Poweroff_status = No<br />
|Poweroff_comments = may need ACPI to work<br />
|LEDs_status = N/A<br />
|HPET_status = Unknown<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = needs board enable: "-m msi:k8n-neo3"<br />
}}<br />
<br />
{{Cc-by-2.5}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=Board:msi/ms7135&diff=6013
Board:msi/ms7135
2008-03-20T23:55:48Z
<p>Jakllsch: update status items after further testing</p>
<hr />
<div>Coreboot on the K8N Neo3 F (MS-7135).<br />
<br />
In addition to the stock 512KiB LPC flash (W39V040A), 1MiB LPC flashes (49VF080A) are usable.<br />
<br />
== The Mainboard ==<br />
<br />
{{Status|<br />
|CPU_status = OK<br />
|CPU_comments = cpu0: AMD Athlon(tm) 64 Processor 3200+, 2210.29 MHz<br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = cpu0: I-cache 64 KB 64B/line 2-way, D-cache 64 KB 64B/line 2-way<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = cpu0: L2 cache 512 KB 64B/line 16-way<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = OK<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_CF_status = OK<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = OK<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|AGP_cards_comments = AGR slot, it's really legacy PCI. Interrupts untested.<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = Untested<br />
|PP_comments = lpt0 at isa0 port 0x378-0x37b irq 7<br />
|PS2_keyboard_status = OK<br />
|PS2_keyboard_comments = Occasionally driver will not successfully attach, may be cold/warm boot related.<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = No<br />
|Watchdog_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = No<br />
|CPUfreq_comments = Probably won't work as long as there's no ACPI implementation for this board.<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board.<br />
|Reboot_status = OK<br />
|Poweroff_status = No<br />
|Poweroff_comments = may need ACPI to work<br />
|LEDs_status = N/A<br />
|HPET_status = Unknown<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = needs board enable: "-m msi:k8n-neo3"<br />
}}<br />
<br />
<br />
{{Cc-by-2.5}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=Board:msi/ms7135&diff=5969
Board:msi/ms7135
2008-03-15T19:35:40Z
<p>Jakllsch: successfully tested flashrom on proprietary bios, note that 8mbit flashes work</p>
<hr />
<div>Coreboot on the K8N Neo3 F (MS-7135).<br />
<br />
In addition to the stock 512KiB LPC flash (W39V040A), 1MiB LPC flashes (49VF080A) are usable.<br />
<br />
== The Mainboard ==<br />
<br />
{{Status|<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = OK<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_CF_status = OK<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|AGP_cards_comments = AGR slot, it's really legacy PCI. Interrupts untested.<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|PP_status = Untested<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|Watchdog_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = No<br />
|CPUfreq_comments = Probably won't work as long as there's no ACPI implementation for this board.<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board.<br />
|Reboot_status = Untested<br />
|Poweroff_status = Untested<br />
|LEDs_status = N/A<br />
|HPET_status = Untested<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = needs board enable: "-m msi:k8n-neo3"<br />
}}<br />
<br />
<br />
{{Cc-by-2.5}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=FAQ&diff=5967
FAQ
2008-03-15T16:17:35Z
<p>Jakllsch: /* Where can I buy BIOS chips (empty or pre-flashed)? */ add a US-based vendor of flash chips</p>
<hr />
<div></div>
Jakllsch
https://www.coreboot.org/index.php?title=Board:msi/ms7135&diff=5720
Board:msi/ms7135
2008-02-26T19:28:02Z
<p>Jakllsch: basic status info</p>
<hr />
<div>Coreboot on the K8N Neo3 F (MS-7135).<br />
<br />
== The Mainboard ==<br />
<br />
{{Status|<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = OK<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = OK<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_CF_status = OK<br />
|IDE_25_status = N/A<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|AGP_cards_comments = AGR slot, it's really legacy PCI. Interrupts untested.<br />
|PCI_cards_status = OK<br />
|PCIE_x1_status = OK<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = Untested<br />
|PP_status = Untested<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = Untested<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|Watchdog_status = Untested<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = No<br />
|CPUfreq_comments = Probably won't work as long as there's no ACPI implementation for this board.<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board.<br />
|Reboot_status = Untested<br />
|Poweroff_status = Untested<br />
|LEDs_status = N/A<br />
|HPET_status = Untested<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
|Flashrom_comments = Currently [[Flashrom]] works fine with coreboot, but it may ''not'' yet work with the proprietary BIOS.<br />
}}<br />
<br />
<br />
{{Cc-by-2.5}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=User:Jakllsch&diff=5717
User:Jakllsch
2008-02-26T18:42:17Z
<p>Jakllsch: New page: I'm Jonathan Kollasch. * [http://jakllsch.kollasch.net/ My web site / wiki]</p>
<hr />
<div>I'm Jonathan Kollasch.<br />
<br />
* [http://jakllsch.kollasch.net/ My web site / wiki]</div>
Jakllsch
https://www.coreboot.org/index.php?title=Nvidia_CK804_Porting_Notes&diff=5715
Nvidia CK804 Porting Notes
2008-02-26T18:28:45Z
<p>Jakllsch: add licencse tag, add a bit more flesh</p>
<hr />
<div>This document does not (at present) attempt to be as complete as the [[AMD Geode Porting Guide]], which has more general information.<br />
<br />
== Documentation ==<br />
<br />
There is no publicly available documentation on the CK804, the source (and, of course, reverse engineering) is your only hope.<br />
<br />
== Audio and Network ==<br />
<br />
If your CK804 has an AC97 codec, or ethernet PHY connected to it, you'll probably want to define '''CK804_USE_ACI''' and '''CK804_USE_NIC''' respectively.<br />
<br />
Without '''CK804_USE_ACI = 1''', the audio driver will time out when attempting to communicate with the codec.<br />
<br />
== Interrupt Routing Registers ==<br />
<br />
Obtained via playing with these registers with '''setpci(8)'''. Some information is still missing.<br />
<br />
These routing registers are in the LPC bridge PCI configuration space (device 1, function 0).<br />
<br />
'''Nibble values for routing registers:'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Nibble<br />
! align="left" | APIC Pin<br />
|- bgcolor="#eeeeee"<br />
| 1h || 23<br />
|- bgcolor="#dddddd"<br />
| 2h || 22?<br />
|- bgcolor="#eeeeee"<br />
| 8h || 20<br />
|- bgcolor="#dddddd"<br />
| Ch || 12<br />
|- bgcolor="#eeeeee"<br />
| Dh || 21<br />
|- bgcolor="#dddddd"<br />
| Eh || 14<br />
|- bgcolor="#eeeeee"<br />
| Fh || 15<br />
|}<br />
<br />
'''7c.l:'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Bits<br />
! align="left" | Description<br />
|- bgcolor="#eeeeee"<br />
| 27:24 || SATA at device 7, second port<br />
|- bgcolor="#dddddd"<br />
| 23:20 || SATA at device 8, second port<br />
|- bgcolor="#eeeeee"<br />
| 15:0 || PCI IRQ mappings?<br />
|}<br />
<br />
'''80.l:'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Bits<br />
! align="left" | Description<br />
|- bgcolor="#eeeeee"<br />
| 31:28 || SATA at device 7, first port<br />
|- bgcolor="#dddddd"<br />
| 27:24 || SATA at device 8, first port<br />
|- bgcolor="#eeeeee"<br />
| 15:12 || EHCI (device 2, function 1)<br />
|}<br />
<br />
'''84.l:'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Bits<br />
! align="left" | Description<br />
|- bgcolor="#eeeeee"<br />
| 11:8 || NIC (device 10, function 0)<br />
|- bgcolor="#dddddd"<br />
| 3:0 || OHCI (device 2, function 0)<br />
|}<br />
<br />
One thing to note is that interrupts on both ports of the SATA controllers<br />
should be routed to the same pin so that the device behaves the way the<br />
driver expects them to.<br />
<br />
{{Cc-by-2.5}}</div>
Jakllsch
https://www.coreboot.org/index.php?title=Nvidia_CK804_Porting_Notes&diff=5705
Nvidia CK804 Porting Notes
2008-02-26T00:10:47Z
<p>Jakllsch: some information collected about the CK804</p>
<hr />
<div>This document does not (at present) attempt to be as complete as the [[AMD_Geode_Porting_Guide]], which has more general information.<br />
<br />
== Documentation ==<br />
There is no publicly available documentation on the CK804, the source (and, of course, reverse engineering) is your only hope.<br />
<br />
== Audio and Network ==<br />
<br />
If your CK804 has an AC97 codec, or ethernet PHY connected to it,<br />
you'll probably want to define CK804_USE_ACI and CK804_USE_NIC respectively.<br />
<br />
Without CK804_USE_ACI=1, the audio driver<br />
will time out when attempting to communicate with the codec.<br />
<br />
== Interrupt Routing Registers ==<br />
Obtained via playing with these registers with setpci(8).<br />
Some information is still missing.<br />
<br />
This table maps nibble values of these registers to APIC pin numbers.<br />
<br />
These registers are in the LPC bridge configuration space.<br />
<br />
{| border="1" class="wikitable"<br />
|+ nibble values for routing registers<br />
! nibble !! pin<br />
|-<br />
| 1h || 23<br />
|-<br />
| 2h || 22?<br />
|-<br />
| 8h || 20<br />
|-<br />
| Ch || 12<br />
|-<br />
| Dh || 21<br />
|-<br />
| Eh || 14<br />
|-<br />
| Fh || 15<br />
|}<br />
<br />
{| border="1" class="wikitable"<br />
|+ 7c.l<br />
! bits !! description<br />
|-<br />
| 27:24 || SATA at device 7, second port<br />
|-<br />
| 23:20 || SATA at device 8, second port<br />
|-<br />
| 15:0 || PCI IRQ mappings?<br />
|}<br />
<br />
{| border="1" class="wikitable"<br />
|+ 80.l<br />
! bits !! description<br />
|-<br />
| 31:28 || SATA at device 7, first port<br />
|-<br />
| 27:24 || SATA at device 8, first port<br />
|-<br />
| 15:12 || EHCI (device 2, function 1)<br />
|}<br />
<br />
{| border="1" class="wikitable"<br />
|+ 84.l<br />
! bits !! description<br />
|-<br />
| 11:8 || NIC (device 10, function 0)<br />
|-<br />
| 3:0 || OHCI (device 2, function 0)<br />
|}</div>
Jakllsch