https://www.coreboot.org/api.php?action=feedcontributions&user=Jn&feedformat=atom
coreboot - User contributions [en]
2024-03-28T15:30:55Z
User contributions
MediaWiki 1.40.0
https://www.coreboot.org/index.php?title=Welcome_to_coreboot&diff=34467
Welcome to coreboot
2018-04-27T02:37:26Z
<p>Jn: Change gerrit guidelines link to the HTML version on doc.coreboot.org</p>
<hr />
<div><table width="100%" valign="top"><tr valign="top"><td width="80%"><br />
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<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
'''coreboot''' is an Open Source project aimed at replacing the proprietary [http://wikipedia.org/wiki/BIOS BIOS] (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a [[Payloads|payload]].<br />
<br />
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly from firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like [[SeaBIOS | PC BIOS services]] or [[TianoCore | UEFI]]. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.<br />
<br />
coreboot currently supports over '''[[Supported Motherboards|230]]''' different mainboards. Check the [[Support]] page to see if your system is supported.<br />
<br />
<small><br />
coreboot was formerly known as [http://www.coreboot.org/pipermail/coreboot/2008-January/029135.html LinuxBIOS]. <br />
</small><br />
</div><br />
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<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
coreboot uses [[git]] for source control and [http://review.coreboot.org gerrit] as the patch review tool. Please read the [https://doc.coreboot.org/gerrit_guidelines.html gerrit etiquette & guidelines] document before submitting or reviewing patches.<br />
</div><br />
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{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%<br />
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{{Box|<br />
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ICON = <small>[[Benefits|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Benefits]]</span>|<br />
CONTENT =<br />
<small><br />
* 100% Free Software (GPL), no royalties, no license fees!<br />
* Fast boot times (500 milliseconds to verified Linux kernel)<br />
<!-- * Avoids the need for a slow/buggy/proprietary BIOS --><br />
<!-- * Runs in 32-Bit protected mode almost from the start --><br />
<!-- * Written in C, contains virtually no assembly code --><br />
* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]<br />
<!-- * Further features: netboot, serial console, remote flashing, ... --><br />
</small><br />
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HEADING = <span style="font-variant:small-caps; font-size:120%">[[Use Cases]]</span>|<br />
CONTENT =<br />
<small><br />
* Desktop PCs, servers, [[Laptop|laptops]]<br />
* [[Clusters]]<br />
<!-- * Set-Top-Boxes, thin clients --><br />
* Embedded solutions<br />
<!-- * [http://en.wikipedia.org/wiki/Small_form_factor Small form factor computers], [http://en.wikipedia.org/wiki/Home_theater_PC Home-theater PCs] --><br />
<!-- * No-moving-parts solutions (ROM chip as "disk") --><br />
<!-- * Non-standard scenarios (e.g. FPGA in Opteron socket) --><br />
</small><br />
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{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = lime|<br />
WIDTH = 100%|<br />
ICON = <small>[[Payloads|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Payloads]]</span>|<br />
CONTENT =<br />
<small><br />
* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] <!-- / [[OpenFirmware]] / [[OpenBIOS]] --><br />
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] <!-- / [http://openbsd.org/ OpenBSD]--><br />
* [[Etherboot]] / [[GPXE]] / [[iPXE]] / [[Payloads|...]]<br />
<!--* [[Memtest86]]<br />
* [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]--><br />
</small><br />
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[[Image:chip_cb.png]]<br />
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'''<span style="font-variant:small-caps; font-size:150%">About</span>'''<br /><small>Find out more about coreboot.</small><small><hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]</small><br />
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{|<br />
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'''<span style="font-variant:small-caps; font-size:150%">Developers</span>'''<br /><small>Get involved! Help us make coreboot better.</small><small><hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree Browse Source] | [[GSoC]] | [[Where to start]] | [[Lesson1| Lesson 1]] | [[Distributed and Automated Testsystem|Testsystem]] | [https://coreboot.org/git-docs git-docs]</small><br />
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{|<br />
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[[Image:chip_status.png]]<br />
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'''<span style="font-variant:small-caps; font-size:150%">Status</span>'''<br /><small>Find out whether your hardware is already supported.</small><small><hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [[Board Status]] | [[Blob Matrix|Blob Matrix]] | [http://qa.coreboot.org Build Status]</small><br />
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[[Image:chip_tools.png]]<br />
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'''<span style="font-variant:small-caps; font-size:150%">Related Tools</span>'''<br /><small>Tools and libraries related to coreboot.</small><small><hr />[http://www.flashrom.org flashrom] | [[Superiotool]] | [[Nvramtool]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [http://serialice.com SerialICE]</small><br />
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[[Image:chip_101.png]]<br />
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'''<span style="font-variant:small-caps; font-size:150%">Getting Started</span>'''<br /><small>Download coreboot and get started.</small><small><hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation/old|Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]</small><br />
|}<br />
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{|<br />
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[[Image:chip_support.png]]<br />
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'''<span style="font-variant:small-caps; font-size:150%">Support</span>'''<br /><small>Learn how to contact us and find help and support.</small><small><hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [[Glossary]] | [[coreboot Options|coreboot Options]]</small><br />
|}<br />
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|}<br />
</td><td width="20%"><br />
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[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]<br />
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<br clear=all /><br />
<!-- Blog feed isn't currently working - commenting out for now.<br />
'''<span style="font-variant:small-caps; font-size:120%">[http://blogs.coreboot.org News (blog)]</span>'''<hr /><br />
<small><br />
<rss max=5>https://blogs.coreboot.org/feed/</rss><br />
</small><br />
--><br />
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'''<span style="font-variant:small-caps; font-size:120%">[[Current events|Events]]</span>'''<hr /><br />
<!-- List of upcoming events (remove events after they have taken place). --><br />
<small><br />
<br />
* Oct 26 - 29, 2017 - [https://ecc2017.coreboot.org European coreboot conference]<br />
* [[coreboot_community_meeting | Bi-weekly community meeting]]<br />
* [https://www.google.com/maps/place/Finowstra%C3%9Fe+2A,+10247+Berlin,+Germany Monthly coreboot users group meeting Berlin]<br />
<!-- * Currently none --><br />
<!--* '''2015/mon/day:''' coreboot event at [[Link]] in somecity --><br />
[https://www.coreboot.org/calendar.html Full calendar]<br />
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</td></tr></table><br />
<br />
__NOTOC__<br />
__NOEDITSECTION__</div>
Jn
https://www.coreboot.org/index.php?title=Board:lowrisc/nexys4ddr&diff=22967
Board:lowrisc/nexys4ddr
2016-12-22T19:04:52Z
<p>Jn: </p>
<hr />
<div>''"[https://www.lowrisc.org lowRISC] is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. We aim to complete our SoC design this year [2016]."''<br />
<br />
This coreboot port runs on the lowRISC bitstream for the [https://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/ Nexys 4 DDR] FPGA development board.<br />
<br />
== Getting the bitstream ==<br />
<br />
The newest bitstream is available at http://www.lowrisc.org/docs/debug-v0.3/fpga/ (you need the "standalone" .bit file). Because this bitstream implements a deprecated page table format (as specified in the RISC-V Privileged Specification 1.7), a new bitstream will be made available soon.<br />
<br />
== Booting coreboot ==<br />
<br />
* make crossgcc-riscv<br />
* select the board in menuconfig<br />
* convert the board to an ELF file through util/riscvtools/make-spike-elf.sh<br />
* Copy coreboot.elf on a µSD card as boot.bin<br />
* Attach the Nexys4DDR to a computer over USB. Two serial ports, called /dev/ttyUSB0 and /dev/ttyUSB1 on linux, should appear. Connect to /dev/ttyUSB1 through microcom or a similar program.<br />
* Boot the FPGA board with this µSD card<br />
<br />
== Booting Linux ==<br />
<br />
TODO. See also [[board:emulation/spike-riscv]]</div>
Jn
https://www.coreboot.org/index.php?title=Board:lowrisc/nexys4ddr&diff=22965
Board:lowrisc/nexys4ddr
2016-12-22T18:46:52Z
<p>Jn: </p>
<hr />
<div>''"[https://www.lowrisc.org lowRISC] is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. We aim to complete our SoC design this year [2016]."''<br />
<br />
This coreboot port runs on the lowRISC bitstream for the [https://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/ Nexys 4 DDR] FPGA development board.<br />
<br />
== Getting the bitstream ==<br />
<br />
The newest bitstream is available at http://www.lowrisc.org/docs/debug-v0.3/fpga/ (you need the "standalone" .bit file). Because this bitstream implements a deprecated page table format (as specified in the RISC-V Privileged Specification 1.7), a new bitstream will be made available.<br />
<br />
== Booting coreboot ==<br />
<br />
* make crossgcc-riscv<br />
* select the board in menuconfig<br />
* convert the board to an ELF file through util/riscvtools/make-spike-elf.sh<br />
* Copy coreboot.elf on a µSD card as boot.bin<br />
* Attach the Nexys4DDR to a computer over USB. Two serial ports, called /dev/ttyUSB0 and /dev/ttyUSB1 on linux, should appear. Connect to /dev/ttyUSB1 through microcom or a similar program.<br />
* Boot the FPGA board with this µSD card<br />
<br />
== Booting Linux ==<br />
<br />
TODO. See also [[board:emulation/spike-riscv]]</div>
Jn
https://www.coreboot.org/index.php?title=Board:lowrisc/nexys4ddr&diff=22964
Board:lowrisc/nexys4ddr
2016-12-22T18:42:29Z
<p>Jn: </p>
<hr />
<div>''"[https://www.lowrisc.org lowRISC] is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. We aim to complete our SoC design this year [2016]."''<br />
<br />
This coreboot port runs on the lowRISC bitstream for the [https://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/ Nexys 4 DDR] FPGA development board.<br />
<br />
== Getting the bitstream ==<br />
<br />
The newest bitstream is available at http://www.lowrisc.org/docs/debug-v0.3/fpga/ (you need the "standalone" .bit file). Because this bitstream implements a deprecated page table format (as specified in the RISC-V Privileged Specification 1.7), a new bitstream will be made available.<br />
<br />
== Booting coreboot ==<br />
<br />
* make crossgcc-riscv<br />
* select the board in menuconfig<br />
* convert the board to an ELF file through util/riscvtools/make-spike-elf.sh<br />
* Copy coreboot.elf on a µSD card as boot.bin<br />
* Attach the Nexys4DDR to a computer over USB. Two serial ports, called /dev/ttyUSB0 and /dev/ttyUSB1 on linux, should appear. Connect to /dev/ttyUSB1 through microcom or a similar program.<br />
* Boot the FPGA board with this µSD card</div>
Jn
https://www.coreboot.org/index.php?title=Board:lowrisc/nexys4ddr&diff=22963
Board:lowrisc/nexys4ddr
2016-12-22T18:35:17Z
<p>Jn: </p>
<hr />
<div>''"[https://www.lowrisc.org lowRISC] is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. We aim to complete our SoC design this year [2016]."''<br />
<br />
This coreboot port runs on the lowRISC bitstream for the [https://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/ Nexys 4 DDR] FPGA development board.<br />
<br />
== Booting coreboot ==<br />
<br />
* make crossgcc-riscv<br />
* select the board in menuconfig<br />
* convert the board to an ELF file through util/riscvtools/make-spike-elf.sh<br />
* Copy coreboot.elf on a µSD card as boot.bin<br />
* Boot the FPGA board with this µSD card</div>
Jn
https://www.coreboot.org/index.php?title=Board:apple/macbookair4_2&diff=22931
Board:apple/macbookair4 2
2016-12-20T20:38:06Z
<p>Jn: Rudimentary information</p>
<hr />
<div>This is the MacBook Air (13-inch, Mid 2011).<br />
<br />
Model number: MC965xx/A or MC966xx/A<br />
<br />
See also [https://support.apple.com/en-us/HT201862 "How to identify your MacBook Air"]</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=22406
Board:emulation/spike-riscv
2016-11-25T01:33:29Z
<p>Jn: Replace the boot log with a newer one.</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is maintained by Ron Minnich and [[User:Jn|jn]].<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/11 14604: buildgcc: Update to GCC 6.1.0, and binutils riscv update (version 11)].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* Edit riscv/processor.cc, processor_t::get_csr(), and add "case CSR_TIME: return 0;"<br />
* run make<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building coreboot==<br />
<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the vmlinux binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/linux booting. I included bash in the initrd.<br />
<br />
�<br />
<br />
coreboot-4.5-320-g2e525bf Fri Nov 18 13:29:36 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 7dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:800000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Found @ offset 80 size 3013<br />
�<br />
<br />
coreboot-4.5-320-g2e525bf Fri Nov 18 13:29:36 UTC 2016 romstage starting...<br />
0x40000000 bytes of memory at 0x80000000<br />
CBFS @ 20100 size 7dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:800000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Found @ offset 3100 size 5403<br />
�<br />
<br />
coreboot-4.5-320-g2e525bf Fri Nov 18 13:29:36 UTC 2016 ramstage starting...<br />
BS: Entering BS_PRE_DEVICE state.<br />
BS: Exiting BS_PRE_DEVICE state.<br />
----------------------------------------<br />
BS: Entering BS_DEV_INIT_CHIPS state.<br />
BS: Exiting BS_DEV_INIT_CHIPS state.<br />
----------------------------------------<br />
BS: Entering BS_DEV_ENUMERATE state.<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
BS: Exiting BS_DEV_ENUMERATE state.<br />
----------------------------------------<br />
BS: Entering BS_DEV_RESOURCES state.<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
BS: Exiting BS_DEV_RESOURCES state.<br />
----------------------------------------<br />
BS: Entering BS_DEV_ENABLE state.<br />
Enabling resources...<br />
done.<br />
BS: Exiting BS_DEV_ENABLE state.<br />
----------------------------------------<br />
BS: Entering BS_DEV_INIT state.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
BS: Exiting BS_DEV_INIT state.<br />
BS: callback (000000008083e308) @ src/vboot/bootmode.c:68.<br />
----------------------------------------<br />
BS: Entering BS_POST_DEVICE state.<br />
Finalize devices...<br />
Devices finalized<br />
BS: Exiting BS_POST_DEVICE state.<br />
----------------------------------------<br />
BS: Entering BS_OS_RESUME_CHECK state.<br />
BS: Exiting BS_OS_RESUME_CHECK state.<br />
----------------------------------------<br />
BS: Entering BS_WRITE_TABLES state.<br />
Writing coreboot table at 0xbffdc000<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 7dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:800000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 800000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum d4c8<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
BS: Exiting BS_WRITE_TABLES state.<br />
----------------------------------------<br />
BS: Entering BS_PAYLOAD_LOAD state.<br />
CBFS @ 20100 size 7dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:800000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Found @ offset 8900 size 34081c<br />
Loading segment from ROM address 0x0000000080028a38<br />
code (compression=0)<br />
New segment dstaddr 0x81000000 memsize 0x300000 srcaddr 0x80028a8c filesize 0x2ffa78<br />
Loading segment from ROM address 0x0000000080028a54<br />
data (compression=0)<br />
New segment dstaddr 0x81300000 memsize 0x40d50 srcaddr 0x80328504 filesize 0x40d50<br />
Loading segment from ROM address 0x0000000080028a70<br />
Entry Point 0xffffffff81000000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x0000000000300000 filesz: 0x00000000002ffa78<br />
lb: [0x0000000080832000, 0x0000000080847170)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x0000000000300000 filesz: 0x00000000002ffa78<br />
it's not compressed!<br />
[ 0x81000000, 812ffa78, 0x81300000) <- 80028a8c<br />
Clearing Segment: addr: 0x00000000812ffa78 memsz: 0x0000000000000588<br />
dest 0000000081000000, end 0000000081300000, bouncebuffer ffffffffffffffff<br />
Loading Segment: addr: 0x0000000081300000 memsz: 0x0000000000040d50 filesz: 0x0000000000040d50<br />
lb: [0x0000000080832000, 0x0000000080847170)<br />
Post relocation: addr: 0x0000000081300000 memsz: 0x0000000000040d50 filesz: 0x0000000000040d50<br />
it's not compressed!<br />
[ 0x81300000, 81340d50, 0x81340d50) <- 80328504<br />
dest 0000000081300000, end 0000000081340d50, bouncebuffer ffffffffffffffff<br />
Loaded segments<br />
BS: Exiting BS_PAYLOAD_LOAD state.<br />
----------------------------------------<br />
BS: Entering BS_PAYLOAD_BOOT state.<br />
Jumping to boot code at ffffffff81000000(00000000bffdc000)<br />
Stack overrun on CPU0 (address 0000000080800000 overwritten). Increase stack from current 4096 bytes<br />
ERROR: BUG ENCOUNTERED at file 'src/lib/stack.c', line 40<br />
Config string: 'platform {<br />
vendor ucb;<br />
arch spike;<br />
};<br />
rtc {<br />
addr 0x40000000;<br />
};<br />
uart {<br />
addr 0x40001000;<br />
};<br />
ram {<br />
0 {<br />
addr 0x80000000;<br />
size 0x40000000;<br />
};<br />
};<br />
core {<br />
0 {<br />
0 {<br />
isa rv64imafdc;<br />
timecmp 0x40000008;<br />
ipi 0x40002000;<br />
};<br />
};<br />
};<br />
'<br />
-----------------------------<br />
Virtual memory status enabled<br />
-----------------------------<br />
Initializing virtual memory...<br />
Finished initializing virtual memory<br />
OK, let's go<br />
Getting hart id...<br />
[ 0.000000] Linux version 4.6.3-riscv-g1ef29a9 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.44 October 3nd, 2016) ) #144 Fri Nov 25 02:18:13 CET 2016<br />
[ 0.000000] bootconsole [early0] enabled<br />
Querying memory, CPU #0...<br />
[ 0.000000] Available physical memory: 1008MB<br />
[ 0.000000] Initial ramdisk at: 0xffffffff81013758 (1415600 bytes)<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000081000000-0x00000000bfffffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000081000000-0x00000000bfffffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000081000000-0x00000000bfffffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 254520<br />
[ 0.000000] Kernel command line: earlyprintk=sbi_console0 keep init=/bin/sh<br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 1013124K/1032192K available (1317K kernel code, 77K rwdata, 288K rodata, 1464K init, 180K bss, 19068K reserved, 0K cma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446 ns<br />
Setting timer to 0000000000989680 (current time is 0000000000000000)...<br />
mcall_set_timer is currently not implemented, ignoring<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 2000.00 BogoMIPS (lpj=10000000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] Trying to unpack rootfs image as initramfs...<br />
[ 0.000000] console [sbi_console0] enabled<br />
[ 0.000000] console [sbi_console0] enabled<br />
[ 0.000000] bootconsole [early0] disabled<br />
[ 0.000000] bootconsole [early0] disabled<br />
[ 0.000000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.000000] io scheduler noop registered<br />
[ 0.000000] io scheduler cfq registered (default)<br />
[ 0.000000] brd: module loaded<br />
[ 0.000000] Freeing unused kernel memory: 1464K (ffffffff81000000 - ffffffff8116e000)<br />
[ 0.000000] This architecture does not have kernel memory protection.<br />
init: cannot set terminal process group (-1): Inappropriate ioctl for device<br />
init: no job control in this shell<br />
init-4.3#</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=22404
Board:emulation/spike-riscv
2016-11-25T00:28:55Z
<p>Jn: update build instrcutions a little</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is maintained by Ron Minnich and [[User:Jn|jn]].<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/11 14604: buildgcc: Update to GCC 6.1.0, and binutils riscv update (version 11)].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* Edit riscv/processor.cc, processor_t::get_csr(), and add "case CSR_TIME: return 0;"<br />
* run make<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building coreboot==<br />
<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the vmlinux binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:lowrisc/nexys4ddr&diff=21827
Board:lowrisc/nexys4ddr
2016-10-29T14:40:35Z
<p>Jn: instructions</p>
<hr />
<div>''"[https://www.lowrisc.org lowRISC] is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. We aim to complete our SoC design this year [2016]."''<br />
<br />
This coreboot port runs on the lowRISC bitstream for the Nexys 4 DDR FPGA development board.<br />
<br />
== Booting coreboot ==<br />
<br />
* make crossgcc-riscv<br />
* select the board in menuconfig<br />
* convert the board to an ELF file through util/riscvtools/make-spike-elf.sh<br />
* Copy coreboot.elf on a µSD card as boot.bin<br />
* Boot the FPGA board with this µSD card</div>
Jn
https://www.coreboot.org/index.php?title=Board:lowrisc/nexys4ddr&diff=21826
Board:lowrisc/nexys4ddr
2016-10-29T14:29:33Z
<p>Jn: create page</p>
<hr />
<div></div>
Jn
https://www.coreboot.org/index.php?title=EHCI_Debug_Port&diff=21415
EHCI Debug Port
2016-10-07T15:54:26Z
<p>Jn: fix a broken link. archive.org FTW!</p>
<hr />
<div>[[Image:PLX_NET20DC.jpg|thumb|right|Ajays (now bankcrupt) NET20DC 2.0 EHCI controller debug device.]]<br />
<br />
Serial ports have been the primary means of early debugging of new coreboot ports. New hardware doesn't always have a serial port and another method for early debugging is needed.<br />
<br />
The '''EHCI Debug Port''' is an optional capability of EHCI controllers which can be used for that purpose.<br />
<br />
All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.<br />
<br />
While the '''Debug Class''' functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.<br />
<br />
== Supported chipsets ==<br />
<br />
The following southbridges have USB debug support in coreboot:<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | Comments<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background:lime" | OK<br />
| Tested by [[User:Uwe|Uwe Hermann]].<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700<br />
| style="background:orange" | WIP<br />
| Probably won't work, a patch is being prepared.<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB900<br />
| style="background:lime" | OK<br />
| Tested on HP Pavilion m6 1035dx<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| A85X (Hudson D4)<br />
| style="background:lime" | OK<br />
| Tested by [[User:Ranma|Tobias Diedrich]] on ASUS F2A85M-LE.<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel<br />
| 82801GX (ICH7)<br />
| style="background:lime" | OK<br />
| Tested by [[User:SvenS|Sven Schnelle]] on Lenovo Thinkpad X60/T60. <br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<br />
| Tested by [[User:Uwe|Uwe Hermann]]. Any physical USB port will work, as the code tries all ports until the one with the attached USB Debug device is found.<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966<br />
| style="background:yellow" | Untested<br />
| '''Note:''' It's unclear if the chipset actually has EHCI Debug Port functionality, and (if yes), whether the current coreboot code supports it properly (or whether it's just copy-pasted code from another chipset).<br />
<br />
|}<br />
<br />
== Finding the USB debug port ==<br />
<br />
Generally, each EHCI controller can offer at most one debug port. That port corresponds to a fixed physical USB port. Locating that physical port without software is rather difficult because you need to look at lots of information.<br />
<br />
* <code>sudo lshw</code> can be used to find EHCI cabpable USB ports. It may yield something like:<br />
<pre><br />
*-usb:1<br />
description: USB controller<br />
product: MCP55 USB Controller<br />
vendor: NVIDIA Corporation<br />
physical id: 2.1<br />
bus info: pci@0000:00:02.1<br />
version: a2<br />
width: 32 bits<br />
clock: 66MHz<br />
capabilities: debug pm ehci bus_master cap_list<br />
configuration: driver=ehci_hcd latency=0 maxlatency=1 mingnt=3<br />
resources: irq:22 memory:ee204000-ee2040ff<br />
</pre><br />
* As <code>dmesg</code> are part of the core system it can be used from Live distributions that often protect the filesystem from file execution which means that scripts cannot be used. The easiest way to locate the physical USB port that has EHCI debug support can be verified by doing the following:<br />
** <code>sudo dmesg -c</code><br />
** Plug a USB flash memory<br />
** <code>dmesg | tail -22 | grep ehci</code><br />
* Carl-Daniel Hailfinger [http://www.coreboot.org/pipermail/coreboot/2008-September/038618.html has written] [http://www.coreboot.org/pipermail/coreboot/attachments/20080909/ae11c291/attachment.sh a script] which can help finding that port. An [http://www.coreboot.org/pipermail/coreboot/attachments/20140530/245547f8/attachment.sh updated script] was posted [http://www.coreboot.org/pipermail/coreboot/2014-May/078022.html here] on May 30 2014.<br />
<br />
== Using the EHCI debug port ==<br />
<br />
=== usb_debug kernel module and minicom ===<br />
<br />
To get a USB debug console, enable both '''CONFIG_USBDEBUG''' and '''CONFIG_CONSOLE_USB''' (menu option '''USB 2.0 EHCI debug dongle support''') in coreboot's kconfig.<br />
<br />
In case your system has more than one debug-capable EHCI, you can select the index as CONFIG_USBDEBUG_HCD_INDEX, with a southbridge-specific value (on AMD Hudson, 0 and 1 both indicate the first port, 2 is the second port).<br />
<br />
On your "host PC" you need a Linux system which is recent enough to provide the '''usb_debug''' kernel module. When you attach the Ajays Net20DC device to your host PC, it will create a '''/dev/ttyUSB0''' device to which you can connect as usual using any serial terminal program, e.g. '''minicom''' (115200, 8n1).<br />
<br />
TODO: Is the Baud rate actually configurable somewhere?<br />
<br />
You must connect the NET20DC to a special USB port on your coreboot target board (not all of the USB ports will work!), often this is USB port 1. If in doubt, try all available ports to check which one works on your board.<br />
<br />
Then you can power up your coreboot target board and you should see the usual coreboot bootlog in minicom on your host PC.<br />
<br />
=== usb_debug_io.c ===<br />
<br />
As an alternative, you can also use [http://tracker.coreboot.org/trac/coreboot/ticket/57 this small libusb-based user-space program] on the host PC to retrieve the coreboot logs.<br />
<br />
== Hardware capability ==<br />
<br />
The Debug Port is optional, please check if EHCI controllers near you support it: <code>lspci -v | grep ehci</code>. If you get any result try <code>lspci -v</code> and locate the entry.<br />
<br />
<br />
This might not work for your system but you can also try:<br />
$ '''for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do<br />
$ ''' lspci -vs $i'''<br />
$ '''done'''<br />
00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])<br />
Subsystem: IBM Unknown device 0566<br />
Flags: bus master, medium devsel, latency 0, IRQ 5<br />
Memory at b0000000 (32-bit, non-prefetchable) [size=1K]<br />
Capabilities: [50] Power Management version 2<br />
Capabilities: [58] '''Debug port'''<br />
<br />
Look for a line like the last one above. Please include the PCI device ID too:<br />
<br />
$ '''for i in $(lspci|grep EHCI|cut -f1 -d' ') ; do<br />
$ ''' lspci -ns $i'''<br />
$ '''done'''<br />
00:1d.7 0c03: 8086:265c (rev 03)<br />
<br />
If your controller isn't already listed below then please add it or send an email to the [[Mailinglist|mailing list]] if you don't have a wiki account yet and want one, or want us to add your controller to the page.<br />
<br />
=== Controllers verified to have the debug port capability ===<br />
<br />
* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)<br />
* 8086:24cd Intel ICH4/ICH4-M<br />
* 8086:24dd Intel ICH5<br />
* 8086:265c Intel ICH6<br />
* 8086:268c Intel 631xESB/632xESB/3100 Chipset (rev 09) (in Dell PE 1950)<br />
* 8086:27cc Intel ICH7<br />
* 8086:2836 Intel ICH8<br />
* 8086:283a Intel ICH8<br />
* 8086:293a Intel ICH9 (rev 2)<br />
* 8086:3a3a Intel ICH10<br />
* 8086:3a3c Intel ICH10<br />
* 10de:0088 NVIDIA MCP2A (rev a2)<br />
* 10de:005b NVIDIA CK804 (rev a3)<br />
* 10de:026e NVIDIA MCP51 (rev a3)<br />
* 10de:036d NVIDIA MCP55 (rev a2)<br />
* 10de:03f2 NVIDIA MCP61 (rev a3)<br />
* 1002:4386 ATI/AMD SB600<br />
* 1002:4396 ATI/AMD SB700<br />
* 1022:7808 AMD A85X<br />
* 1106:3104 VIA VX800 (rev 90)<br />
<br />
=== Controllers verified to lack the debug port capability ===<br />
<br />
* 1033:00e0 NEC Corporation EHCI (rev 02) (Compaq part)<br />
* 1106:3104 VIA Technologies EHCI (rev 82, rev 63, rev 86)<br />
* 1002:4373 ATI Technologies Inc IXP SB400 USB2 Host Controller (rev 80)<br />
* 1022:2095 Advanced Micro Devices [AMD] CS5536 [Geode companion] EHCI (rev 02)<br />
* 8086:24cd Intel Corporation 82801DB/DBM (ICH4/ICH4-M) EHCI (rev 01)<br />
* 1039:7002 SiS EHCI (rev 00)<br />
<br />
==Debug devices==<br />
<br />
=== DIY / BeagleBone Black ===<br />
<br />
==== EHCI Debug gadget driver ====<br />
If you have a device running GNU/Linux that has an usb device port, you could then try to use the [[EHCI Gadget Debug]].<br />
Note that it's not guaranteed to work on old kernels, and may be dependant on the usb device/otg controller driver.<br />
<br />
You can make your own usb debug dongle, see [[DIY EHCI debug dongle]].<br />
<br />
A BeagleBone Black with a 5v power supply can achieve this. [https://johnlewis.ie/coreboot-ehci-debug-gadget-demonstration/] (John Lewis)<br />
<br />
=== Commercial Devices/Dongles ===<br />
<br />
To be able to use the debug port it needs to be connected to a compatible device.<br />
There are two commercial devices available which can use the EHCI Debug Port, the '''AMIDebug Rx''' and '''Ajays NET20DC'''.<br />
<br />
==== AMIDebug Rx ====<br />
[[Image:AMI_Debug_Rx_2009-06-10_012.jpg|thumb|right|AMI Debug Rx USB 2.0 EHCI controller device.]]<br />
<br />
This device is expensive compared to the other devices on this page. The main advantage of this product is that it comes with LCD.<br />
<br />
* http://www.ami.com/products/bios-uefi-tools-and-utilities/amidebug-rx/<br />
<br />
"Interested parties may contact AMI for pricing and purchasing information" - AMI. point of contact: www.ami.com, phone number 1-800-828-9264.<br />
<br />
==== Ajays NET20DC ====<br />
Disclaimer:Ajays is bankcrupt so their product line is end of life (EOL). Symmetry Electronics and other companies have disengaged as a supplier of the Ajays Technology product line. This limits the number of available units on the market.<br />
<br />
* [http://web.archive.org/web/20080219120613/http://www.plxtech.com/products/NET2000/NET20DC/default.asp http://www.plxtech.com/products/NET2000/NET20DC/default.asp] (archive.org)<br />
<br />
The device can be used in both directions, but only one side provides power for the circuit.<br />
Make sure to connect the front port (see picture at the top) to your host device and the rear port to the DUT.<br />
On the host side it doesn't matter which USB port to use, on the DUT side use the DEBUG port.<br />
Under GNU/Linux the device shows up as a regular serial USB device (ttyUSBx).<br />
<br />
== More information ==<br />
<br />
* [http://www.intel.com/technology/usb/download/ehci-r10.pdf EHCI 1.0 spec] (PDF) &mdash; The Debug Port is described in Appendix C.<br />
* [http://developer.intel.com/technology/usb/download/DebugDeviceSpec_R090.pdf Debug Class functional spec] (PDF) &mdash; This is what has to be connected to the EHCI controller.<br />
* [http://www.intel.com/technology/magazine/computing/it09021.pdf Intel Developer UPDATE Magazine on USB debugging] (PDF) &mdash; ''dead URL'' ([https://web.archive.org/web/20050826153054/http://www.intel.com/technology/magazine/computing/it09021.pdf copy at archive.org])<br />
* [http://tracker.coreboot.org/trac/coreboot/ticket/57 libusb host program for PLX NET20DC debug device]<br />
* [http://lkml.org/lkml/2006/12/4/3 Linux x86_64 early USB Debug Port support]<br />
* http://coreboot.org/pipermail/coreboot/2006-December/thread.html#17480<br />
* http://lkml.org/lkml/2006/12/1/214<br />
* http://www.usb.org/developers/presentations/pres0602/john_keys.pdf<br />
* [http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=5c05917e7fe313a187ad6ebb94c1c6cf42862a0b Linux early USB Debug Port support finally commited]<br />
* [http://www.kernel.org/doc/Documentation/x86/earlyprintk.txt early printk support in Linux]<br />
* http://www.spinics.net/lists/linux-usb/msg32912.html (Linux USB EHCI Debug Port device gadget)<br />
* http://cs.usfca.edu/~cruse/cs698s10/ - various EHCI debug port and Ajays resources</div>
Jn
https://www.coreboot.org/index.php?title=DIY_EHCI_debug_dongle&diff=21354
DIY EHCI debug dongle
2016-10-04T09:05:18Z
<p>Jn: /* Firmware */</p>
<hr />
<div>== Hardware ==<br />
<br />
A dongle to debug target with [[EHCI Debug Port]] capability can be built using two Cypress CY7C68013A (aka FX2LP) USB device chips.<br />
Theory of operation is described in Cypress Application Note AN63787[http://www.cypress.com/?rID=45850].<br />
<br />
There are a few boards in the 10-15 EUR pricerange to choose from and a dozen suppliers in ebay.<br />
<br />
A slower uni-directional boot console has been demonstrated to work with one FX2LP and a TTL-UART-to-USB adapter. In theory at least, some JTAG dongles with FX2LP could be used to capture coreboot console from EHCI debug port.<br />
<br />
== Prototype ==<br />
==== LCSoft FX2LP ====<br />
<br />
[[Image:fx2lp_lcsoft_1.JPG|x240px|LCSoft]]<br />
[[Image:fx2lp_lcsoft_2.JPG|x240px|LCSoft]]<br />
<br />
Schematics for [[:File:fx2lp lcsoft schematic A.pdf|prototype board]] and [[:File:ehci lcsoft revA0.pdf|required modification]].<br />
<br />
There are at least two different versions of this board. The old version with only one LED (just connected to the supply), capacitors on the bottom side of the PCB and the reset taster near the EEPROM is the one used in the prototype shown above.<br />
The new version doesn't have capacitors on the bottom side of the PCB, the reset taster near the USB port and three LEDs. The two additional LEDs are connected to PA0 and PA1, which I removed. There is also a 10k resistor connected to the A0 pin of the EEPROM, so you just have to remove the jumpers. The resistor on the reset pin is not R2 but R3. RDY0 und RDY1 are swapped on the silkscreen, but the pins are connected to the same pins of the FX2LP as on the old version, so that's just an error in the silkscreen.<br />
<br />
Warning: On J2 the supply pins 10 and 19 are swapped (one is GND and one is VCC), so you also have to remove these two pins from the J2-F connector if you use one new and one old version of the PCB for this project.<br />
<br />
== Firmware ==<br />
<br />
Firmware is built with sdcc using fx2lib.<br />
<br />
Original git repository [http://git.stackframe.org/?p=fx2lib]. Offline.<br />
<br />
Recent updates are here [http://bitbucket.org/kmalkki/fx2lib].<br />
<br />
More recent code is available at [https://github.com/night199uk/fx2lib]. Note that it uses different pin assignments than the code in the previous repository.<br />
<br />
You have to flash the same debugdevice_full_duplex firmware on both boards.</div>
Jn
https://www.coreboot.org/index.php?title=DIY_EHCI_debug_dongle&diff=21349
DIY EHCI debug dongle
2016-10-04T02:43:24Z
<p>Jn: /* Firmware: another git repo link */</p>
<hr />
<div>== Hardware ==<br />
<br />
A dongle to debug target with [[EHCI Debug Port]] capability can be built using two Cypress CY7C68013A (aka FX2LP) USB device chips.<br />
Theory of operation is described in Cypress Application Note AN63787[http://www.cypress.com/?rID=45850].<br />
<br />
There are a few boards in the 10-15 EUR pricerange to choose from and a dozen suppliers in ebay.<br />
<br />
A slower uni-directional boot console has been demonstrated to work with one FX2LP and a TTL-UART-to-USB adapter. In theory at least, some JTAG dongles with FX2LP could be used to capture coreboot console from EHCI debug port.<br />
<br />
== Prototype ==<br />
==== LCSoft FX2LP ====<br />
<br />
[[Image:fx2lp_lcsoft_1.JPG|x240px|LCSoft]]<br />
[[Image:fx2lp_lcsoft_2.JPG|x240px|LCSoft]]<br />
<br />
Schematics for [[:File:fx2lp lcsoft schematic A.pdf|prototype board]] and [[:File:ehci lcsoft revA0.pdf|required modification]].<br />
<br />
There are at least two different versions of this board. The old version with only one LED (just connected to the supply), capacitors on the bottom side of the PCB and the reset taster near the EEPROM is the one used in the prototype shown above.<br />
The new version doesn't have capacitors on the bottom side of the PCB, the reset taster near the USB port and three LEDs. The two additional LEDs are connected to PA0 and PA1, which I removed. There is also a 10k resistor connected to the A0 pin of the EEPROM, so you just have to remove the jumpers. The resistor on the reset pin is not R2 but R3. RDY0 und RDY1 are swapped on the silkscreen, but the pins are connected to the same pins of the FX2LP as on the old version, so that's just an error in the silkscreen.<br />
<br />
Warning: On J2 the supply pins 10 and 19 are swapped (one is GND and one is VCC), so you also have to remove these two pins from the J2-F connector if you use one new and one old version of the PCB for this project.<br />
<br />
== Firmware ==<br />
<br />
Firmware is built with sdcc using fx2lib.<br />
<br />
Original git repository [http://git.stackframe.org/?p=fx2lib]. Offline.<br />
<br />
Recent updates are here [http://bitbucket.org/kmalkki/fx2lib].<br />
<br />
More recent code is available at [https://github.com/night199uk/fx2lib].<br />
<br />
You have to flash the same debugdevice_full_duplex firmware on both boards.</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=20539
Board:emulation/spike-riscv
2016-08-22T19:04:16Z
<p>Jn: /* Building the toolchain */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/11 14604: buildgcc: Update to GCC 6.1.0, and binutils riscv update (version 11)].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
Using bbl to boot linux will be deprecated. The preferred (but not yet working) way is to directly select linux as a payload.<br />
<br />
* TODO: bbl requires a libc by using autoconf and libc headers. I had to patch around to make it work with the coreboot toolchain.<br />
* TODO: I had to move the payload section around in the linker script, so that it didn't overwrite something else.<br />
* TODO: I patched the SBI putchar handler to use my UART<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=20537
Board:emulation/spike-riscv
2016-08-22T18:59:27Z
<p>Jn: /* Building the toolchain */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/ 14604: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
Using bbl to boot linux will be deprecated. The preferred (but not yet working) way is to directly select linux as a payload.<br />
<br />
* TODO: bbl requires a libc by using autoconf and libc headers. I had to patch around to make it work with the coreboot toolchain.<br />
* TODO: I had to move the payload section around in the linker script, so that it didn't overwrite something else.<br />
* TODO: I patched the SBI putchar handler to use my UART<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19888
Board:emulation/spike-riscv
2016-07-22T18:06:59Z
<p>Jn: /* Build instructions */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/ 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/ 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
Using bbl to boot linux will be deprecated. The preferred (but not yet working) way is to directly select linux as a payload.<br />
<br />
* TODO: bbl requires a libc by using autoconf and libc headers. I had to patch around to make it work with the coreboot toolchain.<br />
* TODO: I had to move the payload section around in the linker script, so that it didn't overwrite something else.<br />
* TODO: I patched the SBI putchar handler to use my UART<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19884
Board:emulation/spike-riscv
2016-07-22T16:08:34Z
<p>Jn: /* Building bbl */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/ 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/ 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
Using bbl to boot linux will be deprecated. The preferred (but not yet working) way is to directly select linux as a payload.<br />
<br />
* TODO: bbl requires a libc by using autoconf and libc headers. I had to patch around to make it work with the coreboot toolchain.<br />
* TODO: I had to move the payload section around in the linker script, so that it didn't overwrite something else.<br />
* TODO: I patched the SBI putchar handler to use my UART<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19831
Board:emulation/spike-riscv
2016-07-20T01:51:32Z
<p>Jn: /* Building coreboot with bbl */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/ 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/ 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19829
Board:emulation/spike-riscv
2016-07-20T00:54:40Z
<p>Jn: /* Building coreboot with bbl */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/ 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/ 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* deselect "<tt>Run payload in S-mode and provide SBI</tt>" in the <tt>Payload</tt> menu<br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19827
Board:emulation/spike-riscv
2016-07-19T22:49:46Z
<p>Jn: /* Building coreboot without a payload */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/ 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/ 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above<br />
* you need these additional patches:<br />
** [https://review.coreboot.org/#/c/15510| 15510: arch/riscv: Make SBI support optional]<br />
** [https://review.coreboot.org/#/c/15511| 15511: spike-riscv: Register RAM resource at 0x80000000]<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* deselect "<tt>Run payload in S-mode and provide SBI</tt>" in the <tt>Payload</tt> menu<br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19482
Board:emulation/spike-riscv
2016-07-01T19:43:13Z
<p>Jn: /* Building coreboot without a payload */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/ 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/ 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* You need the following patches:<br />
** [https://review.coreboot.org/#/c/15290/ 15290: change all eret instructions to mret]<br />
** [https://review.coreboot.org/#/c/15289/ 15289: Remove HTIF and SBI related code]<br />
** [https://review.coreboot.org/#/c/15288/ 15288: Provide a tohost symbol so Spike doesn't hang]<br />
** [https://review.coreboot.org/#/c/15284/ 15284: Move CBMEM into RAM]<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above<br />
* you need these additional patches:<br />
** [https://review.coreboot.org/#/c/15510| 15510: arch/riscv: Make SBI support optional]<br />
** [https://review.coreboot.org/#/c/15511| 15511: spike-riscv: Register RAM resource at 0x80000000]<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* deselect "<tt>Run payload in S-mode and provide SBI</tt>" in the <tt>Payload</tt> menu<br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19481
Board:emulation/spike-riscv
2016-07-01T19:14:04Z
<p>Jn: /* Building the toolchain */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/ 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/ 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* You need the following patches:<br />
** [https://review.coreboot.org/#/c/15290/| 15290: change all eret instructions to mret]<br />
** [https://review.coreboot.org/#/c/15289/| 15289: Remove HTIF and SBI related code]<br />
** [https://review.coreboot.org/#/c/15288/| 15288: Provide a tohost symbol so Spike doesn't hang]<br />
** [https://review.coreboot.org/#/c/15284/| 15284: Move CBMEM into RAM]<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above<br />
* you need these additional patches:<br />
** [https://review.coreboot.org/#/c/15510| 15510: arch/riscv: Make SBI support optional]<br />
** [https://review.coreboot.org/#/c/15511| 15511: spike-riscv: Register RAM resource at 0x80000000]<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* deselect "<tt>Run payload in S-mode and provide SBI</tt>" in the <tt>Payload</tt> menu<br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19464
Board:emulation/spike-riscv
2016-06-30T22:35:44Z
<p>Jn: /* Building coreboot with bbl */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/| 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/| 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* You need the following patches:<br />
** [https://review.coreboot.org/#/c/15290/| 15290: change all eret instructions to mret]<br />
** [https://review.coreboot.org/#/c/15289/| 15289: Remove HTIF and SBI related code]<br />
** [https://review.coreboot.org/#/c/15288/| 15288: Provide a tohost symbol so Spike doesn't hang]<br />
** [https://review.coreboot.org/#/c/15284/| 15284: Move CBMEM into RAM]<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above<br />
* you need these additional patches:<br />
** [https://review.coreboot.org/#/c/15510| 15510: arch/riscv: Make SBI support optional]<br />
** [https://review.coreboot.org/#/c/15511| 15511: spike-riscv: Register RAM resource at 0x80000000]<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* deselect "<tt>Run payload in S-mode and provide SBI</tt>" in the <tt>Payload</tt> menu<br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19445
Board:emulation/spike-riscv
2016-06-30T03:05:56Z
<p>Jn: /* Building coreboot with bbl */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/| 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/| 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* You need the following patches:<br />
** [https://review.coreboot.org/#/c/15290/| 15290: change all eret instructions to mret]<br />
** [https://review.coreboot.org/#/c/15289/| 15289: Remove HTIF and SBI related code]<br />
** [https://review.coreboot.org/#/c/15288/| 15288: Provide a tohost symbol so Spike doesn't hang]<br />
** [https://review.coreboot.org/#/c/15284/| 15284: Move CBMEM into RAM]<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above<br />
* you need these additional patches:<br />
** [https://review.coreboot.org/#/c/15510| 15510: arch/riscv: Make SBI support optional]<br />
** [https://review.coreboot.org/#/c/15511| 15511: spike-riscv: Register RAM resource at 0x80000000]<br />
* select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19444
Board:emulation/spike-riscv
2016-06-30T02:18:56Z
<p>Jn: /* boot log */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/| 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/| 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* You need the following patches:<br />
** [https://review.coreboot.org/#/c/15290/| 15290: change all eret instructions to mret]<br />
** [https://review.coreboot.org/#/c/15289/| 15289: Remove HTIF and SBI related code]<br />
** [https://review.coreboot.org/#/c/15288/| 15288: Provide a tohost symbol so Spike doesn't hang]<br />
** [https://review.coreboot.org/#/c/15284/| 15284: Move CBMEM into RAM]<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above, and select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=Boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19443
Board:emulation/spike-riscv
2016-06-30T02:18:28Z
<p>Jn: /* boot log */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/| 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/| 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* You need the following patches:<br />
** [https://review.coreboot.org/#/c/15290/| 15290: change all eret instructions to mret]<br />
** [https://review.coreboot.org/#/c/15289/| 15289: Remove HTIF and SBI related code]<br />
** [https://review.coreboot.org/#/c/15288/| 15288: Provide a tohost symbol so Spike doesn't hang]<br />
** [https://review.coreboot.org/#/c/15284/| 15284: Move CBMEM into RAM]<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above, and select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K dma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19442
Board:emulation/spike-riscv
2016-06-30T02:15:11Z
<p>Jn: fix boot log</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/| 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/| 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* You need the following patches:<br />
** [https://review.coreboot.org/#/c/15290/| 15290: change all eret instructions to mret]<br />
** [https://review.coreboot.org/#/c/15289/| 15289: Remove HTIF and SBI related code]<br />
** [https://review.coreboot.org/#/c/15288/| 15288: Provide a tohost symbol so Spike doesn't hang]<br />
** [https://review.coreboot.org/#/c/15284/| 15284: Move CBMEM into RAM]<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above, and select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
=boot log=<br />
<br />
Boot log of coreboot/bbl/linux booting (and then failing because linux can't find any block devices.<br />
<br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K cma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19441
Board:emulation/spike-riscv
2016-06-30T02:10:15Z
<p>Jn: /* boot log */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/| 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/| 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* You need the following patches:<br />
** [https://review.coreboot.org/#/c/15290/| 15290: change all eret instructions to mret]<br />
** [https://review.coreboot.org/#/c/15289/| 15289: Remove HTIF and SBI related code]<br />
** [https://review.coreboot.org/#/c/15288/| 15288: Provide a tohost symbol so Spike doesn't hang]<br />
** [https://review.coreboot.org/#/c/15284/| 15284: Move CBMEM into RAM]<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above, and select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
===boot log===<br />
<br />
<code><br />
we don't have virtual memory...<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 bootblock starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/romstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Found @ offset 80 size 2d17<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 romstage starting...<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/ramstage'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Found @ offset 2e00 size 4ed7<br />
?<br />
<br />
coreboot-4.4-652-gbfb3fee Thu Jun 30 01:03:13 UTC 2016 ramstage starting...<br />
Enumerating buses...<br />
Show all devs... Before device enumeration.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Compare with tree...<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
memalign Enter, boundary 8, size 3584, free_mem_ptr 0000000080840c18<br />
memalign 0000000080840c18<br />
CBMEM:<br />
IMD: root @ 00000000bffff000 254 entries.<br />
IMD: root @ 00000000bfffec00 62 entries.<br />
Root Device scanning...<br />
root_dev_scan_bus for Root Device<br />
CPU_CLUSTER: 0 enabled<br />
I2C: 00:06 enabled<br />
root_dev_scan_bus for Root Device done<br />
scan_bus: scanning of bus Root Device took 0 usecs<br />
done<br />
Allocating resources...<br />
Reading resources...<br />
Root Device read_resources bus 0 link: 0<br />
CPU_CLUSTER: 0 missing read_resources<br />
I2C: 00:06 missing read_resources<br />
Root Device read_resources bus 0 link: 0 done<br />
Done reading resources.<br />
Show resources in subtree (Root Device)...After reading.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Setting resources...<br />
Root Device assign_resources, bus 0 link: 0<br />
Root Device assign_resources, bus 0 link: 0<br />
Done setting resources.<br />
Show resources in subtree (Root Device)...After assigning values.<br />
Root Device child on link 0 CPU_CLUSTER: 0<br />
Root Device resource base 80000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 0<br />
CPU_CLUSTER: 0<br />
I2C: 00:06<br />
Done allocating resources.<br />
Enabling resources...<br />
done.<br />
Initializing devices...<br />
Root Device init ...<br />
Devices initialized<br />
Show all devs... After init.<br />
Root Device: enabled 1<br />
CPU_CLUSTER: 0: enabled 1<br />
I2C: 00:06: enabled 1<br />
Finalize devices...<br />
Devices finalized<br />
Writing coreboot table at 0xbffdc000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a18<br />
memalign 0000000080841a18<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841a38<br />
memalign 0000000080841a38<br />
0. 0000000080000000-00000000bffdbfff: RAM<br />
1. 00000000bffdc000-00000000bfffffff: CONFIGURATION TABLES<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
FMAP: Found "FLASH" version 1.1 at 20000.<br />
FMAP: base = 0 size = 400000 #areas = 4<br />
Wrote coreboot table at: 00000000bffdc000, 0x150 bytes, checksum f468<br />
coreboot table: 360 bytes.<br />
IMD ROOT 0. 00000000bffff000 00001000<br />
IMD SMALL 1. 00000000bfffe000 00001000<br />
CONSOLE 2. 00000000bffde000 00020000<br />
COREBOOT 3. 00000000bffdc000 00002000<br />
IMD small region:<br />
IMD ROOT 0. 00000000bfffec00 00000400<br />
CBFS @ 20100 size 3dff00<br />
CBFS: 'Master Header Locator' located CBFS at [20100:400000)<br />
CBFS: Locating 'fallback/payload'<br />
CBFS: Checking offset 0<br />
CBFS: File @ offset 0 size 20<br />
CBFS: Unmatched 'cbfs master header' at 0<br />
CBFS: Checking offset 80<br />
CBFS: File @ offset 80 size 2d17<br />
CBFS: Unmatched 'fallback/romstage' at 80<br />
CBFS: Checking offset 2e00<br />
CBFS: File @ offset 2e00 size 4ed7<br />
CBFS: Unmatched 'fallback/ramstage' at 2e00<br />
CBFS: Checking offset 7d40<br />
CBFS: File @ offset 7d40 size 114<br />
CBFS: Unmatched 'config' at 7d40<br />
CBFS: Checking offset 7ec0<br />
CBFS: File @ offset 7ec0 size 239<br />
CBFS: Unmatched 'revision' at 7ec0<br />
CBFS: Checking offset 8140<br />
CBFS: File @ offset 8140 size 120258<br />
CBFS: Found @ offset 8140 size 120258<br />
Loading segment from rom address 0x0000000080028278<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a58<br />
memalign 0000000080841a58<br />
New segment dstaddr 0x80000000 memsize 0x7e40 srcaddr 0x800282e8 filesize 0x3525<br />
Loading segment from rom address 0x0000000080028294<br />
code (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841a90<br />
memalign 0000000080841a90<br />
New segment dstaddr 0x80008000 memsize 0x1000 srcaddr 0x8002b80d filesize 0x86<br />
Loading segment from rom address 0x00000000800282b0<br />
data (compression=1)<br />
memalign Enter, boundary 8, size 56, free_mem_ptr 0000000080841ac8<br />
memalign 0000000080841ac8<br />
New segment dstaddr 0x81000000 memsize 0x3314c8 srcaddr 0x8002b893 filesize 0x11cc3d<br />
Loading segment from rom address 0x00000000800282cc<br />
Entry Point 0x0000000080000000<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b00<br />
memalign 0000000080841b00<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b20<br />
memalign 0000000080841b20<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b40<br />
memalign 0000000080841b40<br />
memalign Enter, boundary 8, size 32, free_mem_ptr 0000000080841b60<br />
memalign 0000000080841b60<br />
Bounce Buffer at 00000000bffb6000, 153648 bytes<br />
Loading Segment: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080000000 memsz: 0x0000000000007e40 filesz: 0x0000000000003525<br />
using LZMA<br />
[ 0x80000000, 80007d7c, 0x80007e40) <- 800282e8<br />
Clearing Segment: addr: 0x0000000080007d7c memsz: 0x00000000000000c4<br />
dest 0000000080000000, end 0000000080007e40, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000080008000 memsz: 0x0000000000001000 filesz: 0x0000000000000086<br />
using LZMA<br />
[ 0x80008000, 80009000, 0x80009000) <- 8002b80d<br />
dest 0000000080008000, end 0000000080009000, bouncebuffer bffb6000<br />
Loading Segment: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
lb: [0x0000000080832000, 0x0000000080844c18)<br />
Post relocation: addr: 0x0000000081000000 memsz: 0x00000000003314c8 filesz: 0x000000000011cc3d<br />
using LZMA<br />
[ 0x81000000, 813314c8, 0x813314c8) <- 8002b893<br />
dest 0000000081000000, end 00000000813314c8, bouncebuffer bffb6000<br />
Loaded segments<br />
Jumping to boot code at 0000000080000000(00000000bffdc000)<br />
CPU0: stack: 0000000080800000 - 0000000080810000, lowest used address 0000000080800004, stack used: 65532 bytes<br />
handle_command([255,255,80203a00])<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv<br />
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvv <br />
rr vvvvvvvvvvvvvvvvvvvvvvvv rr<br />
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr<br />
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr<br />
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr<br />
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr<br />
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr<br />
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr<br />
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr<br />
<br />
INSTRUCTION SETS WANT TO BE FREE<br />
[ 0.000000] Linux version 4.6.3 (jn@latitude) (gcc version 6.1.0 (coreboot toolchain v1.40 May 4th, 2016) ) #1 Sun Jun 26 02:48:43 CEST 2016<br />
[ 0.000000] Available physical memory: 2044MB<br />
[ 0.000000] Zone ranges:<br />
[ 0.000000] Normal [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Movable zone start for each node<br />
[ 0.000000] Early memory node ranges<br />
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000ffdfffff]<br />
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 516110<br />
[ 0.000000] Kernel command line: <br />
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)<br />
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)<br />
[ 0.000000] Sorting __ex_table...<br />
[ 0.000000] Memory: 2058448K/2093056K available (1952K kernel code, 104K rwdata, 396K rodata, 64K init, 221K bss, 34608K reserved, 0K cma-reserved)<br />
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1<br />
[ 0.000000] NR_IRQS:0 nr_irqs:0 0<br />
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns<br />
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)<br />
[ 0.000000] pid_max: default: 32768 minimum: 301<br />
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)<br />
[ 0.000000] devtmpfs: initialized<br />
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns<br />
[ 0.000000] NET: Registered protocol family 16<br />
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource<br />
[ 0.000000] NET: Registered protocol family 2<br />
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)<br />
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)<br />
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)<br />
[ 0.000000] NET: Registered protocol family 1<br />
[ 0.010000] console [sbi_console0] enabled<br />
[ 0.010000] futex hash table entries: 256 (order: 0, 6144 bytes)<br />
[ 0.010000] workingset: timestamp_bits=61 max_order=19 bucket_order=0<br />
[ 0.020000] jitterentropy: Initialization failed with host not compliant with requirements: 2<br />
[ 0.020000] io scheduler noop registered<br />
[ 0.020000] io scheduler cfq registered (default)<br />
[ 0.020000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6<br />
[ 0.020000] Please append a correct "root=" boot option; here are the available partitions:<br />
[ 0.020000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
[ 0.020000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.3 #1<br />
[ 0.020000] Call Trace:<br />
[ 0.020000] [<ffffffff80011f5c>] walk_stackframe+0x0/0xc8<br />
[ 0.020000] [<ffffffff80053a00>] panic+0xe0/0x1f4<br />
[ 0.020000] [<ffffffff8000115c>] mount_block_root+0x234/0x310<br />
[ 0.020000] [<ffffffff800013f0>] prepare_namespace+0x138/0x188<br />
[ 0.020000] [<ffffffff80000d48>] kernel_init_freeable+0x1b0/0x1e8<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff801f41c0>] kernel_init+0x10/0x110<br />
[ 0.020000] [<ffffffff801f41ac>] rest_init+0x7c/0x80<br />
[ 0.020000] [<ffffffff80010bdc>] ret_from_syscall+0x10/0x14<br />
[ 0.020000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)<br />
</code></div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19439
Board:emulation/spike-riscv
2016-06-30T01:39:14Z
<p>Jn: /* Build instructions */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
The instructions are also not yet complete.<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/| 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/| 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* You need the following patches:<br />
** [https://review.coreboot.org/#/c/15290/| 15290: change all eret instructions to mret]<br />
** [https://review.coreboot.org/#/c/15289/| 15289: Remove HTIF and SBI related code]<br />
** [https://review.coreboot.org/#/c/15288/| 15288: Provide a tohost symbol so Spike doesn't hang]<br />
** [https://review.coreboot.org/#/c/15284/| 15284: Move CBMEM into RAM]<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above, and select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
===boot log===<br />
<br />
<code><br />
TODO<br />
</code></div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19438
Board:emulation/spike-riscv
2016-06-30T01:11:08Z
<p>Jn: /* Building the toolchain */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply the following patches:<br />
** [https://review.coreboot.org/#/c/14604/| 14604: xcompile: rename riscv to riscv64]<br />
** [https://review.coreboot.org/#/c/14257/| 14257: buildgcc: Update to GCC 6.1.0, and binutils riscv update].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* You need the following patches:<br />
** [https://review.coreboot.org/#/c/15290/| 15290: change all eret instructions to mret]<br />
** [https://review.coreboot.org/#/c/15289/| 15289: Remove HTIF and SBI related code]<br />
** [https://review.coreboot.org/#/c/15288/| 15288: Provide a tohost symbol so Spike doesn't hang]<br />
** [https://review.coreboot.org/#/c/15284/| 15284: Move CBMEM into RAM]<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above, and select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
===boot log===<br />
<br />
<code><br />
TODO<br />
</code></div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19437
Board:emulation/spike-riscv
2016-06-30T01:08:08Z
<p>Jn: /* Building coreboot without a payload */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply [https://review.coreboot.org/#/c/14604/ this patch] and [https://review.coreboot.org/#/c/14257 this patch].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* You need the following patches:<br />
** [https://review.coreboot.org/#/c/15290/| 15290: change all eret instructions to mret]<br />
** [https://review.coreboot.org/#/c/15289/| 15289: Remove HTIF and SBI related code]<br />
** [https://review.coreboot.org/#/c/15288/| 15288: Provide a tohost symbol so Spike doesn't hang]<br />
** [https://review.coreboot.org/#/c/15284/| 15284: Move CBMEM into RAM]<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above, and select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
===boot log===<br />
<br />
<code><br />
TODO<br />
</code></div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19434
Board:emulation/spike-riscv
2016-06-29T23:29:26Z
<p>Jn: /* Building coreboot with bbl */</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply [https://review.coreboot.org/#/c/14604/ this patch] and [https://review.coreboot.org/#/c/14257 this patch].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* TODO: patch patch patch<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above, and select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
* run <code>make</code> and the <code>make-spike-elf.sh</code> script as described above<br />
<br />
===boot log===<br />
<br />
<code><br />
TODO<br />
</code></div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=19431
Board:emulation/spike-riscv
2016-06-29T22:40:46Z
<p>Jn: Build instructions</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator. The Spike support in coreboot is mostly being developed by [[User:Jn|jn]] as part of his GSoC 2016.<br />
<br />
=Build instructions=<br />
<br />
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the [[Talk:Board:emulation/spike-riscv|discussion page]] or IRC (or just fix it).<br />
<br />
==Building the toolchain==<br />
<br />
* clone the coreboot git repository<br />
* download and apply [https://review.coreboot.org/#/c/14604/ this patch] and [https://review.coreboot.org/#/c/14257 this patch].<br />
* run <code>make crossgcc-riscv</code> and a have a cup of $BEVERAGE<br />
<br />
==Building spike==<br />
<br />
* download Spike from https://github.com/riscv/riscv-isa-sim<br />
* download and apply [https://github.com/neuschaefer/riscv-isa-sim/commit/664118976cd487c9dec8cc6b5b3b9d52bd3f861c this patch that implements an 8250 UART]<br />
* TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes<br />
* TODO: running make<br />
<br />
==Building coreboot without a payload==<br />
<br />
* TODO: patch patch patch<br />
* run <code>make menuconfig</code> and select <tt>Emulation</tt>/<tt>SPIKE ucb riscv</tt> from the Mainboard menu<br />
* run <code>make</code><br />
* run <code>util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf</code> to create an ELF file (spike can only load ELF files)<br />
* run <code>spike build/coreboot.elf</code><br />
<br />
For general spike usage, look at [https://github.com/riscv/riscv-isa-sim/ its GitHub page].<br />
<br />
==Building Linux==<br />
<br />
* <code>git clone https://github.com/riscv/riscv-linux</code><br />
* download linux 4.6.x from [https://kernel.org kernel.org]<br />
* <code>cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .</code><br />
* <code>make ARCH=riscv defconfig</code><br />
* <code>make ARCH=riscv menuconfig</code>, configure <tt>General setup/Cross-compiler tool prefix</tt><br />
* <code>make ARCH=riscv</code><br />
<br />
==Building bbl==<br />
<br />
* TODO: libc stuff<br />
* TODO: payload linker script foo<br />
* TODO: patching the console output handler<br />
* mkdir build<br />
* cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld<br />
* make<br />
<br />
==Building coreboot with bbl==<br />
<br />
* apply the same coreboot patches as above, and select <tt>Emulation</tt>/<tt>Spike ucb riscv</tt><br />
* in the Payload menu of <code>menuconfig</code>, select "ELF Payload" and enter the path to the bbl binary<br />
<br />
Block devices currently missing<br />
<br />
===boot log===<br />
<br />
<code><br />
TODO<br />
</code></div>
Jn
https://www.coreboot.org/index.php?title=User:Jn&diff=19428
User:Jn
2016-06-29T21:52:43Z
<p>Jn: </p>
<hr />
<div></div>
Jn
https://www.coreboot.org/index.php?title=User:Jn&diff=19427
User:Jn
2016-06-29T21:47:38Z
<p>Jn: </p>
<hr />
<div></div>
Jn
https://www.coreboot.org/index.php?title=Talk:Board:emulation/spike-riscv&diff=19426
Talk:Board:emulation/spike-riscv
2016-06-29T21:41:26Z
<p>Jn: Created page with "* dummy entry"</p>
<hr />
<div>* dummy entry</div>
Jn
https://www.coreboot.org/index.php?title=User:Jn&diff=18867
User:Jn
2016-06-02T01:32:26Z
<p>Jn: </p>
<hr />
<div></div>
Jn
https://www.coreboot.org/index.php?title=User:Jn&diff=18827
User:Jn
2016-05-31T11:22:49Z
<p>Jn: </p>
<hr />
<div></div>
Jn
https://www.coreboot.org/index.php?title=User:Jn&diff=18826
User:Jn
2016-05-31T11:11:36Z
<p>Jn: Created page with "Full name: Jonathan Neuschäfer ==GSoC 2016== During this year's Google Summer of Code, I'm working on improving coreboot's support for RISC-V systems. This involves: - Get..."</p>
<hr />
<div></div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=18825
Board:emulation/spike-riscv
2016-05-31T11:05:13Z
<p>Jn: Link to the RISCV.org spike tool page instead of spike's github repo</p>
<hr />
<div>[https://riscv.org/software-tools/risc-v-isa-simulator/ SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator.</div>
Jn
https://www.coreboot.org/index.php?title=Board:emulation/spike-riscv&diff=18824
Board:emulation/spike-riscv
2016-05-31T11:02:36Z
<p>Jn: Created page with "[https://github.com/riscv/riscv-isa-sim SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator."</p>
<hr />
<div>[https://github.com/riscv/riscv-isa-sim SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator.</div>
Jn