https://www.coreboot.org/api.php?action=feedcontributions&user=Leio&feedformat=atomcoreboot - User contributions [en]2024-03-28T13:38:52ZUser contributionsMediaWiki 1.40.0https://www.coreboot.org/index.php?title=User:Leio&diff=12156User:Leio2013-09-11T10:46:15Z<p>Leio: </p>
<hr />
<div>Mart Raudsepp, Povi Software LLC</div>Leiohttps://www.coreboot.org/index.php?title=AMD_Geode_Porting_Guide&diff=9639AMD Geode Porting Guide2010-05-05T08:44:29Z<p>Leio: Update Geode LX CPU databook link to newest revision. Most prominently G rev changed MC_CF8F_DATA::REORDER_DIS desc and H rev added LX600/DDR2 information and tweaked MC_CF1017_DATA::WR2DAT desc</p>
<hr />
<div>Welcome! This is a collection on information to help you on your way to porting coreboot to an AMD Geode platform. Most of the information is about the Geode LX and CS5536 but may also be relevant to older versions of Geode. (Note that this does not cover the Geode NX).<br />
<br />
If you find something incorrect or other deficiencies in this information please fix them!<br />
<br />
== Documentation ==<br />
* [[Development Guidelines]]<br />
* [[Developer Manual]]<br />
* Many Geode LX systems are based on the [http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_13022%5E13060,00.html DB800 reference design], so that is a good place to start.<br />
* [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234H_LX_databook.pdf Geode LX CPU databook]<br />
* [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33238G_cs5536_db.pdf Geode CS5536 Southbridge databook]<br />
* [http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_13022%5E11363,00.html Geode Linux webpage] - The VSA and GeodeROM Porting guides are interesting.<br />
* [http://linuxbios.org/images/8/88/Crouse-Reprint.pdf Breaking the Chains -- Using LinuxBIOS to Liberate Embedded x86 Processors] - was heavily influenced by the experience of the initial Geode LX port.<br />
<br />
== Build coreboot for Geode ==<br />
Use [[Buildrom|buildrom]]. It can handle the payload and VSA for you.<br />
<br />
$ svn co svn://coreboot.org/buildrom<br />
<br />
Checkout coreboot:<br />
<br />
$ svn co svn://coreboot.org/coreboot/trunk coreboot<br />
<br />
Build a db800 for starters and set buildrom to build your local svn directory in menuconfig.<br />
<br />
$ make menuconfig<br />
$ make<br />
<br />
From this point you can customize the db800 and then make the target, mainboard, and buildrom customization patches later. <br />
<br />
==== Manual build ====<br />
If you really want to get your hands dirty. Roll up your sleeves...<br />
<br />
Go get the current VSA binary, '''gpl_vsa_lx_102.bin.gz''', hosted by [[User:MJones|MJones]] [http://marcjonesconsulting.com/gplvsa/gpl_vsa_lx_102.bin.gz here]. Older versions like '''amd_vsa_lx_1.01.bin.gz''' are still available [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.01.bin.gz here] and extract it. It will need to be compressed and padded to make the correct ROM size. For a typical Geode platform the binary should be 36KB. Calculate the padding as follows: 36864 - size of lx_vsa.nrv2b = padding. The current image requires padding of 3264.<br />
<br />
Then, find a [[Payloads|payload]] and build it.<br />
<br />
$ cd coreboot/targets<br />
$ ./buildtarget amd/db800<br />
$ cd amd/db800/db800<br />
$ cp /from/someplace/payloadx ./payload.elf<br />
$ make<br />
$ cp /from/someplace/gpl_vsa_lx_102.bin .<br />
$ fallback/nrv2b e gpl_vsa_lx_102.bin lx_vsa.nrv2b<br />
$ dd if=/dev/zero of=padding bs=1 count=3264 <br />
$ cat lx_vsa.nrv2b padding > lx_vsa.36k.bin<br />
$ cat lx_vsa.36k.bin db800.rom > amd-db800.rom<br />
<br />
You should now have a 512KB ROM image. You should be able to use [[flashrom]] or a ROM programmer to get the image onto your system. (Be prepared to brick it...)<br />
<br />
The current GPL VSA source is hosted by coreboot.org, <code>svn://coreboot.org/vsa/trunk/gplvsa2</code>.<br />
The original source is still available on [http://dev.laptop.org/git?p=geode-vsa;a=tree;h=10f157122acaae414431c88a2403ed692453c960;hb=10f157122acaae414431c88a2403ed692453c960 laptop.org].<br />
<br />
Although not currently functional: [[OpenVSA]] aims to provide VSA buildable with open tools.<br />
<br />
== Porting ==<br />
Now that you are building Geode coreboot images you are ready to make customizations to your platform. Most customizations can be handled in the mainboard directory.<br />
<br />
$ cd coreboot-v2/src/mainboard/amd/db800<br />
<br />
Make yourself familiar with this directory. There are not too many files.<br />
<br />
=== IRQ routing ===<br />
Almost every platform will require customization of the PIR table in '''irq_table.c'''.<br />
<br />
Make yourself familiar with the [http://www.microsoft.com/whdc/archive/pciirq.mspx PIR table specification].<br />
<br />
If you have the motherboard schematics adjusting the table is fairly simple. <br />
<br />
First check how many on board devices (including PCI slots) and update '''IRQ_SLOT_COUNT''' in Options.lb. Remember any time you change Options.lb or Config.lb you need to redo ./buildtarget.<br />
<br />
Next check the INT lines (GPIOs) into the CS5536.<br />
<br />
{| border="1"<br />
|+ CS5536<br />
! line !! CS5536 signal/pin <br />
|-<br />
! PCI$INTA_X<br />
| GPIO0 / INTA_L<br />
|-<br />
! PCI$INTB_X<br />
| GPIO7 / INTB_X <br />
|-<br />
! PCI$INTC_X <br />
| GPIO12 / INTR <br />
|-<br />
! PCI$INTD_X<br />
| GPIO13 / 8MI_L<br />
|}<br />
<br />
Based on this information you can setup the<br />
register "enable_gpio_int_route" = "0x0D0C0700"<br />
line in Config.lb.<br />
<br />
For each motherboard device check the INT pins. For example a PCI slot would look something like this:<br />
{| border="1"<br />
|+ PCI slot<br />
! pin !! device !! line <br />
|-<br />
! pin A6<br />
| INTA_X || PCI$INTB_X <br />
|-<br />
! pin A7<br />
| INTC_X || PCI$INTD_X <br />
|-<br />
! pin B7<br />
| INTB_X || PCI$INTC_X <br />
|-<br />
! pin B8<br />
| INTD_X || PCI$INTA_X <br />
|}<br />
<br />
Take a closer look at irq_tables.c.<br />
L_PIRQA is the chipset incoming IRQ line and M_PIRQA is the bitmap of IRQ numbers it can generate. These should not change. You can adjust the IRQs generated by changing PIRQA etc. Yes, it is fine if they all share 10 or 11 but it might be easier to debug if they all have a different IRQ.<br />
<br />
The table entries are the slot/device IRQ lines. I will break one entry down.<br />
<br />
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br />
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */<br />
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */<br />
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */<br />
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */<br />
<br />
I will break the last entry down.<br />
<br />
* '''0x00, (0x0E << 3) | 0x0''' &mdash; slot(device) address (IDSEL)<br />
* '''{L_PIRQC, M_PIRQC}''' &mdash; slot INT line A to chipset INT line C (L_PIRQC), it can generate IRQs (M_PIRQC)<br />
* '''{L_PIRQD, M_PIRQD}''' &mdash; slot INT line B to chipset INT line C (L_PIRQD), it can generate IRQs (M_PIRQD)<br />
* '''{L_PIRQA, M_PIRQA}''' &mdash; slot INT line C to chipset INT line A...<br />
* '''{L_PIRQB, M_PIRQB}''' &mdash; slot INT lineD to chipset INT line B...<br />
* '''0x1''' &mdash; arbitrary slot number<br />
* '''0x0''' &mdash; rfu, always 0<br />
<br />
If you don't have the schematics you will have to figure out the routing on your own. With '''lspci''' output and some trial and error you can figure it out. [[IRC]] or the [[Mailinglist|mailing list]] is a good place to get help if you are stuck.<br />
<br />
There's also a wiki entry on [[Creating Valid IRQ Tables|figuring out the routing table]].<br />
<br />
==== LPC Serial IRQs ====<br />
IRQs from [http://en.wikipedia.org/wiki/Low_Pin_Count LPC] need to be passed to the SC5536 [http://en.wikipedia.org/wiki/Intel_8259 PIC]. It is important to only enable the expected sources and to configure the polarity. Enables are a bit mask. It depends on the [http://en.wikipedia.org/wiki/Super_I/O SIO] but typically, the polarity is the inverse of the enables as you can see in the example below. (Note that the Geode MFGPT driver uses IRQ7 by default. That will conflict with LPC SIRQ for the LPT port if you require it.)<br />
<br />
Config.lb - <br />
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK<br />
register "lpc_serirq_enable" = "0x0000105a"<br />
register "lpc_serirq_polarity" = "0x0000EFA5"<br />
register "lpc_serirq_mode" = "1"<br />
<br />
=== Memory ===<br />
On some systems the memory is soldered down and there is no SPD (Serial Presence Detect) which is required to properly setup DDR memory. In this case you will need to provide an SPD values in coreboot. This should be done by customizing '''spd_read_byte()''' in '''cache_as_ram_auto.c''' to do a table lookup. A good example can be found in [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c src/mainboard/pcengines/alix1c/cache_as_ram_auto.c].<br />
<br />
=== Power button ===<br />
By default the CS5536 code sets the power button up for the '''4 second soft off setting'''. If your system is booting and shuts off after four seconds check for a power button enable jumper. If your system doesn't have a power button and comes on when plugged in you will need to adjust the power button MSR. This is best done in cache_as_ram_main() in cache_as_ram_auto.c after the call to cs5536_early_setup(). The MSR name is PM Fail-Safe Delay and Enable (PM_FSD). (Yes, this could be made a Config.lb option)<br />
<br />
Add the following line:<br />
outl(0x00, PMS_IO_BASE + 0x40); // disable the power button<br />
<br />
=== Graphics ===<br />
For Geode graphics, use the upstreamed [http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=tree;f=drivers/video/geode;h=e680c13755a7bfd9fb40d7f41cb7b30b033fdd67;hb=HEAD Geode framebuffer driver] and the [http://gitweb.freedesktop.org/?p=xorg/driver/xf86-video-amd.git;a=summary Geode X driver]. There is no VGA ROM for Geode at this time.<br />
<br />
=== Debug ===<br />
<br />
==== Serial Output ====<br />
The Geode CS5536 has two serial ports but on many mainboards the SIO serial ports are used instead. Setup Config.lb and the serial initialization depending on the configuration of the mainboard.<br />
<br />
Config.lb -<br />
register "com1_enable" = "1"<br />
register "com1_address" = "0x3F8"<br />
register "com1_irq" = "4"<br />
register "com2_enable" = "1"<br />
register "com2_address" = "0x2F8"<br />
register "com2_irq" = "3"<br />
<br />
In this [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb case] ''' "1" ''' enables the CS5536 serial port and the address and irq are setup to these values. The other important part of serial output is to setup the ports very early. This is done in [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/amd/norwich/cache_as_ram_auto.c cache_as_ram_main()].<br />
<br />
For an example of using the SIO serial ports instead of the CS5536, see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb DB800 mainboard].<br />
<br />
==== Dump System Configuration ====<br />
'''print_conf()''' in [http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c#L125 src/northbridge/amd/lx/northbridge.c] can help provide a good picture of the system configuration and should be one of the first tools you use to debug memory or other configuration issues.<br />
<br />
=== Other ===<br />
What are we missing?<br />
<br />
{{GPL}}</div>Leiohttps://www.coreboot.org/index.php?title=Artec_Group_DBE62&diff=8236Artec Group DBE622009-04-02T13:16:56Z<p>Leio: /* Notes */ The binary is not gotten from the AMD site anymore, so tweak the wording regarding that. Also tweak wording in relation to it not being a binary blob, because we have GPL source of it.</p>
<hr />
<div>This page is work in progress.<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = <br />
|CPU_L2_status = <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status =<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status =<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = N/A<br />
|USB_status =<br />
|Onboard_VGA_status =<br />
|Onboard_ethernet_status = <br />
|Onboard_audio_status =<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status =<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = <br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = <br />
|Watchdog_status = <br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = <br />
|Powersave_status = <br />
|ACPI_status = <br />
|Reboot_status = <br />
|Poweroff_status = <br />
|LEDs_status = <br />
|HPET_status = <br />
|RNG_status = <br />
|WakeOnModem_status = N/A <br />
|WakeOnLAN_status = <br />
|WakeOnKeyboard_status =<br />
|WakeOnMouse_status =<br />
|Smartcard_status = N/A<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Notes ==<br />
<br />
This board still needs an additional component, called the VSA.<br />
For coreboot-v3 build as dbe62.<br />
Then add the VSA. You can download a pre-compiled VSA binary from [http://marcjonesconsulting.com/gplvsa/gpl_vsa_lx_102.bin.gz here].<br />
You need to uncompress it. It should be 57504 bytes in size and the MD5 hash should be '''0ed45c3844bc38ffb0f8c84315cfb91b'''.<br />
The source code for this binary is available from svn://coreboot.org/vsa over subversion.<br />
<br />
Copy that file into the root of your build system and execute the following command after coreboot is built and before you flash it.<br />
<br />
$ build/util/lar/lar -C lzma -a build/bios.bin ./gpl_vsa_lx_102.bin:blob/vsa<br />
<br />
It is also a good idea to zero-fill the LAR archive before considering it a final image, to greatly improve boot time:<br />
<br />
$ build/util/lar/lar -z build/bios.bin<br />
<br />
{{GPL}}</div>Leiohttps://www.coreboot.org/index.php?title=Artec_Group_DBE62&diff=8235Artec Group DBE622009-04-02T13:08:05Z<p>Leio: /* Notes */ Update VSA2 link and information to version 1.02 for NAND fixes and add information about zero-filling LAR</p>
<hr />
<div>This page is work in progress.<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = <br />
|CPU_L2_status = <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status =<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status =<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = N/A<br />
|USB_status =<br />
|Onboard_VGA_status =<br />
|Onboard_ethernet_status = <br />
|Onboard_audio_status =<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status =<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = <br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = <br />
|Watchdog_status = <br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = <br />
|Powersave_status = <br />
|ACPI_status = <br />
|Reboot_status = <br />
|Poweroff_status = <br />
|LEDs_status = <br />
|HPET_status = <br />
|RNG_status = <br />
|WakeOnModem_status = N/A <br />
|WakeOnLAN_status = <br />
|WakeOnKeyboard_status =<br />
|WakeOnMouse_status =<br />
|Smartcard_status = N/A<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
== Notes ==<br />
<br />
This board still needs a binary blob from AMD called VSA.<br />
For coreboot-v3 build as dbe62.<br />
Then add the VSA. You can download the VSA blob from [http://marcjonesconsulting.com/gplvsa/gpl_vsa_lx_102.bin.gz here].<br />
You need to uncompress it. It should be 57504 bytes in size and the MD5 hash should be '''0ed45c3844bc38ffb0f8c84315cfb91b'''.<br />
<br />
Copy that file into the root of your build system and execute the following command after coreboot is built and before you flash it.<br />
<br />
$ build/util/lar/lar -C lzma -a build/bios.bin ./gpl_vsa_lx_102.bin:blob/vsa<br />
<br />
It is also a good idea to zero-fill the LAR archive before considering it a final image, to greatly improve boot time:<br />
<br />
$ build/util/lar/lar -z build/bios.bin<br />
<br />
{{GPL}}</div>Leiohttps://www.coreboot.org/index.php?title=FlexyICE&diff=7364FlexyICE2008-11-07T09:59:39Z<p>Leio: Update section about SPI booting</p>
<hr />
<div>This page is maintained by Ward Vandewege (ward at gnu dot org).<br />
<br />
== About the dongle ==<br />
<br />
The dongle is for sale by [http://www.artecgroup.com/products/hardware-products/programmable-lpc-dongle.html Artecgroup], based in Estonia. It costs about EUR 150 (2007-12).<br />
<br />
The dongle connects to a computer via USB. It connects to the target via an LPC header. <br />
<br />
The dongle comes with [http://opencores.org/projects.cgi/web/usb_dongle_fpga/overview free software and full schematics] (scroll all the way to the bottom for download links, or click on the CVS: browse link near the top). The host-based software is written in Python, and works just fine under GNU/Linux. <br />
<br />
The dongle has 16 MByte of onboard memory, divided in 4 banks of 4 Mbyte each. The 'mode-selection' jumpers allow selection of each bank: 00, 01, 10, 11.<br />
<br />
The dongle also has two 16-segment LED displays that can show POST codes.<br />
<br />
If you hold the reset button on the dongle, the second LED will show the version of the VHDL you have - currently 03, 04 or 05.<br />
<br />
Artecgroup provides [http://opencores.org/cvsweb.shtml/usb_dongle_fpga/release/EPCS_update_tool.zip a tool] to upgrade the VHDL on the dongle that can be run under GNU/Linux (it's a python program). They also provide the binary image for the v5 of the VHDL. Of course all sources are available to build that binary image, but currently proprietary software on Windows is needed to do so. You will need a byteblaster-II cable (which can be purchased at http://www.customcircuitsolutions.com/cable.html or http://fpgaguy.110mb.com/, for instance). This tool has only received limited testing, so please be careful and report any problems to the author.<br />
<br />
== Using the dongle ==<br />
=== Drivers for Windows ===<br />
The dongle can be accessed using its usb-to-serial chip (FT245B(M)). For Windows, you need a driver to map it to a COM-port, which can be found at the [http://www.ftdichip.com/Drivers/VCP.htm chip vendor's website].<br />
<br />
=== Reading from and writing to the dongle ===<br />
<br />
If you use Ubuntu, make sure to uninstall brltty (apt-get remove brltty --purge) before you hook up the dongle; otherwise it will hijack the dongle and you won't be able to talk to it. Brltty is a software braille terminal.<br />
<br />
Images are downloaded via USB. With the latest version of the VHDL (v5), it should take about 8 seconds to write a 512KByte image to the dongle.<br />
<br />
Here's a command that writes a 512KByte image to the dongle<br />
<br />
./dongle.py -v -c /dev/ttyUSB0 alix0-1.bin 3584K<br />
<br />
The -v parameter makes the command verbose. -c /dev/ttyUSB0 means 'use device /dev/ttyS0'. Alix0-1.bin is the image that is to be written to the dongle (it's a 512KByte file), and 3584K is the offset at which it should be written. Always calculate that number as 4Mbyte - size of your image.<br />
<br />
And here's how you can read the image back:<br />
<br />
./dongle.py -c /dev/ttyUSB0 -r 3670016 512K test2.rom <br />
<br />
The -r parameter indicates 'read', and 3670016 is the offset at which the program should start reading (this is 3584K), for 512K bytes. You can express the offset in decimal (like in this example, in hex with a leading 0x, or in abbreviated decimal - for instance 3584K). Test2.rom is the file the image will be stored in on your computer.<br />
<br />
If you actually wrote and read an image, you should now md5sum both files to make sure they are identical.<br />
<br />
=== Booting an ALIX.1C ===<br />
<br />
First of all, you'll need to make a custom cable. The ALIX.1C has a 20-pin header (J16) that can be used to hook up the dongle. The pin layout is documented on page 13 and 14 in the [http://pcengines.ch/pdf/alix1c.pdf ALIX.1C manual]:<br />
<br />
<pre><br />
1 LCLK0 LPC clock (33 MHz)<br />
2 GND ground<br />
3 LAD0 LPC data 0<br />
4 GND ground<br />
5 LAD1 LPC data 1<br />
6 GND ground<br />
7 LAD2 LPC data 2<br />
8 GND ground<br />
9 LAD3 LPC data 3<br />
10 GND ground<br />
11 LFRAME# LPC frame<br />
12 GND ground<br />
13 PCIRST# reset (active low)<br />
14 NC reserved<br />
15 ISP high to use LPC flash, low to use on-board flash, pulled low by resistor<br />
16 VCC +5V supply<br />
17 GND ground<br />
18 V3 +3.3V supply<br />
19 SERIRQ serial interrupt<br />
20 LDRQ# LPC DMA request<br />
</pre><br />
<br />
The Artecgroup LPC dongle has a 10-pin LPC dongle that is described [http://www.artecgroup.com/downloads/task,doc_download/gid,5/Itemid,33/ in the schematics]. This is the pin layout:<br />
<br />
<pre><br />
1 RESETX<br />
2 LAD0<br />
3 LAD1<br />
4 LAD2<br />
5 LAD3<br />
6 LFRAME#<br />
7 R33 GND<br />
8 PCICLK1<br />
9 GND<br />
10 VCC 3V in<br />
</pre><br />
<br />
Peter Stuge figured out the correct wiring [http://www.coreboot.org/pipermail/coreboot/2007-December/028011.html here] and [http://www.coreboot.org/pipermail/coreboot/2007-December/028012.html here]. This is the wiring diagram:<br />
<br />
<pre><br />
Dongle - ALIX.1C<br />
<br />
1 - 13<br />
2 - 3<br />
3 - 5<br />
4 - 7<br />
5 - 9<br />
6 - 11<br />
7 - NC<br />
8 - 1<br />
9 - 2/4/6/8/10/12/17 (just pick one)<br />
10 - NC<br />
- 15 connected to 18<br />
</pre><br />
<br />
In the above, pin 7 on the dongle should not be connected to anything on the ALIX.1C. Pin 9 on the dongle should be connected to one of 2/4/6/8/10/12/17 on the ALIX.1C, not all of those pins. Pin 15 and 18 on the ALIX.1C side need to be shorted, but not connected to anything on the dongle side.<br />
<br />
Cable length is important - your cable should not be more than a few centimeter long.<br />
<br />
The easiest way to make such a cable is to take an old floppy or IDE-40 flat ribbon cable (don't use IDE-80, its wires are much thinner which makes things harder), cut it, and put a 10-pin header on the dongle side.<br />
<br />
If you are in the US, you can buy 10-pin headers [https://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?langId=-1&storeId=10001&catalogId=10001&pa=32492&productId=32492 here] (Jameco part number 32492). You might also want to get [https://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?langId=-1&storeId=10001&catalogId=10001&pa=73252&productId=73252 a crimping tool] (Jameco part number 73252).<br />
<br />
This is what a finished cable looks like:<br />
<br />
[[Image:Dscn3151_640_480.jpg||Custom ALIX.1C to Artecgroup LPC dongle cable]]<br />
<br />
You can test your cable by booting the ALIX.1C, and then hooking it up to the dongle (using J16 on the ALIX.1C, of course). Now reboot the ALIX.1C board; the LEDs on the dongle should show post codes as the ALIX.1C shuts down and tries to boot. Unless you've prepared the dongle and stored an image into it, the ALIX.1C will not boot. But if you see POST codes on the LEDs, your cable is likely to be good. If not, use a multimeter and make sure it matches the layout above. Also make sure that it is not too long.<br />
<br />
Now make sure the dongle is correctly configured:<br />
<br />
Jump pin 1/2 on J1. Make sure JMP4 is set to position 1/2 (i.e. NOT to the pins marked as LPC). Make sure that you leave the mode select jumpers in the same position between the writing of the image into the dongle and trying to boot off it.<br />
<br />
Now write your image to the top of the memory bank you want to use (see higher). Then <i>disconnect the dongle from your computer</i>, reconnect it, make sure that you have your cable connected to the LPC port on the dongle and J16 on the ALIX.1C, and plug in power to the ALIX.1C. Also hook up a serial port to the ALIX.1C so that you see what happens during boot. If all goes well, you will see post codes on the dongle LEDs as the ALIX.1C boots.<br />
<br />
=== Booting FWH PLCC boards ===<br />
<br />
It is also possible to boot FWH PLCC boards, if you make a special cable. For an example of such a cable, see some photos here: http://www.artecdesign.ee/~martr/dongle-fwh-plcc-cable/. TODO: we need to find a place to buy such a connector, and we need to document the pinout of the cable.<br />
<br />
=== Booting SPI boards ===<br />
<br />
With a VHDL change and the proper cable, it should be possible to use the dongle to boot SPI-based boards. Artec is considering this as a planned feature for [http://www.opencores.org/projects.cgi/web/artec_dongle_ii_fpga/overview Artec Dongle II] VHDL - when that is done, interested parties can try to backport the relevant open source VHDL parts.<br />
<br />
<br />
<br />
{{GPL}}</div>Leiohttps://www.coreboot.org/index.php?title=Artec_Group_DBE62&diff=6674Artec Group DBE622008-07-01T09:05:50Z<p>Leio: Add to tutorials category</p>
<hr />
<div>This page is work in progress.<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = <br />
|CPU_L2_status = <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status =<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status =<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = N/A<br />
|USB_status =<br />
|Onboard_VGA_status =<br />
|Onboard_ethernet_status = <br />
|Onboard_audio_status =<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = Yes<br />
|COM2_status =<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = <br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = <br />
|Watchdog_status = <br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = <br />
|Powersave_status = <br />
|ACPI_status = <br />
|Reboot_status = <br />
|Poweroff_status = <br />
|LEDs_status = <br />
|HPET_status = <br />
|RNG_status = <br />
|WakeOnModem_status = N/A <br />
|WakeOnLAN_status = <br />
|WakeOnKeyboard_status =<br />
|WakeOnMouse_status =<br />
|Smartcard_status = N/A<br />
|Flashrom_status = Yes<br />
<br />
}}<br />
<br />
== Notes ==<br />
<br />
This board still needs a binary blob from AMD called VSA.<br />
For coreboot-v3 build as dbe62.<br />
Than add the VSA. You can download the VSA blob from [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.01.bin.gz here].<br />
You need to uncompress it. It should be 57504 Bytes in Size and MD5 should be 0f4fd87b3eef78bd90b56a39646f5845.<br />
<br />
Copy that file into the root of you build system and execute the following command after coreboot is build and before you flash it.<br />
<pre><br />
build/util/lar/lar -C lzma -a build/bios.bin ./amd_vsa_lx_1.01.bin:blob/vsa<br />
</pre><br />
<br />
{{GPL}}<br />
<br />
[[Category:Tutorials]]</div>Leiohttps://www.coreboot.org/index.php?title=Artec_Group_DBE62&diff=6673Artec Group DBE622008-07-01T09:04:28Z<p>Leio: Initial page for DBE62</p>
<hr />
<div>This page is work in progress.<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = <br />
|CPU_L2_status = <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status =<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status =<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
<br />
|IDE_status = N/A<br />
|IDE_25_status = N/A<br />
|IDE_CF_status = N/A<br />
|CDROM_DVD_status = N/A<br />
|SATA_status = N/A<br />
|USB_status =<br />
|Onboard_VGA_status =<br />
|Onboard_ethernet_status = <br />
|Onboard_audio_status =<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = Yes<br />
|COM2_status =<br />
|PP_status = N/A<br />
|PS2_keyboard_status = N/A<br />
|PS2_mouse_status = N/A<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = <br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = <br />
|Watchdog_status = <br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = <br />
|Powersave_status = <br />
|ACPI_status = <br />
|Reboot_status = <br />
|Poweroff_status = <br />
|LEDs_status = <br />
|HPET_status = <br />
|RNG_status = <br />
|WakeOnModem_status = N/A <br />
|WakeOnLAN_status = <br />
|WakeOnKeyboard_status =<br />
|WakeOnMouse_status =<br />
|Smartcard_status = N/A<br />
|Flashrom_status = Yes<br />
<br />
}}<br />
<br />
== Notes ==<br />
<br />
This board still needs a binary blob from AMD called VSA.<br />
For coreboot-v3 build as dbe62.<br />
Than add the VSA. You can download the VSA blob from [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.01.bin.gz here].<br />
You need to uncompress it. It should be 57504 Bytes in Size and MD5 should be 0f4fd87b3eef78bd90b56a39646f5845.<br />
<br />
Copy that file into the root of you build system and execute the following command after coreboot is build and before you flash it.<br />
<pre><br />
build/util/lar/lar -C lzma -a build/bios.bin ./amd_vsa_lx_1.01.bin:blob/vsa<br />
</pre><br />
<br />
{{GPL}}</div>Leiohttps://www.coreboot.org/index.php?title=Board:tyan/s2891&diff=6554Board:tyan/s28912008-06-02T13:45:08Z<p>Leio: Add tutorials category, so it would show up in the tutorials list, as seen by Bari</p>
<hr />
<div>===Status===<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Device/functionality<br />
! align="left" | Status<br />
! align="left" | Comments<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| CPU<br />
| style="background:lime" | Works<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| RAM<br />
| style="background:lime" | Works<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| IDE<br />
| style="background:yellow" | ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| IDE using CF-to-IDE adapter<br />
| style="background:yellow" | ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SATA<br />
| style="background:yellow" | WIP<br />
| There are issues with disk detection on the CK804 chipset. This is [http://linuxbios.org/pipermail/linuxbios/2007-September/024937.html being investigated].<br />
|- bgcolor="#eeeeee" valign="top"<br />
| USB<br />
| style="background:yellow" | ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| On-board ethernet<br />
| style="background:lime" | Works<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| PCI add-on cards<br />
| style="background:yellow" | ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| PCI Express add-on cards<br />
| style="background:yellow" | ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Floppy<br />
| style="background:yellow" | ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Serial port (COM1)<br />
| style="background:lime" | Works<br />
| Serial console for coreboot and Linux is fully operational.<br />
|- bgcolor="#eeeeee" valign="top"<br />
| PS/2 keyboard<br />
| style="background:lime" | Works<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| PS/2 mouse<br />
| style="background:yellow" | ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Mainboard sensors/fans<br />
| style="background:yellow" | ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| CPU frequency scaling / powersave modes<br />
| style="background:yellow" | ?<br />
| Probably won't work as long as there's no ACPI implementation for this board(?)<br />
|- bgcolor="#eeeeee" valign="top"<br />
| [[Flashrom]]<br />
| style="background:lime" | Works<br />
| &mdash;<br />
|}<br />
<br />
===Before you begin===<br />
<br />
Do yourself a favor, and get a BiosSavior before you begin. There are different models, make sure you order the one you need. It depends on the size and type of the ROM chip on your board. Our S2891 board has an 8Mbit PLCC chip. This is the list of BiosSavior vendors:<br />
<br />
http://www.ioss.com.tw/web/English/WheretoBuy.html<br />
<br />
Unfortunately the largest BiosSavior of the PMC type is only 512Kbyte; the proprietary BIOS is 1024Kbyte large. You can build a coreboot image in 512Kbyte, so this should not be a problem; you may want to buy a couple of extra 1Mbyte PLCC chips to save a copy of the original BIOS, and put it somewhere safe.<br />
<br />
While coreboot replaces the functions of the proprietary BIOS, it does ''not'' replace the VGA BIOS. If you want VGA on your corebooted machine (not strictly necessary for servers), you will need to extract the VGA BIOS and concatenate it with the coreboot image, before burning it to your ROM. See below for details.<br />
<br />
This wiki page is maintained by Ward Vandewege (ward at gnu dot org).<br />
<br />
===Hardware===<br />
<br />
The S2891 comes with a 8Mbit BIOS chip (SST 49LF080A). This is sufficient to have a fully functional coreboot with FILO or LAB payload, as described below.<br />
<br />
===Payload===<br />
<br />
coreboot requires a [[Payloads|payload]] to boot an operating system.<br />
<br />
If you want to boot from the network, you will need to use [http://www.etherboot.org Etherboot]. <br />
<br />
If you want to boot from an IDE drive, USB stick or CDROM, you can use [[FILO]].<br />
<br />
Booting from SATA is a bit harder; the CK804 chipset on this board does not support a legacy IDE mode, so FILO and Etherboot [http://linuxbios.org/pipermail/linuxbios/2006-May/014654.html can not boot directly from SATA].<br />
<br />
In order to boot from SATA, we need to use 'linux-as-a-bootloader' (LAB) as a payload. You will need a 1MB ROM chip (thankfully the S2891 comes with a 1MB ROM chip) for this payload. It consists of a (stripped down) kernel + busybox, which can then be used to kexec a kernel from disk. If your disks are playing up, you will still have a busybox environment on boot, which could be useful for debugging.<br />
<br />
=== Building the payload ===<br />
<br />
You can build a coreboot image with a kconfig-style configuration tool (buildrom) if you want to use FILO or LAB. This is by far the easiest way to build a ROM image. <br />
<br />
===Buildrom===<br />
<br />
Check out buildrom:<br />
<br />
svn co svn://coreboot.org/buildrom<br />
<br />
Now configure buildrom:<br />
<br />
cd buildrom/buildrom-devel<br />
make menuconfig<br />
<br />
Configure to your liking. If you use the LAB payload, make sure to exclude the kexec binary and boot menu from the initramfs, otherwise your image will be too big. Please note that currently only the FILO and LAB payloads have been tested. The other payloads likely require some more work before they will be useable. Patches are welcome, of course.<br />
<br />
make<br />
<br />
If all goes well, you should now have a ROM image file <br />
<br />
deploy/tyan-s2891.rom<br />
<br />
This image will be exactly 988KB large, leaving 36KB for the VGA BIOS.<br />
<br />
====FILO payload====<br />
<br />
Skip this section if you use the LAB payload.<br />
<br />
When using FILO in GRUB emulation mode, it's important to get a few details right in your GRUB boot stanza. This is what mine looks like:<br />
<br />
title Ubuntu LB, kernel 2.6.21-rc3<br />
root (hd4,0)<br />
kernel /boot/vmlinuz-2.6.21-rc3 root=/dev/sda1 ro console=tty0 console=ttyS0,115200<br />
savedefault<br />
boot<br />
<br />
Note the root device &mdash; FILO sees the first SATA device as hd4.<br />
<br />
In order to get serial output from GRUB, you will also need to add something like this to your menu.lst:<br />
<br />
# serial port 0<br />
serial --unit=0 --speed=115200<br />
terminal --timeout=15 serial console<br />
<br />
====LAB payload====<br />
<br />
Skip this section if you use the FILO payload.<br />
<br />
The LAB payload expects a file /lab.conf on /dev/sda1 with contents like this:<br />
<br />
CMDLINE="root=/dev/sda1 ro console=tty0 console=ttyS0,115200"<br />
KERNEL="/vmlinuz-2.6.22.1"<br />
INITRD=""<br />
VT="1"<br />
<br />
This is the kernel that you will be running after boot. It will be kexec'ed by the kernel that is burned into your ROM chip.<br />
<br />
You will also need a statically linked copy of kexec, which the LAB payload expects to reside at <br />
<br />
/sbin/kexec<br />
<br />
If you are on a Debian-based system, you can easily recompile your kexec package to be statically linked by following these instructions:<br />
<br />
cd /usr/src<br />
apt-get source kexec-tools<br />
export LDFLAGS="-static"<br />
<br />
Now edit kexec-tools-1.101-kdump10/kexec-tools-1.101/kexec/Makefile, change line 53 to<br />
<br />
$(CC) $(LDFLAGS) $(KCFLAGS) -o $@ $(KEXEC_OBJS) $(UTIL_LIB) $(LIBS)<br />
<br />
(you're adding the LDFLAGS variable)<br />
<br />
cd kexec-tools-1.101-kdump10 <br />
dpkg-buildpackage -rfakeroot -b<br />
cd ..<br />
dpkg -i kexec-tools_1.101-kdump10-2ubuntu2_i386.deb<br />
<br />
Adjust the package name as necessary for your distribution. You can tell if your copy of kexec is statically linked by running 'file' on it:<br />
<br />
file /sbin/kexec <br />
<br />
If all is well, you will see something like this:<br />
<br />
/sbin/kexec: ELF 32-bit LSB executable, Intel 80386, version 1 (SYSV), for GNU/Linux 2.2.0, statically linked, for GNU/Linux 2.2.0, stripped<br />
<br />
The binary will also be considerably larger than its dynamically linked cousin.<br />
<br />
Note that you '''must''' build a 32-bit version of kexec, because buildrom puts a 32 bit kernel into the ROM image. A 32-bit kexec can kexec into a 64 bit kernel, so if your system is 64 bit this will work just fine.<br />
<br />
The LAB code currently expects lab.conf and kexec to live in / on /dev/sda1.<br />
<br />
===VGA BIOS===<br />
<br />
Skip this section if you don't need VGA support in your coreboot.<br />
<br />
The S2891 VGA BIOS is 36K long. The last 4KB are not available in RAM after boot (with the proprietary BIOS), however, so we can ''not'' use this method to extract the VGA BIOS:<br />
<br />
While booted with your proprietary BIOS, you can see where your vga bios starts <br />
and how much space it takes by issuing<br />
<code>cat /proc/iomem | grep "Video ROM"</code><br />
Then get a copy of your vga bios.<br />
<code>dd if=/dev/mem of=vgabios.bin bs=1k count=32 skip=768</code><br />
Our vga bios is 32K. Verify that the image is correct - it should start with 55 AA, <br />
and contain strings that indicate it's your VGA bios. You should be able to clearly <br />
make out 'ATI RAGE' etc.<br />
<br />
So this does not work - the last 4K is missing. Thankfully, Anton Borisov has some tools that can extract the VGA BIOS &mdash; and other option ROMs, in fact &mdash; from the BIOS images that Tyan offers on its website. <br />
<br />
You can download the tool for Phoenix here:<br />
<br />
http://www.kaos.ru/biosgfx/download/PhoenixDeco_0.33.src.tar.gz<br />
<br />
Then download the latest proprietary BIOS for the S2891 from the Tyan website:<br />
<br />
http://www.tyan.com/support_download_bios.aspx?model=S.S2891<br />
<br />
Once you have the image, you can display its contents like this:<br />
<br />
./phnxdeco 2891202T.wph -ls<br />
<br />
That should show output like:<br />
<br />
-=PhoenixDeco, version 0.33 (Linux)=-<br />
<br />
Filelength : 100756 (1050454 bytes)<br />
Filename : ../2891202T.wph<br />
PhoenixBIOS hook found at : F6FB0<br />
System Information at : F6FFE<br />
BootBlock : 7000 bytes<br />
BankSize : 1024 KB<br />
Version : DEVEL042<br />
Start : F8BB5<br />
Offset : F0000<br />
BCP Modules : 80<br />
BCPFCP : FCA73<br />
FCP 1st module : 9DD5 (F9DD5)<br />
Released : 30 November 2006 at 11:19:23<br />
/* Copyrighted Information */<br />
NAPI<br />
/* ----------------------- */<br />
<br />
================================== MODULE MAP =================================<br />
Class Code<br />
. Instance<br />
. .<br />
C I LEVEL START END LENGTH RATIO LINK TO FILEOFFSET<br />
---- ----- --------- --------- ------ ----- --------- ----------<br />
G 0 NONE FFFF 8BB5 FFFF 8FFF 430 100% FFFF 8048 F8BB5h<br />
D 0 LZINT FFFF 8048 FFFF 8BB4 B52 70% FFFF 7FDB F8048h<br />
A 1 LZINT FFFF 7FDB FFFF 8047 52 70% FFFF 7FBC F7FDBh<br />
* 0 NONE FFFF 7FBC FFFF 7FDA 4 100% FFFF 7BA3 F7FBCh<br />
B 0 LZINT FFFF 7BA3 FFFF 7FBB 3FE 3% FFFF 0E05 F7BA3h<br />
X 0 NONE FFFF 0E05 FFFF 7BA1 6D82 100% FFFE C525 F0E05h<br />
S 0 LZINT FFFE C525 FFFF 0E04 48C5 46% FFFE 8601 EC525h<br />
E 0 LZINT FFFE 8601 FFFE C524 3F09 41% FFFE 65D5 E8601h<br />
C 0 NONE FFFE 65D5 FFFE 85FF 2010 100% FFFE 0005 E65D5h<br />
X 1 NONE FFFE 0005 FFFE 644F 6430 100% FFFD A653 E0005h<br />
T 0 LZINT FFFD A653 FFFE 0004 5997 42% FFFD 365C DA653h<br />
R 0 LZINT FFFD 365C FFFD A652 6FDC 58% FFFC DAC1 D365Ch<br />
R 1 LZINT FFFC DAC1 FFFD 365B 5B80 63% FFFB 9ED0 CDAC1h<br />
R 2 LZINT FFFB 9ED0 FFFC DAC0 13BD6 61% FFFA 73D5 B9ED0h<br />
R 3 LZINT FFFA 73D5 FFFB 9ECF 12AE0 98% FFF9 48E0 A73D5h<br />
R 4 LZINT FFF9 48E0 FFFA 73D4 12ADA 98% FFF8 B14D 948E0h<br />
R 5 LZINT FFF8 B14D FFF9 48DF 9778 59% FFF8 9830 8B14Dh<br />
L 0 LZINT FFF8 9830 FFF8 B14C 1902 0% FFF8 825D 89830h<br />
M 0 LZINT FFF8 825D FFF8 982F 15B8 64% FFF8 5C92 8825Dh<br />
Q 0 LZINT FFF8 5C92 FFF8 825C 25B0 41% FFF7 F3D7 85C92h<br />
H 0 NONE FFF7 F3D7 FFF8 5C91 68A0 100% FFF7 DDF1 7F3D7h<br />
A 0 LZINT FFF7 DDF1 FFF7 F3D6 15CB 38% FFF7 766B 7DDF1h<br />
B 1 LZINT FFF7 766B FFF7 8D91 170C 25% FFF6 F699 7766Bh<br />
B 2 LZINT FFF6 F699 FFF7 766A 7FB7 73% FFF6 5694 6F699h<br />
B 3 LZINT FFF6 5694 FFF6 F698 9FEA 67% FFF5 A1F3 65694h<br />
B 4 LZINT FFF5 A1F3 FFF6 5693 B486 71% FFF5 917A 5A1F3h<br />
B 5 LZINT FFF5 917A FFF5 A1F2 105E 68% FFF5 8477 5917Ah<br />
B 6 LZINT FFF5 8477 FFF5 9179 CE8 67% 0000 0000 58477h<br />
Total Sections: 28<br />
<br />
Now extract all these parts:<br />
<br />
./phnxdeco 2891202T.wph -xs<br />
<br />
That will create a number of new files:<br />
<br />
-rw-r--r-- 1 ward ward 14643 2007-06-20 15:16 ACPI0.rom<br />
-rw-r--r-- 1 ward ward 116 2007-06-20 15:16 ACPI1.rom<br />
-rw-r--r-- 1 ward ward 28672 2007-06-20 15:16 bb.rom<br />
-rw-r--r-- 1 ward ward 33913 2007-06-20 15:16 BIOSCOD0.rom<br />
-rw-r--r-- 1 ward ward 22987 2007-06-20 15:16 BIOSCOD1.rom<br />
-rw-r--r-- 1 ward ward 44635 2007-06-20 15:16 BIOSCOD2.rom<br />
-rw-r--r-- 1 ward ward 60875 2007-06-20 15:16 BIOSCOD3.rom<br />
-rw-r--r-- 1 ward ward 64891 2007-06-20 15:16 BIOSCOD4.rom<br />
-rw-r--r-- 1 ward ward 6123 2007-06-20 15:16 BIOSCOD5.rom<br />
-rw-r--r-- 1 ward ward 4907 2007-06-20 15:16 BIOSCOD6.rom<br />
-rw-r--r-- 1 ward ward 1099 2007-06-20 15:16 DECOMPC0.rom<br />
-rw-r--r-- 1 ward ward 4128 2007-06-20 15:16 DISPLAY0.rom<br />
-rw-r--r-- 1 ward ward 787512 2007-06-20 15:16 LOGO0.rom<br />
-rw-r--r-- 1 ward ward 8576 2007-06-20 15:16 MISER0.rom<br />
-rw-r--r-- 1 ward ward 49152 2007-06-20 15:16 OPROM0.rom<br />
-rw-r--r-- 1 ward ward 36864 2007-06-20 15:16 OPROM1.rom<br />
-rw-r--r-- 1 ward ward 131072 2007-06-20 15:16 OPROM2.rom<br />
-rw-r--r-- 1 ward ward 77824 2007-06-20 15:16 OPROM3.rom<br />
-rw-r--r-- 1 ward ward 77824 2007-06-20 15:16 OPROM4.rom<br />
-rw-r--r-- 1 ward ward 65536 2007-06-20 15:16 OPROM5.rom<br />
-rw-r--r-- 1 ward ward 28061 2007-06-20 15:16 ROMEXEC0.rom<br />
-rw-r--r-- 1 ward ward 25675 2007-06-20 15:16 ROMEXEC1.rom<br />
-rw-r--r-- 1 ward ward 1234 2007-06-20 15:16 rom.scr<br />
-rw-r--r-- 1 ward ward 39110 2007-06-20 15:16 SETUP0.rom<br />
-rw-r--r-- 1 ward ward 40396 2007-06-20 15:16 STRINGS0.rom<br />
-rw-r--r-- 1 ward ward 4 2007-06-20 15:16 TCPA_*0.rom<br />
-rw-r--r-- 1 ward ward 26784 2007-06-20 15:16 TCPA_H0.rom<br />
-rw-r--r-- 1 ward ward 23136 2007-06-20 15:16 TCPA_Q0.rom<br />
-rw-r--r-- 1 ward ward 53472 2007-06-20 15:16 TEMPLAT0.rom<br />
-rw-r--r-- 1 ward ward 8208 2007-06-20 15:16 UPDATE0.rom<br />
<br />
After a bit of fun with 'strings', we can deduce that the OPROM1.rom file contains our VGA BIOS.<br />
<br />
So, now that we have the proper VGA BIOS image (36K long), we need to concatenate the VGA BIOS with the coreboot image<br />
<br />
cat OPROM1.rom tyan-s2891.rom > final_coreboot.rom<br />
<br />
===Burning the BIOS===<br />
<br />
Make sure your BiosSavior is set to the 'RD1' position (not to 'ORG'!), so that you can always revert to the original BIOS.<br />
<br />
On the target machine:<br />
<br />
cd coreboot-v2/util/flashrom<br />
./flashrom -v -w path/to/your/final_coreboot.rom<br />
<br />
If you want VGA support, make sure you burn the final_coreboot.rom image!<br />
<br />
===Booting coreboot===<br />
<br />
You now need to 'halt' the machine. A soft reset won't work the first time you boot from the proprietary BIOS into coreboot. <br />
<br />
Since we set up serial output in the coreboot configuration files above, you will want to hook up a serial console (or a copy of minicom or the like) to see what the box is doing while starting up. Keep your eyes on the screen after hitting the power button - coreboot will be up and running way before you expect it!<br />
<br />
If you have problems, don't despair. Power down the box, switch the BiosSavior to 'ORG' and boot in the proprietary BIOS. Just don't forget to switch the BiosSavior back to the 'RD1' position before flashing the BIOS!<br />
<br />
See what went wrong, and subscribe and post to the friendly and helpful [[Mailinglist|mailing list]] if you can't figure it out by yourself.<br />
<br />
{{GPL}}<br />
[[Category:Tutorials]]</div>Leiohttps://www.coreboot.org/index.php?title=FlexyICE&diff=6207FlexyICE2008-04-09T11:35:11Z<p>Leio: Update the plcc cable link after move to a subdir. Be more correct about what information carldani has provided Artec</p>
<hr />
<div>== About this page ==<br />
<br />
This page is maintained by Ward Vandewege (ward at gnu dot org).<br />
<br />
== About the dongle ==<br />
<br />
The dongle is for sale by [http://www.artecgroup.com/products/hardware-products/programmable-lpc-dongle.html Artecgroup], based in Estonia. It costs about EUR 150 (2007-12).<br />
<br />
The dongle connects to a computer via USB. It connects to the target via an LPC header. <br />
<br />
The dongle comes with [http://opencores.org/projects.cgi/web/usb_dongle_fpga/overview free software and full schematics] (scroll all the way to the bottom for download links, or click on the CVS: browse link near the top). The host-based software is written in Python, and works just fine under GNU/Linux. <br />
<br />
The dongle has 16 MByte of onboard memory, divided in 4 banks of 4 Mbyte each. The 'mode-selection' jumpers allow selection of each bank: 00, 01, 10, 11.<br />
<br />
The dongle also has two 16-segment LED displays that can show POST codes.<br />
<br />
If you hold the reset button on the dongle, the second LED will show the version of the VHDL you have - currently 03, 04 or 05.<br />
<br />
Artecgroup provides [http://opencores.org/cvsweb.shtml/usb_dongle_fpga/release/EPCS_update_tool.zip a tool] to upgrade the VHDL on the dongle that can be run under GNU/Linux (it's a python program). They also provide the binary image for the v5 of the VHDL. Of course all sources are available to build that binary image, but currently proprietary software on Windows is needed to do so. You will need a byteblaster-II cable (which can be purchased at http://www.customcircuitsolutions.com/cable.html or http://fpgaguy.110mb.com/, for instance). This tool has only received limited testing, so please be careful and report any problems to the author.<br />
<br />
== Using the dongle ==<br />
<br />
=== Reading from and writing to the dongle ===<br />
<br />
If you use Ubuntu, make sure to uninstall brltty (apt-get remove brltty --purge) before you hook up the dongle; otherwise it will hijack the dongle and you won't be able to talk to it. Brltty is a software braille terminal.<br />
<br />
Images are downloaded via USB. With the latest version of the VHDL (v5), it should take about 8 seconds to write a 512KByte image to the dongle.<br />
<br />
Here's a command that writes a 512KByte image to the dongle<br />
<br />
./dongle.py -v -c /dev/ttyUSB0 alix0-1.bin 3584K<br />
<br />
The -v parameter makes the command verbose. -c /dev/ttyUSB0 means 'use device /dev/ttyS0'. Alix0-1.bin is the image that is to be written to the dongle (it's a 512KByte file), and 3584K is the offset at which it should be written. Always calculate that number as 4Mbyte - size of your image.<br />
<br />
And here's how you can read the image back:<br />
<br />
./dongle.py -c /dev/ttyUSB0 -r 3670016 512K test2.rom <br />
<br />
The -r parameter indicates 'read', and 3670016 is the offset at which the program should start reading (this is 3584K), for 512K bytes. You can express the offset in decimal (like in this example, in hex with a leading 0x, or in abbreviated decimal - for instance 3584K). Test2.rom is the file the image will be stored in on your computer.<br />
<br />
If you actually wrote and read an image, you should now md5sum both files to make sure they are identical.<br />
<br />
=== Booting an ALIX.1C ===<br />
<br />
First of all, you'll need to make a custom cable. The ALIX.1C has a 20-pin header (J16) that can be used to hook up the dongle. The pin layout is documented on page 13 and 14 in the [http://pcengines.ch/pdf/alix1c.pdf ALIX.1C manual]:<br />
<br />
<pre><br />
1 LCLK0 LPC clock (33 MHz)<br />
2 GND ground<br />
3 LAD0 LPC data 0<br />
4 GND ground<br />
5 LAD1 LPC data 1<br />
6 GND ground<br />
7 LAD2 LPC data 2<br />
8 GND ground<br />
9 LAD3 LPC data 3<br />
10 GND ground<br />
11 LFRAME# LPC frame<br />
12 GND ground<br />
13 PCIRST# reset (active low)<br />
14 NC reserved<br />
15 ISP high to use LPC flash, low to use on-board flash, pulled low by resistor<br />
16 VCC +5V supply<br />
17 GND ground<br />
18 V3 +3.3V supply<br />
19 SERIRQ serial interrupt<br />
20 LDRQ# LPC DMA request<br />
</pre><br />
<br />
The Artecgroup LPC dongle has a 10-pin LPC dongle that is described [http://www.artecgroup.com/downloads/task,doc_download/gid,5/Itemid,33/ in the schematics]. This is the pin layout:<br />
<br />
<pre><br />
1 RESETX<br />
2 LAD0<br />
3 LAD1<br />
4 LAD2<br />
5 LAD3<br />
6 LFRAME#<br />
7 R33 GND<br />
8 PCICLK1<br />
9 GND<br />
10 VCC 3V in<br />
</pre><br />
<br />
Peter Stuge figured out the correct wiring [http://www.coreboot.org/pipermail/coreboot/2007-December/028011.html here] and [http://www.coreboot.org/pipermail/coreboot/2007-December/028012.html here]. This is the wiring diagram:<br />
<br />
<pre><br />
Dongle - ALIX.1C<br />
<br />
1 - 13<br />
2 - 3<br />
3 - 5<br />
4 - 7<br />
5 - 9<br />
6 - 11<br />
7 - NC<br />
8 - 1<br />
9 - 2/4/6/8/10/12/17 (just pick one)<br />
10 - NC<br />
- 15 connected to 18<br />
</pre><br />
<br />
In the above, pin 7 on the dongle should not be connected to anything on the ALIX.1C. Pin 9 on the dongle should be connected to one of 2/4/6/8/10/12/17 on the ALIX.1C, not all of those pins. Pin 15 and 18 on the ALIX.1C side need to be shorted, but not connected to anything on the dongle side.<br />
<br />
Cable length is important - your cable should not be more than a few centimeter long.<br />
<br />
The easiest way to make such a cable is to take an old floppy or IDE-40 flat ribbon cable (don't use IDE-80, its wires are much thinner which makes things harder), cut it, and put a 10-pin header on the dongle side.<br />
<br />
If you are in the US, you can buy 10-pin headers [https://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?langId=-1&storeId=10001&catalogId=10001&pa=32492&productId=32492 here] (Jameco part number 32492). You might also want to get [https://www.jameco.com/webapp/wcs/stores/servlet/ProductDisplay?langId=-1&storeId=10001&catalogId=10001&pa=73252&productId=73252 a crimping tool] (Jameco part number 73252).<br />
<br />
This is what a finished cable looks like:<br />
<br />
[[Image:Dscn3151_640_480.jpg||Custom ALIX.1C to Artecgroup LPC dongle cable]]<br />
<br />
You can test your cable by booting the ALIX.1C, and then hooking it up to the dongle (using J16 on the ALIX.1C, of course). Now reboot the ALIX.1C board; the LEDs on the dongle should show post codes as the ALIX.1C shuts down and tries to boot. Unless you've prepared the dongle and stored an image into it, the ALIX.1C will not boot. But if you see POST codes on the LEDs, your cable is likely to be good. If not, use a multimeter and make sure it matches the layout above. Also make sure that it is not too long.<br />
<br />
Now make sure the dongle is correctly configured:<br />
<br />
Jump pin 1/2 on J1. Make sure JMP4 is set to position 1/2 (i.e. NOT to the pins marked as LPC). Make sure that you leave the mode select jumpers in the same position between the writing of the image into the dongle and trying to boot off it.<br />
<br />
Now write your image to the top of the memory bank you want to use (see higher). Then <i>disconnect the dongle from your computer</i>, reconnect it, make sure that you have your cable connected to the LPC port on the dongle and J16 on the ALIX.1C, and plug in power to the ALIX.1C. Also hook up a serial port to the ALIX.1C so that you see what happens during boot. If all goes well, you will see post codes on the dongle LEDs as the ALIX.1C boots.<br />
<br />
=== Booting FWH PLCC boards ===<br />
<br />
It is also possible to boot FWH PLCC boards, if you make a special cable. For an example of such a cable, see some photos here: http://www.artecdesign.ee/~martr/dongle-fwh-plcc-cable/. TODO: we need to find a place to buy such a connector, and we need to document the pinout of the cable.<br />
<br />
=== Booting SPI boards ===<br />
<br />
With a VHDL change and the proper cable, it should be possible to use the dongle to boot SPI-based boards. Artec is looking into this, and carldani has provided them with some information on what SPI commands are most essential.<br />
<br />
<br />
<br />
{{GPL}}</div>Leio