https://www.coreboot.org/api.php?action=feedcontributions&user=MartinRoth&feedformat=atomcoreboot - User contributions [en]2024-03-28T18:26:28ZUser contributionsMediaWiki 1.40.0https://www.coreboot.org/index.php?title=Welcome_to_coreboot&diff=35054Welcome to coreboot2018-05-19T15:05:57Z<p>MartinRoth: </p>
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'''coreboot''' is an Open Source project aimed at replacing the proprietary [http://wikipedia.org/wiki/BIOS BIOS] (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a [[Payloads|payload]].<br />
<br />
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly from firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like [[SeaBIOS | PC BIOS services]] or [[TianoCore | UEFI]]. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.<br />
<br />
coreboot currently supports over '''[[Supported Motherboards|230]]''' different mainboards. Check the [[Support]] page to see if your system is supported.<br />
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<small><br />
coreboot was formerly known as [http://www.coreboot.org/pipermail/coreboot/2008-January/029135.html LinuxBIOS]. <br />
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coreboot uses [[git]] for source control and [http://review.coreboot.org gerrit] as the patch review tool. Please read the [https://doc.coreboot.org/gerrit_guidelines.html gerrit etiquette & guidelines] document before submitting or reviewing patches.<br />
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<small><br />
* 100% Free Software (GPL), no royalties, no license fees!<br />
* Fast boot times (500 milliseconds to verified Linux kernel)<br />
<!-- * Avoids the need for a slow/buggy/proprietary BIOS --><br />
<!-- * Runs in 32-Bit protected mode almost from the start --><br />
<!-- * Written in C, contains virtually no assembly code --><br />
* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]<br />
<!-- * Further features: netboot, serial console, remote flashing, ... --><br />
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* Desktop PCs, servers, [[Laptop|laptops]]<br />
* [[Clusters]]<br />
<!-- * Set-Top-Boxes, thin clients --><br />
* Embedded solutions<br />
<!-- * [http://en.wikipedia.org/wiki/Small_form_factor Small form factor computers], [http://en.wikipedia.org/wiki/Home_theater_PC Home-theater PCs] --><br />
<!-- * No-moving-parts solutions (ROM chip as "disk") --><br />
<!-- * Non-standard scenarios (e.g. FPGA in Opteron socket) --><br />
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CONTENT =<br />
<small><br />
* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] <!-- / [[OpenFirmware]] / [[OpenBIOS]] --><br />
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] <!-- / [http://openbsd.org/ OpenBSD]--><br />
* [[Etherboot]] / [[GPXE]] / [[iPXE]] / [[Payloads|...]]<br />
<!--* [[Memtest86]]<br />
* [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]--><br />
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'''<span style="font-variant:small-caps; font-size:150%">About</span>'''<br /><small>Find out more about coreboot.</small><small><hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]</small><br />
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'''<span style="font-variant:small-caps; font-size:150%">Developers</span>'''<br /><small>Get involved! Help us make coreboot better.</small><small><hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree Browse Source] | [[GSoC]] | [[Where to start]] | [[Lesson1| Lesson 1]] | [[Distributed and Automated Testsystem|Testsystem]] | [https://coreboot.org/git-docs git-docs]</small><br />
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'''<span style="font-variant:small-caps; font-size:150%">Status</span>'''<br /><small>Find out whether your hardware is already supported.</small><small><hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [[Board Status]] | [[Blob Matrix|Blob Matrix]] | [http://qa.coreboot.org Build Status]</small><br />
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'''<span style="font-variant:small-caps; font-size:150%">Related Tools</span>'''<br /><small>Tools and libraries related to coreboot.</small><small><hr />[http://www.flashrom.org flashrom] | [[Superiotool]] | [[Nvramtool]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [http://serialice.com SerialICE]</small><br />
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'''<span style="font-variant:small-caps; font-size:150%">Getting Started</span>'''<br /><small>Download coreboot and get started.</small><small><hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation/old|Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]</small><br />
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'''<span style="font-variant:small-caps; font-size:150%">Support</span>'''<br /><small>Learn how to contact us and find help and support.</small><small><hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [[Glossary]] | [[coreboot Options|coreboot Options]]</small><br />
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[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]<br />
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'''<span style="font-variant:small-caps; font-size:120%">[[Current events|Events]]</span>'''<hr /><br />
<!-- List of upcoming events (remove events after they have taken place). --><br />
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== Upcoming Events ==<br />
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* September 12 - 15, 2018 - [https://osfc.io/ Open Source Firmware Conference] in Erlangen, Germany<br />
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<!-- * Currently none --><br />
<!--* '''2015/mon/day:''' coreboot event at [[Link]] in somecity --><br />
[https://www.coreboot.org/calendar.html Full calendar]<br />
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__NOTOC__<br />
__NOEDITSECTION__</div>MartinRothhttps://www.coreboot.org/index.php?title=Current_events&diff=35053Current events2018-05-19T15:04:15Z<p>MartinRoth: </p>
<hr />
<div>Please contact [[User:Stepan|Stefan Reinauer]], [[User:Rminnich|Ronald Minnich]] or [[User:Stuge|Peter Stuge]] for more information on the events.<br />
<br />
== Upcoming Events ==<br />
<br />
'''2018'''<br />
<br />
* September 12 - 15 - [https://osfc.io/ Open Source Firmware Conference] in Erlangen, Germany<br />
<br />
== Past Events ==<br />
<br />
'''2018'''<br />
<br />
* February 3 - 4 - FOSDEM Bruessel, fosdem.org, Brussels, Belgium<br />
<br />
'''2017'''<br />
* June 5 - 7 - American coreboot conference in Denver, CO, USA<br />
<br />
* Oct 26 - 29 - [https://ecc2017.coreboot.org/ European coreboot conference in Bochum], Germany [https://ecc2017.coreboot.org/ https://ecc2017.coreboot.org/]<br />
<br />
* February 4-5 - coreboot table at fosdem 2017 in Brussels<br />
<br />
<br />
'''2016'''<br />
* coreboot and flashrom had a booth at [https://fosdem.org/2016/ FOSDEM 2016], 30 & 31 January 2016<br />
* coreboot user group meeting Berlin on Wednesday, February 17th at 18:00 [https://berlin.ccc.de/wiki/Chaos_Computer_Club_Berlin @chaos computer club berlin].<br />
* coreboot user group meeting Berlin on Wednesday, March 16th at 19:00 [https://berlin.ccc.de/wiki/Chaos_Computer_Club_Berlin @chaos computer club berlin].<br />
* coreboot user group meeting Berlin on Wednesday, May 18th at 18:00 [https://berlin.ccc.de/wiki/Chaos_Computer_Club_Berlin @chaos computer club berlin].<br />
:: This is held the third Wednesday of every month.<br />
* [[coreboot_conference_San_Francisco_2016|coreboot convention in San Francisco, CA, USA]] on Monday June 13 - Thursday June 16, 2016<br />
* coreboot user group meeting Berlin on Wednesday, June 15th at 18:00 [https://berlin.ccc.de/wiki/Chaos_Computer_Club_Berlin @chaos computer club berlin].<br />
* December 27-30 - coreboot table at 33rd Chaos Communication Congress (33C3) in Hamburg]<br />
<br />
<br />
'''2015'''<br />
* coreboot user group meeting berlin 28.10.2015 20:30 [https://berlin.ccc.de/wiki/Chaos_Computer_Club_Berlin @chaos computer club berlin.]<br />
* coreboot conference Europe in Bonn [https://blogs.coreboot.org/blog/2015/08/04/coreboot-conference-in-europe-october-2015/ See blog post.]<br />
* coreboot workshop at [https://events.ccc.de/camp/2015/wiki/Main_Page Chaos Communication Camp 2015 in Mildenberg on August 13-17 August 2015]<br />
<br />
* coreboot and flashrom share a booth at [[FOSDEM 2015]] in Brussels on 31 January and 1 February 2015.<br />
<br />
'''2014'''<br />
* coreboot meeting/hackaton in Prague on August 16-19, 2014. [http://www.coreboot.org/pipermail/coreboot/2014-July/078296.html Invitation thread]<br />
<br />
'''2013'''<br />
* coreboot and flashrom share a booth at [[FOSDEM 2013]] in Brussels on February 2-3, 2013.<br />
<br />
'''2012'''<br />
* [[GSoC|2012 Google Summer of Code]]<br />
* coreboot and flashrom share a booth at [[FOSDEM 2012]] in Brussels on February 4-5, 2012, and a presentation about coreboot on laptops will be held by [[User:Hailfinger|Carl-Daniel Hailfinger]].<br />
<br />
'''2011'''<br />
<br />
* coreboot and flashrom exhibit at [http://www.linuxtag.org/ LinuxTag] in Berlin on May 11-14, 2011.<br />
<br />
* coreboot and flashrom shared a booth at [[FOSDEM 2011]] in Brussels on February 5-6, 2011, and several presentations were held by [[User:Ruik|Rudolf Marek]] and [[User:Hailfinger|Carl-Daniel Hailfinger]].<br />
<br />
<br />
'''2010'''<br />
<br />
* coreboot exhibited at [http://www.linuxtag.org/ LinuxTag 2010] in Berlin on June 9-12, 2010.<br />
* coreboot had its [[FOSDEM 2010|very first DevRoom]] at [http://www.fosdem.org/ FOSDEM] in Brussels on February 6, 2010.<br />
<br />
'''2009'''<br />
<br />
* [[User:Stuge|Peter Stuge]] presented [http://events.ccc.de/congress/2009/Fahrplan/events/3661.en.html coreboot] at [http://events.ccc.de/congress/2009/ the 26th Chaos Communication Congress (26C3)] in Berlin on December 27, 2009.<br />
* [[User:Stuge|Peter Stuge]] presented [http://www.databadge.net/ifsec2009/reg/lin/show_sessions.php coreboot] at [http://www.linux-world.nl/nl-NL/Bezoeker.aspx?sc_lang=en LinuxWorld Conference & Expo] in Utrecht on November 4, 2009.<br />
* [[User:Stuge|Peter Stuge]] presented [https://har2009.org/program/events/210.en.html coreboot] at [https://wiki.har2009.org/page/Main_Page HAR2009] in Vierhouten on August 13, 2009.<br />
* coreboot had a booth at [[LinuxTag 2009|LinuxTag]] in Berlin on June 24-27, 2009.<br />
* [[User:Stuge|Peter Stuge]] presented coreboot at [http://freedomhectaipei.pbworks.com/ FreedomHEC Taipei] on June 11, 2009.<br />
* [[User:Stuge|Peter Stuge]] presented coreboot at [http://goopen2009.friprog.no/ GoOpen 2009] in Oslo on April 16-17, 2009.<br />
* [[User:Stepan|Stefan Reinauer]], [[User:Stuge|Peter Stuge]] and [[User:Ruik|Rudolf Marek]] made a visit at [http://www.embedded-world.de/ embedded world 2009] in N�rnberg on March 3-5.<br />
* [[User:Rminnich|Ron Minnich]] had a [http://scale7x.socallinuxexpo.org/dotorg/coreboot coreboot booth] at the [http://scale7x.socallinuxexpo.org/ Southern California Linux Expo] (SCALE 7x) on February 20-22, 2009.<br />
<br />
'''2008'''<br />
<br />
* [[User:Stuge|Peter Stuge]] presented [http://events.ccc.de/congress/2008/Fahrplan/events/2970.en.html coreboot: Beyond The Final Frontier] and held a coreboot workshop at [http://events.ccc.de/congress/2008/ the 25th Chaos Communication Congress (25C3)] on December 27-30.<br />
* [[User:Stuge|Peter Stuge]] presented coreboot at the [http://www.nluug.nl/events/nj08/ NLUUG Autumn Conference on Mobile Computing] and [http://www.embeddedlinuxconference.com/elc_europe08/ CE Linux Forum - Embedded Linux conference Europe 2008] on November 6-7.<br />
* [[User:Rminnich|Ronald Minnich]], [[User:Stuge|Peter Stuge]] and [[User:Stepan|Stefan Reinauer]] presented coreboot in a [[Screenshots#Google_Tech_Talks_2008:_coreboot_.28aka_LinuxBIOS.29:_The_Free.2FOpen-Source_x86_Firmware|Google TechTalk]] on October 30.<br />
* [[User:Stuge|Peter Stuge]] presented [http://fscons.org/events/?action=event&id=32 coreboot] at the [http://fscons.org/ Free Society Conference and Nordic Summit 2008] on October 24-26.<br />
* [[User:Stuge|Peter Stuge]] presented coreboot at the [http://slackathon.se/2008/ Slackathon 2008] OpenBSD meeting in September.<br />
* Coreboot was exhibiting at [[LinuxTag 2008]] in Berlin on May 28-31.<br />
* The [[Coreboot Symposium 2008|coreboot symposium 2008]] was held in Denver, April 3 � 5, 2008 during the High Performance Computer Science Week [http://www.hpcsw.org HPCSW].<br />
<br />
'''2007'''<br />
<br />
* There was a [[News#2007.2F05.2F23_LinuxBIOS_booth_at_LinuxTag_in_Berlin.2C_29.2F5-2.2F6|LinuxBIOS booth at the LinuxTag in Berlin, May 29 - June 6, 2007]], as well as a hands-on workshop by Peter Stuge.<br />
* Ron Minnich gave [http://www.fosdem.org/2007/schedule/events/linuxbios a talk about LinuxBIOS] on February 24, 2007 at [http://www.fosdem.org/2007/ FOSDEM 2007].<br />
<br />
'''2006'''<br />
<br />
* The [[LinuxBIOS Symposium 2006]] took place on October 1-3, 2006 in Hamburg, Germany.<br />
<br />
'''2005'''<br />
<br />
* The [[LinuxBIOS Summit 2005]] took place on October 11-13 in Santa Fe, NM.</div>MartinRothhttps://www.coreboot.org/index.php?title=EM100pro&diff=34818EM100pro2018-05-10T02:11:22Z<p>MartinRoth: </p>
<hr />
<div>= Linux Utility =<br />
<br />
We have developed a Linux utility to drive the EM100Pro. Get the sources with<br />
$ git clone http://review.coreboot.org/em100<br />
<br />
Browse the source code here: http://review.coreboot.org/gitweb?p=em100.git;a=summary<br />
<br />
Here's how to use the utility:<br />
<br />
em100: EM100pro command line utility<br />
<br />
Example:<br />
./em100 --stop --set M25P80 -d file.bin -v --start -t -O 0xfff00000<br />
<br />
Usage:<br />
-c|--set CHIP: select chip emulation<br />
-d|--download FILE: download FILE into EM100pro<br />
-u|--upload FILE: upload from EM100pro into FILE<br />
-r|--start: em100 shall run<br />
-s|--stop: em100 shall stop<br />
-v|--verify: verify EM100 content matches the file<br />
-t|--trace: trace mode<br />
-O|--offset HEX_VAL: address offset for trace mode<br />
-T|--terminal: terminal mode<br />
-F|--firmware-update FILE: update EM100pro firmware (dangerous)<br />
-f|--firmware-dump FILE: export raw EM100pro firmware to file<br />
-g|--firmware-write FILE: export EM100pro firmware to DPFW file<br />
-S|--set-serialno NUM: set serial number to NUM<br />
-p|--holdpin [LOW|FLOAT|INPUT]: set the hold pin state<br />
-x|--device BUS:DEV use EM100pro on USB bus/device<br />
-x|--device DPxxxxxx use EM100pro with serial no DPxxxxxx<br />
-l|--list-devices list all connected EM100pro devices<br />
-D|--debug: print debug information.<br />
-h|--help: this help text<br />
<br />
= Chip Voltage =<br />
<br />
EM100 uses different firmware for 1.8V and 3.3V chips. Furthermore, the firmware update function only accepts combined MCU and FPGA images.<br />
<br />
TODO: Update tool to automatically select appropriate firmware.<br />
<br />
= USB Tracing =<br />
<br />
When using VMware to run the Windows utilities, the EM100pro will get confused by Windows trying to set the device up after Linux already did. To avoid that, add the following line to your .vmx file:<br />
<br />
usb.quirks.device0 = "0x04b4:0x1235 skip-reset, skip-refresh, skip-setconfig"</div>MartinRothhttps://www.coreboot.org/index.php?title=Memtest86%2B&diff=33278Memtest86+2018-03-12T20:12:31Z<p>MartinRoth: /* Building */</p>
<hr />
<div>== Building ==<br />
<br />
Instead of building coreboot with MemTest86+ as its default payload, it is recommended to simply load the binary from your payload of choice as an extra boot option.<br />
You can also build it directly from the coreboot build by selecting it as a 'seconday payload' from the payloads menu.<br />
<br />
=== Manual build ===<br />
<br />
Clone the source from coreboot's memtest86+ repository. This was based on the latest released archive, then cleaned up, and then had various patches applied.<br />
$ '''git clone https://review.coreboot.org/memtest86plus '''<br />
<br />
CD to the directory and build it:<br />
$ '''cd memtest86plus'''<br />
$ '''make'''<br />
<br />
The resulting binaries are:<br />
memtest: ELF 32-bit LSB executable, Intel 80386, version 1 (SYSV), statically linked, stripped<br />
memtest.bin: DOS/MBR boot sector<br />
<br />
In case GRUB2 is used default payload, add the x86-bootable '''memtest.bin''' to your ROM image with<br />
$ '''cbfstool coreboot.rom add -f memtest.bin -n memtest.bin -t raw'''<br />
and add the following entry to your grub.cfg:<br />
menuentry 'MemTest86+ 5.01' {<br />
set root='cbfsdisk'<br />
linux16 /memtest.bin<br />
}<br />
Alternatively one can also load it directly from disk, e.g. by placing it under '''/boot/memtest.bin''' and adjusting the menuentry accordingly:<br />
search -n --set=root -f /boot/memtest.bin</div>MartinRothhttps://www.coreboot.org/index.php?title=Memtest86%2B&diff=33277Memtest86+2018-03-12T20:11:13Z<p>MartinRoth: /* Manual build */</p>
<hr />
<div>== Building ==<br />
<br />
Instead of building coreboot with MemTest86+ as its default payload, it is recommended to simply load the binary from your payload of choice as an extra boot option.<br />
<br />
=== Manual build ===<br />
<br />
Clone the source from coreboot's memtest86+ repository. This was based on the latest released archive, then cleaned up, and then had various patches applied.<br />
$ '''git clone https://review.coreboot.org/memtest86plus '''<br />
<br />
CD to the directory and build it:<br />
$ '''cd memtest86plus'''<br />
$ '''make'''<br />
<br />
The resulting binaries are:<br />
memtest: ELF 32-bit LSB executable, Intel 80386, version 1 (SYSV), statically linked, stripped<br />
memtest.bin: DOS/MBR boot sector<br />
<br />
In case GRUB2 is used default payload, add the x86-bootable '''memtest.bin''' to your ROM image with<br />
$ '''cbfstool coreboot.rom add -f memtest.bin -n memtest.bin -t raw'''<br />
and add the following entry to your grub.cfg:<br />
menuentry 'MemTest86+ 5.01' {<br />
set root='cbfsdisk'<br />
linux16 /memtest.bin<br />
}<br />
Alternatively one can also load it directly from disk, e.g. by placing it under '''/boot/memtest.bin''' and adjusting the menuentry accordingly:<br />
search -n --set=root -f /boot/memtest.bin</div>MartinRothhttps://www.coreboot.org/index.php?title=Lesson1&diff=29067Lesson12017-10-05T03:17:53Z<p>MartinRoth: /* Step 1 - Install tools and libraries needed for coreboot */</p>
<hr />
<div>coreboot lesson 1 - Starting from scratch<br />
<br />
From a fresh [http://releases.ubuntu.com/16.04/ubuntu-16.04-desktop-amd64.iso ubuntu 16.04 linux] install, here are all the steps required for a very basic build:<br />
<br />
==Download, configure, and build coreboot ==<br />
<br />
===Step [[Lesson1#1|1]] - Install tools and libraries needed for coreboot ===<br />
<br />
$ sudo apt-get install -y bison build-essential curl flex git gnat-5 libncurses5-dev m4 zlib1g-dev<br />
<br />
===Step [[Lesson1#2|2]] - Download coreboot source tree ===<br />
$ git clone https://review.coreboot.org/coreboot<br />
$ cd coreboot<br />
<br />
===Step [[Lesson1#3|3]] - Build the coreboot toolchain ===<br />
Please note that this can take a significant amount of time<br />
$ make crossgcc-i386 CPUS=$(nproc)<br />
<br />
===Step [[Lesson1#4|4]] - Build the payload - coreinfo ===<br />
$ make -C payloads/coreinfo olddefconfig<br />
$ make -C payloads/coreinfo<br />
<br />
===Step [[Lesson1#5|5]] - Configure the mainboard ===<br />
$ make menuconfig<br />
select 'Mainboard' menu<br />
Beside 'Mainboard vendor' should be '(Emulation)'<br />
Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'<br />
select exit<br />
<br />
select 'Payload' menu<br />
select 'Add a Payload'<br />
choose 'An Elf executable payload'<br />
select 'Payload path and filename'<br />
enter 'payloads/coreinfo/build/coreinfo.elf'<br />
select exit<br />
select exit<br />
select yes<br />
<br />
check your configuration (optional step):<br />
$ make savedefconfig<br />
$ cat defconfig<br />
<br />
There should only be two lines:<br />
CONFIG_PAYLOAD_ELF=y<br />
CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"<br />
<br />
===Step [[Lesson1#6|6]] - build coreboot ===<br />
$ make<br />
<br />
At the end of the build, you should see:<br />
Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)<br />
<br />
This means your build was successful. The output from the build<br />
is in the build directory. build/coreboot.rom is the full rom file.<br />
<br />
== Test the image using QEMU ==<br />
<br />
=== Step [[Lesson1#7|7]] - Install QEMU ===<br />
$ sudo apt-get install -y qemu<br />
<br />
=== Step [[Lesson1#8|8]] - Run QEMU ===<br />
Start QEMU, and point it to the ROM you just built:<br />
$ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio<br />
<br />
You should see the serial output of coreboot in the original console window, and a new window will appear running the coreinfo payload.<br />
<br />
==Summary:==<br />
<br />
=== 1 === <br />
Install tools and libraries needed for coreboot.<br />
<br />
You installed the minimum additional requirements for ubuntu to download and build coreboot. <br />
Ubuntu already has most of the other tools that would be required installed by default. <br />
- git is needed to download coreboot from the coreboot git repository.<br />
- libncurses5-dev is needed to build the menu for 'make menuconfig'<br />
- m4, bison, flex, and zlib1g-dev are needed to build the coreboot toolchain.<br />
If you had started from a different distribution, you might need to install the basic gcc toolchain, wget, make, or many other items.<br />
<br />
=== 2 ===<br />
Download coreboot source tree.<br />
<br />
This will download a 'read-only' copy of the coreboot tree. This just means that if you made changes to the coreboot tree, you couldn't immediately contribute them back to the community. To pull a copy of coreboot that would allow you to contribute back, you would first need to sign up for an account on gerrit.<br />
<br />
=== 3 ===<br />
Build the coreboot toolchain.<br />
<br />
This builds one of the coreboot cross-compiler toolchains for X86 platforms. Because of the variability of compilers and the other required tools between the various operating systems that coreboot can be built on, coreboot supplies and uses its own cross-compiler toolchain to build the binaries that end up as part of the coreboot ROM. The toolchain provided by the operating system (the 'host toolchain') is used to build various tools that will run on the local system during the build process.<br />
<br />
=== 4 ===<br />
Build the payload.<br />
<br />
To actually do anything useful with coreboot, you need to build a payload to include in the rom. The idea behind coreboot is that it does the minimum amount possible before passing control of the machine to a payload. There are various payloads such as grub or SeaBIOS that are typically used to boot the operating system. Instead, we used coreinfo, a small demonstration payload that allows the user to look at various things such as memory and the contents of coreboot's cbfs - the pieces that make up the coreboot rom.<br />
<br />
=== 5 ===<br />
Configure the mainboard.<br />
<br />
This step configures coreboot's build options using the menuconfig interface to Kconfig. Kconfig is the same configuration program used by the linux kernel. It allows you to enable, disable, and change various values to control the coreboot build process, including which mainboard(motherboard) to use, which toolchain to use, and how the runtime debug console should be presented and saved.<br />
<br />
Anytime you change mainboards in Kconfig, you should always run "make distclean" before running "make menuconfig". Due to the way that Kconfig works, values will be kept from the previous mainboard if you skip the clean step. This leads to a hybrid configuration which may or may not work as expected.<br />
<br />
=== 6 ===<br />
Build coreboot.<br />
<br />
You may notice that a number of other pieces are downloaded at the beginning of the build process. These are the git submodules used in various coreboot builds. By default, the BLOBs submodule is not downloaded. This git submodule may be required for other builds for microcode or other binaries. To enable downloading this submodule, select the option "Allow use of binary-only repository" in the "General Setup" menu of Kconfig<br />
<br />
This attempts to build the coreboot rom. The rom file itself ends up in the build directory as 'coreboot.rom'. At the end of the build process, the build displayed the contents of the rom file.<br />
<br />
=== 7 ===<br />
Install QEMU<br />
<br />
QEMU is a processor emulator which we can use to show coreboot <br />
<br />
=== 8 ===<br />
Run QEMU.<br />
<br />
Here's the command line broken down:<br />
<br />
qemu-system-x86_64<br />
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge.<br />
<br />
-bios build/coreboot.rom<br />
Use the bios rom image that we just built. If this is left off, the standard SeaBIOS image that comes with QEMU is used.<br />
<br />
-serial stdio<br />
Send the serial output to the console. This allows you to view the coreboot debug output.</div>MartinRothhttps://www.coreboot.org/index.php?title=Lesson1&diff=29066Lesson12017-10-05T03:17:08Z<p>MartinRoth: /* Step 1 - Install tools and libraries needed for coreboot */</p>
<hr />
<div>coreboot lesson 1 - Starting from scratch<br />
<br />
From a fresh [http://releases.ubuntu.com/16.04/ubuntu-16.04-desktop-amd64.iso ubuntu 16.04 linux] install, here are all the steps required for a very basic build:<br />
<br />
==Download, configure, and build coreboot ==<br />
<br />
===Step [[Lesson1#1|1]] - Install tools and libraries needed for coreboot ===<br />
<br />
$ sudo apt-get install -y bison build-essential curl flex git libncurses5-dev m4 zlib1g-dev<br />
<br />
===Step [[Lesson1#2|2]] - Download coreboot source tree ===<br />
$ git clone https://review.coreboot.org/coreboot<br />
$ cd coreboot<br />
<br />
===Step [[Lesson1#3|3]] - Build the coreboot toolchain ===<br />
Please note that this can take a significant amount of time<br />
$ make crossgcc-i386 CPUS=$(nproc)<br />
<br />
===Step [[Lesson1#4|4]] - Build the payload - coreinfo ===<br />
$ make -C payloads/coreinfo olddefconfig<br />
$ make -C payloads/coreinfo<br />
<br />
===Step [[Lesson1#5|5]] - Configure the mainboard ===<br />
$ make menuconfig<br />
select 'Mainboard' menu<br />
Beside 'Mainboard vendor' should be '(Emulation)'<br />
Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'<br />
select exit<br />
<br />
select 'Payload' menu<br />
select 'Add a Payload'<br />
choose 'An Elf executable payload'<br />
select 'Payload path and filename'<br />
enter 'payloads/coreinfo/build/coreinfo.elf'<br />
select exit<br />
select exit<br />
select yes<br />
<br />
check your configuration (optional step):<br />
$ make savedefconfig<br />
$ cat defconfig<br />
<br />
There should only be two lines:<br />
CONFIG_PAYLOAD_ELF=y<br />
CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"<br />
<br />
===Step [[Lesson1#6|6]] - build coreboot ===<br />
$ make<br />
<br />
At the end of the build, you should see:<br />
Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)<br />
<br />
This means your build was successful. The output from the build<br />
is in the build directory. build/coreboot.rom is the full rom file.<br />
<br />
== Test the image using QEMU ==<br />
<br />
=== Step [[Lesson1#7|7]] - Install QEMU ===<br />
$ sudo apt-get install -y qemu<br />
<br />
=== Step [[Lesson1#8|8]] - Run QEMU ===<br />
Start QEMU, and point it to the ROM you just built:<br />
$ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio<br />
<br />
You should see the serial output of coreboot in the original console window, and a new window will appear running the coreinfo payload.<br />
<br />
==Summary:==<br />
<br />
=== 1 === <br />
Install tools and libraries needed for coreboot.<br />
<br />
You installed the minimum additional requirements for ubuntu to download and build coreboot. <br />
Ubuntu already has most of the other tools that would be required installed by default. <br />
- git is needed to download coreboot from the coreboot git repository.<br />
- libncurses5-dev is needed to build the menu for 'make menuconfig'<br />
- m4, bison, flex, and zlib1g-dev are needed to build the coreboot toolchain.<br />
If you had started from a different distribution, you might need to install the basic gcc toolchain, wget, make, or many other items.<br />
<br />
=== 2 ===<br />
Download coreboot source tree.<br />
<br />
This will download a 'read-only' copy of the coreboot tree. This just means that if you made changes to the coreboot tree, you couldn't immediately contribute them back to the community. To pull a copy of coreboot that would allow you to contribute back, you would first need to sign up for an account on gerrit.<br />
<br />
=== 3 ===<br />
Build the coreboot toolchain.<br />
<br />
This builds one of the coreboot cross-compiler toolchains for X86 platforms. Because of the variability of compilers and the other required tools between the various operating systems that coreboot can be built on, coreboot supplies and uses its own cross-compiler toolchain to build the binaries that end up as part of the coreboot ROM. The toolchain provided by the operating system (the 'host toolchain') is used to build various tools that will run on the local system during the build process.<br />
<br />
=== 4 ===<br />
Build the payload.<br />
<br />
To actually do anything useful with coreboot, you need to build a payload to include in the rom. The idea behind coreboot is that it does the minimum amount possible before passing control of the machine to a payload. There are various payloads such as grub or SeaBIOS that are typically used to boot the operating system. Instead, we used coreinfo, a small demonstration payload that allows the user to look at various things such as memory and the contents of coreboot's cbfs - the pieces that make up the coreboot rom.<br />
<br />
=== 5 ===<br />
Configure the mainboard.<br />
<br />
This step configures coreboot's build options using the menuconfig interface to Kconfig. Kconfig is the same configuration program used by the linux kernel. It allows you to enable, disable, and change various values to control the coreboot build process, including which mainboard(motherboard) to use, which toolchain to use, and how the runtime debug console should be presented and saved.<br />
<br />
Anytime you change mainboards in Kconfig, you should always run "make distclean" before running "make menuconfig". Due to the way that Kconfig works, values will be kept from the previous mainboard if you skip the clean step. This leads to a hybrid configuration which may or may not work as expected.<br />
<br />
=== 6 ===<br />
Build coreboot.<br />
<br />
You may notice that a number of other pieces are downloaded at the beginning of the build process. These are the git submodules used in various coreboot builds. By default, the BLOBs submodule is not downloaded. This git submodule may be required for other builds for microcode or other binaries. To enable downloading this submodule, select the option "Allow use of binary-only repository" in the "General Setup" menu of Kconfig<br />
<br />
This attempts to build the coreboot rom. The rom file itself ends up in the build directory as 'coreboot.rom'. At the end of the build process, the build displayed the contents of the rom file.<br />
<br />
=== 7 ===<br />
Install QEMU<br />
<br />
QEMU is a processor emulator which we can use to show coreboot <br />
<br />
=== 8 ===<br />
Run QEMU.<br />
<br />
Here's the command line broken down:<br />
<br />
qemu-system-x86_64<br />
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge.<br />
<br />
-bios build/coreboot.rom<br />
Use the bios rom image that we just built. If this is left off, the standard SeaBIOS image that comes with QEMU is used.<br />
<br />
-serial stdio<br />
Send the serial output to the console. This allows you to view the coreboot debug output.</div>MartinRothhttps://www.coreboot.org/index.php?title=Lesson1&diff=29065Lesson12017-10-05T03:16:06Z<p>MartinRoth: /* Step 1 - Install tools and libraries needed for coreboot */</p>
<hr />
<div>coreboot lesson 1 - Starting from scratch<br />
<br />
From a fresh [http://releases.ubuntu.com/16.04/ubuntu-16.04-desktop-amd64.iso ubuntu 16.04 linux] install, here are all the steps required for a very basic build:<br />
<br />
==Download, configure, and build coreboot ==<br />
<br />
===Step [[Lesson1#1|1]] - Install tools and libraries needed for coreboot ===<br />
<br />
$ sudo apt-get install -y bison curl flex git libncurses5-dev m4 zlib1g-dev<br />
<br />
===Step [[Lesson1#2|2]] - Download coreboot source tree ===<br />
$ git clone https://review.coreboot.org/coreboot<br />
$ cd coreboot<br />
<br />
===Step [[Lesson1#3|3]] - Build the coreboot toolchain ===<br />
Please note that this can take a significant amount of time<br />
$ make crossgcc-i386 CPUS=$(nproc)<br />
<br />
===Step [[Lesson1#4|4]] - Build the payload - coreinfo ===<br />
$ make -C payloads/coreinfo olddefconfig<br />
$ make -C payloads/coreinfo<br />
<br />
===Step [[Lesson1#5|5]] - Configure the mainboard ===<br />
$ make menuconfig<br />
select 'Mainboard' menu<br />
Beside 'Mainboard vendor' should be '(Emulation)'<br />
Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'<br />
select exit<br />
<br />
select 'Payload' menu<br />
select 'Add a Payload'<br />
choose 'An Elf executable payload'<br />
select 'Payload path and filename'<br />
enter 'payloads/coreinfo/build/coreinfo.elf'<br />
select exit<br />
select exit<br />
select yes<br />
<br />
check your configuration (optional step):<br />
$ make savedefconfig<br />
$ cat defconfig<br />
<br />
There should only be two lines:<br />
CONFIG_PAYLOAD_ELF=y<br />
CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"<br />
<br />
===Step [[Lesson1#6|6]] - build coreboot ===<br />
$ make<br />
<br />
At the end of the build, you should see:<br />
Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)<br />
<br />
This means your build was successful. The output from the build<br />
is in the build directory. build/coreboot.rom is the full rom file.<br />
<br />
== Test the image using QEMU ==<br />
<br />
=== Step [[Lesson1#7|7]] - Install QEMU ===<br />
$ sudo apt-get install -y qemu<br />
<br />
=== Step [[Lesson1#8|8]] - Run QEMU ===<br />
Start QEMU, and point it to the ROM you just built:<br />
$ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio<br />
<br />
You should see the serial output of coreboot in the original console window, and a new window will appear running the coreinfo payload.<br />
<br />
==Summary:==<br />
<br />
=== 1 === <br />
Install tools and libraries needed for coreboot.<br />
<br />
You installed the minimum additional requirements for ubuntu to download and build coreboot. <br />
Ubuntu already has most of the other tools that would be required installed by default. <br />
- git is needed to download coreboot from the coreboot git repository.<br />
- libncurses5-dev is needed to build the menu for 'make menuconfig'<br />
- m4, bison, flex, and zlib1g-dev are needed to build the coreboot toolchain.<br />
If you had started from a different distribution, you might need to install the basic gcc toolchain, wget, make, or many other items.<br />
<br />
=== 2 ===<br />
Download coreboot source tree.<br />
<br />
This will download a 'read-only' copy of the coreboot tree. This just means that if you made changes to the coreboot tree, you couldn't immediately contribute them back to the community. To pull a copy of coreboot that would allow you to contribute back, you would first need to sign up for an account on gerrit.<br />
<br />
=== 3 ===<br />
Build the coreboot toolchain.<br />
<br />
This builds one of the coreboot cross-compiler toolchains for X86 platforms. Because of the variability of compilers and the other required tools between the various operating systems that coreboot can be built on, coreboot supplies and uses its own cross-compiler toolchain to build the binaries that end up as part of the coreboot ROM. The toolchain provided by the operating system (the 'host toolchain') is used to build various tools that will run on the local system during the build process.<br />
<br />
=== 4 ===<br />
Build the payload.<br />
<br />
To actually do anything useful with coreboot, you need to build a payload to include in the rom. The idea behind coreboot is that it does the minimum amount possible before passing control of the machine to a payload. There are various payloads such as grub or SeaBIOS that are typically used to boot the operating system. Instead, we used coreinfo, a small demonstration payload that allows the user to look at various things such as memory and the contents of coreboot's cbfs - the pieces that make up the coreboot rom.<br />
<br />
=== 5 ===<br />
Configure the mainboard.<br />
<br />
This step configures coreboot's build options using the menuconfig interface to Kconfig. Kconfig is the same configuration program used by the linux kernel. It allows you to enable, disable, and change various values to control the coreboot build process, including which mainboard(motherboard) to use, which toolchain to use, and how the runtime debug console should be presented and saved.<br />
<br />
Anytime you change mainboards in Kconfig, you should always run "make distclean" before running "make menuconfig". Due to the way that Kconfig works, values will be kept from the previous mainboard if you skip the clean step. This leads to a hybrid configuration which may or may not work as expected.<br />
<br />
=== 6 ===<br />
Build coreboot.<br />
<br />
You may notice that a number of other pieces are downloaded at the beginning of the build process. These are the git submodules used in various coreboot builds. By default, the BLOBs submodule is not downloaded. This git submodule may be required for other builds for microcode or other binaries. To enable downloading this submodule, select the option "Allow use of binary-only repository" in the "General Setup" menu of Kconfig<br />
<br />
This attempts to build the coreboot rom. The rom file itself ends up in the build directory as 'coreboot.rom'. At the end of the build process, the build displayed the contents of the rom file.<br />
<br />
=== 7 ===<br />
Install QEMU<br />
<br />
QEMU is a processor emulator which we can use to show coreboot <br />
<br />
=== 8 ===<br />
Run QEMU.<br />
<br />
Here's the command line broken down:<br />
<br />
qemu-system-x86_64<br />
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge.<br />
<br />
-bios build/coreboot.rom<br />
Use the bios rom image that we just built. If this is left off, the standard SeaBIOS image that comes with QEMU is used.<br />
<br />
-serial stdio<br />
Send the serial output to the console. This allows you to view the coreboot debug output.</div>MartinRothhttps://www.coreboot.org/index.php?title=Build_HOWTO&diff=28705Build HOWTO2017-09-10T02:34:06Z<p>MartinRoth: Undo revision 28699 by IanK (talk)</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++ / gnat (gcc-multilib is ideal, makes building payloads a lot easier)<br />
* make<br />
* cmake (if using clang/llvm)<br />
* ncurses-dev (for '''make menuconfig''')<br />
* iasl (for targets with ACPI support)<br />
* flex and bison (for regenerating parsers)<br />
<br />
Optional:<br />
* doxygen (for generating/viewing documentation)<br />
<br />
==== debian ====<br />
<pre>apt-get install git build-essential gnat flex bison libncurses5-dev wget zlib1g-dev</pre><br />
<br />
== Building a payload (Optional) ==<br />
<br />
The majority of the payloads supported by coreboot are built automatically once they are selected and configured as described in the next section.<br />
<br />
Most beginners want to use the default [[SeaBIOS]] payload. It runs Option ROMs, is able to discover boot devices and provides a very simple boot menu.<br />
<br />
If, however, you need to build a payload that is currently not included in the coreboot build system:<br />
<br />
*First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
*Each payload may have different build instructions and requirements, however most of the time a "make" command will suffice. Please check [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
*The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>https://review.coreboot.org/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
OR<br />
<br />
$ '''make nconfig''' (easier to navigate, uses ncurses)<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of <code>flashrom</code> command)<br />
<br />
More detailed example (generic) configuration (tweak accordingly):<br />
(note that this assumes presence of native graphics initialization on the given board, which is not universally available in coreboot)<br />
<br />
General setup / Expert mode = enable<br />
General / Use CMOS for configuration values = enable (CMOS defaults are located in your boards directory src/mainboard/OEM/MODEL/cmos.default)<br />
Mainboard / Mainboard vendor = Name of manufacturer<br />
Mainboard / Mainboard model = Model name<br />
Mainboard / ROM chip size = size of flash chip<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates (NOTE: you probably want to enable it on some systems)<br />
Devices / Use native graphics initialization = enable (NOTE: not available on all systems)<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Generic Drivers / USB 2.0 EHCI debug dongle support = Enable<br />
Generic Drivers / Enable early (pre-RAM) usbdebug = Enable<br />
Generic Drivers / Type of dongle = Net20DC or compatible<br />
Generic Drivers / Digitizer = Present<br />
Console / USB dongle console output = enable<br />
Payload / Add a payload = An ELF executable payload (change if you want a different payload)<br />
Payload / Payload path and filename = grub.elf (assumes building GRUB manually. Change this if you want a different payload)<br />
<br />
Now go back into Devices (only do this if you didn't enable native graphics initialization; NOTE: instructions for adding a vbios option rom are not mentioned in the above instructions):<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
<br />
<br />
=== Intel boards ===<br />
For Intel boards you have to provide files coreboot can't generate by itself:<br />
* [[Intel Flash Descriptor region]]<br />
* [[Intel Gigabit Ethernet firmware]]<br />
* [[Intel Management Engine]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
* Enter the '''Chipset''' menu<br />
** Do the following based on which blobs you have:<br />
** Untick '''Build with a fake IFD''' (descriptor.bin)<br />
** Tick '''Add gigabit ethernet firmware''' (gbe.bin)<br />
** Tick '''Add Intel Management Engine firmware''' (me.bin)<br />
<br />
=== AMD boards ===<br />
For AMD boards you may have to provide files coreboot can't generate by itself:<br />
* [[NIC firmware]]<br />
* [[AMD IMC]]<br />
* [[AMD XHCI]]<br />
* [[AMD PSP]] (AMD's ME analog)<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
=== Choose the payload ===<br />
Here's the full list of supported [[Payloads]].<br />
<br />
By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process.<br />
<br />
If you want to use another payload (ELF for example):<br />
<br />
* Enter the '''Payload''' menu.<br />
** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
=== VGA support ===<br />
In order to see something on your screen the graphic card has to be initialized by the [[VGA BIOS]] which is actually an [[Option ROM]].<br />
<br />
[[VGA support]] is required for payloads such as GRUB or elf-memtest86+-5.01.<br />
<br />
It isn't required for operating systems such as GNU/Linux as it initializes the graphic card by itself.<br />
<br />
On some platforms there's support for [[native gfx init]]. A VGA BIOS isn't required.<br />
<br />
=== Security Notes ===<br />
<br />
On modern X86 CPU's Microcode updates are required for secure and proper CPU operation. Not including it for philosophical reasons is done at your own risk.<br />
<br />
As an example, the 33xx, 43xx and 63xx "Piledriver" AMD Opteron CPU's have a fatal NMI to gain root exploit in some versions of the onboard microcode that is easily performed with userspace tool.<br />
<br />
=== Compiling ===<br />
<br />
You also need to build the coreboot cross-compiler. This is to compile for the architecture of the platform you are building coreboot FOR, not the system you are building ON. For x86 systems, you currently would use the i386 cross-compiler, not the x64 version.<br />
<br />
You can see all of the options available by running 'make help':<br />
<br />
$ '''make help'''<br />
...<br />
*** Toolchain targets ***<br />
crossgcc - Build coreboot cross-compilers for all platforms<br />
crosstools - Build coreboot cross-compiler and GDB for all platforms<br />
crossgcc-clean - Remove all built coreboot cross-compilers<br />
iasl - Build coreboot IASL compiler (built by all cross targets)<br />
clang - Build coreboot clang compiler<br />
test-toolchain - Reports if toolchain components are out of date<br />
crossgcc-ARCH - Build cross-compiler for specific architecture<br />
crosstools-ARCH - Build cross-compiler with GDB for specific architecture<br />
ARCH can be "i386", "x64", "arm", "aarch64", "mips", "riscv", "power8", "nds32le"<br />
Use "make [target] CPUS=#" to build toolchain using multiple cores<br />
<br />
<br />
To build the cross-compilers for all architectures using 4 threads (This takes a LONG time):<br />
$ '''make crossgcc CPUS=4'''<br />
<br />
To build the cross-compiler for just the x86 architecture with just a single thread:<br />
$ '''make crossgcc-i386'''<br />
<br />
<br />
You can also invoke the cross compiler build script directly (in this example eight threads). But you probably don't want to, because the makefile builds other things you need too:<br />
<br />
$ '''util/crossgcc/buildgcc -j 8'''<br />
<br />
If something fails, the build should tell you what file to look in. You can also try to search for the relevant log (<code>find . -name '*.log' | xargs grep Error</code>) and examine last few lines of it.<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
We have been working on building coreboot with clang/llvm and it basically works.<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
The default and recommended flow is still to use crossgcc.<br />
<br />
== Known issues ==<br />
<br />
Make sure you really have all the requirements installed!<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can [[flashing coreboot|flash]] the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>MartinRothhttps://www.coreboot.org/index.php?title=Denver2017&diff=28703Denver20172017-09-10T01:28:50Z<p>MartinRoth: </p>
<hr />
<div>==Presentations from the 2017 coreboot conference in Denver, CO, USA==<br />
===Monday:===<br />
* Coming of Age: 18 years of coreboot - Stefan Reinauer<br />
* coreboot and the Software Freedom Conservancy - Martin Roth ([[:Media:Coreboot_and_the_Software_Freedom_Conservancy.pdf|slides]])<br />
* creating community - Nate Lappegaard <br />
* Tianocore as a coreboot payload - Evelyn Huang & Logan Carlson ([[:Media:Building_Tianocore_into_coreboot.pdf|slides]])<br />
* How to make your hardware completely incompatible with coreboot - Ron Minnich ([[:Media:How_to_make_hardware_that_is_unfriendly_to_coreboot.pdf|slides]])<br />
* The state of coreboot (according to git) - Martin Roth ([[:Media:The_state_of_coreboot_in_2017.pdf|slides]])<br />
* Coreboot for Dummies - Youness Alaoui (Purism) ([[:Media:Coreboot_for_Dummies_-_Youness_Alaoui.pdf|slides]])<br />
<br />
===Tuesday:===<br />
* U-Root - Ron Minnich ([[:Media:Denver_2017_coreboot_u-root.pdf|slides]])<br />
* AMD and coreboot: History and future - Marshall Dawson ([[:Media:AMD_and_coreboot-_History_and_Future_-_Marshall_Dawson.pdf|slides]])<br />
* How to create a trust anchor with coreboot: Trusted Computing vs Authenticated Code Modules - Philipp Deppenwiese ([[:Media:Tpm_-_Philipp.pdf|slides]])<br />
* Tools, git, gerrit, jenkins, bug tracking and testing - Martin Roth ([[:Media:Tools,_Git,_Gerrit,_Jenkins_and_Testing.pdf|slides]])<br />
* Developer interviews - Marc Jones ([[:Media:Coreboot_developer_interviews_2017.pdf|slides]])<br />
<br />
==Date and time==<br />
The coreboot conference was '''Monday, June 5 and Tuesday June 6, 2017'''.<br />
<br />
[https://goo.gl/uDNN9a Full Schedule]<br />
<br />
==Conference location==<br />
This conference was hosted by the coreboot project and will be held in '''Denver CO, USA''' at:<br/><br />
<br />
[http://www.sustainablecolorado.org/ The Alliance Center]<br/><br />
[https://goo.gl/maps/3NFf389aH972 1536 Wynkoop Street, Suite 100]<br/><br />
<br />
The Alliance Center is in Denver's LoDo (Lower Downtown) neighborhood, which has an incredible amount to do and see, so people were encouraged to come early to experience more of both Denver and Colorado in general.<br />
<br />
[[Category:Meetings]]</div>MartinRothhttps://www.coreboot.org/index.php?title=User:MartinRoth&diff=27533User:MartinRoth2017-07-23T21:51:10Z<p>MartinRoth: /* Useful commands */</p>
<hr />
<div>==Martin Roth==<br />
<br />
[[File:Martin.jpg]]<br />
<br />
Email:<br />
:gaumless@gmail.com<br />
:martinroth@google.com<br />
<br />
IRC:<br />
:martinr (usually)<br />
:gaumless (occasionally)<br />
<br />
==Useful commands==<br />
=== See what Kconfig symbols are used in a platform ===<br />
make clean; make filelist; for file in $(grep -v 'config\.h' build/project_filelist.txt); do grep CONFIG_ "$file"; done | grep -Ev '[_A-Za-z]CONFIG' | sed 's/.*[-(\)\[\$!"[:space:]]CONFIG_/CONFIG_/'|sed 's/[^A-Z0-9_].*//' | sort | uniq<br />
<br />
===Find hex encoded binaries in coreboot===<br />
git grep -c '0x' | grep src/ | grep -v ':.\?.\?.$' | sort -n -k2 -t ':'<br />
<br />
===Find binary files in src tree===<br />
find src -type f -exec file -i '{}' \; | grep 'charset=binary' | grep -v 'x-empty'<br />
<br />
===run checkpatch on files ===<br />
DIR=src/lib;for file in $(git ls-files | grep "${DIR}"); do util/lint/checkpatch.pl --file $file --terse; done<br />
<br />
==Platforms supported by coreboot==<br />
{| class="wikitable"<br />
! Vendor !! Board !! Processor !! Southbridge !! Memory !! Count !! Blobs !! Used as<br />
|-<br />
| ADI || SG-2220 || Intel Rangeley || - || 2GB DDR3L Soldered Down || 1 || FSP ||<br />
|-<br />
| ADI || SG-2440 || Intel Rangeley || - || 4GB DDR3L Soldered Down || 1 || FSP ||<br />
|-<br />
| AMD || Bettong (DB-FP4) || || || || 1 || Yes || <br />
|-<br />
| AMD || Kino || AMD Family 10h || || || 1 || ||<br />
|-<br />
| AMD || Lamar || || || || 1 || ||<br />
|-<br />
| AMD || Mahogony || AMD Family F || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| AMD || Mahogony || AMD Family 10h || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| AMD || Olive Hill || || || || 1 || ||<br />
|-<br />
| AMD || Parmer || AMD Family 15TN || AMD Hudson || || 2 || ||<br />
|-<br />
| AMD || Pistachio || AMD Family F || AMD SB600|| || 1 || ||<br />
|-<br />
| AMD || Persimmon [DB-FT1] || AMD Family 14h || AMD SB800 || || 3 || ||<br />
|-<br />
| AMD || Pumori || || || || 1 || ||<br />
|-<br />
| AMD || Thatcher || AMD Family 15TN || AMD Hudson || || 1 || ||<br />
|-<br />
| AMD || Torpedo || AMD Family 12h || AMD SB900 || || 1 || ||<br />
|-<br />
| Asrock || E350M1/USB3 || AMD Family 14h || || || 1 || ||<br />
|-<br />
| Asrock || IMB-A180 || || || || 2 || ||<br />
|-<br />
| ASUS || F2A85-M || AMD Family 15TN || || || 1 || ||<br />
|-<br />
| ASUS || KGPE-D16 || AMD Family 10h / 15h || || || 1 || None || Lumberingbuilder<br />
|-<br />
| ASUS || KFSN4-DRE || || || || 1 || ||<br />
|-<br />
| ASUS || P5GC-MX || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-B75M-D3H || Intel Ivybridge || || 4 DDR3 UDIMMs || 1 || ME || Happybuilder<br />
|-<br />
| Gigabyte || GA-G41M-ES2L || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-945-GCM-S2L || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-MA78GM || AMD AM2+ socket || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| Gizmosphere || Gizmo || AMD Family 14h || || Soldered down || 3 || ||<br />
|-<br />
| Gizmosphere || Gizmo2 || || || Soldered down || 1 || Yes ||<br />
|-<br />
| Intel || Bakersport || Intel Bay Trail I SOC || - || 1 ECC DDR-3 SODIMM || 1 || FSP, ME ||<br />
|-<br />
| Intel || Bayley Bay || Intel Bay Trail I SOC || - || 2 DDR-3 SODIMM || 1 || FSP, ME ||<br />
|-<br />
| Intel || Camelback Mountain || Broadwell DE SOC || - || 2 DDR-4 UDIMMs || 1 || FSP, ME ||<br />
|-<br />
| Intel || Cougar Canyon || Intel Ivybridge || || || 1 || FSP, ME ||<br />
|-<br />
| Intel || D510MO || || I82801GB (ICH7) || 2 DDR-2 UDIMMs || 1 || None ||<br />
|-<br />
| Intel || Galileo || || || || 2 || None ||<br />
|-<br />
| Intel || Galileo Gen 2 || || || || 1 || None ||<br />
|-<br />
| Intel/Circuitco || Minnowboard Max || Intel Bay Trail I || || || 1 || FSP, ME ||<br />
|-<br />
| Intel/ADI || Minnowboard Turbot || Intel Bay Trail I || || || 1 || FSP, ME ||<br />
|-<br />
| Intel || Mohon Peak || Intel Rangeley || || || 1 || FSP ||<br />
|-<br />
| Lenovo || T500 || || || || 1 || None ||<br />
|-<br />
| Lenovo || W500 || || || || 1 || None ||<br />
|-<br />
| Lenovo || T520 || Intel Sandybridge || || || 1 || ME ||<br />
|-<br />
| Lenovo || T530 || Intel Ivybridge || || 2 DDR-3 SODIMMS || 1 || ME ||<br />
|-<br />
| Lenovo || X230 || Intel Ivybridge || || 2 DDR-3 SODIMMS || 1 || ME ||<br />
|-<br />
| Lenovo || W530 || Intel Ivybridge || || 4 DDR-3 SODIMMS || 2 || ME || Grumpybuilder<br />
|-<br />
| PC Engines || APU2C4 || || || || 1 || ||<br />
|-<br />
| Supermicro || H8SCM || AMD Family 10h / 15h || AMD SP5100 || 4 DDR3 DIMMs || 1 || ||<br />
|}<br />
<br />
==Links==<br />
===General Hardware & BIOS===<br />
* [http://helppc.netcore2k.net/topics HelpPC - Asm, C, Hardware, Interrupts, Tables for DOS & BIOS]<br />
* [http://www.ctyme.com/rbrown.htm Ralf Brown's Interrupt List]<br />
====_HID & EisaID====<br />
* [http://www-pc.uni-regensburg.de/hardware/TECHNIK/PCI_PNP/pnpid.txt EisaId list]<br />
* [http://download.microsoft.com/download/1/6/1/161ba512-40e2-4cc9-843a-923143f3456c/devids.txt EisaId list from Microsoft]<br />
* [http://lkml.iu.edu/hypermail/linux/kernel/1504.0/04084.html PRP0001 specifically means "Use the 'compatible' property to find the driver for this device"]<br />
<br />
===Payloads===<br />
* [http://www.memtest.org/download/ memtest downloads]<br />
<br />
<br />
==Fedora setup==<br />
Tested on Fedora 20 & 21<br />
sudo yum install git gcc gcc-c++ flex bison ncurses-devel acpica-tools wget patch pciutils-devel<br />
git clone http://review.coreboot.org/coreboot<br />
cd coreboot<br />
git submodule update --init --checkout<br />
make crossgcc-i386<br />
<br />
Optional installs:<br />
sudo yum install ccache clang<br />
<br />
<br />
===Flashing 3MB of 8MB ROM on minnowboard max===<br />
echo 00500000:007fffff cb-region > 8mb ; flashrom -p dediprog:voltage=1.8v -l 8mb -i cb-region -w build/coreboot.rom<br />
<br />
<br />
=== Coreboot lessons ===<br />
[[Lesson1]] - Starting from scratch. Download coreboot, build it, and test the image on QEMU.</div>MartinRothhttps://www.coreboot.org/index.php?title=User:MartinRoth&diff=27532User:MartinRoth2017-07-23T21:40:09Z<p>MartinRoth: </p>
<hr />
<div>==Martin Roth==<br />
<br />
[[File:Martin.jpg]]<br />
<br />
Email:<br />
:gaumless@gmail.com<br />
:martinroth@google.com<br />
<br />
IRC:<br />
:martinr (usually)<br />
:gaumless (occasionally)<br />
<br />
==Useful commands==<br />
=== See what Kconfig symbols are used in a platform ===<br />
make clean; make filelist; for file in $(grep -v 'config\.h' build/project_filelist.txt); do grep CONFIG_ "$file"; done | grep -Ev '[_A-Za-z]CONFIG' | sed 's/.*[-(\)\[\$!"[:space:]]CONFIG_/CONFIG_/'|sed 's/[^A-Z0-9_].*//' | sort | uniq<br />
<br />
<br />
==Platforms supported by coreboot==<br />
{| class="wikitable"<br />
! Vendor !! Board !! Processor !! Southbridge !! Memory !! Count !! Blobs !! Used as<br />
|-<br />
| ADI || SG-2220 || Intel Rangeley || - || 2GB DDR3L Soldered Down || 1 || FSP ||<br />
|-<br />
| ADI || SG-2440 || Intel Rangeley || - || 4GB DDR3L Soldered Down || 1 || FSP ||<br />
|-<br />
| AMD || Bettong (DB-FP4) || || || || 1 || Yes || <br />
|-<br />
| AMD || Kino || AMD Family 10h || || || 1 || ||<br />
|-<br />
| AMD || Lamar || || || || 1 || ||<br />
|-<br />
| AMD || Mahogony || AMD Family F || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| AMD || Mahogony || AMD Family 10h || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| AMD || Olive Hill || || || || 1 || ||<br />
|-<br />
| AMD || Parmer || AMD Family 15TN || AMD Hudson || || 2 || ||<br />
|-<br />
| AMD || Pistachio || AMD Family F || AMD SB600|| || 1 || ||<br />
|-<br />
| AMD || Persimmon [DB-FT1] || AMD Family 14h || AMD SB800 || || 3 || ||<br />
|-<br />
| AMD || Pumori || || || || 1 || ||<br />
|-<br />
| AMD || Thatcher || AMD Family 15TN || AMD Hudson || || 1 || ||<br />
|-<br />
| AMD || Torpedo || AMD Family 12h || AMD SB900 || || 1 || ||<br />
|-<br />
| Asrock || E350M1/USB3 || AMD Family 14h || || || 1 || ||<br />
|-<br />
| Asrock || IMB-A180 || || || || 2 || ||<br />
|-<br />
| ASUS || F2A85-M || AMD Family 15TN || || || 1 || ||<br />
|-<br />
| ASUS || KGPE-D16 || AMD Family 10h / 15h || || || 1 || None || Lumberingbuilder<br />
|-<br />
| ASUS || KFSN4-DRE || || || || 1 || ||<br />
|-<br />
| ASUS || P5GC-MX || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-B75M-D3H || Intel Ivybridge || || 4 DDR3 UDIMMs || 1 || ME || Happybuilder<br />
|-<br />
| Gigabyte || GA-G41M-ES2L || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-945-GCM-S2L || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-MA78GM || AMD AM2+ socket || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| Gizmosphere || Gizmo || AMD Family 14h || || Soldered down || 3 || ||<br />
|-<br />
| Gizmosphere || Gizmo2 || || || Soldered down || 1 || Yes ||<br />
|-<br />
| Intel || Bakersport || Intel Bay Trail I SOC || - || 1 ECC DDR-3 SODIMM || 1 || FSP, ME ||<br />
|-<br />
| Intel || Bayley Bay || Intel Bay Trail I SOC || - || 2 DDR-3 SODIMM || 1 || FSP, ME ||<br />
|-<br />
| Intel || Camelback Mountain || Broadwell DE SOC || - || 2 DDR-4 UDIMMs || 1 || FSP, ME ||<br />
|-<br />
| Intel || Cougar Canyon || Intel Ivybridge || || || 1 || FSP, ME ||<br />
|-<br />
| Intel || D510MO || || I82801GB (ICH7) || 2 DDR-2 UDIMMs || 1 || None ||<br />
|-<br />
| Intel || Galileo || || || || 2 || None ||<br />
|-<br />
| Intel || Galileo Gen 2 || || || || 1 || None ||<br />
|-<br />
| Intel/Circuitco || Minnowboard Max || Intel Bay Trail I || || || 1 || FSP, ME ||<br />
|-<br />
| Intel/ADI || Minnowboard Turbot || Intel Bay Trail I || || || 1 || FSP, ME ||<br />
|-<br />
| Intel || Mohon Peak || Intel Rangeley || || || 1 || FSP ||<br />
|-<br />
| Lenovo || T500 || || || || 1 || None ||<br />
|-<br />
| Lenovo || W500 || || || || 1 || None ||<br />
|-<br />
| Lenovo || T520 || Intel Sandybridge || || || 1 || ME ||<br />
|-<br />
| Lenovo || T530 || Intel Ivybridge || || 2 DDR-3 SODIMMS || 1 || ME ||<br />
|-<br />
| Lenovo || X230 || Intel Ivybridge || || 2 DDR-3 SODIMMS || 1 || ME ||<br />
|-<br />
| Lenovo || W530 || Intel Ivybridge || || 4 DDR-3 SODIMMS || 2 || ME || Grumpybuilder<br />
|-<br />
| PC Engines || APU2C4 || || || || 1 || ||<br />
|-<br />
| Supermicro || H8SCM || AMD Family 10h / 15h || AMD SP5100 || 4 DDR3 DIMMs || 1 || ||<br />
|}<br />
<br />
==Links==<br />
===General Hardware & BIOS===<br />
* [http://helppc.netcore2k.net/topics HelpPC - Asm, C, Hardware, Interrupts, Tables for DOS & BIOS]<br />
* [http://www.ctyme.com/rbrown.htm Ralf Brown's Interrupt List]<br />
====_HID & EisaID====<br />
* [http://www-pc.uni-regensburg.de/hardware/TECHNIK/PCI_PNP/pnpid.txt EisaId list]<br />
* [http://download.microsoft.com/download/1/6/1/161ba512-40e2-4cc9-843a-923143f3456c/devids.txt EisaId list from Microsoft]<br />
* [http://lkml.iu.edu/hypermail/linux/kernel/1504.0/04084.html PRP0001 specifically means "Use the 'compatible' property to find the driver for this device"]<br />
<br />
===Payloads===<br />
* [http://www.memtest.org/download/ memtest downloads]<br />
<br />
<br />
==Fedora setup==<br />
Tested on Fedora 20 & 21<br />
sudo yum install git gcc gcc-c++ flex bison ncurses-devel acpica-tools wget patch pciutils-devel<br />
git clone http://review.coreboot.org/coreboot<br />
cd coreboot<br />
git submodule update --init --checkout<br />
make crossgcc-i386<br />
<br />
Optional installs:<br />
sudo yum install ccache clang<br />
<br />
<br />
===Flashing 3MB of 8MB ROM on minnowboard max===<br />
echo 00500000:007fffff cb-region > 8mb ; flashrom -p dediprog:voltage=1.8v -l 8mb -i cb-region -w build/coreboot.rom<br />
<br />
<br />
=== Coreboot lessons ===<br />
[[Lesson1]] - Starting from scratch. Download coreboot, build it, and test the image on QEMU.</div>MartinRothhttps://www.coreboot.org/index.php?title=Lesson1&diff=27217Lesson12017-07-08T20:06:11Z<p>MartinRoth: /* 5 */</p>
<hr />
<div>coreboot lesson 1 - Starting from scratch<br />
<br />
From a fresh [http://releases.ubuntu.com/16.04/ubuntu-16.04-desktop-amd64.iso ubuntu 16.04 linux] install, here are all the steps required for a very basic build:<br />
<br />
==Download, configure, and build coreboot ==<br />
<br />
===Step [[Lesson1#1|1]] - Install tools and libraries needed for coreboot ===<br />
<br />
$ sudo apt-get install -y git libncurses5-dev m4 bison flex zlib1g-dev<br />
<br />
===Step [[Lesson1#2|2]] - Download coreboot source tree ===<br />
$ git clone https://review.coreboot.org/coreboot<br />
$ cd coreboot<br />
<br />
===Step [[Lesson1#3|3]] - Build the coreboot toolchain ===<br />
Please note that this can take a significant amount of time<br />
$ make crossgcc-i386 CPUS=$(nproc)<br />
<br />
===Step [[Lesson1#4|4]] - Build the payload - coreinfo ===<br />
$ make -C payloads/coreinfo olddefconfig<br />
$ make -C payloads/coreinfo<br />
<br />
===Step [[Lesson1#5|5]] - Configure the mainboard ===<br />
$ make menuconfig<br />
select 'Mainboard' menu<br />
Beside 'Mainboard vendor' should be '(Emulation)'<br />
Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'<br />
select exit<br />
<br />
select 'Payload' menu<br />
select 'Add a Payload'<br />
choose 'An Elf executable payload'<br />
select 'Payload path and filename'<br />
enter 'payloads/coreinfo/build/coreinfo.elf'<br />
select exit<br />
select exit<br />
select yes<br />
<br />
check your configuration (optional step):<br />
$ make savedefconfig<br />
$ cat defconfig<br />
<br />
There should only be two lines:<br />
CONFIG_PAYLOAD_ELF=y<br />
CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"<br />
<br />
===Step [[Lesson1#6|6]] - build coreboot ===<br />
$ make<br />
<br />
At the end of the build, you should see:<br />
Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)<br />
<br />
This means your build was successful. The output from the build<br />
is in the build directory. build/coreboot.rom is the full rom file.<br />
<br />
== Test the image using QEMU ==<br />
<br />
=== Step [[Lesson1#7|7]] - Install QEMU ===<br />
$ sudo apt-get install -y qemu<br />
<br />
=== Step [[Lesson1#8|8]] - Run QEMU ===<br />
Start QEMU, and point it to the ROM you just built:<br />
$ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio<br />
<br />
You should see the serial output of coreboot in the original console window, and a new window will appear running the coreinfo payload.<br />
<br />
==Summary:==<br />
<br />
=== 1 === <br />
Install tools and libraries needed for coreboot.<br />
<br />
You installed the minimum additional requirements for ubuntu to download and build coreboot. <br />
Ubuntu already has most of the other tools that would be required installed by default. <br />
- git is needed to download coreboot from the coreboot git repository.<br />
- libncurses5-dev is needed to build the menu for 'make menuconfig'<br />
- m4, bison, flex, and zlib1g-dev are needed to build the coreboot toolchain.<br />
If you had started from a different distribution, you might need to install the basic gcc toolchain, wget, make, or many other items.<br />
<br />
=== 2 ===<br />
Download coreboot source tree.<br />
<br />
This will download a 'read-only' copy of the coreboot tree. This just means that if you made changes to the coreboot tree, you couldn't immediately contribute them back to the community. To pull a copy of coreboot that would allow you to contribute back, you would first need to sign up for an account on gerrit.<br />
<br />
=== 3 ===<br />
Build the coreboot toolchain.<br />
<br />
This builds one of the coreboot cross-compiler toolchains for X86 platforms. Because of the variability of compilers and the other required tools between the various operating systems that coreboot can be built on, coreboot supplies and uses its own cross-compiler toolchain to build the binaries that end up as part of the coreboot ROM. The toolchain provided by the operating system (the 'host toolchain') is used to build various tools that will run on the local system during the build process.<br />
<br />
=== 4 ===<br />
Build the payload.<br />
<br />
To actually do anything useful with coreboot, you need to build a payload to include in the rom. The idea behind coreboot is that it does the minimum amount possible before passing control of the machine to a payload. There are various payloads such as grub or SeaBIOS that are typically used to boot the operating system. Instead, we used coreinfo, a small demonstration payload that allows the user to look at various things such as memory and the contents of coreboot's cbfs - the pieces that make up the coreboot rom.<br />
<br />
=== 5 ===<br />
Configure the mainboard.<br />
<br />
This step configures coreboot's build options using the menuconfig interface to Kconfig. Kconfig is the same configuration program used by the linux kernel. It allows you to enable, disable, and change various values to control the coreboot build process, including which mainboard(motherboard) to use, which toolchain to use, and how the runtime debug console should be presented and saved.<br />
<br />
Anytime you change mainboards in Kconfig, you should always run "make distclean" before running "make menuconfig". Due to the way that Kconfig works, values will be kept from the previous mainboard if you skip the clean step. This leads to a hybrid configuration which may or may not work as expected.<br />
<br />
=== 6 ===<br />
Build coreboot.<br />
<br />
You may notice that a number of other pieces are downloaded at the beginning of the build process. These are the git submodules used in various coreboot builds. By default, the BLOBs submodule is not downloaded. This git submodule may be required for other builds for microcode or other binaries. To enable downloading this submodule, select the option "Allow use of binary-only repository" in the "General Setup" menu of Kconfig<br />
<br />
This attempts to build the coreboot rom. The rom file itself ends up in the build directory as 'coreboot.rom'. At the end of the build process, the build displayed the contents of the rom file.<br />
<br />
=== 7 ===<br />
Install QEMU<br />
<br />
QEMU is a processor emulator which we can use to show coreboot <br />
<br />
=== 8 ===<br />
Run QEMU.<br />
<br />
Here's the command line broken down:<br />
<br />
qemu-system-x86_64<br />
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge.<br />
<br />
-bios build/coreboot.rom<br />
Use the bios rom image that we just built. If this is left off, the standard SeaBIOS image that comes with QEMU is used.<br />
<br />
-serial stdio<br />
Send the serial output to the console. This allows you to view the coreboot debug output.</div>MartinRothhttps://www.coreboot.org/index.php?title=Lesson1&diff=27214Lesson12017-07-08T19:48:35Z<p>MartinRoth: /* 6 */</p>
<hr />
<div>coreboot lesson 1 - Starting from scratch<br />
<br />
From a fresh [http://releases.ubuntu.com/16.04/ubuntu-16.04-desktop-amd64.iso ubuntu 16.04 linux] install, here are all the steps required for a very basic build:<br />
<br />
==Download, configure, and build coreboot ==<br />
<br />
===Step [[Lesson1#1|1]] - Install tools and libraries needed for coreboot ===<br />
<br />
$ sudo apt-get install -y git libncurses5-dev m4 bison flex zlib1g-dev<br />
<br />
===Step [[Lesson1#2|2]] - Download coreboot source tree ===<br />
$ git clone https://review.coreboot.org/coreboot<br />
$ cd coreboot<br />
<br />
===Step [[Lesson1#3|3]] - Build the coreboot toolchain ===<br />
Please note that this can take a significant amount of time<br />
$ make crossgcc-i386 CPUS=$(nproc)<br />
<br />
===Step [[Lesson1#4|4]] - Build the payload - coreinfo ===<br />
$ make -C payloads/coreinfo olddefconfig<br />
$ make -C payloads/coreinfo<br />
<br />
===Step [[Lesson1#5|5]] - Configure the mainboard ===<br />
$ make menuconfig<br />
select 'Mainboard' menu<br />
Beside 'Mainboard vendor' should be '(Emulation)'<br />
Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'<br />
select exit<br />
<br />
select 'Payload' menu<br />
select 'Add a Payload'<br />
choose 'An Elf executable payload'<br />
select 'Payload path and filename'<br />
enter 'payloads/coreinfo/build/coreinfo.elf'<br />
select exit<br />
select exit<br />
select yes<br />
<br />
check your configuration (optional step):<br />
$ make savedefconfig<br />
$ cat defconfig<br />
<br />
There should only be two lines:<br />
CONFIG_PAYLOAD_ELF=y<br />
CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"<br />
<br />
===Step [[Lesson1#6|6]] - build coreboot ===<br />
$ make<br />
<br />
At the end of the build, you should see:<br />
Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)<br />
<br />
This means your build was successful. The output from the build<br />
is in the build directory. build/coreboot.rom is the full rom file.<br />
<br />
== Test the image using QEMU ==<br />
<br />
=== Step [[Lesson1#7|7]] - Install QEMU ===<br />
$ sudo apt-get install -y qemu<br />
<br />
=== Step [[Lesson1#8|8]] - Run QEMU ===<br />
Start QEMU, and point it to the ROM you just built:<br />
$ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio<br />
<br />
You should see the serial output of coreboot in the original console window, and a new window will appear running the coreinfo payload.<br />
<br />
==Summary:==<br />
<br />
=== 1 === <br />
Install tools and libraries needed for coreboot.<br />
<br />
You installed the minimum additional requirements for ubuntu to download and build coreboot. <br />
Ubuntu already has most of the other tools that would be required installed by default. <br />
- git is needed to download coreboot from the coreboot git repository.<br />
- libncurses5-dev is needed to build the menu for 'make menuconfig'<br />
- m4, bison, flex, and zlib1g-dev are needed to build the coreboot toolchain.<br />
If you had started from a different distribution, you might need to install the basic gcc toolchain, wget, make, or many other items.<br />
<br />
=== 2 ===<br />
Download coreboot source tree.<br />
<br />
This will download a 'read-only' copy of the coreboot tree. This just means that if you made changes to the coreboot tree, you couldn't immediately contribute them back to the community. To pull a copy of coreboot that would allow you to contribute back, you would first need to sign up for an account on gerrit.<br />
<br />
=== 3 ===<br />
Build the coreboot toolchain.<br />
<br />
This builds one of the coreboot cross-compiler toolchains for X86 platforms. Because of the variability of compilers and the other required tools between the various operating systems that coreboot can be built on, coreboot supplies and uses its own cross-compiler toolchain to build the binaries that end up as part of the coreboot ROM. The toolchain provided by the operating system (the 'host toolchain') is used to build various tools that will run on the local system during the build process.<br />
<br />
=== 4 ===<br />
Build the payload.<br />
<br />
To actually do anything useful with coreboot, you need to build a payload to include in the rom. The idea behind coreboot is that it does the minimum amount possible before passing control of the machine to a payload. There are various payloads such as grub or SeaBIOS that are typically used to boot the operating system. Instead, we used coreinfo, a small demonstration payload that allows the user to look at various things such as memory and the contents of coreboot's cbfs - the pieces that make up the coreboot rom.<br />
<br />
=== 5 ===<br />
Configure the mainboard.<br />
<br />
This step configures coreboot's build options using the menuconfig interface to Kconfig. Kconfig is the same configuration program used by the linux kernel. It allows you to enable, disable, and change various values to control the coreboot build process, including which mainboard(motherboard) to use, which toolchain to use, and how the runtime debug console should be presented and saved.<br />
<br />
=== 6 ===<br />
Build coreboot.<br />
<br />
You may notice that a number of other pieces are downloaded at the beginning of the build process. These are the git submodules used in various coreboot builds. By default, the BLOBs submodule is not downloaded. This git submodule may be required for other builds for microcode or other binaries. To enable downloading this submodule, select the option "Allow use of binary-only repository" in the "General Setup" menu of Kconfig<br />
<br />
This attempts to build the coreboot rom. The rom file itself ends up in the build directory as 'coreboot.rom'. At the end of the build process, the build displayed the contents of the rom file.<br />
<br />
=== 7 ===<br />
Install QEMU<br />
<br />
QEMU is a processor emulator which we can use to show coreboot <br />
<br />
=== 8 ===<br />
Run QEMU.<br />
<br />
Here's the command line broken down:<br />
<br />
qemu-system-x86_64<br />
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge.<br />
<br />
-bios build/coreboot.rom<br />
Use the bios rom image that we just built. If this is left off, the standard SeaBIOS image that comes with QEMU is used.<br />
<br />
-serial stdio<br />
Send the serial output to the console. This allows you to view the coreboot debug output.</div>MartinRothhttps://www.coreboot.org/index.php?title=Lesson1&diff=27213Lesson12017-07-08T19:44:25Z<p>MartinRoth: /* 3 */</p>
<hr />
<div>coreboot lesson 1 - Starting from scratch<br />
<br />
From a fresh [http://releases.ubuntu.com/16.04/ubuntu-16.04-desktop-amd64.iso ubuntu 16.04 linux] install, here are all the steps required for a very basic build:<br />
<br />
==Download, configure, and build coreboot ==<br />
<br />
===Step [[Lesson1#1|1]] - Install tools and libraries needed for coreboot ===<br />
<br />
$ sudo apt-get install -y git libncurses5-dev m4 bison flex zlib1g-dev<br />
<br />
===Step [[Lesson1#2|2]] - Download coreboot source tree ===<br />
$ git clone https://review.coreboot.org/coreboot<br />
$ cd coreboot<br />
<br />
===Step [[Lesson1#3|3]] - Build the coreboot toolchain ===<br />
Please note that this can take a significant amount of time<br />
$ make crossgcc-i386 CPUS=$(nproc)<br />
<br />
===Step [[Lesson1#4|4]] - Build the payload - coreinfo ===<br />
$ make -C payloads/coreinfo olddefconfig<br />
$ make -C payloads/coreinfo<br />
<br />
===Step [[Lesson1#5|5]] - Configure the mainboard ===<br />
$ make menuconfig<br />
select 'Mainboard' menu<br />
Beside 'Mainboard vendor' should be '(Emulation)'<br />
Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'<br />
select exit<br />
<br />
select 'Payload' menu<br />
select 'Add a Payload'<br />
choose 'An Elf executable payload'<br />
select 'Payload path and filename'<br />
enter 'payloads/coreinfo/build/coreinfo.elf'<br />
select exit<br />
select exit<br />
select yes<br />
<br />
check your configuration (optional step):<br />
$ make savedefconfig<br />
$ cat defconfig<br />
<br />
There should only be two lines:<br />
CONFIG_PAYLOAD_ELF=y<br />
CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"<br />
<br />
===Step [[Lesson1#6|6]] - build coreboot ===<br />
$ make<br />
<br />
At the end of the build, you should see:<br />
Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)<br />
<br />
This means your build was successful. The output from the build<br />
is in the build directory. build/coreboot.rom is the full rom file.<br />
<br />
== Test the image using QEMU ==<br />
<br />
=== Step [[Lesson1#7|7]] - Install QEMU ===<br />
$ sudo apt-get install -y qemu<br />
<br />
=== Step [[Lesson1#8|8]] - Run QEMU ===<br />
Start QEMU, and point it to the ROM you just built:<br />
$ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio<br />
<br />
You should see the serial output of coreboot in the original console window, and a new window will appear running the coreinfo payload.<br />
<br />
==Summary:==<br />
<br />
=== 1 === <br />
Install tools and libraries needed for coreboot.<br />
<br />
You installed the minimum additional requirements for ubuntu to download and build coreboot. <br />
Ubuntu already has most of the other tools that would be required installed by default. <br />
- git is needed to download coreboot from the coreboot git repository.<br />
- libncurses5-dev is needed to build the menu for 'make menuconfig'<br />
- m4, bison, flex, and zlib1g-dev are needed to build the coreboot toolchain.<br />
If you had started from a different distribution, you might need to install the basic gcc toolchain, wget, make, or many other items.<br />
<br />
=== 2 ===<br />
Download coreboot source tree.<br />
<br />
This will download a 'read-only' copy of the coreboot tree. This just means that if you made changes to the coreboot tree, you couldn't immediately contribute them back to the community. To pull a copy of coreboot that would allow you to contribute back, you would first need to sign up for an account on gerrit.<br />
<br />
=== 3 ===<br />
Build the coreboot toolchain.<br />
<br />
This builds one of the coreboot cross-compiler toolchains for X86 platforms. Because of the variability of compilers and the other required tools between the various operating systems that coreboot can be built on, coreboot supplies and uses its own cross-compiler toolchain to build the binaries that end up as part of the coreboot ROM. The toolchain provided by the operating system (the 'host toolchain') is used to build various tools that will run on the local system during the build process.<br />
<br />
=== 4 ===<br />
Build the payload.<br />
<br />
To actually do anything useful with coreboot, you need to build a payload to include in the rom. The idea behind coreboot is that it does the minimum amount possible before passing control of the machine to a payload. There are various payloads such as grub or SeaBIOS that are typically used to boot the operating system. Instead, we used coreinfo, a small demonstration payload that allows the user to look at various things such as memory and the contents of coreboot's cbfs - the pieces that make up the coreboot rom.<br />
<br />
=== 5 ===<br />
Configure the mainboard.<br />
<br />
This step configures coreboot's build options using the menuconfig interface to Kconfig. Kconfig is the same configuration program used by the linux kernel. It allows you to enable, disable, and change various values to control the coreboot build process, including which mainboard(motherboard) to use, which toolchain to use, and how the runtime debug console should be presented and saved.<br />
<br />
=== 6 ===<br />
Build coreboot.<br />
<br />
This attempts to build the coreboot rom. The rom file itself ends up in the build directory as 'coreboot.rom'. If you noticed at the end of the build process, the build displayed the contents of the rom file.<br />
<br />
=== 7 ===<br />
Install QEMU<br />
<br />
QEMU is a processor emulator which we can use to show coreboot <br />
<br />
=== 8 ===<br />
Run QEMU.<br />
<br />
Here's the command line broken down:<br />
<br />
qemu-system-x86_64<br />
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge.<br />
<br />
-bios build/coreboot.rom<br />
Use the bios rom image that we just built. If this is left off, the standard SeaBIOS image that comes with QEMU is used.<br />
<br />
-serial stdio<br />
Send the serial output to the console. This allows you to view the coreboot debug output.</div>MartinRothhttps://www.coreboot.org/index.php?title=Lesson1&diff=27210Lesson12017-07-08T18:32:23Z<p>MartinRoth: /* Step 5 - Configure the mainboard */</p>
<hr />
<div>coreboot lesson 1 - Starting from scratch<br />
<br />
From a fresh [http://releases.ubuntu.com/16.04/ubuntu-16.04-desktop-amd64.iso ubuntu 16.04 linux] install, here are all the steps required for a very basic build:<br />
<br />
==Download, configure, and build coreboot ==<br />
<br />
===Step [[Lesson1#1|1]] - Install tools and libraries needed for coreboot ===<br />
<br />
$ sudo apt-get install -y git libncurses5-dev m4 bison flex zlib1g-dev<br />
<br />
===Step [[Lesson1#2|2]] - Download coreboot source tree ===<br />
$ git clone https://review.coreboot.org/coreboot<br />
$ cd coreboot<br />
<br />
===Step [[Lesson1#3|3]] - Build the coreboot toolchain ===<br />
Please note that this can take a significant amount of time<br />
$ make crossgcc-i386 CPUS=$(nproc)<br />
<br />
===Step [[Lesson1#4|4]] - Build the payload - coreinfo ===<br />
$ make -C payloads/coreinfo olddefconfig<br />
$ make -C payloads/coreinfo<br />
<br />
===Step [[Lesson1#5|5]] - Configure the mainboard ===<br />
$ make menuconfig<br />
select 'Mainboard' menu<br />
Beside 'Mainboard vendor' should be '(Emulation)'<br />
Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'<br />
select exit<br />
<br />
select 'Payload' menu<br />
select 'Add a Payload'<br />
choose 'An Elf executable payload'<br />
select 'Payload path and filename'<br />
enter 'payloads/coreinfo/build/coreinfo.elf'<br />
select exit<br />
select exit<br />
select yes<br />
<br />
check your configuration (optional step):<br />
$ make savedefconfig<br />
$ cat defconfig<br />
<br />
There should only be two lines:<br />
CONFIG_PAYLOAD_ELF=y<br />
CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"<br />
<br />
===Step [[Lesson1#6|6]] - build coreboot ===<br />
$ make<br />
<br />
At the end of the build, you should see:<br />
Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)<br />
<br />
This means your build was successful. The output from the build<br />
is in the build directory. build/coreboot.rom is the full rom file.<br />
<br />
== Test the image using QEMU ==<br />
<br />
=== Step [[Lesson1#7|7]] - Install QEMU ===<br />
$ sudo apt-get install -y qemu<br />
<br />
=== Step [[Lesson1#8|8]] - Run QEMU ===<br />
Start QEMU, and point it to the ROM you just built:<br />
$ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio<br />
<br />
You should see the serial output of coreboot in the original console window, and a new window will appear running the coreinfo payload.<br />
<br />
==Summary:==<br />
<br />
=== 1 === <br />
Install tools and libraries needed for coreboot.<br />
<br />
You installed the minimum additional requirements for ubuntu to download and build coreboot. <br />
Ubuntu already has most of the other tools that would be required installed by default. <br />
- git is needed to download coreboot from the coreboot git repository.<br />
- libncurses5-dev is needed to build the menu for 'make menuconfig'<br />
- m4, bison, flex, and zlib1g-dev are needed to build the coreboot toolchain.<br />
If you had started from a different distribution, you might need to install the basic gcc toolchain, wget, make, or many other items.<br />
<br />
=== 2 ===<br />
Download coreboot source tree.<br />
<br />
This will download a 'read-only' copy of the coreboot tree. This just means that if you made changes to the coreboot tree, you couldn't immediately contribute them back to the community. To pull a copy of coreboot that would allow you to contribute back, you would first need to sign up for an account on gerrit.<br />
<br />
=== 3 ===<br />
Build the coreboot toolchain.<br />
<br />
This builds one of the coreboot cross-compiler toolchains for X86 platforms. Because of the variability of compilers and the other required tools between the various operating systems that coreboot can be built on, coreboot supplies and uses its own cross-compiler toolchain to build the binaries that end up as part of the coreboot ROM. The toolchain provided by the operating system (the 'host toolchain') is used to build various tools that will run on the local system during the build process.<br />
<br />
You may also notice that a number of other pieces are downloaded at the beginning of the build process. These are the git submodules used in various coreboot builds.<br />
<br />
=== 4 ===<br />
Build the payload.<br />
<br />
To actually do anything useful with coreboot, you need to build a payload to include in the rom. The idea behind coreboot is that it does the minimum amount possible before passing control of the machine to a payload. There are various payloads such as grub or SeaBIOS that are typically used to boot the operating system. Instead, we used coreinfo, a small demonstration payload that allows the user to look at various things such as memory and the contents of coreboot's cbfs - the pieces that make up the coreboot rom.<br />
<br />
=== 5 ===<br />
Configure the mainboard.<br />
<br />
This step configures coreboot's build options using the menuconfig interface to Kconfig. Kconfig is the same configuration program used by the linux kernel. It allows you to enable, disable, and change various values to control the coreboot build process, including which mainboard(motherboard) to use, which toolchain to use, and how the runtime debug console should be presented and saved.<br />
<br />
=== 6 ===<br />
Build coreboot.<br />
<br />
This attempts to build the coreboot rom. The rom file itself ends up in the build directory as 'coreboot.rom'. If you noticed at the end of the build process, the build displayed the contents of the rom file.<br />
<br />
=== 7 ===<br />
Install QEMU<br />
<br />
QEMU is a processor emulator which we can use to show coreboot <br />
<br />
=== 8 ===<br />
Run QEMU.<br />
<br />
Here's the command line broken down:<br />
<br />
qemu-system-x86_64<br />
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge.<br />
<br />
-bios build/coreboot.rom<br />
Use the bios rom image that we just built. If this is left off, the standard SeaBIOS image that comes with QEMU is used.<br />
<br />
-serial stdio<br />
Send the serial output to the console. This allows you to view the coreboot debug output.</div>MartinRothhttps://www.coreboot.org/index.php?title=Lesson1&diff=27209Lesson12017-07-08T18:31:59Z<p>MartinRoth: /* Step 5 - Configure the mainboard */</p>
<hr />
<div>coreboot lesson 1 - Starting from scratch<br />
<br />
From a fresh [http://releases.ubuntu.com/16.04/ubuntu-16.04-desktop-amd64.iso ubuntu 16.04 linux] install, here are all the steps required for a very basic build:<br />
<br />
==Download, configure, and build coreboot ==<br />
<br />
===Step [[Lesson1#1|1]] - Install tools and libraries needed for coreboot ===<br />
<br />
$ sudo apt-get install -y git libncurses5-dev m4 bison flex zlib1g-dev<br />
<br />
===Step [[Lesson1#2|2]] - Download coreboot source tree ===<br />
$ git clone https://review.coreboot.org/coreboot<br />
$ cd coreboot<br />
<br />
===Step [[Lesson1#3|3]] - Build the coreboot toolchain ===<br />
Please note that this can take a significant amount of time<br />
$ make crossgcc-i386 CPUS=$(nproc)<br />
<br />
===Step [[Lesson1#4|4]] - Build the payload - coreinfo ===<br />
$ make -C payloads/coreinfo olddefconfig<br />
$ make -C payloads/coreinfo<br />
<br />
===Step [[Lesson1#5|5]] - Configure the mainboard ===<br />
$ make menuconfig<br />
select 'Mainboard' menu<br />
Beside 'Mainboard vendor' should be '(Emulation)'<br />
Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'<br />
select exit<br />
<br />
select 'Payload' menu<br />
select 'Add a Payload'<br />
choose 'An Elf executable payload'<br />
select 'Payload path and filename'<br />
enter 'payloads/coreinfo/build/coreinfo.elf'<br />
select exit<br />
select exit<br />
select yes<br />
<br />
check your configuration (optinal step):<br />
$ make savedefconfig<br />
$ cat defconfig<br />
There should only be two lines:<br />
CONFIG_PAYLOAD_ELF=y<br />
CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"<br />
<br />
===Step [[Lesson1#6|6]] - build coreboot ===<br />
$ make<br />
<br />
At the end of the build, you should see:<br />
Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)<br />
<br />
This means your build was successful. The output from the build<br />
is in the build directory. build/coreboot.rom is the full rom file.<br />
<br />
== Test the image using QEMU ==<br />
<br />
=== Step [[Lesson1#7|7]] - Install QEMU ===<br />
$ sudo apt-get install -y qemu<br />
<br />
=== Step [[Lesson1#8|8]] - Run QEMU ===<br />
Start QEMU, and point it to the ROM you just built:<br />
$ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio<br />
<br />
You should see the serial output of coreboot in the original console window, and a new window will appear running the coreinfo payload.<br />
<br />
==Summary:==<br />
<br />
=== 1 === <br />
Install tools and libraries needed for coreboot.<br />
<br />
You installed the minimum additional requirements for ubuntu to download and build coreboot. <br />
Ubuntu already has most of the other tools that would be required installed by default. <br />
- git is needed to download coreboot from the coreboot git repository.<br />
- libncurses5-dev is needed to build the menu for 'make menuconfig'<br />
- m4, bison, flex, and zlib1g-dev are needed to build the coreboot toolchain.<br />
If you had started from a different distribution, you might need to install the basic gcc toolchain, wget, make, or many other items.<br />
<br />
=== 2 ===<br />
Download coreboot source tree.<br />
<br />
This will download a 'read-only' copy of the coreboot tree. This just means that if you made changes to the coreboot tree, you couldn't immediately contribute them back to the community. To pull a copy of coreboot that would allow you to contribute back, you would first need to sign up for an account on gerrit.<br />
<br />
=== 3 ===<br />
Build the coreboot toolchain.<br />
<br />
This builds one of the coreboot cross-compiler toolchains for X86 platforms. Because of the variability of compilers and the other required tools between the various operating systems that coreboot can be built on, coreboot supplies and uses its own cross-compiler toolchain to build the binaries that end up as part of the coreboot ROM. The toolchain provided by the operating system (the 'host toolchain') is used to build various tools that will run on the local system during the build process.<br />
<br />
You may also notice that a number of other pieces are downloaded at the beginning of the build process. These are the git submodules used in various coreboot builds.<br />
<br />
=== 4 ===<br />
Build the payload.<br />
<br />
To actually do anything useful with coreboot, you need to build a payload to include in the rom. The idea behind coreboot is that it does the minimum amount possible before passing control of the machine to a payload. There are various payloads such as grub or SeaBIOS that are typically used to boot the operating system. Instead, we used coreinfo, a small demonstration payload that allows the user to look at various things such as memory and the contents of coreboot's cbfs - the pieces that make up the coreboot rom.<br />
<br />
=== 5 ===<br />
Configure the mainboard.<br />
<br />
This step configures coreboot's build options using the menuconfig interface to Kconfig. Kconfig is the same configuration program used by the linux kernel. It allows you to enable, disable, and change various values to control the coreboot build process, including which mainboard(motherboard) to use, which toolchain to use, and how the runtime debug console should be presented and saved.<br />
<br />
=== 6 ===<br />
Build coreboot.<br />
<br />
This attempts to build the coreboot rom. The rom file itself ends up in the build directory as 'coreboot.rom'. If you noticed at the end of the build process, the build displayed the contents of the rom file.<br />
<br />
=== 7 ===<br />
Install QEMU<br />
<br />
QEMU is a processor emulator which we can use to show coreboot <br />
<br />
=== 8 ===<br />
Run QEMU.<br />
<br />
Here's the command line broken down:<br />
<br />
qemu-system-x86_64<br />
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge.<br />
<br />
-bios build/coreboot.rom<br />
Use the bios rom image that we just built. If this is left off, the standard SeaBIOS image that comes with QEMU is used.<br />
<br />
-serial stdio<br />
Send the serial output to the console. This allows you to view the coreboot debug output.</div>MartinRothhttps://www.coreboot.org/index.php?title=Lesson1&diff=27208Lesson12017-07-08T18:31:01Z<p>MartinRoth: /* Step 2 - Download coreboot source tree */</p>
<hr />
<div>coreboot lesson 1 - Starting from scratch<br />
<br />
From a fresh [http://releases.ubuntu.com/16.04/ubuntu-16.04-desktop-amd64.iso ubuntu 16.04 linux] install, here are all the steps required for a very basic build:<br />
<br />
==Download, configure, and build coreboot ==<br />
<br />
===Step [[Lesson1#1|1]] - Install tools and libraries needed for coreboot ===<br />
<br />
$ sudo apt-get install -y git libncurses5-dev m4 bison flex zlib1g-dev<br />
<br />
===Step [[Lesson1#2|2]] - Download coreboot source tree ===<br />
$ git clone https://review.coreboot.org/coreboot<br />
$ cd coreboot<br />
<br />
===Step [[Lesson1#3|3]] - Build the coreboot toolchain ===<br />
Please note that this can take a significant amount of time<br />
$ make crossgcc-i386 CPUS=$(nproc)<br />
<br />
===Step [[Lesson1#4|4]] - Build the payload - coreinfo ===<br />
$ make -C payloads/coreinfo olddefconfig<br />
$ make -C payloads/coreinfo<br />
<br />
===Step [[Lesson1#5|5]] - Configure the mainboard ===<br />
$ make menuconfig<br />
select 'Mainboard' menu<br />
Beside 'Mainboard vendor' should be '(Emulation)'<br />
Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'<br />
select exit<br />
<br />
select 'Payload' menu<br />
select 'Add a Payload'<br />
choose 'An Elf executable payload'<br />
select 'Payload path and filename'<br />
enter 'payloads/coreinfo/build/coreinfo.elf'<br />
select exit<br />
select exit<br />
select yes<br />
<br />
check your configuration:<br />
$ make savedefconfig<br />
$ cat defconfig<br />
There should only be two lines:<br />
CONFIG_PAYLOAD_ELF=y<br />
CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"<br />
<br />
===Step [[Lesson1#6|6]] - build coreboot ===<br />
$ make<br />
<br />
At the end of the build, you should see:<br />
Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)<br />
<br />
This means your build was successful. The output from the build<br />
is in the build directory. build/coreboot.rom is the full rom file.<br />
<br />
== Test the image using QEMU ==<br />
<br />
=== Step [[Lesson1#7|7]] - Install QEMU ===<br />
$ sudo apt-get install -y qemu<br />
<br />
=== Step [[Lesson1#8|8]] - Run QEMU ===<br />
Start QEMU, and point it to the ROM you just built:<br />
$ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio<br />
<br />
You should see the serial output of coreboot in the original console window, and a new window will appear running the coreinfo payload.<br />
<br />
==Summary:==<br />
<br />
=== 1 === <br />
Install tools and libraries needed for coreboot.<br />
<br />
You installed the minimum additional requirements for ubuntu to download and build coreboot. <br />
Ubuntu already has most of the other tools that would be required installed by default. <br />
- git is needed to download coreboot from the coreboot git repository.<br />
- libncurses5-dev is needed to build the menu for 'make menuconfig'<br />
- m4, bison, flex, and zlib1g-dev are needed to build the coreboot toolchain.<br />
If you had started from a different distribution, you might need to install the basic gcc toolchain, wget, make, or many other items.<br />
<br />
=== 2 ===<br />
Download coreboot source tree.<br />
<br />
This will download a 'read-only' copy of the coreboot tree. This just means that if you made changes to the coreboot tree, you couldn't immediately contribute them back to the community. To pull a copy of coreboot that would allow you to contribute back, you would first need to sign up for an account on gerrit.<br />
<br />
=== 3 ===<br />
Build the coreboot toolchain.<br />
<br />
This builds one of the coreboot cross-compiler toolchains for X86 platforms. Because of the variability of compilers and the other required tools between the various operating systems that coreboot can be built on, coreboot supplies and uses its own cross-compiler toolchain to build the binaries that end up as part of the coreboot ROM. The toolchain provided by the operating system (the 'host toolchain') is used to build various tools that will run on the local system during the build process.<br />
<br />
You may also notice that a number of other pieces are downloaded at the beginning of the build process. These are the git submodules used in various coreboot builds.<br />
<br />
=== 4 ===<br />
Build the payload.<br />
<br />
To actually do anything useful with coreboot, you need to build a payload to include in the rom. The idea behind coreboot is that it does the minimum amount possible before passing control of the machine to a payload. There are various payloads such as grub or SeaBIOS that are typically used to boot the operating system. Instead, we used coreinfo, a small demonstration payload that allows the user to look at various things such as memory and the contents of coreboot's cbfs - the pieces that make up the coreboot rom.<br />
<br />
=== 5 ===<br />
Configure the mainboard.<br />
<br />
This step configures coreboot's build options using the menuconfig interface to Kconfig. Kconfig is the same configuration program used by the linux kernel. It allows you to enable, disable, and change various values to control the coreboot build process, including which mainboard(motherboard) to use, which toolchain to use, and how the runtime debug console should be presented and saved.<br />
<br />
=== 6 ===<br />
Build coreboot.<br />
<br />
This attempts to build the coreboot rom. The rom file itself ends up in the build directory as 'coreboot.rom'. If you noticed at the end of the build process, the build displayed the contents of the rom file.<br />
<br />
=== 7 ===<br />
Install QEMU<br />
<br />
QEMU is a processor emulator which we can use to show coreboot <br />
<br />
=== 8 ===<br />
Run QEMU.<br />
<br />
Here's the command line broken down:<br />
<br />
qemu-system-x86_64<br />
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge.<br />
<br />
-bios build/coreboot.rom<br />
Use the bios rom image that we just built. If this is left off, the standard SeaBIOS image that comes with QEMU is used.<br />
<br />
-serial stdio<br />
Send the serial output to the console. This allows you to view the coreboot debug output.</div>MartinRothhttps://www.coreboot.org/index.php?title=Denver2017&diff=26878Denver20172017-06-22T03:42:53Z<p>MartinRoth: </p>
<hr />
<div>==Date and time==<br />
<br />
==Presentations from the 2016 coreboot conference in San Francisco, CA, USA==<br />
===Monday:===<br />
* Coming of Age: 18 years of coreboot - Stefan Reinauer<br />
* coreboot and the Software Freedom Conservancy - Martin Roth ([[:Media:Coreboot_and_the_Software_Freedom_Conservancy.pdf|slides]])<br />
* creating community - Nate Lappegaard <br />
* Tianocore as a coreboot payload - Evelyn Huang & Logan Carlson ([[:Media:Building_Tianocore_into_coreboot.pdf|slides]])<br />
* How to make your hardware completely incompatible with coreboot - Ron Minnich ([[:Media:How_to_make_hardware_that_is_unfriendly_to_coreboot.pdf|slides]])<br />
* The state of coreboot (according to git) - Martin Roth ([[:Media:The_state_of_coreboot_in_2017.pdf|slides]])<br />
* Coreboot for Dummies - Youness Alaoui (Purism) ([[:Media:Coreboot_for_Dummies_-_Youness_Alaoui.pdf|slides]])<br />
<br />
===Tuesday:===<br />
* U-Root - Ron Minnich ([[:Media:Denver_2017_coreboot_u-root.pdf|slides]])<br />
* AMD and coreboot: History and future - Marshall Dawson ([[:Media:AMD_and_coreboot-_History_and_Future_-_Marshall_Dawson.pdf|slides]])<br />
* How to create a trust anchor with coreboot: Trusted Computing vs Authenticated Code Modules - Philipp Deppenwiese ([[:Media:Tpm_-_Philipp.pdf|slides]])<br />
* Tools, git, gerrit, jenkins, bug tracking and testing - Martin Roth ([[:Media:Tools,_Git,_Gerrit,_Jenkins_and_Testing.pdf|slides]])<br />
* Developer interviews - Marc Jones ([[:Media:Coreboot_developer_interviews_2017.pdf|slides]])<br />
<br />
==Date and time==<br />
The coreboot conference was '''Monday, June 5 and Tuesday June 6, 2017'''.<br />
<br />
[https://goo.gl/uDNN9a Full Schedule]<br />
<br />
==Conference location==<br />
This conference was hosted by the coreboot project and will be held in '''Denver CO, USA''' at:<br/><br />
<br />
[http://www.sustainablecolorado.org/ The Alliance Center]<br/><br />
[https://goo.gl/maps/3NFf389aH972 1536 Wynkoop Street, Suite 100]<br/><br />
<br />
The Alliance Center is in Denver's LoDo (Lower Downtown) neighborhood, which has an incredible amount to do and see, so people were encouraged to come early to experience more of both Denver and Colorado in general.<br />
<br />
[[Category:Meetings]]</div>MartinRothhttps://www.coreboot.org/index.php?title=File:Coreboot_developer_interviews_2017.pdf&diff=26877File:Coreboot developer interviews 2017.pdf2017-06-22T03:41:55Z<p>MartinRoth: </p>
<hr />
<div></div>MartinRothhttps://www.coreboot.org/index.php?title=File:Tools,_Git,_Gerrit,_Jenkins_and_Testing.pdf&diff=26876File:Tools, Git, Gerrit, Jenkins and Testing.pdf2017-06-22T03:36:37Z<p>MartinRoth: </p>
<hr />
<div></div>MartinRothhttps://www.coreboot.org/index.php?title=File:Tpm_-_Philipp.pdf&diff=26875File:Tpm - Philipp.pdf2017-06-22T03:35:31Z<p>MartinRoth: </p>
<hr />
<div></div>MartinRothhttps://www.coreboot.org/index.php?title=File:AMD_and_coreboot-_History_and_Future_-_Marshall_Dawson.pdf&diff=26874File:AMD and coreboot- History and Future - Marshall Dawson.pdf2017-06-22T03:33:55Z<p>MartinRoth: </p>
<hr />
<div></div>MartinRothhttps://www.coreboot.org/index.php?title=File:Denver_2017_coreboot_u-root.pdf&diff=26873File:Denver 2017 coreboot u-root.pdf2017-06-22T03:33:09Z<p>MartinRoth: </p>
<hr />
<div></div>MartinRothhttps://www.coreboot.org/index.php?title=File:Coreboot_for_Dummies_-_Youness_Alaoui.pdf&diff=26872File:Coreboot for Dummies - Youness Alaoui.pdf2017-06-22T03:32:22Z<p>MartinRoth: </p>
<hr />
<div></div>MartinRothhttps://www.coreboot.org/index.php?title=File:The_state_of_coreboot_in_2017.pdf&diff=26871File:The state of coreboot in 2017.pdf2017-06-22T03:31:37Z<p>MartinRoth: </p>
<hr />
<div></div>MartinRothhttps://www.coreboot.org/index.php?title=File:How_to_make_hardware_that_is_unfriendly_to_coreboot.pdf&diff=26870File:How to make hardware that is unfriendly to coreboot.pdf2017-06-22T03:30:15Z<p>MartinRoth: </p>
<hr />
<div></div>MartinRothhttps://www.coreboot.org/index.php?title=File:Building_Tianocore_into_coreboot.pdf&diff=26869File:Building Tianocore into coreboot.pdf2017-06-22T03:29:05Z<p>MartinRoth: </p>
<hr />
<div></div>MartinRothhttps://www.coreboot.org/index.php?title=File:Coreboot_and_the_Software_Freedom_Conservancy.pdf&diff=26868File:Coreboot and the Software Freedom Conservancy.pdf2017-06-22T03:21:52Z<p>MartinRoth: </p>
<hr />
<div></div>MartinRothhttps://www.coreboot.org/index.php?title=Denver2017&diff=26867Denver20172017-06-22T03:20:33Z<p>MartinRoth: </p>
<hr />
<div>==Date and time==<br />
<br />
==Presentations from the 2016 coreboot conference in San Francisco, CA, USA==<br />
===Monday:===<br />
* Coming of Age: 18 years of coreboot - Stefan Reinauer<br />
* coreboot and the Software Freedom Conservancy - Martin Roth<br />
* creating community - Nate Lappegaard<br />
* Tianocore as a coreboot payload - Evelyn Huang & Logan Carlson<br />
* How to make your hardware completely incompatible with coreboot - Ron Minnich<br />
* The state of coreboot (according to git) - Martin Roth<br />
* Coreboot for Dummies - Youness Alaoui (Purism)<br />
<br />
===Tuesday:===<br />
* U-Root - Ron Minnich<br />
* AMD and coreboot: History and future - Marshall Dawson<br />
* How to create a trust anchor with coreboot: Trusted Computing vs Authenticated Code Modules - Philipp Deppenwiese<br />
* Porting the W520 to coreboot - Charlotte++<br />
* Tools, git, gerrit, jenkins, bug tracking and testing - Martin Roth<br />
* Developer interviews - Marc Jones<br />
<br />
==Date and time==<br />
The coreboot conference was '''Monday, June 5 and Tuesday June 6, 2017'''.<br />
<br />
[https://goo.gl/uDNN9a Full Schedule]<br />
<br />
==Conference location==<br />
This conference was hosted by the coreboot project and will be held in '''Denver CO, USA''' at:<br/><br />
<br />
[http://www.sustainablecolorado.org/ The Alliance Center]<br/><br />
[https://goo.gl/maps/3NFf389aH972 1536 Wynkoop Street, Suite 100]<br/><br />
<br />
The Alliance Center is in Denver's LoDo (Lower Downtown) neighborhood, which has an incredible amount to do and see, so people were encouraged to come early to experience more of both Denver and Colorado in general.<br />
<br />
[[Category:Meetings]]</div>MartinRothhttps://www.coreboot.org/index.php?title=Welcome_to_coreboot&diff=26612Welcome to coreboot2017-06-09T17:07:30Z<p>MartinRoth: </p>
<hr />
<div><table width="100%" valign="top"><tr valign="top"><td width="80%"><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
'''coreboot''' is an Open Source project aimed at replacing the proprietary [http://wikipedia.org/wiki/BIOS BIOS] (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a [[Payloads|payload]].<br />
<br />
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly from firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like [[SeaBIOS | PC BIOS services]] or [[TianoCore | UEFI]]. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.<br />
<br />
coreboot currently supports over '''[[Supported Motherboards|230]]''' different mainboards. Check the [[Support]] page to see if your system is supported.<br />
<br />
<small><br />
coreboot was formerly known as [http://www.coreboot.org/pipermail/coreboot/2008-January/029135.html LinuxBIOS]. <br />
</small><br />
</div><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
coreboot uses [[git]] for source control and [http://review.coreboot.org gerrit] as the patch review tool. Please read the [https://review.coreboot.org/gitweb/cgit/coreboot.git/plain/Documentation/gerrit_guidelines.md gerrit etiquette & guidelines] document before submitting or reviewing patches.<br />
</div><br />
<br />
{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%<br />
|-<br />
|style="vertical-align:top"|<br />
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{{Box|<br />
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BACKGROUND = yellow|<br />
WIDTH = 100%|<br />
ICON = <small>[[Benefits|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Benefits]]</span>|<br />
CONTENT =<br />
<small><br />
* 100% Free Software (GPL), no royalties, no license fees!<br />
* Fast boot times (500 milliseconds to verified Linux kernel)<br />
<!-- * Avoids the need for a slow/buggy/proprietary BIOS --><br />
<!-- * Runs in 32-Bit protected mode almost from the start --><br />
<!-- * Written in C, contains virtually no assembly code --><br />
* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]<br />
<!-- * Further features: netboot, serial console, remote flashing, ... --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = #d1adf6|<br />
WIDTH = 100%|<br />
ICON = <small>[[Use Cases|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Use Cases]]</span>|<br />
CONTENT =<br />
<small><br />
* Desktop PCs, servers, [[Laptop|laptops]]<br />
* [[Clusters]]<br />
<!-- * Set-Top-Boxes, thin clients --><br />
* Embedded solutions<br />
<!-- * [http://en.wikipedia.org/wiki/Small_form_factor Small form factor computers], [http://en.wikipedia.org/wiki/Home_theater_PC Home-theater PCs] --><br />
<!-- * No-moving-parts solutions (ROM chip as "disk") --><br />
<!-- * Non-standard scenarios (e.g. FPGA in Opteron socket) --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = lime|<br />
WIDTH = 100%|<br />
ICON = <small>[[Payloads|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Payloads]]</span>|<br />
CONTENT =<br />
<small><br />
* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] <!-- / [[OpenFirmware]] / [[OpenBIOS]] --><br />
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] <!-- / [http://openbsd.org/ OpenBSD]--><br />
* [[Etherboot]] / [[GPXE]] / [[iPXE]] / [[Payloads|...]]<br />
<!--* [[Memtest86]]<br />
* [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]--><br />
</small><br />
}}<br />
<br />
|}<br />
<br />
{| cellspacing=5 cellpadding=15 border=0 valign="top" width=100%<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_cb.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">About</span>'''<br /><small>Find out more about coreboot.</small><small><hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_devel.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Developers</span>'''<br /><small>Get involved! Help us make coreboot better.</small><small><hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree Browse Source] | [[GSoC]] | [[Where to start]] | [[Lesson1| Lesson 1]] | [[Distributed and Automated Testsystem|Testsystem]] | [https://coreboot.org/git-docs git-docs]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_status.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Status</span>'''<br /><small>Find out whether your hardware is already supported.</small><small><hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [[Blob Matrix|Blob Matrix]] | [http://qa.coreboot.org Build Status]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_tools.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Related Tools</span>'''<br /><small>Tools and libraries related to coreboot.</small><small><hr />[http://www.flashrom.org flashrom] | [[Superiotool]] | [[Nvramtool]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [http://serialice.com SerialICE]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_101.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Getting Started</span>'''<br /><small>Download coreboot and get started.</small><small><hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_support.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Support</span>'''<br /><small>Learn how to contact us and find help and support.</small><small><hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [[Glossary]] | [[coreboot Options|coreboot Options]]</small><br />
|}<br />
<br />
|}<br />
</td><td width="20%"><br />
<br />
[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]<br />
<br />
<br clear=all /><br />
<!-- Blog feed isn't currently working - commenting out for now.<br />
'''<span style="font-variant:small-caps; font-size:120%">[http://blogs.coreboot.org News (blog)]</span>'''<hr /><br />
<small><br />
<rss max=5>https://blogs.coreboot.org/feed/</rss><br />
</small><br />
--><br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[Current events|Events]]</span>'''<hr /><br />
<!-- List of upcoming events (remove events after they have taken place). --><br />
<small><br />
<br />
* Oct 26 - 29, 2017 - [https://ecc2017.coreboot.org European coreboot conference]<br />
* [[coreboot_community_meeting | Bi-weekly community meeting]]<br />
* [https://www.google.com/maps/place/Finowstra%C3%9Fe+2A,+10247+Berlin,+Germany Monthly coreboot users group meeting Berlin]<br />
<!-- * Currently none --><br />
<!--* '''2015/mon/day:''' coreboot event at [[Link]] in somecity --><br />
[https://www.coreboot.org/calendar.html Full calendar]<br />
</small><br />
<br />
<br />
<br clear=all /><br />
<br />
</td></tr></table><br />
<br />
__NOTOC__<br />
__NOEDITSECTION__</div>MartinRothhttps://www.coreboot.org/index.php?title=Build_HOWTO&diff=26611Build HOWTO2017-06-09T17:06:21Z<p>MartinRoth: /* Building coreboot */</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++ (gcc-multilib is ideal, makes building payloads a lot easier)<br />
* make<br />
* cmake (if using clang/llvm)<br />
* ncurses-dev (for '''make menuconfig''')<br />
* iasl (for targets with ACPI support)<br />
* flex and bison (for regenerating parsers)<br />
<br />
Optional:<br />
* doxygen (for generating/viewing documentation)<br />
<br />
==== debian ====<br />
<pre>apt-get install git build-essential flex bison libncurses5-dev wget zlib1g-dev</pre><br />
<br />
== Building a payload (Optional) ==<br />
<br />
The majority of the payloads supported by coreboot are built automatically once they are selected and configured as described in the next section.<br />
<br />
Most beginners want to use the default [[SeaBIOS]] payload. It runs Option ROMs, is able to discover boot devices and provides a very simple boot menu.<br />
<br />
If, however, you need to build a payload that is currently not included in the coreboot build system:<br />
<br />
*First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
*Each payload may have different build instructions and requirements, however most of the time a "make" command will suffice. Please check [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
*The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>https://review.coreboot.org/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
$ '''git submodule update --init --checkout'''<br />
<br />
The last step is important! It checks out a sub-repository in the 3rdparty directory.<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
OR<br />
<br />
$ '''make nconfig''' (easier to navigate, uses ncurses)<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of <code>flashrom</code> command)<br />
<br />
More detailed example (generic) configuration (tweak accordingly):<br />
(note that this assumes presence of native graphics initialization on the given board, which is not universally available in coreboot)<br />
<br />
General setup / Expert mode = enable<br />
General / Use CMOS for configuration values = enable (CMOS defaults are located in your boards directory src/mainboard/OEM/MODEL/cmos.default)<br />
Mainboard / Mainboard vendor = Name of manufacturer<br />
Mainboard / Mainboard model = Model name<br />
Mainboard / ROM chip size = size of flash chip<br />
Chipset / Include CPU microcode in CBFS = Do not include microcode updates (NOTE: you probably want to enable it on some systems)<br />
Devices / Use native graphics initialization = enable (NOTE: not available on all systems)<br />
Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer)<br />
Generic Drivers / USB 2.0 EHCI debug dongle support = Enable<br />
Generic Drivers / Enable early (pre-RAM) usbdebug = Enable<br />
Generic Drivers / Type of dongle = Net20DC or compatible<br />
Generic Drivers / Digitizer = Present<br />
Console / USB dongle console output = enable<br />
Payload / Add a payload = An ELF executable payload (change if you want a different payload)<br />
Payload / Payload path and filename = grub.elf (assumes building GRUB manually. Change this if you want a different payload)<br />
<br />
Now go back into Devices (only do this if you didn't enable native graphics initialization; NOTE: instructions for adding a vbios option rom are not mentioned in the above instructions):<br />
<br />
Devices / Run VGA Option ROMs = disable<br />
Devices / Run Option ROMs on PCI devices = disable<br />
<br />
<br />
=== Intel boards ===<br />
For Intel boards you have to provide files coreboot can't generate by itself:<br />
* [[Intel Flash Descriptor region]]<br />
* [[Intel Gigabit Ethernet firmware]]<br />
* [[Intel Management Engine]]<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
* Enter the '''Chipset''' menu<br />
** Do the following based on which blobs you have:<br />
** Untick '''Build with a fake IFD''' (descriptor.bin)<br />
** Tick '''Add gigabit ethernet firmware''' (gbe.bin)<br />
** Tick '''Add Intel Management Engine firmware''' (me.bin)<br />
<br />
=== AMD boards ===<br />
For AMD boards you may have to provide files coreboot can't generate by itself:<br />
* [[NIC firmware]]<br />
* [[AMD IMC]]<br />
* [[AMD XHCI]]<br />
* [[AMD PSP]] (AMD's ME analog)<br />
<br />
Please have a look at [[Binary situation]] for a full overview.<br />
The files have to be extracted from your vendor bios.<br />
<br />
=== Choose the payload ===<br />
Here's the full list of supported [[Payloads]].<br />
<br />
By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process.<br />
<br />
If you want to use another payload (ELF for example):<br />
<br />
* Enter the '''Payload''' menu.<br />
** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
=== VGA support ===<br />
In order to see something on your screen the graphic card has to be initialized by the [[VGA BIOS]] which is actually an [[Option ROM]].<br />
<br />
[[VGA support]] is required for payloads such as GRUB or elf-memtest86+-5.01.<br />
<br />
It isn't required for operating systems such as GNU/Linux as it initializes the graphic card by itself.<br />
<br />
On some platforms there's support for [[native gfx init]]. A VGA BIOS isn't required.<br />
<br />
=== Security Notes ===<br />
<br />
Microcode updates are almost always required for secure CPU operation, not including it for philosophy reasons is only proper on a very small set of CPU's and is done at your own risk.<br />
<br />
As an example, the 33xx, 43xx and 63xx "Piledriver" AMD Opteron CPU's have a fatal NMI to gain root exploit in some versions of the onboard microcode that is easily performed with userspace tool.<br />
<br />
=== Compiling ===<br />
<br />
You also need to build the coreboot cross-compiler. This is to compile for the architecture of the platform you are building coreboot FOR, not the system you are building ON. For x86 systems, you currently would use the i386 cross-compiler, not the x64 version.<br />
<br />
You can see all of the options available by running 'make help':<br />
<br />
$ '''make help'''<br />
...<br />
*** Toolchain targets ***<br />
crossgcc - Build coreboot cross-compilers for all platforms<br />
crosstools - Build coreboot cross-compiler and GDB for all platforms<br />
crossgcc-clean - Remove all built coreboot cross-compilers<br />
iasl - Build coreboot IASL compiler (built by all cross targets)<br />
clang - Build coreboot clang compiler<br />
test-toolchain - Reports if toolchain components are out of date<br />
crossgcc-ARCH - Build cross-compiler for specific architecture<br />
crosstools-ARCH - Build cross-compiler with GDB for specific architecture<br />
ARCH can be "i386", "x64", "arm", "aarch64", "mips", "riscv", "power8", "nds32le"<br />
Use "make [target] CPUS=#" to build toolchain using multiple cores<br />
<br />
<br />
To build the cross-compilers for all architectures using 4 threads (This takes a LONG time):<br />
$ '''make crossgcc CPUS=4'''<br />
<br />
To build the cross-compiler for just the x86 architecture with just a single thread:<br />
$ '''make crossgcc-i386'''<br />
<br />
<br />
You can also invoke the cross compiler build script directly (in this example eight threads):<br />
<br />
$ '''util/crossgcc/buildgcc -j 8'''<br />
<br />
If something fails, the build should tell you what file to look in. You can also try to search for the relevant log (<code>find . -name '*.log' | xargs grep Error</code>) and examine last few lines of it.<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.<br />
<br />
== Compiling with Clang/LLVM ==<br />
<br />
We have been working on building coreboot with clang/llvm and it basically works.<br />
Remaining issues can be reported upstream and then block this meta bug here:<br />
<br />
[http://llvm.org/bugs/show_bug.cgi?id=21691 META Compiling the Coreboot with clang]<br />
<br />
The default and recommended flow is still to use crossgcc.<br />
<br />
== Known issues ==<br />
<br />
Make sure you really have all the requirements installed!<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Development version ==<br />
<br />
If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.<br />
<br />
You '''must''' run '''make crossgcc''' and rebuild coreboot before reporting an issue or contributing a patch.<br />
<br />
To get set up to submit a patch please run '''make gitconfig''', then [[Git|register with gerrit]].<br />
<br />
== Flashing coreboot ==<br />
<br />
You can [[flashing coreboot|flash]] the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>MartinRothhttps://www.coreboot.org/index.php?title=Denver2017&diff=26333Denver20172017-05-25T18:21:23Z<p>MartinRoth: </p>
<hr />
<div>==Date and time==<br />
The coreboot conference is '''Monday, June 5 and Tuesday June 6, 2017'''.<br />
<br />
An optional hacking day will follow on '''Wednesday June 7, 2017'''.<br />
<br />
Summary:<br />
* Monday - Presentations: 9:00 - 17:00<br />
* Tuesday - Presentations & Discussions: 9:00 - 17:00<br />
* Wednesday - Hacking: 9:00 - 17:00<br />
<br />
[https://goo.gl/uDNN9a Full Schedule]<br />
<br />
==Conference location==<br />
This conference is being hosted by the coreboot project and will be held in '''Denver CO, USA''' at:<br/><br />
===Conference Days - June 5, 6===<br />
[http://www.sustainablecolorado.org/ The Alliance Center]<br/><br />
[https://goo.gl/maps/3NFf389aH972 1536 Wynkoop Street, Suite 100]<br/><br />
<br />
The Alliance Center is in Denver's LoDo (Lower Downtown) neighborhood, which has an incredible amount to do and see, so people are encouraged to come early to experience more of both Denver and Colorado in general.<br />
<br />
===Hacking Day - June 7===<br />
[https://www.denverlibrary.org/ Denver Public Library - Central Library]<br/><br />
[https://goo.gl/maps/sCqn6MAnR3s 10 W 14th Ave Pkwy]<br/><br />
<br />
The Denver Central Library is located in Downtown Denver. It is a short free Mall Shuttle ride from the conference location and hotels in LoDo. We have a room reserved and may have access the the [https://www.denverlibrary.org/idealab-central IdeaLab].<br />
<br />
<br/><br/><br />
<br />
==Signing up / Registration==<br />
Please sign up using [https://goo.gl/o2j4gX this form]. If you have any trouble signing up, email [mailto:convention@coreboot.org convention@coreboot.org]<br />
<br/><br />
<br />
===Fees===<br />
Registration:<br />
* $300 for corporate conference attendees.<br />
* $150 for non-corporate contributors.<br />
* $75 for students<br />
.<br />
<br/><br/><br />
<br />
==Getting to the convention==<br />
It's expected that most people will fly into [https://www.flydenver.com/ Denver International Airport (DEN)]. <br />
<br />
From there, there are a number of [https://www.flydenver.com/parking_transit/transportation_den services] that will take you to the downtown area:<br />
* [http://www.denver.org/about-denver/transportation/airport-rail/ The A Line] costs $9 to take you from the airport to Union station, where you can walk to your hotel<br />
* [https://www.lyft.com/ Lyft] or [https://www.uber.com/ Uber] ride service cost about $45 to downtown<br />
* Taxi $60<br />
<br />
If you are traveling from outside of the US and have a passport from a country participating in the Visa Waiver Program (VWP), you may apply for an [https://www.usavisaonline.com/esta.html 'ESTA' Travel Authorization].<br />
<br />
=== Getting Around Denver ===<br />
* [http://godenverapp.com/app Go Denver App]<br />
* [http://www.rtd-denver.com/FREEMallRide.shtml 16th St Mall Shuttle]<br />
* [https://www.lyft.com/ Lyft] or [https://www.uber.com/ Uber] <br />
* [http://www.rtd-denver.com/index.shtml Bus]<br />
* [http://denver.bcycle.com/pages-in-top-navigation/map Denver Bcycle]<br />
* Taxi<br />
<br />
====Parking====<br />
* [http://www.bestparking.com/denver-parking/neighborhoods/union-station-lodo-parking Parking Map]<br />
<br/><br/><br />
<br />
<br />
==Accommodation==<br />
* $50+ [https://hostelfish.com/ Hostel Fish]<br />
* $185+ [http://www.springhillsuitesdenver.com/ Springhill Suites]<br />
* $200+ [http://www.nativhotels.com/ Nativ Hotel]<br />
* $325+ [http://www.theoxfordhotel.com/denver-accommodations/ Oxford Hotel]<br />
* $339+ [http://www.thecrawfordhotel.com/ Crawford Hotel]<br />
* [https://www.airbnb.com/s/lodo--denver-co?source=hdr airbnb] also has a number of listings in the area.<br />
<br/><br/><br />
<br />
<br />
==Food and drinks==<br />
We will be supplying coffee, lunch, and a variety of snacks and drinks throughout the convention.<br />
<br />
We plan to go out for group dinners after each day's events are finished.<br />
<br />
Breakfast will '''not''' be provided, so eat at your hotel or in one of the many fantastic restaurants in the area. There is a coffee shop at the Alliance Center for all your caffeine needs.<br />
<br/><br/><br />
<br />
<br />
==Goodies==<br />
We will have an assortment of coreboot items available.<br />
* Stickers<br />
* T-Shirts<br />
* Travel Cups<br />
<br/><br/><br />
<br />
==Things To Do ==<br />
* [https://www.denver.org/ Visit Denver]<br />
* [http://denverbreweryguide.com/default.aspx Denver Breweries] - open source + beer == awesome!<br />
* [https://rinoartdistrict.org/ RiNo Art District] - Just North of LoDo<br />
* [http://dayhikesneardenver.com/ Day Hikes Near Denver]<br />
* [http://redrocksonline.com/ Red Rocks Amphitheater]<br />
* [https://denver.eater.com/ Eater- Denver] - for foodies<br />
* [http://www.westword.com/marijuana/what-tourists-should-know-before-going-to-a-denver-dispensary-9088144 Pot,] yes it is legal in CO. Dont' eat the entire edible.<br />
<br/><br/><br />
<br />
<br />
<br />
[[Category:Meetings]]</div>MartinRothhttps://www.coreboot.org/index.php?title=Denver2017&diff=26332Denver20172017-05-25T18:20:19Z<p>MartinRoth: /* Goodies */</p>
<hr />
<div>==Date and time==<br />
The coreboot conference is '''Monday, June 5 and Tuesday June 6, 2017'''.<br />
<br />
An optional hacking day will follow on '''Wednesday June 7, 2017'''.<br />
<br />
Summary:<br />
* Monday - Presentations: 9:00 - 17:00<br />
* Tuesday - Presentations & Discussions: 9:00 - 17:00<br />
* Wednesday - Hacking: 9:00 - 17:00<br />
<br />
[https://goo.gl/uDNN9a Full Schedule]<br />
<br />
==Conference location==<br />
This conference is being hosted by the coreboot project and will be held in '''Denver CO, USA''' at:<br/><br />
===Conference Days - June 5, 6===<br />
[http://www.sustainablecolorado.org/ The Alliance Center]<br/><br />
[https://goo.gl/maps/3NFf389aH972 1536 Wynkoop Street, Suite 100]<br/><br />
<br />
The Alliance Center is in Denver's LoDo (Lower Downtown) neighborhood, which has an incredible amount to do and see, so people are encouraged to come early to experience more of both Denver and Colorado in general.<br />
<br />
===Hacking Day - June 7===<br />
[https://www.denverlibrary.org/ Denver Public Library - Central Library]<br/><br />
[https://goo.gl/maps/sCqn6MAnR3s 10 W 14th Ave Pkwy]<br/><br />
<br />
The Denver Central Library is located in Downtown Denver. It is a short free Mall Shuttle ride from the conference location and hotels in LoDo. We have a room reserved and may have access the the [https://www.denverlibrary.org/idealab-central IdeaLab].<br />
<br />
<br/><br/><br />
<br />
==Signing up / Registration==<br />
Please sign up using [https://goo.gl/o2j4gX this form]. If you have any trouble signing up, email [mailto:convention@coreboot.org convention@coreboot.org]<br />
<br/><br />
<br />
===Fees===<br />
Registration:<br />
* $300 for corporate conference attendees.<br />
* $150 for non-corporate contributors.<br />
* $75 for students<br />
.<br />
<br/><br/><br />
<br />
==Getting to the convention==<br />
It's expected that most people will fly into [https://www.flydenver.com/ Denver International Airport (DEN)]. <br />
<br />
From there, there are a number of [https://www.flydenver.com/parking_transit/transportation_den services] that will take you to the downtown area:<br />
* [http://www.denver.org/about-denver/transportation/airport-rail/ The A Line] costs $9 to take you from the airport to Union station, where you can walk to your hotel<br />
* [https://www.lyft.com/ Lyft] or [https://www.uber.com/ Uber] ride service cost about $45 to downtown<br />
* Taxi $60<br />
<br />
If you are traveling from outside of the US and have a passport from a country participating in the Visa Waiver Program (VWP), you may apply for an [https://www.usavisaonline.com/esta.html 'ESTA' Travel Authorization].<br />
<br />
=== Getting Around Denver ===<br />
* [http://godenverapp.com/app Go Denver App]<br />
* [http://www.rtd-denver.com/FREEMallRide.shtml 16th St Mall Shuttle]<br />
* [https://www.lyft.com/ Lyft] or [https://www.uber.com/ Uber] <br />
* [http://www.rtd-denver.com/index.shtml Bus]<br />
* [http://denver.bcycle.com/pages-in-top-navigation/map Denver Bcycle]<br />
* Taxi<br />
<br />
====Parking====<br />
* [http://www.bestparking.com/denver-parking/neighborhoods/union-station-lodo-parking Parking Map]<br />
<br/><br/><br />
<br />
<br />
==Accommodation==<br />
* $50+ [https://hostelfish.com/ Hostel Fish]<br />
* $185+ [http://www.springhillsuitesdenver.com/ Springhill Suites]<br />
* $200+ [http://www.nativhotels.com/ Nativ Hotel]<br />
* $325+ [http://www.theoxfordhotel.com/denver-accommodations/ Oxford Hotel]<br />
* $339+ [http://www.thecrawfordhotel.com/ Crawford Hotel]<br />
* [https://www.airbnb.com/s/lodo--denver-co?source=hdr airbnb] also has a number of listings in the area.<br />
<br/><br/><br />
<br />
<br />
==Food and drinks==<br />
We will be supplying coffee, lunch, and a variety of snacks and drinks throughout the convention.<br />
<br />
We plan to go out for group dinners after each day's events are finished.<br />
<br />
Breakfast will '''not''' be provided, so eat at your hotel or in one of the many fantastic restaurants in the area. There is a coffee shop at the Alliance Center for all your caffeine needs.<br />
<br/><br/><br />
<br />
<br />
==Goodies==<br />
We will have an assortment of coreboot items available.<br />
* Stickers<br />
* T-Shirts<br />
* Travel Cups<br />
<br/><br/><br />
<br />
==Things To Do ==<br />
* [https://www.denver.org/ Visit Denver]<br />
* [http://denverbreweryguide.com/default.aspx Denver Breweries] - open source + beer == awesome!<br />
* [https://rinoartdistrict.org/ RiNo Art District] - Just North of LoDo<br />
* [http://dayhikesneardenver.com/ Day Hikes Near Denver]<br />
* [http://redrocksonline.com/ Red Rocks Amphitheater]<br />
* [https://denver.eater.com/ Eater- Denver] - for foodies<br />
* [http://www.westword.com/marijuana/what-tourists-should-know-before-going-to-a-denver-dispensary-9088144 Pot,] yes it is legal in CO. Dont' eat the entire edible.<br />
<br/><br/><br />
<br />
==Call for presentations==<br />
We are looking for interesting talks/presentations about coreboot related topics for the first and seconds day of the conference. Please note that those presentations are not intended to be advertisements or company portfolio presentations. Expected duration is between 15 and 60 minutes.<br />
<br />
=== Presentation Deadlines===<br />
Submission: Please send the title, a brief summary, the expected duration and name/organization of the speaker to [mailto:convention@coreboot.org convention@coreboot.org] until '''May 5'''. We will notify you of acceptance by '''May 13'''.<br />
<br/><br/><br />
<br />
==Call for discussion topics and development suggestions==<br />
We hope to stimulate discussion and foster new ideas as well as explore ways to improve code, testing, documentation, development and deployment. The format for this will be a few minutes (5-10) of presenting your idea/topic followed by discussing it with the audience for approximately 5-20 minutes.<br />
<br/><br/><br />
<br />
===Discussion topic Deadlines===<br />
While there is no formal deadline for submission, we'd appreciate a submission to [mailto:convention@coreboot.org convention@coreboot.org] before '''May 27''' to be able to list the topic on the agenda to allow others to think about the topic in advance.<br />
<br/><br/><br />
<br />
<br />
==Call for developers==<br />
If you want to do development all day, every day, sign up to come and do it. We have power, networking, development tools and some spare hardware - please tell us in advance if you need something specific.<br />
<br/><br/><br />
<br />
[[Category:Meetings]]</div>MartinRothhttps://www.coreboot.org/index.php?title=Denver2017&diff=26331Denver20172017-05-25T18:19:05Z<p>MartinRoth: /* Fees */</p>
<hr />
<div>==Date and time==<br />
The coreboot conference is '''Monday, June 5 and Tuesday June 6, 2017'''.<br />
<br />
An optional hacking day will follow on '''Wednesday June 7, 2017'''.<br />
<br />
Summary:<br />
* Monday - Presentations: 9:00 - 17:00<br />
* Tuesday - Presentations & Discussions: 9:00 - 17:00<br />
* Wednesday - Hacking: 9:00 - 17:00<br />
<br />
[https://goo.gl/uDNN9a Full Schedule]<br />
<br />
==Conference location==<br />
This conference is being hosted by the coreboot project and will be held in '''Denver CO, USA''' at:<br/><br />
===Conference Days - June 5, 6===<br />
[http://www.sustainablecolorado.org/ The Alliance Center]<br/><br />
[https://goo.gl/maps/3NFf389aH972 1536 Wynkoop Street, Suite 100]<br/><br />
<br />
The Alliance Center is in Denver's LoDo (Lower Downtown) neighborhood, which has an incredible amount to do and see, so people are encouraged to come early to experience more of both Denver and Colorado in general.<br />
<br />
===Hacking Day - June 7===<br />
[https://www.denverlibrary.org/ Denver Public Library - Central Library]<br/><br />
[https://goo.gl/maps/sCqn6MAnR3s 10 W 14th Ave Pkwy]<br/><br />
<br />
The Denver Central Library is located in Downtown Denver. It is a short free Mall Shuttle ride from the conference location and hotels in LoDo. We have a room reserved and may have access the the [https://www.denverlibrary.org/idealab-central IdeaLab].<br />
<br />
<br/><br/><br />
<br />
==Signing up / Registration==<br />
Please sign up using [https://goo.gl/o2j4gX this form]. If you have any trouble signing up, email [mailto:convention@coreboot.org convention@coreboot.org]<br />
<br/><br />
<br />
===Fees===<br />
Registration:<br />
* $300 for corporate conference attendees.<br />
* $150 for non-corporate contributors.<br />
* $75 for students<br />
.<br />
<br/><br/><br />
<br />
==Getting to the convention==<br />
It's expected that most people will fly into [https://www.flydenver.com/ Denver International Airport (DEN)]. <br />
<br />
From there, there are a number of [https://www.flydenver.com/parking_transit/transportation_den services] that will take you to the downtown area:<br />
* [http://www.denver.org/about-denver/transportation/airport-rail/ The A Line] costs $9 to take you from the airport to Union station, where you can walk to your hotel<br />
* [https://www.lyft.com/ Lyft] or [https://www.uber.com/ Uber] ride service cost about $45 to downtown<br />
* Taxi $60<br />
<br />
If you are traveling from outside of the US and have a passport from a country participating in the Visa Waiver Program (VWP), you may apply for an [https://www.usavisaonline.com/esta.html 'ESTA' Travel Authorization].<br />
<br />
=== Getting Around Denver ===<br />
* [http://godenverapp.com/app Go Denver App]<br />
* [http://www.rtd-denver.com/FREEMallRide.shtml 16th St Mall Shuttle]<br />
* [https://www.lyft.com/ Lyft] or [https://www.uber.com/ Uber] <br />
* [http://www.rtd-denver.com/index.shtml Bus]<br />
* [http://denver.bcycle.com/pages-in-top-navigation/map Denver Bcycle]<br />
* Taxi<br />
<br />
====Parking====<br />
* [http://www.bestparking.com/denver-parking/neighborhoods/union-station-lodo-parking Parking Map]<br />
<br/><br/><br />
<br />
<br />
==Accommodation==<br />
* $50+ [https://hostelfish.com/ Hostel Fish]<br />
* $185+ [http://www.springhillsuitesdenver.com/ Springhill Suites]<br />
* $200+ [http://www.nativhotels.com/ Nativ Hotel]<br />
* $325+ [http://www.theoxfordhotel.com/denver-accommodations/ Oxford Hotel]<br />
* $339+ [http://www.thecrawfordhotel.com/ Crawford Hotel]<br />
* [https://www.airbnb.com/s/lodo--denver-co?source=hdr airbnb] also has a number of listings in the area.<br />
<br/><br/><br />
<br />
<br />
==Food and drinks==<br />
We will be supplying coffee, lunch, and a variety of snacks and drinks throughout the convention.<br />
<br />
We plan to go out for group dinners after each day's events are finished.<br />
<br />
Breakfast will '''not''' be provided, so eat at your hotel or in one of the many fantastic restaurants in the area. There is a coffee shop at the Alliance Center for all your caffeine needs.<br />
<br/><br/><br />
<br />
<br />
==Goodies==<br />
We will have an assortment of coreboot items available. The list is not yet set, but we will definitely have the following items available.<br />
* Stickers<br />
* T-Shirts<br />
* Backpacks<br />
<br/><br/><br />
<br />
<br />
==Things To Do ==<br />
* [https://www.denver.org/ Visit Denver]<br />
* [http://denverbreweryguide.com/default.aspx Denver Breweries] - open source + beer == awesome!<br />
* [https://rinoartdistrict.org/ RiNo Art District] - Just North of LoDo<br />
* [http://dayhikesneardenver.com/ Day Hikes Near Denver]<br />
* [http://redrocksonline.com/ Red Rocks Amphitheater]<br />
* [https://denver.eater.com/ Eater- Denver] - for foodies<br />
* [http://www.westword.com/marijuana/what-tourists-should-know-before-going-to-a-denver-dispensary-9088144 Pot,] yes it is legal in CO. Dont' eat the entire edible.<br />
<br/><br/><br />
<br />
==Call for presentations==<br />
We are looking for interesting talks/presentations about coreboot related topics for the first and seconds day of the conference. Please note that those presentations are not intended to be advertisements or company portfolio presentations. Expected duration is between 15 and 60 minutes.<br />
<br />
=== Presentation Deadlines===<br />
Submission: Please send the title, a brief summary, the expected duration and name/organization of the speaker to [mailto:convention@coreboot.org convention@coreboot.org] until '''May 5'''. We will notify you of acceptance by '''May 13'''.<br />
<br/><br/><br />
<br />
==Call for discussion topics and development suggestions==<br />
We hope to stimulate discussion and foster new ideas as well as explore ways to improve code, testing, documentation, development and deployment. The format for this will be a few minutes (5-10) of presenting your idea/topic followed by discussing it with the audience for approximately 5-20 minutes.<br />
<br/><br/><br />
<br />
===Discussion topic Deadlines===<br />
While there is no formal deadline for submission, we'd appreciate a submission to [mailto:convention@coreboot.org convention@coreboot.org] before '''May 27''' to be able to list the topic on the agenda to allow others to think about the topic in advance.<br />
<br/><br/><br />
<br />
<br />
==Call for developers==<br />
If you want to do development all day, every day, sign up to come and do it. We have power, networking, development tools and some spare hardware - please tell us in advance if you need something specific.<br />
<br/><br/><br />
<br />
[[Category:Meetings]]</div>MartinRothhttps://www.coreboot.org/index.php?title=Welcome_to_coreboot&diff=25867Welcome to coreboot2017-05-05T23:32:03Z<p>MartinRoth: </p>
<hr />
<div><table width="100%" valign="top"><tr valign="top"><td width="80%"><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
'''coreboot''' is an Open Source project aimed at replacing the proprietary [http://wikipedia.org/wiki/BIOS BIOS] (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a [[Payloads|payload]].<br />
<br />
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly from firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like [[SeaBIOS | PC BIOS services]] or [[TianoCore | UEFI]]. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.<br />
<br />
coreboot currently supports over '''[[Supported Motherboards|230]]''' different mainboards. Check the [[Support]] page to see if your system is supported.<br />
<br />
<small><br />
coreboot was formerly known as [http://www.coreboot.org/pipermail/coreboot/2008-January/029135.html LinuxBIOS]. <br />
</small><br />
</div><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
coreboot uses [[git]] for source control and [http://review.coreboot.org gerrit] as the patch review tool. Please read the [https://review.coreboot.org/gitweb/cgit/coreboot.git/plain/Documentation/gerrit_guidelines.md gerrit etiquette & guidelines] document before submitting or reviewing patches.<br />
</div><br />
<br />
{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%<br />
|-<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = yellow|<br />
WIDTH = 100%|<br />
ICON = <small>[[Benefits|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Benefits]]</span>|<br />
CONTENT =<br />
<small><br />
* 100% Free Software (GPL), no royalties, no license fees!<br />
* Fast boot times (500 milliseconds to verified Linux kernel)<br />
<!-- * Avoids the need for a slow/buggy/proprietary BIOS --><br />
<!-- * Runs in 32-Bit protected mode almost from the start --><br />
<!-- * Written in C, contains virtually no assembly code --><br />
* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]<br />
<!-- * Further features: netboot, serial console, remote flashing, ... --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = #d1adf6|<br />
WIDTH = 100%|<br />
ICON = <small>[[Use Cases|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Use Cases]]</span>|<br />
CONTENT =<br />
<small><br />
* Desktop PCs, servers, [[Laptop|laptops]]<br />
* [[Clusters]]<br />
<!-- * Set-Top-Boxes, thin clients --><br />
* Embedded solutions<br />
<!-- * [http://en.wikipedia.org/wiki/Small_form_factor Small form factor computers], [http://en.wikipedia.org/wiki/Home_theater_PC Home-theater PCs] --><br />
<!-- * No-moving-parts solutions (ROM chip as "disk") --><br />
<!-- * Non-standard scenarios (e.g. FPGA in Opteron socket) --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = lime|<br />
WIDTH = 100%|<br />
ICON = <small>[[Payloads|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Payloads]]</span>|<br />
CONTENT =<br />
<small><br />
* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] <!-- / [[OpenFirmware]] / [[OpenBIOS]] --><br />
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] <!-- / [http://openbsd.org/ OpenBSD]--><br />
* [[Etherboot]] / [[GPXE]] / [[iPXE]] / [[Payloads|...]]<br />
<!--* [[Memtest86]]<br />
* [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]--><br />
</small><br />
}}<br />
<br />
|}<br />
<br />
{| cellspacing=5 cellpadding=15 border=0 valign="top" width=100%<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_cb.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">About</span>'''<br /><small>Find out more about coreboot.</small><small><hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_devel.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Developers</span>'''<br /><small>Get involved! Help us make coreboot better.</small><small><hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree Browse Source] | [[GSoC]] | [[Where to start]] | [[Lesson1| Lesson 1]] | [[Distributed and Automated Testsystem|Testsystem]] | [https://coreboot.org/git-docs git-docs]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_status.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Status</span>'''<br /><small>Find out whether your hardware is already supported.</small><small><hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [[Blob Matrix|Blob Matrix]] | [http://qa.coreboot.org Build Status]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_tools.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Related Tools</span>'''<br /><small>Tools and libraries related to coreboot.</small><small><hr />[http://www.flashrom.org flashrom] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [http://serialice.com SerialICE]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_101.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Getting Started</span>'''<br /><small>Download coreboot and get started.</small><small><hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_support.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Support</span>'''<br /><small>Learn how to contact us and find help and support.</small><small><hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [[Glossary]] | [[coreboot Options|coreboot Options]]</small><br />
|}<br />
<br />
|}<br />
</td><td width="20%"><br />
<br />
[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]<br />
<br />
<br clear=all /><br />
<!-- Blog feed isn't currently working - commenting out for now.<br />
'''<span style="font-variant:small-caps; font-size:120%">[http://blogs.coreboot.org News (blog)]</span>'''<hr /><br />
<small><br />
<rss max=5>https://blogs.coreboot.org/feed/</rss><br />
</small><br />
--><br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[Current events|Events]]</span>'''<hr /><br />
<!-- List of upcoming events (remove events after they have taken place). --><br />
<small><br />
<br />
* June 5 - 7, 2017- [[Denver2017 | North American coreboot conference]]<br />
* Oct 26 - 29, 2017 - [https://ecc2017.coreboot.org European coreboot conference]<br />
* [[coreboot_community_meeting | Bi-weekly community meeting]]<br />
* [https://www.google.com/maps/place/Finowstra%C3%9Fe+2A,+10247+Berlin,+Germany Monthly coreboot users group meeting Berlin]<br />
<!-- * Currently none --><br />
<!--* '''2015/mon/day:''' coreboot event at [[Link]] in somecity --><br />
[https://www.coreboot.org/calendar.html Full calendar]<br />
</small><br />
<br />
<br />
<br clear=all /><br />
<br />
</td></tr></table><br />
<br />
__NOTOC__<br />
__NOEDITSECTION__</div>MartinRothhttps://www.coreboot.org/index.php?title=User:MartinRoth&diff=25303User:MartinRoth2017-04-11T14:14:51Z<p>MartinRoth: /* Platforms supported by coreboot */</p>
<hr />
<div>==Martin Roth==<br />
<br />
[[File:Martin.jpg]]<br />
<br />
Email:<br />
:gaumless@gmail.com<br />
:martinroth@google.com<br />
<br />
IRC:<br />
:martinr (usually)<br />
:gaumless (occasionally)<br />
<br />
==Platforms supported by coreboot==<br />
{| class="wikitable"<br />
! Vendor !! Board !! Processor !! Southbridge !! Memory !! Count !! Blobs !! Used as<br />
|-<br />
| ADI || SG-2220 || Intel Rangeley || - || 2GB DDR3L Soldered Down || 1 || FSP ||<br />
|-<br />
| ADI || SG-2440 || Intel Rangeley || - || 4GB DDR3L Soldered Down || 1 || FSP ||<br />
|-<br />
| AMD || Bettong (DB-FP4) || || || || 1 || Yes || <br />
|-<br />
| AMD || Kino || AMD Family 10h || || || 1 || ||<br />
|-<br />
| AMD || Lamar || || || || 1 || ||<br />
|-<br />
| AMD || Mahogony || AMD Family F || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| AMD || Mahogony || AMD Family 10h || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| AMD || Olive Hill || || || || 1 || ||<br />
|-<br />
| AMD || Parmer || AMD Family 15TN || AMD Hudson || || 2 || ||<br />
|-<br />
| AMD || Pistachio || AMD Family F || AMD SB600|| || 1 || ||<br />
|-<br />
| AMD || Persimmon [DB-FT1] || AMD Family 14h || AMD SB800 || || 3 || ||<br />
|-<br />
| AMD || Pumori || || || || 1 || ||<br />
|-<br />
| AMD || Thatcher || AMD Family 15TN || AMD Hudson || || 1 || ||<br />
|-<br />
| AMD || Torpedo || AMD Family 12h || AMD SB900 || || 1 || ||<br />
|-<br />
| Asrock || E350M1/USB3 || AMD Family 14h || || || 1 || ||<br />
|-<br />
| Asrock || IMB-A180 || || || || 2 || ||<br />
|-<br />
| ASUS || F2A85-M || AMD Family 15TN || || || 1 || ||<br />
|-<br />
| ASUS || KGPE-D16 || AMD Family 10h / 15h || || || 1 || None || Lumberingbuilder<br />
|-<br />
| ASUS || KFSN4-DRE || || || || 1 || ||<br />
|-<br />
| ASUS || P5GC-MX || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-B75M-D3H || Intel Ivybridge || || 4 DDR3 UDIMMs || 1 || ME || Happybuilder<br />
|-<br />
| Gigabyte || GA-G41M-ES2L || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-945-GCM-S2L || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-MA78GM || AMD AM2+ socket || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| Gizmosphere || Gizmo || AMD Family 14h || || Soldered down || 3 || ||<br />
|-<br />
| Gizmosphere || Gizmo2 || || || Soldered down || 1 || Yes ||<br />
|-<br />
| Intel || Bakersport || Intel Bay Trail I SOC || - || 1 ECC DDR-3 SODIMM || 1 || FSP, ME ||<br />
|-<br />
| Intel || Bayley Bay || Intel Bay Trail I SOC || - || 2 DDR-3 SODIMM || 1 || FSP, ME ||<br />
|-<br />
| Intel || Camelback Mountain || Broadwell DE SOC || - || 2 DDR-4 UDIMMs || 1 || FSP, ME ||<br />
|-<br />
| Intel || Cougar Canyon || Intel Ivybridge || || || 1 || FSP, ME ||<br />
|-<br />
| Intel || D510MO || || I82801GB (ICH7) || 2 DDR-2 UDIMMs || 1 || None ||<br />
|-<br />
| Intel || Galileo || || || || 2 || None ||<br />
|-<br />
| Intel || Galileo Gen 2 || || || || 1 || None ||<br />
|-<br />
| Intel/Circuitco || Minnowboard Max || Intel Bay Trail I || || || 1 || FSP, ME ||<br />
|-<br />
| Intel/ADI || Minnowboard Turbot || Intel Bay Trail I || || || 1 || FSP, ME ||<br />
|-<br />
| Intel || Mohon Peak || Intel Rangeley || || || 1 || FSP ||<br />
|-<br />
| Lenovo || T500 || || || || 1 || None ||<br />
|-<br />
| Lenovo || W500 || || || || 1 || None ||<br />
|-<br />
| Lenovo || T520 || Intel Sandybridge || || || 1 || ME ||<br />
|-<br />
| Lenovo || T530 || Intel Ivybridge || || 2 DDR-3 SODIMMS || 1 || ME ||<br />
|-<br />
| Lenovo || W530 || Intel Ivybridge || || 4 DDR-3 SODIMMS || 2 || ME || Grumpybuilder<br />
|-<br />
| PC Engines || APU2C4 || || || || 1 || ||<br />
|-<br />
| Supermicro || H8SCM || AMD Family 10h / 15h || AMD SP5100 || 4 DDR3 DIMMs || 1 || ||<br />
|}<br />
<br />
==Links==<br />
===General Hardware & BIOS===<br />
* [http://helppc.netcore2k.net/topics HelpPC - Asm, C, Hardware, Interrupts, Tables for DOS & BIOS]<br />
* [http://www.ctyme.com/rbrown.htm Ralf Brown's Interrupt List]<br />
====_HID & EisaID====<br />
* [http://www-pc.uni-regensburg.de/hardware/TECHNIK/PCI_PNP/pnpid.txt EisaId list]<br />
* [http://download.microsoft.com/download/1/6/1/161ba512-40e2-4cc9-843a-923143f3456c/devids.txt EisaId list from Microsoft]<br />
* [http://lkml.iu.edu/hypermail/linux/kernel/1504.0/04084.html PRP0001 specifically means "Use the 'compatible' property to find the driver for this device"]<br />
<br />
===Payloads===<br />
* [http://www.memtest.org/download/ memtest downloads]<br />
<br />
<br />
==Fedora setup==<br />
Tested on Fedora 20 & 21<br />
sudo yum install git gcc gcc-c++ flex bison ncurses-devel acpica-tools wget patch pciutils-devel<br />
git clone http://review.coreboot.org/coreboot<br />
cd coreboot<br />
git submodule update --init --checkout<br />
make crossgcc-i386<br />
<br />
Optional installs:<br />
sudo yum install ccache clang<br />
<br />
<br />
===Flashing 3MB of 8MB ROM on minnowboard max===<br />
echo 00500000:007fffff cb-region > 8mb ; flashrom -p dediprog:voltage=1.8v -l 8mb -i cb-region -w build/coreboot.rom<br />
<br />
<br />
=== Coreboot lessons ===<br />
[[Lesson1]] - Starting from scratch. Download coreboot, build it, and test the image on QEMU.</div>MartinRothhttps://www.coreboot.org/index.php?title=User:MartinRoth&diff=25210User:MartinRoth2017-04-07T15:48:04Z<p>MartinRoth: /* Platforms supported by coreboot */</p>
<hr />
<div>==Martin Roth==<br />
<br />
[[File:Martin.jpg]]<br />
<br />
Email:<br />
:gaumless@gmail.com<br />
:martinroth@google.com<br />
<br />
IRC:<br />
:martinr (usually)<br />
:gaumless (occasionally)<br />
<br />
==Platforms supported by coreboot==<br />
{| class="wikitable"<br />
! Vendor !! Board !! Processor !! Southbridge !! Memory !! Count !! Blobs !! Used as<br />
|-<br />
| ADI || SG-2220 || Intel Rangeley || - || 2GB DDR3L Soldered Down || 1 || FSP ||<br />
|-<br />
| ADI || SG-2440 || Intel Rangeley || - || 4GB DDR3L Soldered Down || 1 || FSP ||<br />
|-<br />
| AMD || Bettong (DB-FP4) || || || || 1 || Yes || <br />
|-<br />
| AMD || Kino || AMD Family 10h || || || 1 || ||<br />
|-<br />
| AMD || Lamar || || || || 1 || ||<br />
|-<br />
| AMD || Mahogony || AMD Family F || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| AMD || Mahogony || AMD Family 10h || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| AMD || Olive Hill || || || || 1 || ||<br />
|-<br />
| AMD || Parmer || AMD Family 15h || AMD Hudson || || 2 || ||<br />
|-<br />
| AMD || Pistachio || AMD Family F || AMD SB600|| || 1 || ||<br />
|-<br />
| AMD || Persimmon [DB-FT1] || AMD Family 14h || AMD SB800 || || 3 || ||<br />
|-<br />
| AMD || Pumori || || || || 1 || ||<br />
|-<br />
| AMD || Thatcher || AMD Family 15h || AMD Hudson || || 1 || ||<br />
|-<br />
| AMD || Torpedo || AMD Family 12h || AMD SB900 || || 1 || ||<br />
|-<br />
| Asrock || E350M1/USB3 || AMD Family 14h || || || 1 || ||<br />
|-<br />
| Asrock || IMB-A180 || || || || 2 || ||<br />
|-<br />
| ASUS || F2A85-M || || || || 1 || ||<br />
|-<br />
| ASUS || KGPE-D16 || AMD Family 10h / 15h || || || 1 || None || Lumberingbuilder<br />
|-<br />
| ASUS || KFSN4-DRE || || || || 1 || ||<br />
|-<br />
| ASUS || P5GC-MX || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-B75M-D3H || Intel Ivybridge || || 4 DDR3 UDIMMs || 1 || ME || Happybuilder<br />
|-<br />
| Gigabyte || GA-G41M-ES2L || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-945-GCM-S2L || || || 2 DDR2 UDIMMs || 1 || None ||<br />
|-<br />
| Gigabyte || GA-MA78GM || AMD AM2+ socket || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| Gizmosphere || Gizmo || AMD Family 14h || || Soldered down || 3 || ||<br />
|-<br />
| Gizmosphere || Gizmo2 || || || Soldered down || 1 || Yes ||<br />
|-<br />
| Intel || Bakersport || Intel Bay Trail I SOC || - || 1 ECC DDR-3 SODIMM || 1 || FSP, ME ||<br />
|-<br />
| Intel || Bayley Bay || Intel Bay Trail I SOC || - || 2 DDR-3 SODIMM || 1 || FSP, ME ||<br />
|-<br />
| Intel || Camelback Mountain || Broadwell DE SOC || - || 2 DDR-4 UDIMMs || 1 || FSP, ME ||<br />
|-<br />
| Intel || Cougar Canyon || Intel Ivybridge || || || 1 || FSP, ME ||<br />
|-<br />
| Intel || D510MO || || I82801GB (ICH7) || 2 DDR-2 UDIMMs || 1 || None ||<br />
|-<br />
| Intel || Galileo || || || || 2 || None ||<br />
|-<br />
| Intel || Galileo Gen 2 || || || || 1 || None ||<br />
|-<br />
| Intel/Circuitco || Minnowboard Max || Intel Bay Trail I || || || 1 || FSP, ME ||<br />
|-<br />
| Intel/ADI || Minnowboard Turbot || Intel Bay Trail I || || || 1 || FSP, ME ||<br />
|-<br />
| Intel || Mohon Peak || Intel Rangeley || || || 1 || FSP ||<br />
|-<br />
| Lenovo || T500 || || || || 1 || None ||<br />
|-<br />
| Lenovo || W500 || || || || 1 || None ||<br />
|-<br />
| Lenovo || T520 || Intel Sandybridge || || || 1 || ME ||<br />
|-<br />
| Lenovo || T530 || Intel Ivybridge || || 2 DDR-3 SODIMMS || 1 || ME ||<br />
|-<br />
| Lenovo || W530 || Intel Ivybridge || || 4 DDR-3 SODIMMS || 2 || ME || Grumpybuilder<br />
|-<br />
| PC Engines || APU2C4 || || || || 1 || ||<br />
|-<br />
| Supermicro || H8SCM || AMD Family 10h / 15h || AMD SP5100 || 4 DDR3 DIMMs || 1 || ||<br />
|}<br />
<br />
==Links==<br />
===General Hardware & BIOS===<br />
* [http://helppc.netcore2k.net/topics HelpPC - Asm, C, Hardware, Interrupts, Tables for DOS & BIOS]<br />
* [http://www.ctyme.com/rbrown.htm Ralf Brown's Interrupt List]<br />
====_HID & EisaID====<br />
* [http://www-pc.uni-regensburg.de/hardware/TECHNIK/PCI_PNP/pnpid.txt EisaId list]<br />
* [http://download.microsoft.com/download/1/6/1/161ba512-40e2-4cc9-843a-923143f3456c/devids.txt EisaId list from Microsoft]<br />
* [http://lkml.iu.edu/hypermail/linux/kernel/1504.0/04084.html PRP0001 specifically means "Use the 'compatible' property to find the driver for this device"]<br />
<br />
===Payloads===<br />
* [http://www.memtest.org/download/ memtest downloads]<br />
<br />
<br />
==Fedora setup==<br />
Tested on Fedora 20 & 21<br />
sudo yum install git gcc gcc-c++ flex bison ncurses-devel acpica-tools wget patch pciutils-devel<br />
git clone http://review.coreboot.org/coreboot<br />
cd coreboot<br />
git submodule update --init --checkout<br />
make crossgcc-i386<br />
<br />
Optional installs:<br />
sudo yum install ccache clang<br />
<br />
<br />
===Flashing 3MB of 8MB ROM on minnowboard max===<br />
echo 00500000:007fffff cb-region > 8mb ; flashrom -p dediprog:voltage=1.8v -l 8mb -i cb-region -w build/coreboot.rom<br />
<br />
<br />
=== Coreboot lessons ===<br />
[[Lesson1]] - Starting from scratch. Download coreboot, build it, and test the image on QEMU.</div>MartinRothhttps://www.coreboot.org/index.php?title=Current_events&diff=24660Current events2017-03-16T22:18:01Z<p>MartinRoth: </p>
<hr />
<div>Please contact [[User:Stepan|Stefan Reinauer]], [[User:Rminnich|Ronald Minnich]] or [[User:Stuge|Peter Stuge]] for more information on the events.<br />
<br />
== Upcoming Events ==<br />
<br />
'''2017'''<br />
* June 5 - 7 - American coreboot conference in Denver, CO, USA<br />
<br />
* Oct 26 - 29 - European coreboot conference in Bochum, Germany<br />
<br />
== Past Events ==<br />
<br />
'''2017'''<br />
* February 4-5 - coreboot table at fosdem 2017 in Brussels<br />
<br />
<br />
'''2016'''<br />
* coreboot and flashrom had a booth at [https://fosdem.org/2016/ FOSDEM 2016], 30 & 31 January 2016<br />
* coreboot user group meeting Berlin on Wednesday, February 17th at 18:00 [https://berlin.ccc.de/wiki/Chaos_Computer_Club_Berlin @chaos computer club berlin].<br />
* coreboot user group meeting Berlin on Wednesday, March 16th at 19:00 [https://berlin.ccc.de/wiki/Chaos_Computer_Club_Berlin @chaos computer club berlin].<br />
* coreboot user group meeting Berlin on Wednesday, May 18th at 18:00 [https://berlin.ccc.de/wiki/Chaos_Computer_Club_Berlin @chaos computer club berlin].<br />
:: This is held the third Wednesday of every month.<br />
* [[coreboot_conference_San_Francisco_2016|coreboot convention in San Francisco, CA, USA]] on Monday June 13 - Thursday June 16, 2016<br />
* coreboot user group meeting Berlin on Wednesday, June 15th at 18:00 [https://berlin.ccc.de/wiki/Chaos_Computer_Club_Berlin @chaos computer club berlin].<br />
* December 27-30 - coreboot table at 33rd Chaos Communication Congress (33C3) in Hamburg]<br />
<br />
<br />
'''2015'''<br />
* coreboot user group meeting berlin 28.10.2015 20:30 [https://berlin.ccc.de/wiki/Chaos_Computer_Club_Berlin @chaos computer club berlin.]<br />
* coreboot conference Europe in Bonn [https://blogs.coreboot.org/blog/2015/08/04/coreboot-conference-in-europe-october-2015/ See blog post.]<br />
* coreboot workshop at [https://events.ccc.de/camp/2015/wiki/Main_Page Chaos Communication Camp 2015 in Mildenberg on August 13-17 August 2015]<br />
<br />
* coreboot and flashrom share a booth at [[FOSDEM 2015]] in Brussels on 31 January and 1 February 2015.<br />
<br />
'''2014'''<br />
* coreboot meeting/hackaton in Prague on August 16-19, 2014. [http://www.coreboot.org/pipermail/coreboot/2014-July/078296.html Invitation thread]<br />
<br />
'''2013'''<br />
* coreboot and flashrom share a booth at [[FOSDEM 2013]] in Brussels on February 2-3, 2013.<br />
<br />
'''2012'''<br />
* [[GSoC|2012 Google Summer of Code]]<br />
* coreboot and flashrom share a booth at [[FOSDEM 2012]] in Brussels on February 4-5, 2012, and a presentation about coreboot on laptops will be held by [[User:Hailfinger|Carl-Daniel Hailfinger]].<br />
<br />
'''2011'''<br />
<br />
* coreboot and flashrom exhibit at [http://www.linuxtag.org/ LinuxTag] in Berlin on May 11-14, 2011.<br />
<br />
* coreboot and flashrom shared a booth at [[FOSDEM 2011]] in Brussels on February 5-6, 2011, and several presentations were held by [[User:Ruik|Rudolf Marek]] and [[User:Hailfinger|Carl-Daniel Hailfinger]].<br />
<br />
<br />
'''2010'''<br />
<br />
* coreboot exhibited at [http://www.linuxtag.org/ LinuxTag 2010] in Berlin on June 9-12, 2010.<br />
* coreboot had its [[FOSDEM 2010|very first DevRoom]] at [http://www.fosdem.org/ FOSDEM] in Brussels on February 6, 2010.<br />
<br />
'''2009'''<br />
<br />
* [[User:Stuge|Peter Stuge]] presented [http://events.ccc.de/congress/2009/Fahrplan/events/3661.en.html coreboot] at [http://events.ccc.de/congress/2009/ the 26th Chaos Communication Congress (26C3)] in Berlin on December 27, 2009.<br />
* [[User:Stuge|Peter Stuge]] presented [http://www.databadge.net/ifsec2009/reg/lin/show_sessions.php coreboot] at [http://www.linux-world.nl/nl-NL/Bezoeker.aspx?sc_lang=en LinuxWorld Conference & Expo] in Utrecht on November 4, 2009.<br />
* [[User:Stuge|Peter Stuge]] presented [https://har2009.org/program/events/210.en.html coreboot] at [https://wiki.har2009.org/page/Main_Page HAR2009] in Vierhouten on August 13, 2009.<br />
* coreboot had a booth at [[LinuxTag 2009|LinuxTag]] in Berlin on June 24-27, 2009.<br />
* [[User:Stuge|Peter Stuge]] presented coreboot at [http://freedomhectaipei.pbworks.com/ FreedomHEC Taipei] on June 11, 2009.<br />
* [[User:Stuge|Peter Stuge]] presented coreboot at [http://goopen2009.friprog.no/ GoOpen 2009] in Oslo on April 16-17, 2009.<br />
* [[User:Stepan|Stefan Reinauer]], [[User:Stuge|Peter Stuge]] and [[User:Ruik|Rudolf Marek]] made a visit at [http://www.embedded-world.de/ embedded world 2009] in N�rnberg on March 3-5.<br />
* [[User:Rminnich|Ron Minnich]] had a [http://scale7x.socallinuxexpo.org/dotorg/coreboot coreboot booth] at the [http://scale7x.socallinuxexpo.org/ Southern California Linux Expo] (SCALE 7x) on February 20-22, 2009.<br />
<br />
'''2008'''<br />
<br />
* [[User:Stuge|Peter Stuge]] presented [http://events.ccc.de/congress/2008/Fahrplan/events/2970.en.html coreboot: Beyond The Final Frontier] and held a coreboot workshop at [http://events.ccc.de/congress/2008/ the 25th Chaos Communication Congress (25C3)] on December 27-30.<br />
* [[User:Stuge|Peter Stuge]] presented coreboot at the [http://www.nluug.nl/events/nj08/ NLUUG Autumn Conference on Mobile Computing] and [http://www.embeddedlinuxconference.com/elc_europe08/ CE Linux Forum - Embedded Linux conference Europe 2008] on November 6-7.<br />
* [[User:Rminnich|Ronald Minnich]], [[User:Stuge|Peter Stuge]] and [[User:Stepan|Stefan Reinauer]] presented coreboot in a [[Screenshots#Google_Tech_Talks_2008:_coreboot_.28aka_LinuxBIOS.29:_The_Free.2FOpen-Source_x86_Firmware|Google TechTalk]] on October 30.<br />
* [[User:Stuge|Peter Stuge]] presented [http://fscons.org/events/?action=event&id=32 coreboot] at the [http://fscons.org/ Free Society Conference and Nordic Summit 2008] on October 24-26.<br />
* [[User:Stuge|Peter Stuge]] presented coreboot at the [http://slackathon.se/2008/ Slackathon 2008] OpenBSD meeting in September.<br />
* Coreboot was exhibiting at [[LinuxTag 2008]] in Berlin on May 28-31.<br />
* The [[Coreboot Symposium 2008|coreboot symposium 2008]] was held in Denver, April 3 � 5, 2008 during the High Performance Computer Science Week [http://www.hpcsw.org HPCSW].<br />
<br />
'''2007'''<br />
<br />
* There was a [[News#2007.2F05.2F23_LinuxBIOS_booth_at_LinuxTag_in_Berlin.2C_29.2F5-2.2F6|LinuxBIOS booth at the LinuxTag in Berlin, May 29 - June 6, 2007]], as well as a hands-on workshop by Peter Stuge.<br />
* Ron Minnich gave [http://www.fosdem.org/2007/schedule/events/linuxbios a talk about LinuxBIOS] on February 24, 2007 at [http://www.fosdem.org/2007/ FOSDEM 2007].<br />
<br />
'''2006'''<br />
<br />
* The [[LinuxBIOS Symposium 2006]] took place on October 1-3, 2006 in Hamburg, Germany.<br />
<br />
'''2005'''<br />
<br />
* The [[LinuxBIOS Summit 2005]] took place on October 11-13 in Santa Fe, NM.</div>MartinRothhttps://www.coreboot.org/index.php?title=Denver2017&diff=23759Denver20172017-02-02T17:17:14Z<p>MartinRoth: /* Fees */</p>
<hr />
<div>==Date and time==<br />
The coreboot conference is '''Monday, June 5 and Tuesday June 6, 2017'''.<br />
<br />
An optional hacking day will follow on '''Wednesday June 7, 2017'''.<br />
<br />
Summary:<br />
* Monday - Presentations: 9:00 - 17:00<br />
* Tuesday - Presentations & Discussions: 9:00 - 17:00<br />
* Wednesday - Hacking: 9:00 - 17:00<br />
<br />
[https://goo.gl/uDNN9a Full Schedule]<br />
<br />
==Conference location==<br />
This conference is being hosted by the coreboot project and will be held in '''Denver CO, USA''' at:<br/><br />
<br />
[http://www.sustainablecolorado.org/ The Alliance Center]<br/><br />
[https://goo.gl/maps/3NFf389aH972 1536 Wynkoop Street, Suite 100].<br/><br />
<br />
This is in Denver's LoDo neighborhood, which has an incredible amount to do and see, so people are encouraged to come early to experience more of both Denver and Colorado in general.<br />
<br/><br/><br />
<br />
==Signing up / Registration==<br />
Please sign up using [https://goo.gl/o2j4gX this form]. If you have any trouble signing up, email [mailto:convention@coreboot.org convention@coreboot.org]<br />
<br/><br/><br />
<br />
===Fees===<br />
Registration:<br />
* $250 for corporate conference attendees.<br />
* $100 for non-corporate contributors.<br />
* $25 for students<br />
<br />
After May 5, these fees go up $50 each, so please book early.<br />
<br/><br/><br />
<br />
==Call for presentations==<br />
We are looking for interesting talks/presentations about coreboot related topics for the first and seconds day of the conference. Please note that those presentations are not intended to be advertisements or company portfolio presentations. Expected duration is between 15 and 60 minutes.<br />
<br />
=== Presentation Deadlines===<br />
Submission: Please send the title, a brief summary, the expected duration and name/organization of the speaker to [mailto:convention@coreboot.org convention@coreboot.org] until '''May 5'''. We will notify you of acceptance by '''May 13'''.<br />
<br/><br/><br />
<br />
==Call for discussion topics and development suggestions==<br />
We hope to stimulate discussion and foster new ideas as well as explore ways to improve code, testing, documentation, development and deployment. The format for this will be a few minutes (5-10) of presenting your idea/topic followed by discussing it with the audience for approximately 5-20 minutes.<br />
<br/><br/><br />
<br />
===Discussion topic Deadlines===<br />
While there is no formal deadline for submission, we'd appreciate a submission to [mailto:convention@coreboot.org convention@coreboot.org] before '''May 27''' to be able to list the topic on the agenda to allow others to think about the topic in advance.<br />
<br/><br/><br />
<br />
<br />
==Call for developers==<br />
If you want to do development all day, every day, sign up to come and do it. We have power, networking, development tools and some spare hardware - please tell us in advance if you need something specific.<br />
<br/><br/><br />
<br />
==Getting to the convention==<br />
It's expected that most people will fly into [https://www.flydenver.com/ Denver International Airport (DEN)]. <br />
<br />
From there, there are a number of [https://www.flydenver.com/parking_transit/transportation_den services] that will take you to the downtown area:<br />
* [http://www.denver.org/about-denver/transportation/airport-rail/ The A Line] costs $9 to take you from the airport to Union station, where you can walk to your hotel<br />
* [https://www.lyft.com/ Lyft] or [https://www.uber.com/ Uber] ride service cost about $45 to downtown<br />
* Taxi $60<br />
<br />
If you are traveling from outside of the US and have a passport from a country participating in the Visa Waiver Program (VWP), you may apply for an [https://www.usavisaonline.com/esta.html 'ESTA' Travel Authorization].<br />
<br/><br/><br />
<br />
==Accommodation==<br />
* $50+ [https://hostelfish.com/ Hostel Fish]<br />
* $185+ [http://www.springhillsuitesdenver.com/ Springhill Suites]<br />
* $200+ [http://www.nativhotels.com/ Nativ Hotel]<br />
* $325+ [http://www.theoxfordhotel.com/denver-accommodations/ Oxford Hotel]<br />
* $339+ [http://www.thecrawfordhotel.com/ Crawford Hotel]<br />
* [https://www.airbnb.com/s/lodo--denver-co?source=hdr airbnb] also has a number of listings in the area.<br />
<br/><br/><br />
<br />
==Food and drinks==<br />
We will be supplying lunch as well as a variety of snacks and drinks throughout the convention.<br />
<br />
We plan to go out for group dinners after each day's events are finished.<br />
<br />
Breakfast will '''not''' be provided, so eat at your hotel or in one of the many fantastic restaurants in the area.<br />
<br/><br/><br />
<br />
==Goodies==<br />
We will have an assortment of coreboot items available. The list is not yet set, but we will definitely have the following items available.<br />
* Stickers<br />
* T-Shirts<br />
* Backpacks<br />
<br/><br/><br />
<br />
[[Category:Meetings]]</div>MartinRothhttps://www.coreboot.org/index.php?title=Denver2017&diff=23758Denver20172017-02-02T17:16:49Z<p>MartinRoth: /* Date and time */</p>
<hr />
<div>==Date and time==<br />
The coreboot conference is '''Monday, June 5 and Tuesday June 6, 2017'''.<br />
<br />
An optional hacking day will follow on '''Wednesday June 7, 2017'''.<br />
<br />
Summary:<br />
* Monday - Presentations: 9:00 - 17:00<br />
* Tuesday - Presentations & Discussions: 9:00 - 17:00<br />
* Wednesday - Hacking: 9:00 - 17:00<br />
<br />
[https://goo.gl/uDNN9a Full Schedule]<br />
<br />
==Conference location==<br />
This conference is being hosted by the coreboot project and will be held in '''Denver CO, USA''' at:<br/><br />
<br />
[http://www.sustainablecolorado.org/ The Alliance Center]<br/><br />
[https://goo.gl/maps/3NFf389aH972 1536 Wynkoop Street, Suite 100].<br/><br />
<br />
This is in Denver's LoDo neighborhood, which has an incredible amount to do and see, so people are encouraged to come early to experience more of both Denver and Colorado in general.<br />
<br/><br/><br />
<br />
==Signing up / Registration==<br />
Please sign up using [https://goo.gl/o2j4gX this form]. If you have any trouble signing up, email [mailto:convention@coreboot.org convention@coreboot.org]<br />
<br/><br/><br />
<br />
===Fees===<br />
Early Registration:<br />
* $250 for corporate conference attendees.<br />
* $100 for non-corporate contributors.<br />
* $25 for students<br />
<br />
After May 5, these fees go up $50 each, so please book early.<br />
<br/><br/><br />
<br />
==Call for presentations==<br />
We are looking for interesting talks/presentations about coreboot related topics for the first and seconds day of the conference. Please note that those presentations are not intended to be advertisements or company portfolio presentations. Expected duration is between 15 and 60 minutes.<br />
<br />
=== Presentation Deadlines===<br />
Submission: Please send the title, a brief summary, the expected duration and name/organization of the speaker to [mailto:convention@coreboot.org convention@coreboot.org] until '''May 5'''. We will notify you of acceptance by '''May 13'''.<br />
<br/><br/><br />
<br />
==Call for discussion topics and development suggestions==<br />
We hope to stimulate discussion and foster new ideas as well as explore ways to improve code, testing, documentation, development and deployment. The format for this will be a few minutes (5-10) of presenting your idea/topic followed by discussing it with the audience for approximately 5-20 minutes.<br />
<br/><br/><br />
<br />
===Discussion topic Deadlines===<br />
While there is no formal deadline for submission, we'd appreciate a submission to [mailto:convention@coreboot.org convention@coreboot.org] before '''May 27''' to be able to list the topic on the agenda to allow others to think about the topic in advance.<br />
<br/><br/><br />
<br />
<br />
==Call for developers==<br />
If you want to do development all day, every day, sign up to come and do it. We have power, networking, development tools and some spare hardware - please tell us in advance if you need something specific.<br />
<br/><br/><br />
<br />
==Getting to the convention==<br />
It's expected that most people will fly into [https://www.flydenver.com/ Denver International Airport (DEN)]. <br />
<br />
From there, there are a number of [https://www.flydenver.com/parking_transit/transportation_den services] that will take you to the downtown area:<br />
* [http://www.denver.org/about-denver/transportation/airport-rail/ The A Line] costs $9 to take you from the airport to Union station, where you can walk to your hotel<br />
* [https://www.lyft.com/ Lyft] or [https://www.uber.com/ Uber] ride service cost about $45 to downtown<br />
* Taxi $60<br />
<br />
If you are traveling from outside of the US and have a passport from a country participating in the Visa Waiver Program (VWP), you may apply for an [https://www.usavisaonline.com/esta.html 'ESTA' Travel Authorization].<br />
<br/><br/><br />
<br />
==Accommodation==<br />
* $50+ [https://hostelfish.com/ Hostel Fish]<br />
* $185+ [http://www.springhillsuitesdenver.com/ Springhill Suites]<br />
* $200+ [http://www.nativhotels.com/ Nativ Hotel]<br />
* $325+ [http://www.theoxfordhotel.com/denver-accommodations/ Oxford Hotel]<br />
* $339+ [http://www.thecrawfordhotel.com/ Crawford Hotel]<br />
* [https://www.airbnb.com/s/lodo--denver-co?source=hdr airbnb] also has a number of listings in the area.<br />
<br/><br/><br />
<br />
==Food and drinks==<br />
We will be supplying lunch as well as a variety of snacks and drinks throughout the convention.<br />
<br />
We plan to go out for group dinners after each day's events are finished.<br />
<br />
Breakfast will '''not''' be provided, so eat at your hotel or in one of the many fantastic restaurants in the area.<br />
<br/><br/><br />
<br />
==Goodies==<br />
We will have an assortment of coreboot items available. The list is not yet set, but we will definitely have the following items available.<br />
* Stickers<br />
* T-Shirts<br />
* Backpacks<br />
<br/><br/><br />
<br />
[[Category:Meetings]]</div>MartinRothhttps://www.coreboot.org/index.php?title=Denver2017&diff=23737Denver20172017-02-01T19:11:54Z<p>MartinRoth: /* Date and time */</p>
<hr />
<div>==Date and time==<br />
The coreboot conference is '''Monday, June 5 and Tuesday June 6, 2017'''.<br />
<br />
An optional hacking day will follow on '''Wednesday June 7, 2017'''.<br />
<br />
Summary:<br />
* Monday - Presentations: 8:30 - 17:00<br />
* Tuesday - Presentations & Discussions: 8:30 - 17:00<br />
* Wednesday - Hacking: 8:30 - 17:00<br />
<br />
[https://goo.gl/uDNN9a Full Schedule]<br />
<br />
==Conference location==<br />
This conference is being hosted by the coreboot project and will be held in '''Denver CO, USA''' at:<br/><br />
<br />
[http://www.sustainablecolorado.org/ The Alliance Center]<br/><br />
[https://goo.gl/maps/3NFf389aH972 1536 Wynkoop Street, Suite 100].<br/><br />
<br />
This is in Denver's LoDo neighborhood, which has an incredible amount to do and see, so people are encouraged to come early to experience more of both Denver and Colorado in general.<br />
<br/><br/><br />
<br />
==Signing up / Registration==<br />
Please sign up using [https://goo.gl/o2j4gX this form]. If you have any trouble signing up, email [mailto:convention@coreboot.org convention@coreboot.org]<br />
<br/><br/><br />
<br />
===Fees===<br />
Early Registration:<br />
* $250 for corporate conference attendees.<br />
* $100 for non-corporate contributors.<br />
* $25 for students<br />
<br />
After May 5, these fees go up $50 each, so please book early.<br />
<br/><br/><br />
<br />
==Call for presentations==<br />
We are looking for interesting talks/presentations about coreboot related topics for the first and seconds day of the conference. Please note that those presentations are not intended to be advertisements or company portfolio presentations. Expected duration is between 15 and 60 minutes.<br />
<br />
=== Presentation Deadlines===<br />
Submission: Please send the title, a brief summary, the expected duration and name/organization of the speaker to [mailto:convention@coreboot.org convention@coreboot.org] until '''May 5'''. We will notify you of acceptance by '''May 13'''.<br />
<br/><br/><br />
<br />
==Call for discussion topics and development suggestions==<br />
We hope to stimulate discussion and foster new ideas as well as explore ways to improve code, testing, documentation, development and deployment. The format for this will be a few minutes (5-10) of presenting your idea/topic followed by discussing it with the audience for approximately 5-20 minutes.<br />
<br/><br/><br />
<br />
===Discussion topic Deadlines===<br />
While there is no formal deadline for submission, we'd appreciate a submission to [mailto:convention@coreboot.org convention@coreboot.org] before '''May 27''' to be able to list the topic on the agenda to allow others to think about the topic in advance.<br />
<br/><br/><br />
<br />
<br />
==Call for developers==<br />
If you want to do development all day, every day, sign up to come and do it. We have power, networking, development tools and some spare hardware - please tell us in advance if you need something specific.<br />
<br/><br/><br />
<br />
==Getting to the convention==<br />
It's expected that most people will fly into [https://www.flydenver.com/ Denver International Airport (DEN)]. <br />
<br />
From there, there are a number of [https://www.flydenver.com/parking_transit/transportation_den services] that will take you to the downtown area:<br />
* [http://www.denver.org/about-denver/transportation/airport-rail/ The A Line] costs $9 to take you from the airport to Union station, where you can walk to your hotel<br />
* [https://www.lyft.com/ Lyft] or [https://www.uber.com/ Uber] ride service cost about $45 to downtown<br />
* Taxi $60<br />
<br />
If you are traveling from outside of the US and have a passport from a country participating in the Visa Waiver Program (VWP), you may apply for an [https://www.usavisaonline.com/esta.html 'ESTA' Travel Authorization].<br />
<br/><br/><br />
<br />
==Accommodation==<br />
* $50+ [https://hostelfish.com/ Hostel Fish]<br />
* $185+ [http://www.springhillsuitesdenver.com/ Springhill Suites]<br />
* $200+ [http://www.nativhotels.com/ Nativ Hotel]<br />
* $325+ [http://www.theoxfordhotel.com/denver-accommodations/ Oxford Hotel]<br />
* $339+ [http://www.thecrawfordhotel.com/ Crawford Hotel]<br />
* [https://www.airbnb.com/s/lodo--denver-co?source=hdr airbnb] also has a number of listings in the area.<br />
<br/><br/><br />
<br />
==Food and drinks==<br />
We will be supplying lunch as well as a variety of snacks and drinks throughout the convention.<br />
<br />
We plan to go out for group dinners after each day's events are finished.<br />
<br />
Breakfast will '''not''' be provided, so eat at your hotel or in one of the many fantastic restaurants in the area.<br />
<br/><br/><br />
<br />
==Goodies==<br />
We will have an assortment of coreboot items available. The list is not yet set, but we will definitely have the following items available.<br />
* Stickers<br />
* T-Shirts<br />
* Backpacks<br />
<br/><br/><br />
<br />
[[Category:Meetings]]</div>MartinRothhttps://www.coreboot.org/index.php?title=Denver2017&diff=23701Denver20172017-01-30T23:56:23Z<p>MartinRoth: </p>
<hr />
<div>==Date and time==<br />
The date of the coreboot conference is '''Monday, June 5 to Tuesday June 6, 2017'''.<br />
<br />
An optional day of hacking will follow on '''Wednesday June 7, 2017'''.<br />
<br />
Summary:<br />
* Monday - Presentations: 8:30 - 19:00<br />
* Tuesday - Presentations & Discussions: 8:30 - 19:00<br />
* Wednesday - Hacking: 8:30 - 19:00<br />
<br />
[https://goo.gl/uDNN9a Full Schedule]<br />
<br />
==Conference location==<br />
This conference is being hosted by the coreboot project and will be held in Denver CO, USA at [https://goo.gl/maps/3NFf389aH972 1536 Wynkoop Street, Suite 100]. This is in Denver's LoDo neighorhood, which has an incredible amount to do and see, so people are encouraged to come early to experience more of both Denver and Colorado in general.<br />
<br />
==Signing up / Registration==<br />
Please sign up using [https://goo.gl/o2j4gX this form]. If you have any trouble signing up, email [mailto:convention@coreboot.org convention@coreboot.org]<br />
<br />
==Fees==<br />
Early Registration:<br />
* $250 for corporate conference attendees.<br />
* $100 for non-corporate contributors.<br />
* $25 for students<br />
<br />
After May 5, these fees go up $50 each, so please book early.<br />
<br />
==Call for presentations==<br />
We are looking for interesting talks/presentations about coreboot related topics for the first and seconds day of the conference. Please note that those presentations are not intended to be advertisements or company portfolio presentations. Expected duration is between 15 and 60 minutes.<br />
<br />
=== Presentation Deadlines===<br />
Submission: Please send the title, a brief summary, the expected duration and name/organization of the speaker to [mailto:convention@coreboot.org convention@coreboot.org] until '''May 5'''. We will notify you of acceptance by '''May 13'''.<br />
<br />
==Call for discussion topics and development suggestions==<br />
We hope to stimulate discussion and foster new ideas as well as explore ways to improve code, testing, documentation, development and deployment. The format for this will be a few minutes (5-10) of presenting your idea/topic followed by discussing it with the audience for approximately 5-20 minutes.<br />
<br />
===Discussion topic Deadlines===<br />
While there is no formal deadline for submission, we'd appreciate a submission to [mailto:convention@coreboot.org convention@coreboot.org] before '''May 27''' to be able to list the topic on the agenda to allow others to think about the topic in advance.<br />
<br />
==Call for developers==<br />
If you want to do development all day, every day, sign up to come and do it. We have power, networking, development tools and some spare hardware - please tell us in advance if you need something specific.<br />
<br />
===Getting to the convention===<br />
It's expected that most people will fly into Denver International Airport (DEN). From there, there are a number of services that will take you to the downtown area.<br />
[http://www.denver.org/about-denver/transportation/airport-rail/ The A Line] costs $9 to take you from the airport to Union station.<br />
<br />
If you are traveling from outside of the US and have a passport from a country participating in the Visa Waiver Program (VWP), you may apply for an [https://www.usavisaonline.com/esta.html 'ESTA' Travel Authorization].<br />
<br />
==Accommodation==<br />
From cheapest to most expensive<br />
* $50+ [https://hostelfish.com/ Hostel Fish]<br />
* $185+ [http://www.springhillsuitesdenver.com/ Springhill Suites]<br />
* $200+ [http://www.nativhotels.com/ Nativ Hotel]<br />
* $325+ [http://www.theoxfordhotel.com/denver-accommodations/ Oxford Hotel]<br />
* $339+ [http://www.thecrawfordhotel.com/ Crawford Hotel]<br />
* [https://www.airbnb.com/s/lodo--denver-co?source=hdr airbnb] also has a number of listings in the area.<br />
<br />
==Food and drinks==<br />
We will be supplying lunch as well as a variety of snacks and drinks throughout the convention.<br />
<br />
We plan to go out for group dinners after each day's events are finished.<br />
<br />
Breakfast will '''not''' be provided, so eat at your hotel or in one of the many fantastic restaurants in the area.<br />
<br />
==Goodies==<br />
We will have an assortment of coreboot items available. The list is not yet set, but we will definitely have the following items available.<br />
* Stickers<br />
* T-Shirts<br />
* Backpacks<br />
<br />
<br />
[[Category:Meetings]]</div>MartinRothhttps://www.coreboot.org/index.php?title=Denver2017&diff=23700Denver20172017-01-30T22:27:31Z<p>MartinRoth: Created page with "==Date and time== The date of the coreboot conference is '''Monday, June 5 to Tuesday June 6, 2017'''. An optional day of hacking will follow on '''Wednesday June 7, 2017'''...."</p>
<hr />
<div>==Date and time==<br />
The date of the coreboot conference is '''Monday, June 5 to Tuesday June 6, 2017'''.<br />
<br />
An optional day of hacking will follow on '''Wednesday June 7, 2017'''.<br />
<br />
Summary:<br />
* Monday - Presentations: 8:30 - 19:00<br />
* Tuesday - Presentations & Discussions: 8:30 - 19:00<br />
* Wednesday - Hacking: 8:30 - 19:00<br />
<br />
==Conference location==<br />
This conference is being hosted by the coreboot project and will be held in Denver CO, USA at [https://goo.gl/maps/3NFf389aH972 1536 Wynkoop Street, Suite 100]. This is in Denver's LoDo neighorhood, which has an incredible amount to do and see, so people are encouraged to come early to experience more of both Denver and Colorado in general.<br />
<br />
==Signing up / Registration==<br />
Please sign up using [https://goo.gl/o2j4gX this form]. If you have any trouble signing up, email [mailto:convention@coreboot.org convention@coreboot.org]<br />
<br />
==Fees==<br />
Early Registration:<br />
* $250 for corporate conference attendees.<br />
* $100 for non-corporate contributors.<br />
* $25 for students<br />
<br />
After May 5, these fees go up $50 each, so please book early.<br />
<br />
==Call for presentations==<br />
We are looking for interesting talks/presentations about coreboot related topics for the first and seconds day of the conference. Please note that those presentations are not intended to be advertisements or company portfolio presentations. Expected duration is between 15 and 60 minutes.<br />
<br />
=== Presentation Deadlines===<br />
Submission: Please send the title, a brief summary, the expected duration and name/organization of the speaker to [mailto:convention@coreboot.org convention@coreboot.org] until '''May 5'''. We will notify you of acceptance by '''May 13'''.<br />
<br />
==Call for discussion topics and development suggestions==<br />
We hope to stimulate discussion and foster new ideas as well as explore ways to improve code, testing, documentation, development and deployment. The format for this will be a few minutes (5-10) of presenting your idea/topic followed by discussing it with the audience for approximately 5-20 minutes.<br />
<br />
===Discussion topic Deadlines===<br />
While there is no formal deadline for submission, we'd appreciate a submission to [mailto:convention@coreboot.org convention@coreboot.org] before '''May 27''' to be able to list the topic on the agenda to allow others to think about the topic in advance.<br />
<br />
==Call for developers==<br />
If you want to do development all day, every day, sign up to come and do it. We have power, networking, development tools and some spare hardware - please tell us in advance if you need something specific.<br />
<br />
===Getting to the convention===<br />
It's expected that most people will fly into Denver International Airport (DEN). From there, there are a number of services that will take you to the downtown area.<br />
[http://www.denver.org/about-denver/transportation/airport-rail/ The A Line] costs $9 to take you from the airport to Union station.<br />
<br />
If you are traveling from outside of the US and have a passport from a country participating in the Visa Waiver Program (VWP), you may apply for an [https://www.usavisaonline.com/esta.html 'ESTA' Travel Authorization].<br />
<br />
==Accommodation==<br />
From cheapest to most expensive<br />
* $50+ [https://hostelfish.com/ Hostel Fish]<br />
* $185+ [http://www.springhillsuitesdenver.com/ Springhill Suites]<br />
* $200+ [http://www.nativhotels.com/ Nativ Hotel]<br />
* $325+ [http://www.theoxfordhotel.com/denver-accommodations/ Oxford Hotel]<br />
* $339+ [http://www.thecrawfordhotel.com/ Crawford Hotel]<br />
* [https://www.airbnb.com/s/lodo--denver-co?source=hdr airbnb] also has a number of listings in the area.<br />
<br />
==Food and drinks==<br />
We will be supplying lunch as well as a variety of snacks and drinks throughout the convention.<br />
<br />
We plan to go out for group dinners after each day's events are finished.<br />
<br />
Breakfast will '''not''' be provided, so eat at your hotel or in one of the many fantastic restaurants in the area.<br />
<br />
==Goodies==<br />
We will have an assortment of coreboot items available. The list is not yet set, but we will definitely have the following items available.<br />
* Stickers<br />
* T-Shirts<br />
* Backpacks<br />
<br />
<br />
[[Category:Meetings]]</div>MartinRothhttps://www.coreboot.org/index.php?title=Project_Ideas&diff=23585Project Ideas2017-01-25T15:45:30Z<p>MartinRoth: /* Native graphics init */</p>
<hr />
<div>The following are ideas that have been proposed in the community. These are projects that we think can be managed in the short period of GSoC, and they cover areas where coreboot is trying to reach new users and new use cases. But of course these are not the only things that could be done. Maybe you have a great idea that we just didn't think of yet. Please let us know! <br />
<br />
<br />
Prospective [[GSoC]] students' application should expand on the ideas and provide specific information in the application. If you have questions or comments, please please contact the coreboot [[Mailinglist|mailing list]] or visit our [[IRC]] channel <code>#coreboot</code> on [https://webchat.freenode.net irc.freenode.net]. Our [[GSoC#Mentors]] are here to help.<br />
<br />
<br />
= coreboot Projects =<br />
<br />
== coreboot mainboard test suite ==<br />
<br />
Create a tool (possibly a bootable CD/USB drive image) to be run on a platform booted with coreboot (using SeaBIOS, GRUB, FILO or some other method) that runs a suite of tests and gathers the results. The tool may also be run on vendor BIOS to verify an issue created/fixed by coreboot or SeaBIOS.<br />
<br />
When applying for this task, please state in your proposal what you think the base image/kernel would be used, the method of generating the image, what test you are targeting, and how results are gathered.<br />
<br />
Possibilities for a container for the tool could include:<br />
* Downloading a script that sets up a live image to run various tests (Limits the number of tests)<br />
* Creating a script that builds a new live image for this purpose (More flexibility)<br />
* Customizing a distro or something to do what is needed - see the fwts-live image or BITS as examples. Create a new bootable ISO (Most flexible, and the most work)<br />
<br />
Possibilities for tests:<br />
* Extending FWTS to check for coreboot specific items (ubuntu & FWTS-live specific)<br />
* Parsing output of cbmem timestamps and coreboot boot log <br />
* Rebooting with various kernel parameters to test different items<br />
* Working with the community & coreboot vendors to develop additional tests<br />
<br />
'''Links'''<br />
* https://wiki.ubuntu.com/Kernel/Reference/fwts<br />
* https://wiki.ubuntu.com/FirmwareTestSuite/FirmwareTestSuiteLive<br />
* http://biosbits.org/ <br />
* https://help.ubuntu.com/community/LiveCDCustomization<br />
* https://os-autoinst.github.io/openQA/<br />
* [[Supported Motherboards]]<br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: novice<br />
* Linux scripting and application development: competent<br />
<br />
'''Requirements'''<br />
* A coreboot mainboard <br />
<br />
'''Mentors'''<br />
* [https://www.coreboot.org/User:MartinRoth Martin Roth]<br />
<br/><br/><br />
<br />
== coreboot mainboard test suite reporting ==<br />
<br />
One of the biggest challenges in coreboot is that it supports many systems in the same codebase. As coreboot develop and systems age, the condition of mainboards becomes unknown. Because of this, we have an increasing interest in automated tests on real hardware, with reporting. This project would define a coreboot test results reporting mechanism, gather data, and report passing and failing systems on a webpage. Build something more scalable than the current system of [https://review.coreboot.org/gitweb?p=board-status.git;a=tree git repository] + [[Supported Motherboards]].<br />
<br />
There should be an authenticated reporting endpoint and some web frontend, that can run on a typical linux system (ultimately hosted on coreboot.org). It should be possible to filter for various criteria. Feature extraction from log files would be a good idea, too. It should also be possible to import the existing data set.<br />
Language/framework/library is pretty much your choice, but shouldn't be too exotic unless you can convince us that you intend to maintain it for the long term.<br />
<br />
This project would work closely with the coreboot test suite project and/or the hardware test rig project. A good example of test results gathering and reporting is done by the Phoronix/Openbenchmark. The student should investigate other test and reporting solutions to leverage the best options for coreboot. It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.<br />
<br />
'''Links'''<br />
* http://openbenchmarking.org/<br />
* http://www.flashrom.org/Supported_hardware<br />
* [[Supported Motherboards]]<br />
* [https://review.coreboot.org/gitweb?p=board-status.git;a=tree Board status git repo]<br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: novice<br />
* web development: competent<br />
* machine learning: certainly helps building a good project<br />
<br />
'''Requirements'''<br />
* web development environment<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== coreboot on the open source Berkeley RISC V processor ==<br />
<br />
We've got a preliminary port of coreboot to the Berkeley RISC V. Much work remains to get the port running on real hardware. We have a board with an FPGA version of the chip, which can be provided to the student.<br />
<br />
This work would be to make the build process bullet proof and then show that we can boot linux on RISCV under coreboot. Ron has talked to the RISCV folks about this and promises that we'll have really good support. They've been very helpful already.<br />
<br />
'''Links'''<br />
* http://http://riscv.org/<br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: competent<br />
* linux: competent<br />
<br />
'''Requirements'''<br />
* Need a system on which to build and run the RISCV toolchain, coreboot, and run simulators.<br />
<br />
'''Mentors'''<br />
<br/>Ron Minnich<br/><br />
<br />
<br />
== Infrastructure for automatic code checking ==<br />
<br />
coreboot has a build bot that builds various configurations of coreboot on every gerrit commit. We would like to extend the current build infrastructure with various code validation routines, for example:<br />
* Validate that there's no regression in doxygen documentation (eg. are all arguments to functions still explained in @param tags, eg. after new arguments were added?)<br />
* Make code lint clean (and maybe extend lint to not fall into our traps), and run lint over the tree. Report regressions<br />
* Use LLVM's static code checking facilities, report regressions.<br />
* Implement automatic building on various OS types - FreeBSD, NetBSD, OSX, and Windows all seem to be used.<br />
<br />
<br />
'''Links'''<br />
* LLVM tools: [http://clang.llvm.org/StaticAnalysis.html Clang static analyser], [http://llvm.org/ProjectsWithLLVM/#Calysto SSA assertion checker], http://klee.llvm.org/, http://oclint.org/<br />
* Lint tools: [http://lclint.cs.virginia.edu/ Splint]<br />
* Semantic Tester: https://code.google.com/p/c-semantics/<br />
* [http://frama-c.com/ Frama-C]<br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: novice<br />
* compiler build and makefile knowledge: competent<br />
* Jenkins and test automation: novice<br />
<br />
'''Requirements'''<br />
* coreboot build environment <br />
<br />
<br />
'''Mentors'''<br />
* [https://www.coreboot.org/User:MartinRoth Martin Roth]<br />
<br/><br/><br />
<br />
<br />
== Implement advanced coreboot features on existing mainboards ==<br />
<br />
A lot of cool new coreboot features are only available on a small subset of the supported mainboards. Those features include:<br />
* global variables in romstage<br />
* relocatable ramstage<br />
* cbmem console<br />
* timestamps/performance data<br />
<br />
This project would identify how to bring those features forward to more boards and complete porting of said mainboards.<br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: competent<br />
<br />
'''Requirements'''<br />
* coreboot mainboard(s)<br />
<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== coreboot ACPI 4.0 and S3 power management ==<br />
<br />
coreboot has support for ACPI tables and S3 support for some platforms, but the implementations are mainboard specific and mostly based on ACPI 2.0. Create a generic solution for ACPI 4.0 table generation and S3 support across all mainboards. <br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: competent to expert<br />
* ACPI and power management: novice to competent<br />
<br />
'''Requirements'''<br />
* coreboot mainboard<br />
* flash recovery mechanism <br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== coreboot panic room ==<br />
<br />
Create a safe boot solution for coreboot to easily and cheaply recover the system. <br />
<br />
The basic idea is that the system flash image always contains executable for SerialICE. Instead of loading a coreboot romstage, firmware can boot to SerialICE based on some GPIO state, a keypress sequence or a logged failure on earlier boots. It is possible to integrate this into the coreboot build tree as a bootblock option, in the same spot as the fallback/normal switch and the simple loader.<br />
<br />
Having this capability opens up new possibilities:<br />
<br />
During the lifetime of a mainboard, new requirements for ACPI hacks and CPU microcodes introduce the need to update boot firmware at customer site. The firmware shall have recovery path against any failures during the firmware update process. The most straight-forward solution is to do intelligent allocation of files in the CBFS such that files critical to the recovery are located on write-protected pages. The recovery path shall require only an USB mass-storage with compatible filesystem (ext2, fat32).<br />
<br />
The ability to dual-boot reduces the amount of tools required to reverse-engineer proprietary BIOS on ports for new mainboards. It is increasingly common that the flash chips are a) not socketed or b) physically hard to access (laptops). Even if chipset support existed already for a board, there are a lot of configuration registers for PCI-e links and GPIO signals that are difficult to get right by code disassembly only. With panic room implementation there would be no need to use external programmers or flashchip hot-swap method to alternate between SerialICE (for proprietary BIOS) and coreboot romstage boots.<br />
<br />
SerialICE requires minimal hardware resources and does not require installed RAM or display hardware. It could be used as the first power-on environment after mainboard PCB verification and assembly to verify integrated components enumerate correctly. At the end of this first power-on, actual board firmware can be programmed without the need for external programmers and SOIC-8 clips, as the SPI controller embedded in the chipset can be used instead. As setting up EHCI debug port console is fairly simple across different chipsets, it can be used to print detailed diagnostics instead of POST codes on LPC bus.<br />
<br />
<br />
GSoC 2011 project [http://blogs.coreboot.org/blog/2011/05/09/gsoc-project-coreboot-panic-room-diagnostics-also-remote-flashing/] was able to:<br />
* Link flashrom with libpayload and flash from USB drive in a pre-OS environment.<br />
* Optimise flashrom memory usage to flash in pre-ram/cache-as-ram environment.<br />
* Build SerialICE boot ROM inside the coreboot tree and share some of the PnP/SuperIO source code.<br />
* Demonstrate booting alternative payload on keypress.<br />
<br />
<br />
There are remaining open tasks to:<br />
* Bring the GSoC 2011 patches up-to-date with current flashrom and libpayload trees.<br />
* Create generic solution to jump to recovery mode using input from GPIOs and/or use of power-button override.<br />
* Use SMBus/SMLink to send POST failure codes over ethernet using integrated network controllers.<br />
* After panic(), dump RAM contents before they are overwritten.<br />
<br />
'''Skill Level'''<br />
* coreboot: competent to expert<br />
<br />
'''Requirements'''<br />
* coreboot mainboard<br />
* flash recovery mechanism<br />
<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== Board config infrastructure ==<br />
<br />
Design data structures that host information about the board layout so coreboot can better initialize components and generate all kinds of tables (mptable, pirq, acpi, ...) from that dynamically (at build or runtime, as appropriate). Adapt boards to use that instead of the current hardcodes.<br />
<br />
We had some data structure work being done in coreboot v3 (based on DTS device tree source), but the approach back then didn't have the desired results. Still, if you want to tackle this task you can get some valuable information in past coreboot v3 discussions about what's feasible and what's infeasible.<br />
<br />
'''Links'''<br />
* Check out the various devicetree.cb files in the src/ directory of the coreboot repository.<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== Infrastructure for accessing block devices ==<br />
<br />
Create a simple interface to access block devices, such as NAND, SD cards, MMC, etc. This is needed on some lower-end ARM SoCs in order to load successive coreboot stages.<br />
<br />
'''Example:''' On Allwinner A10 SoCs, the hardware bootloader will load up to a 24KiB bootblock. That's barely sufficient to initialize DRAM and load the next stage from MMC, and is nowhere near enough to run all stages of coreboot. Coreboot will need to know how to read MMC.<br />
<br />
'''Links'''<br />
* [[User_talk:MrNuke/Block_Device_API | Initial proposal]]<br />
* [[Board:cubietech/cubieboard | Cubieboard page]]<br />
<br />
'''Skill Level'''<br />
* coreboot and ARM firmware: competent<br />
<br />
'''Requirements'''<br />
* An ARM board with low-end SoC (for example, Cubieboard, with Allwinner A10)<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
<br />
== Native graphics init ==<br />
<br />
Implement native initialization of the graphics hardware (probably AMD or Intel) so no Video BIOS is needed.<br />
<br />
<br />
<br />
A test and performance possibility, like a payload testing the correct initialization, needs to be added too.<br />
<br />
This could be done in combination with making a board port.<br />
<br />
'''Links'''<br />
* [http://www.coreboot.org/pipermail/coreboot/2013-March/075512.html Small discussion about initialization of AMD graphics hardware]<br />
<br />
'''Skill Level'''<br />
* coreboot: competent<br />
* Linux graphics stack: competent<br />
<br />
'''Requirements'''<br />
* coreboot mainboard<br />
* flash recovery mechanism<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== End user flash tool ==<br />
<br />
A tool that takes a coreboot image without payload, and payload binaries (so the user can select which payload to use), combines them according to user wishes. <br />
It copies other required components (EC/ME firmware, VGABIOS) from the running system (ie. dump flash, extract data) and compares their hash against a white list (so we can vouch for their compatibility), then writes the result to flash, unlocking flash if necessary.<br />
<br />
Ideally it's a portable graphical tool (assuming that flashrom is available for the target OS). It could use libflashrom, the bios_extract tools, and cbfstool in the background and provide the glue to make things work.<br />
<br />
Additional info about the purpose of this tool:<br />
The challenge is to give users a simple way to create a '''working''' coreboot image with all the necessary components, including the components we can't provide as coreboot.org downloads for technical or legal reasons. This tool is intended as one-stop shop (one-click tool by default) to create working images without the user having to worry about which options are correct for his/her system. If any options are not applicable for a given system or if those options might result in a system not booting as expected, they should not be shown at all. It is explicitly not desired to just get a GUI exposing the complexity of the underlying tools (we have that, and it's called the command line).<br />
<br />
Technical challenges for the design and implementation:<br />
To provide a working image for a given board, hardware peculiarities have to be handled automatically as much as possible. The tool has to<br />
* extract/dump some data/contents from the running system while coreboot is not yet installed, zero or more of the following<br />
** EDID data<br />
** PCI configuration (lspci -nn)<br />
** old flash chip contents<br />
** VGA BIOS in its mangled form dumped from memory (C segment)<br />
** VGA BIOS in its original form extracted from the flash chip contents<br />
** onboard network firmware/configuration/MACaddr, possibly extracted from the flash chip contents or other in-system data sources<br />
* possibly download and mangle BIOS update files from a vendor site<br />
** mostly in case the data mentioned above can't be extracted from the running system or in case newer data is available as download from the vendor<br />
* detect the exact variant of the hardware including any special handling needed (e.g. there are dozens of different Thinkpad T60/T60p variants all using the exact same coreboot code, but some need a VGA option ROM and some don't, the TFT panel definitions differ, etc.)<br />
* check whether the extracted data (mostly VGA BIOS etc.) matches the data that's known to work, e.g. by comparing hashes<br />
* check whether the extracted data has correct internal checksums and if not, check whether fixups are needed or wanted for this particular hardware (e.g. some C segment dumps from VGA option ROMs have broken checksums and their checksums should be fixed automatically by the tool, other VGA option ROMs should yield an error instead)<br />
* present the end user only with the choices that make sense for this specific piece of hardware<br />
* warn the user if hardware with this exact hardware has no complete (or none at all) rule set for working images<br />
* provide a way to import or store rules for doing all the stuff above for multiple boards or board variants<br />
<br />
The complexity of that logic is very hard to handle if you're open-coding everything, and it might make sense to either invent a language for the rules and actions mentioned above or use JSON or XML wisely. Please note that the tool itself is not supposed to be written in JSON or XML, but rather a cross-platform capable language, preferably with a graphical (i.e. not text mode) user interface.<br />
<br />
Providing example logic for one supported coreboot mainboard (not qemu!) based on wiki contents (e.g. for Thinkpad T60) would be a goal as well.<br />
<br />
'''Skill Level'''<br />
* coreboot: novice<br />
* Systems programming, GUI programming: competent<br />
<br />
'''Requirements'''<br />
* coreboot mainboard<br />
* flash recovery mechanism<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
<br />
== proper configuration support in upstream (devtree -> kconfig -> runtime values) ==<br />
'''Skill Level'''<br />
* coreboot: medium<br />
* C, build system.<br />
<br />
'''Requirements'''<br />
* knowledge of what types of configuration exist in coreboot<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
==<br />
This would involve refactoring the current print system, and allowing sections to enable/disable different levels of output. coreboot currently has a very basic way to do this, turning debug on and off for various sections at build time. Something that is significantly more granular would be nice, and something that could be updated at runtime would be good.<br />
<br />
'''Skill Level'''<br />
* coreboot: novice<br />
* Systems programming<br />
<br />
'''Requirements'''<br />
* none - this can be tested with coreboot booting in QEMU<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== console via SMBus ==<br />
<br />
Not all boards have an accessible serial port, but all boards with socketed RAM have a somehow accessible SMBus (used for reading the SPD-EEPROMs), which can be used very early in the boot process. As a device to receive the logs for example a beaglebone black or a cheap stm32 board with the i2c-star firmware can be used. The console via SMBus isn't that much slower than a serial console and ways faster than the speakermodem output.<br />
<br />
'''Skill Level'''<br />
* coreboot: medium<br />
* soldering: medium<br />
<br />
'''Requirements'''<br />
* none<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== ARM64 qemu port ==<br />
<br />
Develop mainboard/chipset support for a ARM64 qemu target. In order to work on ARM64 code one usually needs a ARM64 board. To reduce that barrier, work on a ARM64 qemu port.<br />
<br />
'''Skill Level'''<br />
* coreboot: medium<br />
<br />
'''Requirements'''<br />
* none<br />
<br />
'''Mentors'''<br />
* adurbin<br />
<br/><br/><br />
<br />
== Add U-Boot as a generic coreboot payload ==<br />
<br />
U-Boot already will run as a coreboot payload, but it needs to be modified for each different platform. Some work has already been done to add it to the coreboot build as a payload, but it still doesn't work correctly in a generic fashion. It also won't currently build with the coreboot toolchain.<br />
<br />
This project will require work on both the coreboot and U-Boot projects.<br />
<br />
'''Skill Level'''<br />
* coreboot: novice<br />
* Makefile and toolchain skills: medium<br />
<br />
'''Requirements'''<br />
* none<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== Provide toolchain binaries ==<br />
<br />
Provides packages/installers of our compiler toolchain for Linux distros, Windows, Mac OS. For Windows, this should also include the environment (shell, make, ...).<br />
<br />
'''Skill Level'''<br />
* coreboot: novice<br />
<br />
'''Requirements'''<br />
* knowledge of package/installer tooling on their target OS<br />
<br />
'''Mentors'''<br />
<br/>pgeorgi<br/><br />
<br />
= flashrom Projects =<br />
<br />
Flashrom is a project that is closely associated with coreboot and we work together where possible. They maintain a list of project ideas on their own website:<br />
<br />
[http://www.flashrom.org/GSoC flashrom project ideas]<br />
<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
= SerialICE Projects =<br />
<br />
SerialICE is a project that started out as tool for coreboot development. They maintain a list of project ideas on their own website:<br />
<br />
<br />
* [http://serialice.com/GSoC SerialICE project ideas]<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
= ROM-O-Matic =<br />
<br />
The ROM-O-Matic is envisioned to be a build server that would be usable by the general public to build ROMS for their mainboards without the need to set up coreboot build system themselves. The coreboot project does not distribute ROM files, requiring users to build their own ROMs.<br />
<br />
== Creation of the server ==<br />
It could be developed in a series of steps:<br />
# Build a very limited number of Mainboards, only from known good versions contained in the board-status repository. These would be boards that are blob-free or have all necessary blobs contained in the 3rd-party/blobs repo.<br />
#* Either the toolchain required for the mainboard would be re-built for each build, or a cached toolchain could be used.<br />
#* The build can be verified to match the MD5 sum of the original build.<br />
#* User gets binaries along with source tree to satisfy licenses.<br />
# Extend the board list to boards that needed external blobs which can be found freely available on the internet. This would be cases where the OEM BIOS can be downloaded, and the pieces can be extracted. Still only versions that are listed in board-status would be available for building.<br />
#* Tools to automate the download and extraction of these blobs would need to be created.<br />
# Allow building from any valid git commit<br />
# Allow building any valid board.<br />
# Allow including patches into the build for customization of the build.<br />
#* At this point, security becomes an issue, and the build would need to be locked down, similar to the current jenkins setup, which builds in a chroot with network disabled.<br />
# Allow additional binaries to be uploaded to be included into the build.<br />
<br />
'''Mentors'''<br />
* [https://www.coreboot.org/User:MartinRoth Martin Roth]<br />
<br/><br/></div>MartinRothhttps://www.coreboot.org/index.php?title=Project_Ideas&diff=23584Project Ideas2017-01-25T15:39:29Z<p>MartinRoth: /* Tianocore as payload */</p>
<hr />
<div>The following are ideas that have been proposed in the community. These are projects that we think can be managed in the short period of GSoC, and they cover areas where coreboot is trying to reach new users and new use cases. But of course these are not the only things that could be done. Maybe you have a great idea that we just didn't think of yet. Please let us know! <br />
<br />
<br />
Prospective [[GSoC]] students' application should expand on the ideas and provide specific information in the application. If you have questions or comments, please please contact the coreboot [[Mailinglist|mailing list]] or visit our [[IRC]] channel <code>#coreboot</code> on [https://webchat.freenode.net irc.freenode.net]. Our [[GSoC#Mentors]] are here to help.<br />
<br />
<br />
= coreboot Projects =<br />
<br />
== coreboot mainboard test suite ==<br />
<br />
Create a tool (possibly a bootable CD/USB drive image) to be run on a platform booted with coreboot (using SeaBIOS, GRUB, FILO or some other method) that runs a suite of tests and gathers the results. The tool may also be run on vendor BIOS to verify an issue created/fixed by coreboot or SeaBIOS.<br />
<br />
When applying for this task, please state in your proposal what you think the base image/kernel would be used, the method of generating the image, what test you are targeting, and how results are gathered.<br />
<br />
Possibilities for a container for the tool could include:<br />
* Downloading a script that sets up a live image to run various tests (Limits the number of tests)<br />
* Creating a script that builds a new live image for this purpose (More flexibility)<br />
* Customizing a distro or something to do what is needed - see the fwts-live image or BITS as examples. Create a new bootable ISO (Most flexible, and the most work)<br />
<br />
Possibilities for tests:<br />
* Extending FWTS to check for coreboot specific items (ubuntu & FWTS-live specific)<br />
* Parsing output of cbmem timestamps and coreboot boot log <br />
* Rebooting with various kernel parameters to test different items<br />
* Working with the community & coreboot vendors to develop additional tests<br />
<br />
'''Links'''<br />
* https://wiki.ubuntu.com/Kernel/Reference/fwts<br />
* https://wiki.ubuntu.com/FirmwareTestSuite/FirmwareTestSuiteLive<br />
* http://biosbits.org/ <br />
* https://help.ubuntu.com/community/LiveCDCustomization<br />
* https://os-autoinst.github.io/openQA/<br />
* [[Supported Motherboards]]<br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: novice<br />
* Linux scripting and application development: competent<br />
<br />
'''Requirements'''<br />
* A coreboot mainboard <br />
<br />
'''Mentors'''<br />
* [https://www.coreboot.org/User:MartinRoth Martin Roth]<br />
<br/><br/><br />
<br />
== coreboot mainboard test suite reporting ==<br />
<br />
One of the biggest challenges in coreboot is that it supports many systems in the same codebase. As coreboot develop and systems age, the condition of mainboards becomes unknown. Because of this, we have an increasing interest in automated tests on real hardware, with reporting. This project would define a coreboot test results reporting mechanism, gather data, and report passing and failing systems on a webpage. Build something more scalable than the current system of [https://review.coreboot.org/gitweb?p=board-status.git;a=tree git repository] + [[Supported Motherboards]].<br />
<br />
There should be an authenticated reporting endpoint and some web frontend, that can run on a typical linux system (ultimately hosted on coreboot.org). It should be possible to filter for various criteria. Feature extraction from log files would be a good idea, too. It should also be possible to import the existing data set.<br />
Language/framework/library is pretty much your choice, but shouldn't be too exotic unless you can convince us that you intend to maintain it for the long term.<br />
<br />
This project would work closely with the coreboot test suite project and/or the hardware test rig project. A good example of test results gathering and reporting is done by the Phoronix/Openbenchmark. The student should investigate other test and reporting solutions to leverage the best options for coreboot. It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.<br />
<br />
'''Links'''<br />
* http://openbenchmarking.org/<br />
* http://www.flashrom.org/Supported_hardware<br />
* [[Supported Motherboards]]<br />
* [https://review.coreboot.org/gitweb?p=board-status.git;a=tree Board status git repo]<br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: novice<br />
* web development: competent<br />
* machine learning: certainly helps building a good project<br />
<br />
'''Requirements'''<br />
* web development environment<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== coreboot on the open source Berkeley RISC V processor ==<br />
<br />
We've got a preliminary port of coreboot to the Berkeley RISC V. Much work remains to get the port running on real hardware. We have a board with an FPGA version of the chip, which can be provided to the student.<br />
<br />
This work would be to make the build process bullet proof and then show that we can boot linux on RISCV under coreboot. Ron has talked to the RISCV folks about this and promises that we'll have really good support. They've been very helpful already.<br />
<br />
'''Links'''<br />
* http://http://riscv.org/<br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: competent<br />
* linux: competent<br />
<br />
'''Requirements'''<br />
* Need a system on which to build and run the RISCV toolchain, coreboot, and run simulators.<br />
<br />
'''Mentors'''<br />
<br/>Ron Minnich<br/><br />
<br />
<br />
== Infrastructure for automatic code checking ==<br />
<br />
coreboot has a build bot that builds various configurations of coreboot on every gerrit commit. We would like to extend the current build infrastructure with various code validation routines, for example:<br />
* Validate that there's no regression in doxygen documentation (eg. are all arguments to functions still explained in @param tags, eg. after new arguments were added?)<br />
* Make code lint clean (and maybe extend lint to not fall into our traps), and run lint over the tree. Report regressions<br />
* Use LLVM's static code checking facilities, report regressions.<br />
* Implement automatic building on various OS types - FreeBSD, NetBSD, OSX, and Windows all seem to be used.<br />
<br />
<br />
'''Links'''<br />
* LLVM tools: [http://clang.llvm.org/StaticAnalysis.html Clang static analyser], [http://llvm.org/ProjectsWithLLVM/#Calysto SSA assertion checker], http://klee.llvm.org/, http://oclint.org/<br />
* Lint tools: [http://lclint.cs.virginia.edu/ Splint]<br />
* Semantic Tester: https://code.google.com/p/c-semantics/<br />
* [http://frama-c.com/ Frama-C]<br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: novice<br />
* compiler build and makefile knowledge: competent<br />
* Jenkins and test automation: novice<br />
<br />
'''Requirements'''<br />
* coreboot build environment <br />
<br />
<br />
'''Mentors'''<br />
* [https://www.coreboot.org/User:MartinRoth Martin Roth]<br />
<br/><br/><br />
<br />
<br />
== Implement advanced coreboot features on existing mainboards ==<br />
<br />
A lot of cool new coreboot features are only available on a small subset of the supported mainboards. Those features include:<br />
* global variables in romstage<br />
* relocatable ramstage<br />
* cbmem console<br />
* timestamps/performance data<br />
<br />
This project would identify how to bring those features forward to more boards and complete porting of said mainboards.<br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: competent<br />
<br />
'''Requirements'''<br />
* coreboot mainboard(s)<br />
<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== coreboot ACPI 4.0 and S3 power management ==<br />
<br />
coreboot has support for ACPI tables and S3 support for some platforms, but the implementations are mainboard specific and mostly based on ACPI 2.0. Create a generic solution for ACPI 4.0 table generation and S3 support across all mainboards. <br />
<br />
'''Skill Level'''<br />
* coreboot and firmware: competent to expert<br />
* ACPI and power management: novice to competent<br />
<br />
'''Requirements'''<br />
* coreboot mainboard<br />
* flash recovery mechanism <br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== coreboot panic room ==<br />
<br />
Create a safe boot solution for coreboot to easily and cheaply recover the system. <br />
<br />
The basic idea is that the system flash image always contains executable for SerialICE. Instead of loading a coreboot romstage, firmware can boot to SerialICE based on some GPIO state, a keypress sequence or a logged failure on earlier boots. It is possible to integrate this into the coreboot build tree as a bootblock option, in the same spot as the fallback/normal switch and the simple loader.<br />
<br />
Having this capability opens up new possibilities:<br />
<br />
During the lifetime of a mainboard, new requirements for ACPI hacks and CPU microcodes introduce the need to update boot firmware at customer site. The firmware shall have recovery path against any failures during the firmware update process. The most straight-forward solution is to do intelligent allocation of files in the CBFS such that files critical to the recovery are located on write-protected pages. The recovery path shall require only an USB mass-storage with compatible filesystem (ext2, fat32).<br />
<br />
The ability to dual-boot reduces the amount of tools required to reverse-engineer proprietary BIOS on ports for new mainboards. It is increasingly common that the flash chips are a) not socketed or b) physically hard to access (laptops). Even if chipset support existed already for a board, there are a lot of configuration registers for PCI-e links and GPIO signals that are difficult to get right by code disassembly only. With panic room implementation there would be no need to use external programmers or flashchip hot-swap method to alternate between SerialICE (for proprietary BIOS) and coreboot romstage boots.<br />
<br />
SerialICE requires minimal hardware resources and does not require installed RAM or display hardware. It could be used as the first power-on environment after mainboard PCB verification and assembly to verify integrated components enumerate correctly. At the end of this first power-on, actual board firmware can be programmed without the need for external programmers and SOIC-8 clips, as the SPI controller embedded in the chipset can be used instead. As setting up EHCI debug port console is fairly simple across different chipsets, it can be used to print detailed diagnostics instead of POST codes on LPC bus.<br />
<br />
<br />
GSoC 2011 project [http://blogs.coreboot.org/blog/2011/05/09/gsoc-project-coreboot-panic-room-diagnostics-also-remote-flashing/] was able to:<br />
* Link flashrom with libpayload and flash from USB drive in a pre-OS environment.<br />
* Optimise flashrom memory usage to flash in pre-ram/cache-as-ram environment.<br />
* Build SerialICE boot ROM inside the coreboot tree and share some of the PnP/SuperIO source code.<br />
* Demonstrate booting alternative payload on keypress.<br />
<br />
<br />
There are remaining open tasks to:<br />
* Bring the GSoC 2011 patches up-to-date with current flashrom and libpayload trees.<br />
* Create generic solution to jump to recovery mode using input from GPIOs and/or use of power-button override.<br />
* Use SMBus/SMLink to send POST failure codes over ethernet using integrated network controllers.<br />
* After panic(), dump RAM contents before they are overwritten.<br />
<br />
'''Skill Level'''<br />
* coreboot: competent to expert<br />
<br />
'''Requirements'''<br />
* coreboot mainboard<br />
* flash recovery mechanism<br />
<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== Board config infrastructure ==<br />
<br />
Design data structures that host information about the board layout so coreboot can better initialize components and generate all kinds of tables (mptable, pirq, acpi, ...) from that dynamically (at build or runtime, as appropriate). Adapt boards to use that instead of the current hardcodes.<br />
<br />
We had some data structure work being done in coreboot v3 (based on DTS device tree source), but the approach back then didn't have the desired results. Still, if you want to tackle this task you can get some valuable information in past coreboot v3 discussions about what's feasible and what's infeasible.<br />
<br />
'''Links'''<br />
* Check out the various devicetree.cb files in the src/ directory of the coreboot repository.<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== Infrastructure for accessing block devices ==<br />
<br />
Create a simple interface to access block devices, such as NAND, SD cards, MMC, etc. This is needed on some lower-end ARM SoCs in order to load successive coreboot stages.<br />
<br />
'''Example:''' On Allwinner A10 SoCs, the hardware bootloader will load up to a 24KiB bootblock. That's barely sufficient to initialize DRAM and load the next stage from MMC, and is nowhere near enough to run all stages of coreboot. Coreboot will need to know how to read MMC.<br />
<br />
'''Links'''<br />
* [[User_talk:MrNuke/Block_Device_API | Initial proposal]]<br />
* [[Board:cubietech/cubieboard | Cubieboard page]]<br />
<br />
'''Skill Level'''<br />
* coreboot and ARM firmware: competent<br />
<br />
'''Requirements'''<br />
* An ARM board with low-end SoC (for example, Cubieboard, with Allwinner A10)<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
<br />
== Native graphics init ==<br />
<br />
Implement native initialization of the graphics hardware (probably AMD or Intel) so no Video BIOS is needed.<br />
<br />
<br />
<br />
A test and performance possibility, like a payload testing the correct initialization, needs to be added too.<br />
<br />
This could be done in combination with making a board port.<br />
<br />
'''Links'''<br />
* [<br />
* [http://www.coreboot.org/pipermail/coreboot/2013-March/075512.html Small discussion about initialization of AMD graphics hardware]<br />
* [<br />
<br />
'''Skill Level'''<br />
* coreboot: competent<br />
* Linux graphics stack: competent<br />
<br />
'''Requirements'''<br />
* coreboot mainboard<br />
* flash recovery mechanism<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== End user flash tool ==<br />
<br />
A tool that takes a coreboot image without payload, and payload binaries (so the user can select which payload to use), combines them according to user wishes. <br />
It copies other required components (EC/ME firmware, VGABIOS) from the running system (ie. dump flash, extract data) and compares their hash against a white list (so we can vouch for their compatibility), then writes the result to flash, unlocking flash if necessary.<br />
<br />
Ideally it's a portable graphical tool (assuming that flashrom is available for the target OS). It could use libflashrom, the bios_extract tools, and cbfstool in the background and provide the glue to make things work.<br />
<br />
Additional info about the purpose of this tool:<br />
The challenge is to give users a simple way to create a '''working''' coreboot image with all the necessary components, including the components we can't provide as coreboot.org downloads for technical or legal reasons. This tool is intended as one-stop shop (one-click tool by default) to create working images without the user having to worry about which options are correct for his/her system. If any options are not applicable for a given system or if those options might result in a system not booting as expected, they should not be shown at all. It is explicitly not desired to just get a GUI exposing the complexity of the underlying tools (we have that, and it's called the command line).<br />
<br />
Technical challenges for the design and implementation:<br />
To provide a working image for a given board, hardware peculiarities have to be handled automatically as much as possible. The tool has to<br />
* extract/dump some data/contents from the running system while coreboot is not yet installed, zero or more of the following<br />
** EDID data<br />
** PCI configuration (lspci -nn)<br />
** old flash chip contents<br />
** VGA BIOS in its mangled form dumped from memory (C segment)<br />
** VGA BIOS in its original form extracted from the flash chip contents<br />
** onboard network firmware/configuration/MACaddr, possibly extracted from the flash chip contents or other in-system data sources<br />
* possibly download and mangle BIOS update files from a vendor site<br />
** mostly in case the data mentioned above can't be extracted from the running system or in case newer data is available as download from the vendor<br />
* detect the exact variant of the hardware including any special handling needed (e.g. there are dozens of different Thinkpad T60/T60p variants all using the exact same coreboot code, but some need a VGA option ROM and some don't, the TFT panel definitions differ, etc.)<br />
* check whether the extracted data (mostly VGA BIOS etc.) matches the data that's known to work, e.g. by comparing hashes<br />
* check whether the extracted data has correct internal checksums and if not, check whether fixups are needed or wanted for this particular hardware (e.g. some C segment dumps from VGA option ROMs have broken checksums and their checksums should be fixed automatically by the tool, other VGA option ROMs should yield an error instead)<br />
* present the end user only with the choices that make sense for this specific piece of hardware<br />
* warn the user if hardware with this exact hardware has no complete (or none at all) rule set for working images<br />
* provide a way to import or store rules for doing all the stuff above for multiple boards or board variants<br />
<br />
The complexity of that logic is very hard to handle if you're open-coding everything, and it might make sense to either invent a language for the rules and actions mentioned above or use JSON or XML wisely. Please note that the tool itself is not supposed to be written in JSON or XML, but rather a cross-platform capable language, preferably with a graphical (i.e. not text mode) user interface.<br />
<br />
Providing example logic for one supported coreboot mainboard (not qemu!) based on wiki contents (e.g. for Thinkpad T60) would be a goal as well.<br />
<br />
'''Skill Level'''<br />
* coreboot: novice<br />
* Systems programming, GUI programming: competent<br />
<br />
'''Requirements'''<br />
* coreboot mainboard<br />
* flash recovery mechanism<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
<br />
== proper configuration support in upstream (devtree -> kconfig -> runtime values) ==<br />
'''Skill Level'''<br />
* coreboot: medium<br />
* C, build system.<br />
<br />
'''Requirements'''<br />
* knowledge of what types of configuration exist in coreboot<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
==<br />
This would involve refactoring the current print system, and allowing sections to enable/disable different levels of output. coreboot currently has a very basic way to do this, turning debug on and off for various sections at build time. Something that is significantly more granular would be nice, and something that could be updated at runtime would be good.<br />
<br />
'''Skill Level'''<br />
* coreboot: novice<br />
* Systems programming<br />
<br />
'''Requirements'''<br />
* none - this can be tested with coreboot booting in QEMU<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== console via SMBus ==<br />
<br />
Not all boards have an accessible serial port, but all boards with socketed RAM have a somehow accessible SMBus (used for reading the SPD-EEPROMs), which can be used very early in the boot process. As a device to receive the logs for example a beaglebone black or a cheap stm32 board with the i2c-star firmware can be used. The console via SMBus isn't that much slower than a serial console and ways faster than the speakermodem output.<br />
<br />
'''Skill Level'''<br />
* coreboot: medium<br />
* soldering: medium<br />
<br />
'''Requirements'''<br />
* none<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== ARM64 qemu port ==<br />
<br />
Develop mainboard/chipset support for a ARM64 qemu target. In order to work on ARM64 code one usually needs a ARM64 board. To reduce that barrier, work on a ARM64 qemu port.<br />
<br />
'''Skill Level'''<br />
* coreboot: medium<br />
<br />
'''Requirements'''<br />
* none<br />
<br />
'''Mentors'''<br />
* adurbin<br />
<br/><br/><br />
<br />
== Add U-Boot as a generic coreboot payload ==<br />
<br />
U-Boot already will run as a coreboot payload, but it needs to be modified for each different platform. Some work has already been done to add it to the coreboot build as a payload, but it still doesn't work correctly in a generic fashion. It also won't currently build with the coreboot toolchain.<br />
<br />
This project will require work on both the coreboot and U-Boot projects.<br />
<br />
'''Skill Level'''<br />
* coreboot: novice<br />
* Makefile and toolchain skills: medium<br />
<br />
'''Requirements'''<br />
* none<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
== Provide toolchain binaries ==<br />
<br />
Provides packages/installers of our compiler toolchain for Linux distros, Windows, Mac OS. For Windows, this should also include the environment (shell, make, ...).<br />
<br />
'''Skill Level'''<br />
* coreboot: novice<br />
<br />
'''Requirements'''<br />
* knowledge of package/installer tooling on their target OS<br />
<br />
'''Mentors'''<br />
<br/>pgeorgi<br/><br />
<br />
= flashrom Projects =<br />
<br />
Flashrom is a project that is closely associated with coreboot and we work together where possible. They maintain a list of project ideas on their own website:<br />
<br />
[http://www.flashrom.org/GSoC flashrom project ideas]<br />
<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
= SerialICE Projects =<br />
<br />
SerialICE is a project that started out as tool for coreboot development. They maintain a list of project ideas on their own website:<br />
<br />
<br />
* [http://serialice.com/GSoC SerialICE project ideas]<br />
<br />
'''Mentors'''<br />
<br/><br/><br />
<br />
= ROM-O-Matic =<br />
<br />
The ROM-O-Matic is envisioned to be a build server that would be usable by the general public to build ROMS for their mainboards without the need to set up coreboot build system themselves. The coreboot project does not distribute ROM files, requiring users to build their own ROMs.<br />
<br />
== Creation of the server ==<br />
It could be developed in a series of steps:<br />
# Build a very limited number of Mainboards, only from known good versions contained in the board-status repository. These would be boards that are blob-free or have all necessary blobs contained in the 3rd-party/blobs repo.<br />
#* Either the toolchain required for the mainboard would be re-built for each build, or a cached toolchain could be used.<br />
#* The build can be verified to match the MD5 sum of the original build.<br />
#* User gets binaries along with source tree to satisfy licenses.<br />
# Extend the board list to boards that needed external blobs which can be found freely available on the internet. This would be cases where the OEM BIOS can be downloaded, and the pieces can be extracted. Still only versions that are listed in board-status would be available for building.<br />
#* Tools to automate the download and extraction of these blobs would need to be created.<br />
# Allow building from any valid git commit<br />
# Allow building any valid board.<br />
# Allow including patches into the build for customization of the build.<br />
#* At this point, security becomes an issue, and the build would need to be locked down, similar to the current jenkins setup, which builds in a chroot with network disabled.<br />
# Allow additional binaries to be uploaded to be included into the build.<br />
<br />
'''Mentors'''<br />
* [https://www.coreboot.org/User:MartinRoth Martin Roth]<br />
<br/><br/></div>MartinRothhttps://www.coreboot.org/index.php?title=GSoC&diff=23493GSoC2017-01-20T21:52:25Z<p>MartinRoth: </p>
<hr />
<div>coreboot is applying for [https://summerofcode.withgoogle.com/ Google Summer of Code 2017] as a mentoring organization.<br />
It is not assumed that we are accepted yet. We will announce this on the mailing list, chat.coreboot.org and update this page when we are informed on 27 February.<br />
<br />
coreboot has many [[Project Ideas]] for various ability levels. The coreboot project also acts as an umbrella organization for other open-source firmware related projects.<br />
<br />
Official student application period in 2017 is from March 20 to April 3, with results announced on April 4. For the complete timeline, please see the [https://summerofcode.withgoogle.com/how-it-works/#timeline GSoC 2017 timeline].<br />
<br />
__FORCETOC__<br />
<br />
== coreboot contacts ==<br />
<br />
If you are interested in participating in GSoC as a student student, please visit [https://chat.coreboot.org/ chat.coreboot.org]. Working closely with the community is highly encouraged, as we've seen that our most successful students are generally very involved.<br />
<br />
[[User:PatrickGeorgi|Patrick Georgi]] and [[User:MartinRoth|Martin Roth]] are the coreboot GSoC admins for 2017. Please feel free to reach out to them directly if you have any questions.<br />
<br />
= Why work on coreboot for GSoC 2017? =<br />
<br />
* coreboot offers you the opportunity to work with various architectures right on the iron. coreboot supports both current and older silicon for a wide variety of chips and technologies.<br />
* coreboot has a worldwide developer and user base.<br />
* We are a very passionate team, so you will interact directly with the project initiators and project leaders. <br />
* We have a large, helpful community. coreboot has some extremely talented and helpful experts in firmware involved in the project. They are ready to assist and mentor students participating in GSoC.<br />
* One of the last areas where open source software is not common is firmware. Running proprietary firmware can have severe effects on user's freedom and security. coreboot changes that by providing a common framework for initial hardware initialization and you can help us succeed.<br />
<br />
= GSoC Student requirements =<br />
<br />
What will be required of you to be a coreboot GSoC student?<br />
<br />
Google Summer of Code is a full-time job. This means we expect you to work roughly 40 hours per week on your project, during the three months of coding. Obviously we have flexibility, but if your schedule (exams, courses, other obligations) does not give you this amount of time, then you should not apply. We expect to be able to see this level of effort in student output.<br />
<br />
== Before applying ==<br />
*Prior to project acceptance, you have demonstrated that you can work with the coreboot codebase. <br />
:*By the time you have submitted your application, you should have downloaded, built and booted coreboot in QEMU, SimNow, or on real hardware. Please email your serial output results to the mailing list. <br />
:*Look over some of the development processes guidelines: [[git]], [https://review.coreboot.org/cgit/coreboot.git/plain/Documentation/gerrit_guidelines.md? Gerrit Etiquette and Guidelines], [[Development Guidelines]], and [[Developer Manual]]<br />
:*Get signed up for gerrit and push at least one patch to Gerrit for review. Check [[Easy projects]] or ask for simple tasks on the mailing list or on chat.coreboot.org if you need ideas.<br />
:*Look through some patches on gerrit to get an understanding of the review process and common issues<br />
*Before applying, you should also join the [https://www.coreboot.org/mailman/listinfo/coreboot mailing list] and [https://chat.coreboot.org chat.coreboot.org]. Introduce yourself and mention that you are a prospective GSoC student. Ask questions and discuss the project that you are considering. Community involvement is a key component of coreboot development.<br />
<br />
== During the program ==<br />
* To pass and to be paid by Google requires that you meet certain milestones. <br />
:* First, you must be in good standing with the community before the official start of the program. We expect you to post some design emails to the mailing list, and get feedback on them, both before applying, and during the "community bonding period" between acceptance and official start.<br />
:* You must have made progress and committed significant code before the mid-term point and by the final.<br />
:* We require that accepted students to maintain a blog, where you are expected to write about your project *WEEKLY*. This is a way to measure progress and for the community at large to be able to help you. GSoC is *NOT* a private contract between your mentor and you. [https://blogs.coreboot.org/ blogs.coreboot.org]<br />
* Student must be active in the community on chat.coreboot.org and the mailing list.<br />
* Students are expected to work on development publicly, and to push commits to the project on a regular basis. Depending on the project and what your mentor agrees to, these can be published directly to the project or to a public repository such as gitlab or github. If you are not publishing directly to the project codebase, be aware that we do not want large dumps of code that need to be rushed to meet the mid-term and final goals.<br />
<br />
We don't expect our students to be experts in our problem domain, but we don't want you to fail because some basic misunderstanding was in your way of completing the task.<br />
<br />
= Projects =<br />
<br />
There are many development tasks available in coreboot. Please visit the following pages for some ideas or come up with your own idea. <br />
* [[Project Ideas|coreboot project ideas]]<br />
* [https://www.flashrom.org/GSoC flashrom project ideas]<br />
* [https://serialice.com/GSoC SerialICE project ideas]<br />
<br />
We keep a list of [[previous GSoC Projects]] which might be of interest to you to see what others have accomplished.<br />
Similarly the [https://blogs.coreboot.org/blog/category/gsoc/ blog posts related to previous GSoC projects] might give some insights to what it is like to be a coreboot GSoC student.<br />
<br />
== Your own Project Ideas ==<br />
<br />
We have come up with some ideas for cool Summer of Code projects. These are projects that we think can be managed in the short period of GSoC, and they cover areas where coreboot is trying to reach new users and new use cases.<br />
<br />
Of course your application does not need to be based on any of the ideas listed. The opposite: Maybe you have a great idea that we just didn't think of yet. Please let us know!<br />
<br />
= coreboot Summer of Code Application =<br />
<br />
coreboot welcomes students from all backgrounds and levels of experience. <br />
<br />
Your application should include a complete project proposal. You should document that you have the knowledge and the ability to complete your proposed project. This may require a little research and understanding of coreboot prior to sending your application. The community and coreboot project mentors are your best resource in fleshing out your project ideas and helping with a project timeline. We recommend that you get feedback and recommendations on your proposal before the application deadline.<br />
<br />
Please complete the standard Google SoC application and project proposal. Prospective coreboot GSoC student should provide the following information as part of their application. If you are applying for a flashrom or SerialICE project use common sense when using the template below, this is part of the test. ;)<br />
<br />
=== Personal Information ===<br />
:Name:<br />
:Email:<br />
:Phone number:<br />
:chat/IM/IRC/Skype/other contact:<br />
:Country/Timezone:<br />
:Normal working hours(UTC):<br />
:School:<br />
:Degree Program:<br />
:Expected graduation date:<br />
:Short bio / overview of your background:<br />
:What are your other time commitments? Do you have a job, classes, vacations? When and how long?<br />
<br />
=== Software experience ===<br />
:Github / Web Page / Blog / Microblog / Portfolio:<br />
:Links to one or more patches submitted to the project you're applying for:<br />
:Links to posts on the mailing list with the serial output of your build: [https://www.coreboot.org/pipermail/coreboot/ Mailing List Archives]<br />
:Please comment on your software and firmware experience.<br />
:Have you contributed to an open source project? Which one? What was your experience?<br />
:Did you build and run coreboot? Did you have problems?<br />
<br />
=== Your project ===<br />
: Please provide an overview of your project (in your own words).<br />
:: Provide break down of your project in small specific weekly goals. Think about the potential timeline.<br />
:: How will you accomplish this goal? What is your working style?<br />
:: Explain what risks or potential problems your project might experience.<br />
:: What would you expect as a minimum level of success?<br />
:: Do you have a stretch goal?<br />
<br />
=== Other ===<br />
:Resume (optional):<br />
<br />
== Advice on how to apply ==<br />
* The Drupal project has a great page on [https://www.drupal.org/node/59037 how to write an SOC application].<br />
* GSoC Student Guide: [http://en.flossmanuals.net/GSoCStudentGuide/]<br />
* Secrets for GSoC success: [http://softwareswirl.blogspot.com/2014/03/my-secret-tip-for-gsoc-success.html]<br />
<br />
= Mentors =<br />
<br />
Each accepted project will have a lead mentor and a backup mentor. We will match mentors and students based on the project, experience level, and geographic location (native language, culture and time zone).<br />
<br />
Summer of Code primary mentors, are expected to stay in frequent contact with the student and provide guidance such as code reviews, pointers to useful documentation, etc. This should generally be a time commitment of one to two hours a week.<br />
<br />
Backup mentors are expected to coordinate with the primary mentor and student on a regular basis, and keep track of the student process. They should be work with the primary mentor and be available to take over mentoring duty if the primary mentor is unavailable (vacations, sickness, emergencies).<br />
<br />
== Volunteering to be a mentor ==<br />
<br />
If you'd like to volunteer to be a mentor, please read the [https://developers.google.com/open-source/gsoc/resources/manual#mentor_manual GSoC Mentor Manual]. This will give you a better idea of expectations, and where to go for help.<br />
After that, contact Martin or Patrick and let them know that you're interested.<br />
<br />
The following coreboot developers have volunteered to be GSoC 2017 mentors. Please stop by [https://chat.coreboot.org chat.coreboot.org] and say hi to them and ask them questions.<br />
<br />
{| class="wikitable"<br />
|-<br />
! Name !! Role !! Comms !! AFK / Vacation MMDD-MMDD<br />
|-<br />
| [[User:MartinRoth|Martin Roth]] || coreboot: co-organizer and mentor || chat: martinr Email: gaumless@gmail.com|| No dates yet<br />
|-<br />
| [[User:PatrickGeorgi|Patrick Georgi]] || coreboot: co-organizer and mentor || chat: patrickg, pgeorgi ||<br />
|-<br />
| [[User:Stepan|Stefan Reinauer]] || coreboot/serialice: mentor || chat: stepan ||<br />
|-<br />
| [[User:Rminnich|Ron Minnich]] || coreboot: mentor || chat: rminnich ||<br />
|-<br />
|}</div>MartinRothhttps://www.coreboot.org/index.php?title=Easy_projects&diff=23491Easy projects2017-01-20T20:13:21Z<p>MartinRoth: /* coreboot */</p>
<hr />
<div>You probably came here trying to find a small (minutes to hours) and easy task where you can get your hands dirty and get results immediately.<br />
<br />
If you're a coreboot or flashrom newbie, this page is for you.<br />
<br />
== coreboot ==<br />
<br />
=== Formatting and whitespace cleanup ===<br />
<br />
We try to maintain the code in the [[Development_Guidelines#Coding_Style Linux style]], but occasionally white-space and other formatting issues find their way into the project. Formatting and white-space changes should be done in small groups as a separate patch from code changes. Be careful running indent/lindent. The results are not always the right thing to do and require review.<br />
<br />
Run 'util/lint/lint-007-checkpatch' to see a list of issues that need to be addressed. Note that these should probably be addressed in groups - Handle a group of LEADING_SPACE issues or SPACING issues together.<br />
<br />
=== Adding copyright headers to all files ===<br />
<br />
We want to have copyright headers on all .c, .h, and .asl files (and maybe others as well, but if we had them in all of these files, that would be great.) The list of files that don't have headers can be seen by running the util/lint/lint-000-license-headers script from the coreboot directory. To add a header to the file, you need to verify the origin of the file, so you should run a git log on it. There may also already be information at the top of the file about what kind of license should be used. If the file is original to coreboot, it should get the standard coreboot license header. If it has some other license, the appropriate header should be added.<br />
<br />
Run 'util/lint/lint-000-license-headers' to see a list of files that still need headers.<br />
<br />
== Payloads ==<br />
<br />
coreboot can use a number of different [[Payloads|payloads]].<br />
<br />
=== Add/test new supported payloads ===<br />
<br />
* Test syslinux (probably requires [[SeaBIOS]] in addition, needs to be checked).<br />
<br />
== flashrom ==<br />
<br />
The [http://www.flashrom.org flashrom] tool can read/write coreboot/BIOS images from/to flash chips.<br />
<br />
* See [http://flashrom.org/Easy_projects flashrom's Easy Projects] list for details.<br />
<br />
== Other ==<br />
<br />
* Add [http://tracker.coreboot.org/trac/coreboot/ticket/95 support for using coreboot in VirtualBox].</div>MartinRothhttps://www.coreboot.org/index.php?title=User:MartinRoth&diff=23319User:MartinRoth2017-01-12T21:26:47Z<p>MartinRoth: /* Platforms supported by coreboot */</p>
<hr />
<div>==Martin Roth==<br />
<br />
[[File:Martin.jpg]]<br />
<br />
Email:<br />
:gaumless@gmail.com<br />
:martinroth@google.com<br />
<br />
IRC:<br />
:martinr (usually)<br />
:gaumless (occasionally)<br />
<br />
==Platforms supported by coreboot==<br />
{| class="wikitable"<br />
! Vendor !! Board !! Processor !! Southbridge !! Memory !! Count !! Blob Free !! Used as<br />
|-<br />
| ADI || SG-2220 || Intel Rangeley || || || 1 || No ||<br />
|-<br />
| ADI || SG-2440 || Intel Rangeley || || || 1 || No ||<br />
|-<br />
| AMD || Bettong (DB-FP4) || || || || 1 || No || <br />
|-<br />
| AMD || Kino || AMD Family 10h || || || 1 || ||<br />
|-<br />
| AMD || Lamar || || || || 1 || ||<br />
|-<br />
| AMD || Mahogony || AMD Family F || || || 1 || ||<br />
|-<br />
| AMD || Mahogony || AMD Family 10h || || || 1 || ||<br />
|-<br />
| AMD || Olive Hill || || || || 1 || ||<br />
|-<br />
| AMD || Parmer || AMD Family 15h || || || 2 || ||<br />
|-<br />
| AMD || Pistachio || AMD Family F || || || 1 || ||<br />
|-<br />
| AMD || Persimmon [DB-FT1] || AMD Family 14h || || || 3 || ||<br />
|-<br />
| AMD || Pumori || || || || 1 || ||<br />
|-<br />
| AMD || Thatcher || AMD Family 15h || || || 1 || ||<br />
|-<br />
| AMD || Torpedo || AMD Family 12h || || || 1 || ||<br />
|-<br />
| Asrock || E350M1/USB3 || AMD Family 14h || || || 1 || ||<br />
|-<br />
| Asrock || IMB-A180 || || || || 2 || ||<br />
|-<br />
| ASUS || F2A85-M || || || || 1 || ||<br />
|-<br />
| ASUS || KGPE-D16 || AMD Family 10h / 15h || || || 1 || || Lumberingbuilder<br />
|-<br />
| ASUS || KFSN4-DRE || || || || 1 || ||<br />
|-<br />
| ASUS || P5GC-MX || || || 2 DDR2 UDIMMs || 1 || Yes ||<br />
|-<br />
| Gigabyte || GA-B75M-D3H || Intel Ivybridge || || 4 DDR3 UDIMMs || 1 || No || Happybuilder<br />
|-<br />
| Gigabyte || GA-G41M-ES2L || || || 2 DDR2 UDIMMs || 1 || Yes ||<br />
|-<br />
| Gigabyte || GA-945-GCM-S2L || || || 2 DDR2 UDIMMs || 1 || Yes ||<br />
|-<br />
| Gigabyte || GA-MA78GM || AMD AM2+ socket || AMD SB700 || 4 DDR2 UDIMMs || 1 || ||<br />
|-<br />
| Gizmosphere || Gizmo || AMD Family 14h || || Soldered down || 3 || ||<br />
|-<br />
| Gizmosphere || Gizmo2 || || || Soldered down || 1 || No ||<br />
|-<br />
| Intel || Bakersport || Intel Bay Trail I || || 1 ECC DDR-3 SODIMM || 1 || No ||<br />
|-<br />
| Intel || Bayley Bay || Intel Bay Trail I || || 2 DDR-3 SODIMM || 1 || No ||<br />
|-<br />
| Intel || Camelback Mountain || Broadwell DE || || 2 DDR-4 UDIMMs || 1 || No ||<br />
|-<br />
| Intel || Cougar Canyon || Intel Ivybridge || || || 1 || No ||<br />
|-<br />
| Intel || D510MO || || || || 1 || Yes ||<br />
|-<br />
| Intel || Galileo || || || || 2 || Yes ||<br />
|-<br />
| Intel || Galileo Gen 2 || || || || 1 || Yes ||<br />
|-<br />
| Intel/Circuitco || Minnowboard Max || Intel Bay Trail I || || || 1 || No ||<br />
|-<br />
| Intel/ADI || Minnowboard Turbot || Intel Bay Trail I || || || 1 || No ||<br />
|-<br />
| Intel || Mohon Peak || Intel Rangeley || || || 1 || No ||<br />
|-<br />
| Lenovo || T500 || || || || 1 || Yes ||<br />
|-<br />
| Lenovo || W500 || || || || 1 || Yes ||<br />
|-<br />
| Lenovo || T520 || Intel Sandybridge || || || 1 || No ||<br />
|-<br />
| Lenovo || T530 || Intel Ivybridge || || 2 DDR-3 SODIMMS || 1 || No ||<br />
|-<br />
| Lenovo || W530 || Intel Ivybridge || || 4 DDR-3 SODIMMS || 2 || No || Grumpybuilder<br />
|-<br />
| PC Engines || APU2C4 || || || || 1 || ||<br />
|-<br />
| Supermicro || H8SCM || AMD Family 10h / 15h || AMD SP5100 || 4 DDR3 DIMMs || 1 || ||<br />
|}<br />
<br />
==Links==<br />
===General Hardware & BIOS===<br />
* [http://helppc.netcore2k.net/topics HelpPC - Asm, C, Hardware, Interrupts, Tables for DOS & BIOS]<br />
* [http://www.ctyme.com/rbrown.htm Ralf Brown's Interrupt List]<br />
====_HID & EisaID====<br />
* [http://www-pc.uni-regensburg.de/hardware/TECHNIK/PCI_PNP/pnpid.txt EisaId list]<br />
* [http://download.microsoft.com/download/1/6/1/161ba512-40e2-4cc9-843a-923143f3456c/devids.txt EisaId list from Microsoft]<br />
* [http://lkml.iu.edu/hypermail/linux/kernel/1504.0/04084.html PRP0001 specifically means "Use the 'compatible' property to find the driver for this device"]<br />
<br />
===Payloads===<br />
* [http://www.memtest.org/download/ memtest downloads]<br />
<br />
<br />
==Fedora setup==<br />
Tested on Fedora 20 & 21<br />
sudo yum install git gcc gcc-c++ flex bison ncurses-devel acpica-tools wget patch pciutils-devel<br />
git clone http://review.coreboot.org/coreboot<br />
cd coreboot<br />
git submodule update --init --checkout<br />
make crossgcc-i386<br />
<br />
Optional installs:<br />
sudo yum install ccache clang<br />
<br />
<br />
===Flashing 3MB of 8MB ROM on minnowboard max===<br />
echo 00500000:007fffff cb-region > 8mb ; flashrom -p dediprog:voltage=1.8v -l 8mb -i cb-region -w build/coreboot.rom<br />
<br />
<br />
=== Coreboot lessons ===<br />
[[Lesson1]] - Starting from scratch. Download coreboot, build it, and test the image on QEMU.</div>MartinRothhttps://www.coreboot.org/index.php?title=Coreboot_conference_San_Francisco_2016&diff=23190Coreboot conference San Francisco 20162017-01-05T21:27:33Z<p>MartinRoth: /* Monday: */</p>
<hr />
<div>==Presentations from the 2016 coreboot conference in San Francisco, CA, USA==<br />
===Monday:===<br />
* Apollolake implementation: Andrey Petrov ([https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf slides] )<br />
* [https://youtu.be/4EvTcfcYfMY Verified Boot: Surviving in the Internet of Insecure Things: Randall Spangler] ( [https://www.coreboot.org/images/c/ce/Verified_Boot_-_Surviving_in_the_Internet_of_Insecure_Things.pdf slides] )<br />
* [https://youtu.be/CDNIWuf1jAk coreboot on RISC-V: Ron Minnich]<br />
* [https://youtu.be/hQb8waUBVSQ An Open Source Embedded Controller: Bill Richardson] ( [https://www.coreboot.org/images/5/50/An_Open_Source_EC.pdf slides] )<br />
* [https://youtu.be/B708jdCiW7o KB9012 EC Firmware Reverse Engineering: Paul Kocialkowski]<br />
* [https://youtu.be/_Aex9RwgHHQ Towards (reasonably) trustworthy x86 laptops: Joanna Rutkowska]<br />
<br />
===Tuesday:===<br />
* [https://youtu.be/Bhwd5i6pGfg Talos, Openpower, and the World Beyond X86: Timothy Pearson] ( [https://www.coreboot.org/images/d/de/The_World_Beyond_X86.pdf slides] )<br />
* [https://youtu.be/I08NHJLu6Us EDK-II & CorebootPayloadPackage: Lee Leahy & Vincent Zimmer]<br />
* [https://youtu.be/z-KpAA4_afs coreboot on ARM: Julius Werner]<br />
* [https://youtu.be/uvoEAkfhXNY Proposal for Improving Firmware Security in the Industry: Jan Monsch]<br />
* [https://youtu.be/f0ykeMmqglI RISC-V (Instruction Sets Want to be Free!): Andrew Waterman]<br />
* [https://youtu.be/uzfiTiP9dEM Intel FSP v2.0 Overview: Giri Mudusuru, Vincent Zimmer]<br />
* [https://youtu.be/7YUXr1MH9d4 coreboot Internals: Aaron Durbin]<br />
===Wednesday:===<br />
* [https://youtu.be/SpL8LbquSVs Skylake FSP to coreboot integration overview: Robbie Zhang]<br />
* [https://youtu.be/GfwTijFnFl0 S3 implementation of Braswell: Hannah Williams]<br />
<br />
==Date and time==<br />
The date of the coreboot conference was '''Monday, June 13 to Thursday June 16, 2016'''.<br />
<br />
[https://goo.gl/WF9al6 The official schedule]<br />
<br />
==Conference location==<br />
This conference was hosted by the coreboot project and held in San Francisco, CA, USA at the Google office at [https://goo.gl/maps/hAoF9uYhbNK2 345 Spear St]. Google has been a significant contributor to the coreboot project, and several key members of the community work for Google. Google's chromebooks and chromeboxes use coreboot as a significant piece of their verified boot security model.<br />
<br />
[[Category:Meetings]]</div>MartinRoth