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coreboot - User contributions [en]
2024-03-28T20:22:46Z
User contributions
MediaWiki 1.40.0
https://www.coreboot.org/index.php?title=Download_coreboot&diff=11065
Download coreboot
2012-04-12T18:32:48Z
<p>Uwe: </p>
<hr />
<div>__NOTOC__<br />
'''Note: These snapshots are for people, who use Linux as operating system and are able to build software from the source code.''' <br />
<br />
There is no ''easy to install package'' for people who want to quickly try out a new BIOS on their computer, yet. However, we provide some images for the [[QEMU]] emulator to test coreboot (and some [[Payloads|payloads]]) on your Linux, Mac OS X, and Windows computers (without having to do any hardware changes). But please note that these images can '''not''' be used on any mainboard, they will only work in [[QEMU]]!<br />
<br />
== Snapshots ==<br />
<br />
There is an archive of coreboot snapshots available at [http://qa.coreboot.org/ qa.coreboot.org]. A new tar.bz2 file is created whenever the repository changes.<br />
<br />
= Git =<br />
<br />
coreboot has switched to using Git for version control. Please see the [[Git]] page for much useful information on how to work with Git and gerrit in coreboot.<br />
<br />
Old subversion repository references that still apply will continue to be kept here.<br />
<br />
== Git clone ==<br />
<br />
coreboot keeps its development tree in a [http://git-scm.com/ Git] repository.<br />
<br />
=== Anonymous access ===<br />
<br />
To clone the coreboot repository (ca. 120 MB data as of 04/2012):<br />
<br />
$ git clone http://review.coreboot.org/p/coreboot<br />
<br />
If you want the <span style="color: #ff0000">obsolete, unsupported, and experimental</span> '''coreboot v3''' tree (ca. 18 MB data as of 11/2009):<br />
<br />
$ svn co svn://coreboot.org/repository/coreboot-v3<br />
<br />
If you want the '''old, unmaintained and unsupported coreboot v1''' tree (ca. 47 MB data as of 10/2008):<br />
<br />
$ svn co svn://coreboot.org/coreboot/branches/coreboot-v1<br />
<br />
=== Developer access with write permission ===<br />
<br />
Please see our wiki page about [[Git]] for all the details.<br />
<br />
== Source code browsing ==<br />
<br />
You can browse the coreboot Git repository online using [http://review.coreboot.org/gitweb?p=coreboot.git gitweb] including its [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree tree view] for accessing the files.<br />
<br />
== Repositories on coreboot.org ==<br />
<br />
'''coreboot current Git tree:'''<br />
* <nowiki>http://review.coreboot.org/p/coreboot</nowiki><br />
<br />
'''coreboot v1 (obsolete):'''<br />
* svn://coreboot.org/coreboot/branches/coreboot-v1<br />
* <nowiki>https://svn.coreboot.org/coreboot/branches/coreboot-v1</nowiki><br />
<br />
'''coreboot v3 (obsolete):'''<br />
* svn://coreboot.org/repository/coreboot-v3<br />
* <nowiki>https://svn.coreboot.org/repository/coreboot-v3</nowiki><br />
<br />
'''[[FILO]]:'''<br />
* svn://coreboot.org/filo/<br />
* <nowiki>https://svn.coreboot.org/filo/</nowiki><br />
<br />
'''[[Buildrom]]:'''<br />
* svn://coreboot.org/buildrom/<br />
* <nowiki>https://svn.coreboot.org/buildrom/</nowiki><br />
<br />
'''[[Distributed and Automated Testsystem]]:'''<br />
* svn://coreboot.org/testsystem<br />
* <nowiki>https://svn.coreboot.org/testsystem/</nowiki></div>
Uwe
https://www.coreboot.org/index.php?title=Coreboot_Options&diff=10903
Coreboot Options
2011-10-13T22:46:45Z
<p>Uwe: Update.</p>
<hr />
<div>This is an automatically generated list of '''coreboot compile-time options'''.<br />
<br />
Last update: 2011/10/14 00:44:39. (runknown)<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Option<br />
! align="left" | Source<br />
! align="left" | Format<br />
! align="left" | Short&nbsp;Description<br />
! align="left" | Description<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: General setup || || || ||<br />
|- bgcolor="#eeeeee"<br />
| EXPERT || toplevel || bool || Expert mode || <br />
This allows you to select certain advanced configuration options.<br />
<br />
Warning: Only enable this option if you really know what you are<br />
doing! You have been warned!<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| LOCALVERSION || toplevel || string || Local version string || <br />
Append an extra string to the end of the coreboot version.<br />
<br />
This can be useful if, for instance, you want to append the<br />
respective board's hostname or some other identifying string to<br />
the coreboot version number, so that you can easily distinguish<br />
boot logs of different boards from each other.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CBFS_PREFIX || toplevel || string || CBFS prefix to use || <br />
Select the prefix to all files put into the image. It's "fallback"<br />
by default, "normal" is a common alternative.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CBFS_PREFIX || toplevel || string || Compiler || <br />
This option allows you to select the compiler used for building<br />
coreboot.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SCANBUILD_ENABLE || toplevel || bool || Build with scan-build for static analysis || <br />
Changes the build process to scan-build is used.<br />
Requires scan-build in path.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SCANBUILD_REPORT_LOCATION || toplevel || string || Directory to put scan-build report in || <br />
Where the scan-build report should be stored<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CCACHE || toplevel || bool || ccache || <br />
Enables the use of ccache for faster builds.<br />
Requires ccache in path.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison || <br />
Enable this option if you are working on the sconfig<br />
device tree parser and made changes to sconfig.l and<br />
sconfig.y.<br />
Otherwise, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values || <br />
Enable this option if coreboot shall read options from the "CMOS"<br />
NVRAM instead of using hard coded values.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COMPRESS_RAMSTAGE || toplevel || bool || Compress ramstage with LZMA || <br />
Compress ramstage to save memory in the flash image. Note<br />
that decompression might slow down booting if the boot flash<br />
is connected through a slow Link (i.e. SPI)<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot config file into the ROM image || <br />
Include in CBFS the coreboot config file that was used to compile the ROM image<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Mainboard || || || ||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_LENOVO_X60 || mainboard/lenovo || bool || ThinkPad X60 / X60s || <br />
The following X60 series ThinkPad machines have been verified to<br />
work correctly:<br />
<br />
ThinkPad X60s (Model 1702, 1703)<br />
ThinkPad X60 (Model 1709)<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_LENOVO_T60 || mainboard/lenovo || bool || ThinkPad T60 / T60p || <br />
The following T60 series ThinkPad machines have been verified to<br />
work correctly:<br />
<br />
Thinkpad T60p (Model 2007)<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision || <br />
Look on the bottom side for a number like 406-0001-30. The last 2<br />
digits state the PCB revision (3.0 in this example). For 2.0 or older<br />
boards choose Y, for 3.0 and newer say N.<br />
<br />
Old revision boards need a jumper shorting the power button to<br />
power on automatically. You may enable the button only after this<br />
jumper has been removed. New revision boards are not restricted<br />
in this way, and always have the power button enabled.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 || <br />
If selected, both on-board serial ports will operate in RS485 mode<br />
instead of RS232.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 &amp; 2 to RS485 || <br />
If selected, the first two on-board serial ports will operate in RS485<br />
mode instead of RS232.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave || <br />
If selected, the on-board Compact Flash card socket will act as IDE<br />
Slave instead of Master.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 || <br />
If selected, both on-board serial ports will operate in RS485 mode<br />
instead of RS232.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 || <br />
If selected, both on-board serial ports will operate in RS485 mode<br />
instead of RS232.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave || <br />
If selected, the on-board SSD will act as IDE Slave instead of Master.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SIO_PORT || mainboard/supermicro/h8qgi || hex || || <br />
though UARTs are on the NUVOTON BMC, port 0x164E<br />
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_ROMSIZE_KB_16384 || mainboard || bool || ROM chip size || <br />
Select the size of the ROM chip you intend to flash coreboot on.<br />
<br />
The build system will take care of creating a coreboot.rom file<br />
of the matching size.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB || <br />
Choose this option if you have a 128 KB ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB || <br />
Choose this option if you have a 256 KB ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB || <br />
Choose this option if you have a 512 KB ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) || <br />
Choose this option if you have a 1024 KB (1 MB) ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) || <br />
Choose this option if you have a 2048 KB (2 MB) ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) || <br />
Choose this option if you have a 4096 KB (4 MB) ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) || <br />
Choose this option if you have a 8192 KB (8 MB) ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) || <br />
Choose this option if you have a 16384 KB (16 MB) ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button || <br />
The selected mainboard can optionally have the power button tied<br />
to ground with a jumper so that the button appears to be<br />
constantly depressed. If this option is enabled and the jumper is<br />
installed then the board will turn on, but turn off again after a<br />
short timeout, usually 4 seconds.<br />
<br />
Select Y here if you have removed the jumper and want to use an<br />
actual power button. Select N if you have the jumper installed.<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Architecture (x86) || || || ||<br />
|- bgcolor="#eeeeee"<br />
| UPDATE_IMAGE || arch/x86 || bool || Update existing coreboot.rom image || <br />
If this option is enabled, no new coreboot.rom file<br />
is created. Instead it is expected that there already<br />
is a suitable file for further processing.<br />
The bootblock will not be modified.<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Chipset || || || ||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || CPU ||<br />
|- bgcolor="#eeeeee"<br />
| UPDATE_CPU_MICROCODE || cpu/amd/model_10xxx || bool || Update CPU microcode || <br />
Select this to apply patches to the CPU microcode provided by<br />
AMD without source, and distributed with coreboot, to address<br />
issues in the CPU post production.<br />
<br />
Microcode updates distributed with coreboot are not necessarily<br />
the latest version available from AMD. Updates are only applied<br />
if they are newer than the microcode already in your CPU.<br />
<br />
Unselect this to let Fam10h CPUs run with microcode as shipped<br />
from factory. No binary microcode patches will be included in the<br />
coreboot image in that case, which can help with creating an image<br />
for which complete source code is available, which in turn might<br />
simplify license compliance.<br />
<br />
Microcode updates intend to solve issues that have been discovered<br />
after CPU production. The common case is that systems work as<br />
intended with updated microcode, but we have also seen cases where<br />
issues were solved by not applying the microcode updates.<br />
<br />
Note that some operating system include these same microcode<br />
patches, so you may need to also disable microcode updates in<br />
your operating system in order for this option to matter.<br />
<br />
||<br />
||<br />
|- bgcolor="#eeeeee"<br />
| GEODE_VSA_FILE || cpu/amd/model_gx2 || bool || Add a VSA image || <br />
Select this option if you have an AMD Geode GX2 vsa that you would<br />
like to add to your ROM.<br />
<br />
You will be able to specify the location and file name of the<br />
image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VSA_FILENAME || cpu/amd/model_gx2 || string || AMD Geode GX2 VSA path and filename || <br />
The path and filename of the file to use as VSA.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| GEODE_VSA_FILE || cpu/amd/model_lx || bool || Add a VSA image || <br />
Select this option if you have an AMD Geode LX vsa that you would<br />
like to add to your ROM.<br />
<br />
You will be able to specify the location and file name of the<br />
image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VSA_FILENAME || cpu/amd/model_lx || string || AMD Geode LX VSA path and filename || <br />
The path and filename of the file to use as VSA.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family10 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console || <br />
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.<br />
<br />
Warning: Only enable this option when debuging or tracing AMD AGESA code.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SMP || cpu || bool || || <br />
This option is used to enable certain functions to make coreboot<br />
work correctly on symmetric multi processor (SMP) systems.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MMX || cpu || bool || || <br />
Select MMX in your socket or model Kconfig if your CPU has MMX<br />
streaming SIMD instructions. ROMCC can build more efficient<br />
code if it can spill to MMX registers.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SSE || cpu || bool || || <br />
Select SSE in your socket or model Kconfig if your CPU has SSE<br />
streaming SIMD instructions. ROMCC can build more efficient<br />
code if it can spill to SSE (aka XMM) registers.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SSE2 || cpu || bool || || <br />
Select SSE2 in your socket or model Kconfig if your CPU has SSE2<br />
streaming SIMD instructions. Some parts of coreboot can be built<br />
with more efficient code if SSE2 instructions are available.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VAR_MTRR_HOLE || cpu || bool || || <br />
Unset this if you don't want the MTRR code to use<br />
subtractive MTRRs<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || Northbridge ||<br />
|- bgcolor="#eeeeee"<br />
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || || <br />
Select this for boards with a Voltage Regulator able to operate<br />
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.<br />
<br />
||<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: HyperTransport setup || || || ||<br />
|- bgcolor="#eeeeee"<br />
| None || northbridge/amd || None || HyperTransport frequency || <br />
This option sets the maximum permissible HyperTransport link<br />
frequency.<br />
<br />
Use of this option will only limit the autodetected HT frequency.<br />
It will not (and cannot) increase the frequency beyond the<br />
autodetected limits.<br />
<br />
This is primarily used to work around poorly designed or laid out<br />
HT traces on certain motherboards.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| LIMIT_HT_SPEED_AUTO || northbridge/amd || bool || HyperTransport downlink width || <br />
This option sets the maximum permissible HyperTransport<br />
downlink width.<br />
<br />
Use of this option will only limit the autodetected HT width.<br />
It will not (and cannot) increase the width beyond the autodetected<br />
limits.<br />
<br />
This is primarily used to work around poorly designed or laid out HT<br />
traces on certain motherboards.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd || bool || HyperTransport uplink width || <br />
This option sets the maximum permissible HyperTransport<br />
uplink width.<br />
<br />
Use of this option will only limit the autodetected HT width.<br />
It will not (and cannot) increase the width beyond the autodetected<br />
limits.<br />
<br />
This is primarily used to work around poorly designed or laid out HT<br />
traces on certain motherboards.<br />
<br />
||<br />
<br />
|- bgcolor="#eeeeee"<br />
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool || || <br />
This option affects how the SDRAMC register is programmed.<br />
Memory clock signals will not be routed properly if this option<br />
is set wrong.<br />
<br />
If your board has 4 DIMM slots, you must use select this option, in<br />
your Kconfig file of the board. On boards with 3 DIMM slots,<br />
do _not_ select this option.<br />
<br />
<br />
||<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || || <br />
Usually system firmware turns off system memory clock<br />
signals to unused SO-DIMM slots to reduce EMI and power<br />
consumption.<br />
However, some boards do not like unused clock signals to<br />
be disabled.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || || <br />
If non-zero, this designates the maximum DDR frequency<br />
the board supports, despite what the chipset should be<br />
capable of.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || Southbridge ||<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: AMD Geode GX1 video support || || || ||<br />
<br />
|- bgcolor="#eeeeee"<br />
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || || <br />
Select if RS690 should be setup to support MMCONF.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| USBDEBUG_DEFAULT_PORT || southbridge/amd/sb600 || int || SATA Mode || <br />
Select the mode in which SATA should be driven. IDE or AHCI.<br />
The default is IDE.<br />
<br />
config SATA_MODE_IDE<br />
bool "IDE"<br />
<br />
config SATA_MODE_AHCI<br />
bool "AHCI"<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode || <br />
If Combined Mode is enabled. IDE controller is exposed and<br />
SATA controller has control over Port0 through Port3,<br />
IDE controller has control over Port4 and Port5.<br />
<br />
If Combined Mode is disabled, IDE controller is hidden and<br />
SATA controller has full control of all 6 Ports when operating in non-IDE mode.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode || <br />
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.<br />
The default is NATIVE.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE || <br />
NATIVE is the default mode and does not require a ROM.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI || <br />
AHCI may work with or without AHCI ROM. It depends on the payload support.<br />
For example, seabios does not require the AHCI ROM.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID || <br />
sb800 RAID mode must have the two required ROM files.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs || <br />
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position || <br />
The RAID ROM requires that the MISC ROM is located between the range<br />
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.<br />
The CONFIG_ROM_SIZE must larger than 0x100000.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex || || <br />
0x0 = Native IDE mode.<br />
0x1 = RAID mode.<br />
0x2 = AHCI mode.<br />
0x3 = Legacy IDE mode.<br />
0x4 = IDE-&gt;AHCI mode.<br />
0x5 = AHCI mode as 7804 ID (AMD driver).<br />
0x6 = IDE-&gt;AHCI mode as 7804 ID (AMD driver).<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool || || <br />
n = Disable PCI Bridge Device 14 Function 4.<br />
y = Enable PCI Bridge Device 14 Function 4.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex || || <br />
Set SCI IRQ to 9.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary || <br />
Select this option to add a CMC state machine binary to<br />
the resulting coreboot image.<br />
<br />
Note: Without this binary coreboot will not work<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename || <br />
The path and filename of the file to use as CMC state machine<br />
binary.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || Super I/O ||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || Devices ||<br />
|- bgcolor="#eeeeee"<br />
| VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter || <br />
Allow bridges to set up legacy decoding ranges for VGA. Don't disable<br />
this unless you're sure you don't want the briges setup for VGA.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VGA_ROM_RUN || devices || bool || Run VGA option ROMs || <br />
Execute VGA option ROMs, if found. This is required to enable<br />
PCI/AGP/PCI-E video cards.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs || <br />
Execute non-VGA PCI option ROMs, if found.<br />
<br />
Examples include IDE/SATA controller option ROMs and option ROMs<br />
for network cards (NICs).<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Native mode || <br />
If you select this option, PCI option ROMs will be executed<br />
natively on the CPU in real mode. No CPU emulation is involved,<br />
so this is the fastest, but also the least secure option.<br />
(only works on x86/x64 systems)<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PCI_OPTION_ROM_RUN_YABEL || devices || bool || Secure mode || <br />
If you select this option, the x86emu CPU emulator will be used to<br />
execute PCI option ROMs.<br />
<br />
This option prevents option ROMs from doing dirty tricks with the<br />
system (such as installing SMM modules or hypervisors), but it is<br />
also significantly slower than the native option ROM initialization<br />
method.<br />
<br />
This is the default choice for non-x86 systems.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| YABEL_PCI_ACCESS_OTHER_DEVICES || devices || bool || Allow option ROMs to access other devices || <br />
Per default, YABEL only allows option ROMs to access the PCI device<br />
that they are associated with. However, this causes trouble for some<br />
onboard graphics chips whose option ROM needs to reconfigure the<br />
north bridge.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| YABEL_VIRTMEM_LOCATION || devices || hex || Location of YABEL's virtual memory || <br />
YABEL requires 1MB memory for its CPU emulation. This memory is<br />
normally located at 16MB.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| YABEL_DIRECTHW || devices || bool || Direct hardware access || <br />
YABEL consists of two parts: It uses x86emu for the CPU emulation and<br />
additionally provides a PC system emulation that filters bad device<br />
and memory access (such as PCI config space access to other devices<br />
than the initialized one).<br />
<br />
When choosing this option, x86emu will pass through all hardware<br />
accesses to memory and I/O devices to the underlying memory and I/O<br />
addresses. While this option prevents option ROMs from doing dirty<br />
tricks with the CPU (such as installing SMM modules or hypervisors),<br />
they can still access all devices in the system.<br />
Enable this option for a good compromise between security and speed.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || Embedded Controllers ||<br />
|- bgcolor="#eeeeee"<br />
| EC_ACPI || ec/acpi || bool || || <br />
ACPI Embedded Controller interface. Mostly found in laptops.<br />
<br />
||<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Generic Drivers || || || ||<br />
|- bgcolor="#eeeeee"<br />
| DRIVERS_OXFORD_OXPCIE || drivers/oxford/oxpcie || bool || Oxford OXPCIe952 || <br />
Support for Oxford OXPCIe952 serial port PCIe cards.<br />
Currently only devices with the vendor ID 0x1415 and device ID<br />
0xc158 will work.<br />
NOTE: Right now you have to set the base address of your OXPCIe952<br />
card to exactly the value that the device allocator would set them<br />
later on, or serial console functionality will stop as soon as the<br />
resource allocator assigns a new base address to the device.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OXFORD_OXPCIE_BRIDGE_BUS || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge bus number || <br />
While coreboot is executing code from ROM, the coreboot resource<br />
allocator has not been running yet. Hence PCI devices living behind<br />
a bridge are not yet visible to the system. In order to use an<br />
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge<br />
that controls the OXPCIe952 controller first.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OXFORD_OXPCIE_BRIDGE_DEVICE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge device number || <br />
While coreboot is executing code from ROM, the coreboot resource<br />
allocator has not been running yet. Hence PCI devices living behind<br />
a bridge are not yet visible to the system. In order to use an<br />
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge<br />
that controls the OXPCIe952 controller first.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OXFORD_OXPCIE_BRIDGE_FUNCTION || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge function number || <br />
While coreboot is executing code from ROM, the coreboot resource<br />
allocator has not been running yet. Hence PCI devices living behind<br />
a bridge are not yet visible to the system. In order to use an<br />
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge<br />
that controls the OXPCIe952 controller first.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OXFORD_OXPCIE_BRIDGE_SUBORDINATE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge subordinate bus || <br />
While coreboot is executing code from ROM, the coreboot resource<br />
allocator has not been running yet. Hence PCI devices living behind<br />
a bridge are not yet visible to the system. In order to use an<br />
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge<br />
that controls the OXPCIe952 controller first.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OXFORD_OXPCIE_BASE_ADDRESS || drivers/oxford/oxpcie || hex || Base address for rom stage console || <br />
While coreboot is executing code from ROM, the coreboot resource<br />
allocator has not been running yet. Hence PCI devices living behind<br />
a bridge are not yet visible to the system. In order to use an<br />
OXPCIe952 based PCIe card, coreboot has to set up a temporary address<br />
for the OXPCIe952 controller.<br />
<br />
<br />
||<br />
<br />
||<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DRIVERS_SIL_3114 || drivers/sil || bool || Silicon Image SIL3114 || <br />
It sets PCI class to IDE compatible native mode, allowing<br />
SeaBIOS, FILO etc... to boot from it.<br />
<br />
<br />
<br />
||<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Console || || || ||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL8250 || console || bool || Serial port console output || <br />
Send coreboot debug output to an I/O mapped serial port console.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL8250MEM || console || bool || Serial port console output (memory mapped) || <br />
Send coreboot debug output to a memory mapped serial port console.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 || <br />
Serial console on COM1/ttyS0 at I/O port 0x3f8.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 || <br />
Serial console on COM2/ttyS1 at I/O port 0x2f8.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 || <br />
Serial console on COM3/ttyS2 at I/O port 0x3e8.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 || <br />
Serial console on COM4/ttyS3 at I/O port 0x2e8.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| TTYS0_BASE || console || hex || || <br />
Map the COM port names to the respective I/O port.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_115200 || console || bool || 115200 || <br />
Set serial port Baud rate to 115200.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_57600 || console || bool || 57600 || <br />
Set serial port Baud rate to 57600.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_38400 || console || bool || 38400 || <br />
Set serial port Baud rate to 38400.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_19200 || console || bool || 19200 || <br />
Set serial port Baud rate to 19200.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_9600 || console || bool || 9600 || <br />
Set serial port Baud rate to 9600.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| TTYS0_BAUD || console || int || || <br />
Map the Baud rates to an integer.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| USBDEBUG || console || bool || USB 2.0 EHCI debug dongle support || <br />
This option allows you to use a so-called USB EHCI Debug device<br />
(such as the Ajays NET20DC, AMIDebug RX, or a system using the<br />
Linux "EHCI Debug Device gadget" driver found in recent kernel)<br />
to retrieve the coreboot debug messages (instead, or in addition<br />
to, a serial port).<br />
<br />
This feature is NOT supported on all chipsets in coreboot!<br />
<br />
It also requires a USB2 controller which supports the EHCI<br />
Debug Port capability.<br />
<br />
See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list<br />
of supported controllers.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| USBDEBUG_DEFAULT_PORT || console || int || Default USB port to use as Debug Port || <br />
This option selects which physical USB port coreboot will try to<br />
use as EHCI Debug Port first (valid values are: 1-15).<br />
<br />
If coreboot doesn't detect an EHCI Debug Port dongle on this port,<br />
it will try all the other ports one after the other. This will take<br />
a few seconds of time though, and thus slow down the booting process.<br />
<br />
Hence, if you select the correct port here, you can speed up<br />
your boot time. Which USB port number (1-15) refers to which<br />
actual port on your mainboard (potentially also USB pin headers<br />
on your mainboard) is highly board-specific, and you'll likely<br />
have to find out by trial-and-error.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_VGA_IS_PRIMARY || console || bool || Use onboard VGA as primary video device || <br />
If not selected, the last adapter found will be used.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_NE2K || console || bool || Network console over NE2000 compatible Ethernet adapter || <br />
Send coreboot debug output to a Ethernet console, it works<br />
same way as Linux netconsole, packets are received to UDP<br />
port 6666 on IP/MAC specified with options bellow.<br />
Use following netcat command: nc -u -l -p 6666<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_NE2K_DST_MAC || console || string || Destination MAC address of remote system || <br />
Type in either MAC address of logging system or MAC address<br />
of the router.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system || <br />
This is IP adress of the system running for example<br />
netcat command to dump the packets.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_NE2K_SRC_IP || console || string || IP address of coreboot system || <br />
This is the IP of the coreboot system<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_NE2K_IO_PORT || console || hex || NE2000 adapter fixed IO port address || <br />
This is the IO port address for the IO port<br />
on the card, please select some non-conflicting region,<br />
32 bytes of IO spaces will be used (and align on 32 bytes<br />
boundary, qemu needs broader align)<br />
<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW || <br />
Way too many details.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG || <br />
Debug-level messages.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO || <br />
Informational messages.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE || <br />
Normal but significant conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING || <br />
Warning conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR || <br />
Error conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT || <br />
Critical conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT || <br />
Action must be taken immediately.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG || <br />
System is unusable.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL || console || int || || <br />
Map the log level config names to an integer.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW || <br />
Way too many details.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG || <br />
Debug-level messages.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO || <br />
Informational messages.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE || <br />
Normal but significant conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING || <br />
Warning conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR || <br />
Error conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT || <br />
Critical conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT || <br />
Action must be taken immediately.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG || <br />
System is unusable.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL || console || int || || <br />
Map the log level config names to an integer.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_POST || console || bool || Show POST codes on the debug console || <br />
If enabled, coreboot will additionally print POST codes (which are<br />
usually displayed using a so-called "POST card" ISA/PCI/PCI-E<br />
device) on the debug console.<br />
<br />
||<br />
<br />
|- bgcolor="#eeeeee"<br />
| HAVE_HARD_RESET || toplevel || bool || || <br />
This variable specifies whether a given board has a hard_reset<br />
function, no matter if it's provided by board code or chipset code.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_OPTION_TABLE || toplevel || bool || || <br />
This variable specifies whether a given board has a cmos.layout<br />
file containing NVRAM/CMOS bit definitions.<br />
It defaults to 'n' but can be selected in mainboard/*/Kconfig.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VGA || toplevel || bool || || <br />
Build board-specific VGA code.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| GFXUMA || toplevel || bool || || <br />
Enable Unified Memory Architecture for graphics.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_ACPI_TABLES || toplevel || bool || || <br />
This variable specifies whether a given board has ACPI table support.<br />
It is usually set in mainboard/*/Kconfig.<br />
Whether or not the ACPI tables are actually generated by coreboot<br />
is configurable by the user via GENERATE_ACPI_TABLES.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_MP_TABLE || toplevel || bool || || <br />
This variable specifies whether a given board has MP table support.<br />
It is usually set in mainboard/*/Kconfig.<br />
Whether or not the MP table is actually generated by coreboot<br />
is configurable by the user via GENERATE_MP_TABLE.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_PIRQ_TABLE || toplevel || bool || || <br />
This variable specifies whether a given board has PIRQ table support.<br />
It is usually set in mainboard/*/Kconfig.<br />
Whether or not the PIRQ table is actually generated by coreboot<br />
is configurable by the user via GENERATE_PIRQ_TABLE.<br />
<br />
||<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: System tables || || || ||<br />
|- bgcolor="#eeeeee"<br />
| GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables || <br />
Generate ACPI tables for this board.<br />
<br />
If unsure, say Y.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table || <br />
Generate an MP table (conforming to the Intel MultiProcessor<br />
specification 1.4) for this board.<br />
<br />
If unsure, say Y.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table || <br />
Generate a PIRQ table for this board.<br />
<br />
If unsure, say Y.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| GENERATE_SMBIOS_TABLES || toplevel || bool || Generate SMBIOS tables || <br />
Generate SMBIOS tables for this board.<br />
<br />
If unsure, say Y.<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Payload || || || ||<br />
|- bgcolor="#eeeeee"<br />
| PAYLOAD_NONE || toplevel || bool || None || <br />
Select this option if you want to create an "empty" coreboot<br />
ROM image for a certain mainboard, i.e. a coreboot ROM image<br />
which does not yet contain a payload.<br />
<br />
For such an image to be useful, you have to use 'cbfstool'<br />
to add a payload to the ROM image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PAYLOAD_ELF || toplevel || bool || An ELF executable payload || <br />
Select this option if you have a payload image (an ELF file)<br />
which coreboot should run as soon as the basic hardware<br />
initialization is completed.<br />
<br />
You will be able to specify the location and file name of the<br />
payload image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PAYLOAD_SEABIOS || toplevel || bool || SeaBIOS || <br />
Select this option if you want to build a coreboot image<br />
with a SeaBIOS payload. If you don't know what this is<br />
about, just leave it enabled.<br />
<br />
See http://coreboot.org/Payloads for more information.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PAYLOAD_FILO || toplevel || bool || FILO || <br />
Select this option if you want to build a coreboot image<br />
with a FILO payload. If you don't know what this is<br />
about, just leave it enabled.<br />
<br />
See http://coreboot.org/Payloads for more information.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SEABIOS_STABLE || toplevel || bool || stable || <br />
Stable SeaBIOS version<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SEABIOS_MASTER || toplevel || bool || master || <br />
Newest SeaBIOS version<br />
||<br />
|- bgcolor="#eeeeee"<br />
| FILO_STABLE || toplevel || bool || 0.6.0 || <br />
Stable FILO version<br />
||<br />
|- bgcolor="#eeeeee"<br />
| FILO_MASTER || toplevel || bool || HEAD || <br />
Newest FILO version<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PAYLOAD_FILE || toplevel || string || Payload path and filename || <br />
The path and filename of the ELF executable file to use as payload.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads || <br />
In order to reduce the size payloads take up in the ROM chip<br />
coreboot can compress them using the LZMA algorithm.<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: VGA BIOS || || || ||<br />
|- bgcolor="#eeeeee"<br />
| VGA_BIOS || toplevel || bool || Add a VGA BIOS image || <br />
Select this option if you have a VGA BIOS image that you would<br />
like to add to your ROM.<br />
<br />
You will be able to specify the location and file name of the<br />
image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename || <br />
The path and filename of the file to use as VGA BIOS.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VGA_BIOS_ID || toplevel || string || VGA device PCI IDs || <br />
The comma-separated PCI vendor and device ID that would associate<br />
your VGA BIOS to your video card.<br />
<br />
Example: 1106,3230<br />
<br />
In the above example 1106 is the PCI vendor ID (in hex, but without<br />
the "0x" prefix) and 3230 specifies the PCI device ID of the<br />
video card (also in hex, without "0x" prefix).<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| INTEL_MBI || toplevel || bool || Add an MBI image || <br />
Select this option if you have an Intel MBI image that you would<br />
like to add to your ROM.<br />
<br />
You will be able to specify the location and file name of the<br />
image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MBI_FILE || toplevel || string || Intel MBI path and filename || <br />
The path and filename of the file to use as VGA BIOS.<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Display || || || ||<br />
|- bgcolor="#eeeeee"<br />
| FRAMEBUFFER_SET_VESA_MODE || toplevel || bool || Set VESA framebuffer mode || <br />
Set VESA framebuffer mode (needed for bootsplash)<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| FRAMEBUFFER_VESA_MODE || toplevel || hex || VESA framebuffer video mode || <br />
This option sets the resolution used for the coreboot framebuffer (and<br />
bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will<br />
some day make this a "choice".<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| FRAMEBUFFER_KEEP_VESA_MODE || toplevel || bool || Keep VESA framebuffer || <br />
This option keeps the framebuffer mode set after coreboot finishes<br />
execution. If this option is enabled, coreboot will pass a<br />
framebuffer entry in its coreboot table and the payload will need a<br />
framebuffer driver. If this option is disabled, coreboot will switch<br />
back to text mode before handing control to a payload.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| BOOTSPLASH || toplevel || bool || Show graphical bootsplash || <br />
This option shows a graphical bootsplash screen. The grapics are<br />
loaded from the CBFS file bootsplash.jpg.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename || <br />
The path and filename of the file to use as graphical bootsplash<br />
screen. The file format has to be jpg.<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Debugging || || || ||<br />
|- bgcolor="#eeeeee"<br />
| GDB_STUB || toplevel || bool || GDB debugging support || <br />
If enabled, you will be able to set breakpoints for gdb debugging.<br />
See src/arch/x86/lib/c_start.S for details.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages || <br />
This option enables additional RAM init related debug messages.<br />
It is recommended to enable this when debugging issues on your<br />
board which might be RAM init related.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_CAR || toplevel || bool || Output verbose Cache-as-RAM debug messages || <br />
This option enables additional CAR related debug messages.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_PIRQ || toplevel || bool || Check PIRQ table consistency || <br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages || <br />
This option enables additional SMBus (and SPD) debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages || <br />
This option enables additional SMI related debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_SMM_RELOCATION || toplevel || bool || Debug SMM relocation code || <br />
This option enables additional SMM handler relocation related<br />
debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_MALLOC || toplevel || bool || Output verbose malloc debug messages || <br />
This option enables additional malloc related debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_ACPI || toplevel || bool || Output verbose ACPI debug messages || <br />
This option enables additional ACPI related debug messages.<br />
<br />
Note: This option will slightly increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| REALMODE_DEBUG || toplevel || bool || Enable debug messages for option ROM execution || <br />
This option enables additional x86emu related debug messages.<br />
<br />
Note: This option will increase the time to emulate a ROM.<br />
<br />
If unsure, say N.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages || <br />
This option enables additional x86emu related debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF || <br />
Print information about JMP and RETF opcodes from x86emu.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes || <br />
Print _all_ opcodes that are executed by x86emu.<br />
<br />
WARNING: This will produce a LOT of output and take a long time.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&amp;Play accesses || <br />
Print Plug And Play accesses made by option ROMs.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O || <br />
Print Disk I/O related messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_PMM || toplevel || bool || Log PMM || <br />
Print messages related to POST Memory Manager (PMM).<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions || <br />
Print messages related to VESA BIOS Extension (VBE) functions.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console || <br />
Let INT10 (i.e. character output) calls print messages to debug output.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls || <br />
Print messages related to interrupt handling.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses || <br />
Print messages related to accesses to certain areas of the virtual<br />
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses || <br />
Print memory accesses made by option ROM.<br />
Note: This also includes accesses to fetch instructions.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses || <br />
Print I/O accesses made by option ROM.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| LLSHELL || toplevel || bool || Built-in low-level shell || <br />
If enabled, you will have a low level shell to examine your machine.<br />
Put llshell() in your (romstage) code to start the shell.<br />
See src/arch/x86/llshell/llshell.inc for details.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| TRACE || toplevel || bool || Trace function calls || <br />
If enabled, every function will print information to console once<br />
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)<br />
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP<br />
of calling function. Please note some printk releated functions<br />
are omitted from trace to have good looking console dumps.<br />
||<br />
<br />
|- bgcolor="#eeeeee"<br />
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || hex || || <br />
Select when the board has a power button which can optionally be<br />
disabled by the user.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || hex || || <br />
Select when the board has a power button which can optionally be<br />
enabled by the user, e.g. when the board ships with a jumper over<br />
the power switch contacts.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| POWER_BUTTON_FORCE_ENABLE || toplevel || hex || || <br />
Select when the board requires that the power button is always<br />
enabled.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| POWER_BUTTON_FORCE_DISABLE || toplevel || hex || || <br />
Select when the board requires that the power button is always<br />
disabled, e.g. when it has been hardwired to ground.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| POWER_BUTTON_IS_OPTIONAL || toplevel || bool || || <br />
Internal option that controls ENABLE_POWER_BUTTON visibility.<br />
<br />
||<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Deprecated || || || ||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_HAS_HARD_RESET || toplevel.deprecated_options || bool || || <br />
This variable specifies whether a given board has a reset.c<br />
file containing a hard_reset() function.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_HAS_FADT || toplevel.deprecated_options || bool || || <br />
This variable specifies whether a given board has a board-local<br />
FADT in fadt.c. Long-term, those should be moved to appropriate<br />
chipset components (eg. southbridge).<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_BUS_CONFIG || toplevel.deprecated_options || bool || || <br />
This variable specifies whether a given board has a get_bus_conf.c<br />
file containing information about bus routing.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DRIVERS_PS2_KEYBOARD || toplevel.deprecated_options || bool || PS/2 keyboard init || <br />
Enable this option to initialize PS/2 keyboards found connected<br />
to the PS/2 port.<br />
<br />
Some payloads (eg, filo) require this option. Other payloads<br />
(eg, SeaBIOS, Linux) do not require it.<br />
Initializing a PS/2 keyboard can take several hundred milliseconds.<br />
<br />
If you know you will only use a payload which does not require<br />
this option, then you can say N here to speed up boot time.<br />
Otherwise say Y.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PCIE_TUNING || toplevel.deprecated_options || bool || || <br />
This variable enables certain PCIe optimizations. Right now it's<br />
only ASPM and it's untested.<br />
<br />
||<br />
<br />
|}</div>
Uwe
https://www.coreboot.org/index.php?title=Build_HOWTO&diff=10902
Build HOWTO
2011-10-13T22:44:36Z
<p>Uwe: /* Building coreboot */</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on.<br />
* Enter the '''Payload''' menu.<br />
** By default, the [[SeaBIOS]] payload will be downloaded and built during the coreboot build process. If you want to use another payload:<br />
*** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
*** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip.<br />
<br />
== Known issue ==<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>
Uwe
https://www.coreboot.org/index.php?title=Superiotool&diff=10890
Superiotool
2011-09-11T22:35:15Z
<p>Uwe: /* Support of various devices */ Fintek F71889 log.</p>
<hr />
<div>'''Superiotool''' is a GPL'd user-space helper tool for coreboot development purposes (but may also be useful for other things). It allows you to detect which [[wikipedia:Super I/O|Super I/O]] you have on your mainboard, and it can provide detailed information about the register contents of the Super I/O.<br />
<br />
This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.<br />
<br />
<gallery><br />
Image:Ite it8705f.jpg|<small>ITE IT8705F</small><br />
Image:Winbond w83977ef.jpg|<small>Winbond W83977EF</small><br />
</gallery><br />
<br />
== Support of various devices ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M1535/M1535D/M1535+/M1535D+<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/048024.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5105<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5107<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5109<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5113<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5119<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M512x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513x<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513xB<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513xF<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M514x<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-September/024916.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-July/050471.html 2], [http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html 3]<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71862FG / F71863FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71889<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/attachments/20110515/b04d0142/attachment-0005.ksh 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71872F/FG / F71806F/FG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71882FG/F71883FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040016.html 1], [http://www.flashrom.org/pipermail/flashrom/2010-August/004390.html 2]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-November/026831.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F8000<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C711<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C712<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C721<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C735<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8228E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8502E/F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8510E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8511E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8512E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8661F/IT8770F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://article.gmane.org/gmane.linux.bios/42100/ 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F/IT8687R<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2010-May/058010.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT86793<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8702F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8703F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8705F/AF / IT8700F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026913.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8706R<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8708F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024879.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8710F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8711F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 2]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024884.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8720F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8721F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8722F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8726F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8761E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8780F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| HMC<br />
| HMC83755<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Holtek<br />
| HT6552IR<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS307<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS308<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS309<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS317<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS338<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS351<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97307<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/047843.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87309<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87360<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026991.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87351<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87364<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87365<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87363<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87366<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87382<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8739x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/043447.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87591x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8741x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87372<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8374L<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071014/19fe07aa/attachment-0001.htm 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87427<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87373<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| WPCE775x / NPCE781x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| WPCM450<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| NCT6776F (B)<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| NCT6776F (C)<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xFR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N971<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-July/003832.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N972<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N252<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-June/050276.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M172<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xAPM<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C67x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B80x/FDC37M707<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N958FR<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027036.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B77x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B78x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M602<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M60x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B72x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M81x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B27x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027245.html 1]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027248.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B37x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47U33x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B34x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S42x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M10x/112/13x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025451.html 1] <br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B357<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M14x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M15x/192/997<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-December/028269.html 1]<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-February/030897.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S45x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M292<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B387<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B397<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M182<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M584<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| MEC1308<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| DME1737<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5504<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N217<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5514D-NS<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3112<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3114<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3116<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5317<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5027<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH4307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669FR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N237<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N769<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024883.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N3869/FDC37N869<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N227<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025846.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SIO10N268<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C665GT/IR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C666GT<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SIS6801<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SIS950<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686A/VT82C686B<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977CTF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977EF/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040507.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83527HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627SF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697HF/F/HG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-August/004443.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83L517D/D-F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83637HF/HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627THF/THG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment.txt 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025599.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-August/037685.html 3], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 4]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment-0001.txt 1]<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627DHG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-January/029517.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627DHG-P/-PT<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627UHG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83667HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977F-A/G-A/AF-A/AG-A<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977AF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977TF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627HF/F/HG/G<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025453.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025592.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697SF/UF/UG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025914.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627EHF/EF/EHG/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024887.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025284.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-January/029416.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877AF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-February/002119.html]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877TF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| WPCD376I<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-October/053894.html 1]<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM82C862<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8663BF<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8669<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8670<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|}<br />
<br />
|}<br />
<br />
'''Extended dumps (EC, HWM) available for:'''<br />
<br />
Use the '''--extra-dump''' option to see the contents of these registers.<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 1]<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond<br />
| W83627THF/THG HWM<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMSC<br />
| LPC47N227 runtime register block<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
<br />
<small><br />
<sup>1</sup> Previosly National Semiconductor, now bought by Winbond.<br /><br />
<sup>2</sup> Register dump output from a running coreboot system (vs. proprietary BIOS).<br /><br />
</small><br />
<br />
== Installation ==<br />
<br />
'''Manual installation'''<br />
<br />
$ git clone http://review.coreboot.org/p/coreboot<br />
$ cd coreboot/util/superiotool<br />
$ make<br />
$ sudo make install<br />
<br />
'''Debian / Ubuntu'''<br />
<br />
$ apt-get install superiotool<br />
<br />
'''Fedora'''<br />
<br />
$ yum install superiotool<br />
<br />
== Usage ==<br />
<br />
Probe/detect the Super I/O in your mainboard:<br />
<br />
$ superiotool<br />
<br />
Register dump as table of hex-values (if the Super I/O is detected):<br />
<br />
$ superiotool -d<br />
<br />
Please see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool/README README] for further information.<br />
<br />
{{GPL}}</div>
Uwe
https://www.coreboot.org/index.php?title=Board:asrock/e350m1&diff=10855
Board:asrock/e350m1
2011-07-02T19:43:06Z
<p>Uwe: Small fixes.</p>
<hr />
<div>== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = <br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = <br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = OK<br />
|CPU_multicore_comments = Both cores seem to be detected.<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = WIP<br />
|RAM_DDR3_comments = 2GB working properly, >=4GB reported incorrectly. Work in progress.<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = N/A<br />
|RAM_ecc_comments = <br />
<br />
|Onboard_SCSI_status = N/A<br />
|IDE_status = N/A<br />
|IDE_comments = <br />
|IDE_25_status = N/A<br />
|IDE_CF_status = Untested<br />
|CDROM_DVD_status = Untested<br />
|SATA_status = OK<br />
|USB_status = WIP<br />
|USB_comments = Mass storage devices will seldom mount and generate errors in dmesg.<br />
|Onboard_VGA_status = OK<br />
|Onboard_VGA_comments = Must add VBIOS.<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = N/A<br />
|PCIE_x1_status = Untested<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = ?<br />
|PCIE_x16_comments = <br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = N/A<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PS2_keyboard_status = Untested<br />
|PS2_mouse_status = Untested<br />
|PP_status = N/A<br />
|PP_comments =<br />
|Game_port_status = N/A<br />
|IR_status = ?<br />
|Speaker_status = ?<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments = CPU temperature seems to be displayed properly by lm-sensors.<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = Untested<br />
|CPUfreq_comments = CPU might report (or have) wrong frequency.<br />
|Powersave_status = ?<br />
|ACPI_status = ?<br />
|ACPI_comments = <br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|LEDs_status = N/A<br />
|HPET_status = Unknown<br />
|RNG_status = ?<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}</div>
Uwe
https://www.coreboot.org/index.php?title=Welcome_to_coreboot&diff=10843
Welcome to coreboot
2011-06-24T16:49:28Z
<p>Uwe: Use gitweb for "Browse Source", svn is obsolete.</p>
<hr />
<div><table width="100%" valign="top"><tr valign="top"><td width="80%"><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
'''coreboot''' is a Free Software project aimed at replacing the proprietary [http://wikipedia.org/wiki/BIOS BIOS] (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a [[Payloads|payload]].<br />
<br />
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly from firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like [[SeaBIOS | PC BIOS services]] or [[TianoCore | UEFI]]. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.<br />
<br />
coreboot currently supports over '''[[Supported Motherboards|230]]''' different mainboards. Check the [[Support]] page to see if your system is supported.<br />
<br />
<small><br />
coreboot was formerly known as [http://www.coreboot.org/pipermail/coreboot/2008-January/029133.html LinuxBIOS]. <br />
</small><br />
</div><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
coreboot recently switched to [[git]] and [http://review.coreboot.org gerrit] is now used as patch review tool.<br />
</div><br />
<br />
{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%<br />
|-<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = yellow|<br />
WIDTH = 100%|<br />
ICON = <small>[[Benefits|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Benefits]]</span>|<br />
CONTENT =<br />
<small><br />
* 100% Free Software (GPL), no royalties, no license fees!<br />
* Fast boot times (3 seconds to Linux console)<br />
<!-- * Avoids the need for a slow/buggy/proprietary BIOS --><br />
<!-- * Runs in 32-Bit protected mode almost from the start --><br />
<!-- * Written in C, contains virtually no assembly code --><br />
* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]<br />
<!-- * Further features: netboot, serial console, remote flashing, ... --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = #d1adf6|<br />
WIDTH = 100%|<br />
ICON = <small>[[Use Cases|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Use Cases]]</span>|<br />
CONTENT =<br />
<small><br />
* Desktop PCs, servers, [[Laptop|laptops]]<br />
* [[Clusters]]<br />
<!-- * Set-Top-Boxes, thin clients --><br />
* Embedded solutions<br />
<!-- * [http://en.wikipedia.org/wiki/Small_form_factor Small form factor computers], [http://en.wikipedia.org/wiki/Home_theater_PC Home-theater PCs] --><br />
<!-- * No-moving-parts solutions (ROM chip as "disk") --><br />
<!-- * Non-standard scenarios (e.g. FPGA in Opteron socket) --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = lime|<br />
WIDTH = 100%|<br />
ICON = <small>[[Payloads|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Payloads]]</span>|<br />
CONTENT =<br />
<small><br />
* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] <!-- / [[OpenFirmware]] / [[OpenBIOS]] --><br />
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] <!-- / [http://openbsd.org/ OpenBSD]--><br />
* [[Etherboot]] / [[GPXE]] / [[Payloads|...]]<br />
<!--* [[Memtest86]]<br />
* [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]--><br />
</small><br />
}}<br />
<br />
|}<br />
<br />
{| cellspacing=5 cellpadding=15 border=0 valign="top" width=100%<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_cb.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">About</span>'''<br /><small>Find out more about coreboot.</small><small><hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_devel.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Developers</span>'''<br /><small>Get involved! Help us make coreboot better.</small><small><hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree Browse Source] | [[GSoC]] | [[Flag Days]] | [[Distributed and Automated Testsystem|Testsystem]]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_status.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Status</span>'''<br /><small>Find out whether your hardware is already supported.</small><small><hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [http://qa.coreboot.org Build Status]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_tools.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Related Tools</span>'''<br /><small>Tools and libraries related to coreboot.</small><small><hr />[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [[SerialICE]]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_101.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Getting Started</span>'''<br /><small>Download coreboot and get started.</small><small><hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_support.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Support</span>'''<br /><small>Learn how to contact us and find help and support.</small><small><hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|coreboot Options]]</small><br />
|}<br />
<br />
|}<br />
</td><td width="20%"><br />
<br />
[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]<br />
<br />
<br clear=all /><br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[http://blogs.coreboot.org News (blog)]</span>'''<hr /><br />
<small><br />
<rss max=5>http://blogs.coreboot.org/feed/</rss><br />
</small><br />
<br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[Current events|Upcoming Events]]</span>'''<hr /><br />
<!-- List of upcoming events (remove events after they have taken place). --><br />
<small><br />
<!-- * '''2011/mon/day:''' coreboot event at [[Link]] in somecity --><br />
* '''2011/05/11-14:''' coreboot and [[Flashrom|flashrom]] booths at [http://www.linuxtag.org/ LinuxTag] in Berlin<br />
* [[GSoC|2011 Google Summer of Code]]<br />
</small><br />
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<br clear=all /><br />
{{#widget:Ohloh Project|id=coreboot|type=partner_badge}}<br />
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</td></tr></table><br />
<br />
__NOTOC__<br />
__NOEDITSECTION__</div>
Uwe
https://www.coreboot.org/index.php?title=Coreboot_Options&diff=10842
Coreboot Options
2011-06-23T16:49:18Z
<p>Uwe: Update coreboot option list.</p>
<hr />
<div>This is an automatically generated list of '''coreboot compile-time options'''.<br />
<br />
Last update: 2011/06/23 18:44:41.<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Option<br />
! align="left" | Source<br />
! align="left" | Format<br />
! align="left" | Short&nbsp;Description<br />
! align="left" | Description<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: General setup || || || ||<br />
|- bgcolor="#eeeeee"<br />
| EXPERT || toplevel || bool || Expert mode || <br />
This allows you to select certain advanced configuration options.<br />
<br />
Warning: Only enable this option if you really know what you are<br />
doing! You have been warned!<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| LOCALVERSION || toplevel || string || Local version string || <br />
Append an extra string to the end of the coreboot version.<br />
<br />
This can be useful if, for instance, you want to append the<br />
respective board's hostname or some other identifying string to<br />
the coreboot version number, so that you can easily distinguish<br />
boot logs of different boards from each other.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CBFS_PREFIX || toplevel || string || CBFS prefix to use || <br />
Select the prefix to all files put into the image. It's "fallback"<br />
by default, "normal" is a common alternative.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CBFS_PREFIX || toplevel || string || Compiler || <br />
This option allows you to select the compiler used for building<br />
coreboot.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SCANBUILD_ENABLE || toplevel || bool || Build with scan-build for static analysis || <br />
Changes the build process to scan-build is used.<br />
Requires scan-build in path.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SCANBUILD_REPORT_LOCATION || toplevel || string || Directory to put scan-build report in || <br />
Where the scan-build report should be stored<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CCACHE || toplevel || bool || ccache || <br />
Enables the use of ccache for faster builds.<br />
Requires ccache in path.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison || <br />
Enable this option if you are working on the sconfig<br />
device tree parser and made changes to sconfig.l and<br />
sconfig.y.<br />
Otherwise, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values || <br />
Enable this option if coreboot shall read options from the "CMOS"<br />
NVRAM instead of using hard coded values.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COMPRESS_RAMSTAGE || toplevel || bool || Compress ramstage with LZMA || <br />
Compress ramstage to save memory in the flash image. Note<br />
that decompression might slow down booting if the boot flash<br />
is connected through a slow Link (i.e. SPI)<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot config file into the ROM image || <br />
Include in CBFS the coreboot config file that was used to compile the ROM image<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Mainboard || || || ||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_LENOVO_X60 || mainboard/lenovo || bool || ThinkPad X60 / X60s || <br />
The following X60 series ThinkPad machines have been verified to<br />
work correctly:<br />
<br />
ThinkPad X60s (Model 1702, 1703)<br />
ThinkPad X60 (Model 1709)<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_LENOVO_T60 || mainboard/lenovo || bool || ThinkPad T60 / T60p || <br />
The following T60 series ThinkPad machines have been verified to<br />
work correctly:<br />
<br />
Thinkpad T60p (Model 2007)<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision || <br />
Look on the bottom side for a number like 406-0001-30. The last 2<br />
digits state the PCB revision (3.0 in this example). For 2.0 or older<br />
boards choose Y, for 3.0 and newer say N.<br />
<br />
Old revision boards need a jumper shorting the power button to<br />
power on automatically. You may enable the button only after this<br />
jumper has been removed. New revision boards are not restricted<br />
in this way, and always have the power button enabled.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 || <br />
If selected, both on-board serial ports will operate in RS485 mode<br />
instead of RS232.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 &amp; 2 to RS485 || <br />
If selected, the first two on-board serial ports will operate in RS485<br />
mode instead of RS232.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave || <br />
If selected, the on-board Compact Flash card socket will act as IDE<br />
Slave instead of Master.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 || <br />
If selected, both on-board serial ports will operate in RS485 mode<br />
instead of RS232.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 || <br />
If selected, both on-board serial ports will operate in RS485 mode<br />
instead of RS232.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave || <br />
If selected, the on-board SSD will act as IDE Slave instead of Master.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_ROMSIZE_KB_16384 || mainboard || bool || ROM chip size || <br />
Select the size of the ROM chip you intend to flash coreboot on.<br />
<br />
The build system will take care of creating a coreboot.rom file<br />
of the matching size.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB || <br />
Choose this option if you have a 128 KB ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB || <br />
Choose this option if you have a 256 KB ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB || <br />
Choose this option if you have a 512 KB ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) || <br />
Choose this option if you have a 1024 KB (1 MB) ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) || <br />
Choose this option if you have a 2048 KB (2 MB) ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) || <br />
Choose this option if you have a 4096 KB (4 MB) ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) || <br />
Choose this option if you have a 8192 KB (8 MB) ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) || <br />
Choose this option if you have a 16384 KB (16 MB) ROM chip.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button || <br />
The selected mainboard can optionally have the power button tied<br />
to ground with a jumper so that the button appears to be<br />
constantly depressed. If this option is enabled and the jumper is<br />
installed then the board will turn on, but turn off again after a<br />
short timeout, usually 4 seconds.<br />
<br />
Select Y here if you have removed the jumper and want to use an<br />
actual power button. Select N if you have the jumper installed.<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Architecture (x86) || || || ||<br />
|- bgcolor="#eeeeee"<br />
| UPDATE_IMAGE || arch/x86 || bool || Update existing coreboot.rom image || <br />
If this option is enabled, no new coreboot.rom file<br />
is created. Instead it is expected that there already<br />
is a suitable file for further processing.<br />
The bootblock will not be modified.<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Chipset || || || ||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || CPU ||<br />
|- bgcolor="#eeeeee"<br />
| UPDATE_CPU_MICROCODE || cpu/amd/model_10xxx || bool || Update CPU microcode || <br />
Select this to apply patches to the CPU microcode provided by<br />
AMD without source, and distributed with coreboot, to address<br />
issues in the CPU post production.<br />
<br />
Microcode updates distributed with coreboot are not necessarily<br />
the latest version available from AMD. Updates are only applied<br />
if they are newer than the microcode already in your CPU.<br />
<br />
Unselect this to let Fam10h CPUs run with microcode as shipped<br />
from factory. No binary microcode patches will be included in the<br />
coreboot image in that case, which can help with creating an image<br />
for which complete source code is available, which in turn might<br />
simplify license compliance.<br />
<br />
Microcode updates intend to solve issues that have been discovered<br />
after CPU production. The common case is that systems work as<br />
intended with updated microcode, but we have also seen cases where<br />
issues were solved by not applying the microcode updates.<br />
<br />
Note that some operating system include these same microcode<br />
patches, so you may need to also disable microcode updates in<br />
your operating system in order for this option to matter.<br />
<br />
||<br />
||<br />
|- bgcolor="#eeeeee"<br />
| GEODE_VSA_FILE || cpu/amd/model_gx2 || bool || Add a VSA image || <br />
Select this option if you have an AMD Geode GX2 vsa that you would<br />
like to add to your ROM.<br />
<br />
You will be able to specify the location and file name of the<br />
image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VSA_FILENAME || cpu/amd/model_gx2 || string || AMD Geode GX2 VSA path and filename || <br />
The path and filename of the file to use as VSA.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| GEODE_VSA_FILE || cpu/amd/model_lx || bool || Add a VSA image || <br />
Select this option if you have an AMD Geode LX vsa that you would<br />
like to add to your ROM.<br />
<br />
You will be able to specify the location and file name of the<br />
image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VSA_FILENAME || cpu/amd/model_lx || string || AMD Geode LX VSA path and filename || <br />
The path and filename of the file to use as VSA.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SMP || cpu || bool || || <br />
This option is used to enable certain functions to make coreboot<br />
work correctly on symmetric multi processor (SMP) systems.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MMX || cpu || bool || || <br />
Select MMX in your socket or model Kconfig if your CPU has MMX<br />
streaming SIMD instructions. ROMCC can build more efficient<br />
code if it can spill to MMX registers.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SSE || cpu || bool || || <br />
Select SSE in your socket or model Kconfig if your CPU has SSE<br />
streaming SIMD instructions. ROMCC can build more efficient<br />
code if it can spill to SSE (aka XMM) registers.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SSE2 || cpu || bool || || <br />
Select SSE2 in your socket or model Kconfig if your CPU has SSE2<br />
streaming SIMD instructions. Some parts of coreboot can be built<br />
with more efficient code if SSE2 instructions are available.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VAR_MTRR_HOLE || cpu || bool || || <br />
Unset this if you don't want the MTRR code to use<br />
subtractive MTRRs<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || Northbridge ||<br />
|- bgcolor="#eeeeee"<br />
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || || <br />
Select this for boards with a Voltage Regulator able to operate<br />
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.<br />
<br />
||<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: HyperTransport setup || || || ||<br />
|- bgcolor="#eeeeee"<br />
| None || northbridge/amd || None || HyperTransport frequency || <br />
This option sets the maximum permissible HyperTransport link<br />
frequency.<br />
<br />
Use of this option will only limit the autodetected HT frequency.<br />
It will not (and cannot) increase the frequency beyond the<br />
autodetected limits.<br />
<br />
This is primarily used to work around poorly designed or laid out<br />
HT traces on certain motherboards.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| LIMIT_HT_SPEED_AUTO || northbridge/amd || bool || HyperTransport downlink width || <br />
This option sets the maximum permissible HyperTransport<br />
downlink width.<br />
<br />
Use of this option will only limit the autodetected HT width.<br />
It will not (and cannot) increase the width beyond the autodetected<br />
limits.<br />
<br />
This is primarily used to work around poorly designed or laid out HT<br />
traces on certain motherboards.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd || bool || HyperTransport uplink width || <br />
This option sets the maximum permissible HyperTransport<br />
uplink width.<br />
<br />
Use of this option will only limit the autodetected HT width.<br />
It will not (and cannot) increase the width beyond the autodetected<br />
limits.<br />
<br />
This is primarily used to work around poorly designed or laid out HT<br />
traces on certain motherboards.<br />
<br />
||<br />
<br />
|- bgcolor="#eeeeee"<br />
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool || || <br />
This option affects how the SDRAMC register is programmed.<br />
Memory clock signals will not be routed properly if this option<br />
is set wrong.<br />
<br />
If your board has 4 DIMM slots, you must use select this option, in<br />
your Kconfig file of the board. On boards with 3 DIMM slots,<br />
do _not_ select this option.<br />
<br />
<br />
||<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || || <br />
Usually system firmware turns off system memory clock<br />
signals to unused SO-DIMM slots to reduce EMI and power<br />
consumption.<br />
However, some boards do not like unused clock signals to<br />
be disabled.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || || <br />
If non-zero, this designates the maximum DDR frequency<br />
the board supports, despite what the chipset should be<br />
capable of.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || Southbridge ||<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: AMD Geode GX1 video support || || || ||<br />
<br />
|- bgcolor="#eeeeee"<br />
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || || <br />
Select if RS690 should be setup to support MMCONF.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| USBDEBUG_DEFAULT_PORT || southbridge/amd/sb600 || int || SATA Mode || <br />
Select the mode in which SATA should be driven. IDE or AHCI.<br />
The default is IDE.<br />
<br />
config SATA_MODE_IDE<br />
bool "IDE"<br />
<br />
config SATA_MODE_AHCI<br />
bool "AHCI"<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary || <br />
Select this option to add a CMC state machine binary to<br />
the resulting coreboot image.<br />
<br />
Note: Without this binary coreboot will not work<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename || <br />
The path and filename of the file to use as CMC state machine<br />
binary.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || Super I/O ||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || Devices ||<br />
|- bgcolor="#eeeeee"<br />
| VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter || <br />
Allow bridges to set up legacy decoding ranges for VGA. Don't disable<br />
this unless you're sure you don't want the briges setup for VGA.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VGA_ROM_RUN || devices || bool || Run VGA option ROMs || <br />
Execute VGA option ROMs, if found. This is required to enable<br />
PCI/AGP/PCI-E video cards.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs || <br />
Execute non-VGA PCI option ROMs, if found.<br />
<br />
Examples include IDE/SATA controller option ROMs and option ROMs<br />
for network cards (NICs).<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Native mode || <br />
If you select this option, PCI option ROMs will be executed<br />
natively on the CPU in real mode. No CPU emulation is involved,<br />
so this is the fastest, but also the least secure option.<br />
(only works on x86/x64 systems)<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PCI_OPTION_ROM_RUN_YABEL || devices || bool || Secure mode || <br />
If you select this option, the x86emu CPU emulator will be used to<br />
execute PCI option ROMs.<br />
<br />
This option prevents option ROMs from doing dirty tricks with the<br />
system (such as installing SMM modules or hypervisors), but it is<br />
also significantly slower than the native option ROM initialization<br />
method.<br />
<br />
This is the default choice for non-x86 systems.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| YABEL_PCI_ACCESS_OTHER_DEVICES || devices || bool || Allow option ROMs to access other devices || <br />
Per default, YABEL only allows option ROMs to access the PCI device<br />
that they are associated with. However, this causes trouble for some<br />
onboard graphics chips whose option ROM needs to reconfigure the<br />
north bridge.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| YABEL_VIRTMEM_LOCATION || devices || hex || Location of YABEL's virtual memory || <br />
YABEL requires 1MB memory for its CPU emulation. This memory is<br />
normally located at 16MB.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| YABEL_DIRECTHW || devices || bool || Direct hardware access || <br />
YABEL consists of two parts: It uses x86emu for the CPU emulation and<br />
additionally provides a PC system emulation that filters bad device<br />
and memory access (such as PCI config space access to other devices<br />
than the initialized one).<br />
<br />
When choosing this option, x86emu will pass through all hardware<br />
accesses to memory and I/O devices to the underlying memory and I/O<br />
addresses. While this option prevents option ROMs from doing dirty<br />
tricks with the CPU (such as installing SMM modules or hypervisors),<br />
they can still access all devices in the system.<br />
Enable this option for a good compromise between security and speed.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| || || (comment) || || Embedded Controllers ||<br />
|- bgcolor="#eeeeee"<br />
| EC_ACPI || ec/acpi || bool || || <br />
ACPI Embedded Controller interface. Mostly found in laptops.<br />
<br />
||<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Generic Drivers || || || ||<br />
|- bgcolor="#eeeeee"<br />
| DRIVERS_OXFORD_OXPCIE || drivers/oxford/oxpcie || bool || Oxford OXPCIe952 || <br />
Support for Oxford OXPCIe952 serial port PCIe cards.<br />
Currently only devices with the vendor ID 0x1415 and device ID<br />
0xc158 will work.<br />
NOTE: Right now you have to set the base address of your OXPCIe952<br />
card to exactly the value that the device allocator would set them<br />
later on, or serial console functionality will stop as soon as the<br />
resource allocator assigns a new base address to the device.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OXFORD_OXPCIE_BRIDGE_BUS || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge bus number || <br />
While coreboot is executing code from ROM, the coreboot resource<br />
allocator has not been running yet. Hence PCI devices living behind<br />
a bridge are not yet visible to the system. In order to use an<br />
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge<br />
that controls the OXPCIe952 controller first.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OXFORD_OXPCIE_BRIDGE_DEVICE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge device number || <br />
While coreboot is executing code from ROM, the coreboot resource<br />
allocator has not been running yet. Hence PCI devices living behind<br />
a bridge are not yet visible to the system. In order to use an<br />
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge<br />
that controls the OXPCIe952 controller first.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OXFORD_OXPCIE_BRIDGE_FUNCTION || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge function number || <br />
While coreboot is executing code from ROM, the coreboot resource<br />
allocator has not been running yet. Hence PCI devices living behind<br />
a bridge are not yet visible to the system. In order to use an<br />
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge<br />
that controls the OXPCIe952 controller first.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OXFORD_OXPCIE_BRIDGE_SUBORDINATE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge subordinate bus || <br />
While coreboot is executing code from ROM, the coreboot resource<br />
allocator has not been running yet. Hence PCI devices living behind<br />
a bridge are not yet visible to the system. In order to use an<br />
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge<br />
that controls the OXPCIe952 controller first.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| OXFORD_OXPCIE_BASE_ADDRESS || drivers/oxford/oxpcie || hex || Base address for rom stage console || <br />
While coreboot is executing code from ROM, the coreboot resource<br />
allocator has not been running yet. Hence PCI devices living behind<br />
a bridge are not yet visible to the system. In order to use an<br />
OXPCIe952 based PCIe card, coreboot has to set up a temporary address<br />
for the OXPCIe952 controller.<br />
<br />
<br />
||<br />
<br />
||<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DRIVERS_SIL_3114 || drivers/sil || bool || Silicon Image SIL3114 || <br />
It sets PCI class to IDE compatible native mode, allowing<br />
SeaBIOS, FILO etc... to boot from it.<br />
<br />
<br />
<br />
||<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Console || || || ||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL8250 || console || bool || Serial port console output || <br />
Send coreboot debug output to an I/O mapped serial port console.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL8250MEM || console || bool || Serial port console output (memory mapped) || <br />
Send coreboot debug output to a memory mapped serial port console.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 || <br />
Serial console on COM1/ttyS0 at I/O port 0x3f8.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 || <br />
Serial console on COM2/ttyS1 at I/O port 0x2f8.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 || <br />
Serial console on COM3/ttyS2 at I/O port 0x3e8.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 || <br />
Serial console on COM4/ttyS3 at I/O port 0x2e8.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| TTYS0_BASE || console || hex || || <br />
Map the COM port names to the respective I/O port.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_115200 || console || bool || 115200 || <br />
Set serial port Baud rate to 115200.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_57600 || console || bool || 57600 || <br />
Set serial port Baud rate to 57600.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_38400 || console || bool || 38400 || <br />
Set serial port Baud rate to 38400.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_19200 || console || bool || 19200 || <br />
Set serial port Baud rate to 19200.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_SERIAL_9600 || console || bool || 9600 || <br />
Set serial port Baud rate to 9600.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| TTYS0_BAUD || console || int || || <br />
Map the Baud rates to an integer.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| USBDEBUG || console || bool || USB 2.0 EHCI debug dongle support || <br />
This option allows you to use a so-called USB EHCI Debug device<br />
(such as the Ajays NET20DC, AMIDebug RX, or a system using the<br />
Linux "EHCI Debug Device gadget" driver found in recent kernel)<br />
to retrieve the coreboot debug messages (instead, or in addition<br />
to, a serial port).<br />
<br />
This feature is NOT supported on all chipsets in coreboot!<br />
<br />
It also requires a USB2 controller which supports the EHCI<br />
Debug Port capability.<br />
<br />
See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list<br />
of supported controllers.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| USBDEBUG_DEFAULT_PORT || console || int || Default USB port to use as Debug Port || <br />
This option selects which physical USB port coreboot will try to<br />
use as EHCI Debug Port first (valid values are: 1-15).<br />
<br />
If coreboot doesn't detect an EHCI Debug Port dongle on this port,<br />
it will try all the other ports one after the other. This will take<br />
a few seconds of time though, and thus slow down the booting process.<br />
<br />
Hence, if you select the correct port here, you can speed up<br />
your boot time. Which USB port number (1-15) refers to which<br />
actual port on your mainboard (potentially also USB pin headers<br />
on your mainboard) is highly board-specific, and you'll likely<br />
have to find out by trial-and-error.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| ONBOARD_VGA_IS_PRIMARY || console || bool || Use onboard VGA as primary video device || <br />
If not selected, the last adapter found will be used.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_NE2K || console || bool || Network console over NE2000 compatible Ethernet adapter || <br />
Send coreboot debug output to a Ethernet console, it works<br />
same way as Linux netconsole, packets are received to UDP<br />
port 6666 on IP/MAC specified with options bellow.<br />
Use following netcat command: nc -u -l -p 6666<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_NE2K_DST_MAC || console || string || Destination MAC address of remote system || <br />
Type in either MAC address of logging system or MAC address<br />
of the router.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system || <br />
This is IP adress of the system running for example<br />
netcat command to dump the packets.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_NE2K_SRC_IP || console || string || IP address of coreboot system || <br />
This is the IP of the coreboot system<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_NE2K_IO_PORT || console || hex || NE2000 adapter fixed IO port address || <br />
This is the IO port address for the IO port<br />
on the card, please select some non-conflicting region,<br />
32 bytes of IO spaces will be used (and align on 32 bytes<br />
boundary, qemu needs broader align)<br />
<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW || <br />
Way too many details.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG || <br />
Debug-level messages.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO || <br />
Informational messages.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE || <br />
Normal but significant conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING || <br />
Warning conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR || <br />
Error conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT || <br />
Critical conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT || <br />
Action must be taken immediately.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG || <br />
System is unusable.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MAXIMUM_CONSOLE_LOGLEVEL || console || int || || <br />
Map the log level config names to an integer.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW || <br />
Way too many details.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG || <br />
Debug-level messages.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO || <br />
Informational messages.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE || <br />
Normal but significant conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING || <br />
Warning conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR || <br />
Error conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT || <br />
Critical conditions.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT || <br />
Action must be taken immediately.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG || <br />
System is unusable.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEFAULT_CONSOLE_LOGLEVEL || console || int || || <br />
Map the log level config names to an integer.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| CONSOLE_POST || console || bool || Show POST codes on the debug console || <br />
If enabled, coreboot will additionally print POST codes (which are<br />
usually displayed using a so-called "POST card" ISA/PCI/PCI-E<br />
device) on the debug console.<br />
<br />
||<br />
<br />
|- bgcolor="#eeeeee"<br />
| HAVE_HARD_RESET || toplevel || bool || || <br />
This variable specifies whether a given board has a hard_reset<br />
function, no matter if it's provided by board code or chipset code.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_OPTION_TABLE || toplevel || bool || || <br />
This variable specifies whether a given board has a cmos.layout<br />
file containing NVRAM/CMOS bit definitions.<br />
It defaults to 'n' but can be selected in mainboard/*/Kconfig.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VGA || toplevel || bool || || <br />
Build board-specific VGA code.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| GFXUMA || toplevel || bool || || <br />
Enable Unified Memory Architecture for graphics.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_ACPI_TABLES || toplevel || bool || || <br />
This variable specifies whether a given board has ACPI table support.<br />
It is usually set in mainboard/*/Kconfig.<br />
Whether or not the ACPI tables are actually generated by coreboot<br />
is configurable by the user via GENERATE_ACPI_TABLES.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_MP_TABLE || toplevel || bool || || <br />
This variable specifies whether a given board has MP table support.<br />
It is usually set in mainboard/*/Kconfig.<br />
Whether or not the MP table is actually generated by coreboot<br />
is configurable by the user via GENERATE_MP_TABLE.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_PIRQ_TABLE || toplevel || bool || || <br />
This variable specifies whether a given board has PIRQ table support.<br />
It is usually set in mainboard/*/Kconfig.<br />
Whether or not the PIRQ table is actually generated by coreboot<br />
is configurable by the user via GENERATE_PIRQ_TABLE.<br />
<br />
||<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: System tables || || || ||<br />
|- bgcolor="#eeeeee"<br />
| GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables || <br />
Generate ACPI tables for this board.<br />
<br />
If unsure, say Y.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table || <br />
Generate an MP table (conforming to the Intel MultiProcessor<br />
specification 1.4) for this board.<br />
<br />
If unsure, say Y.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table || <br />
Generate a PIRQ table for this board.<br />
<br />
If unsure, say Y.<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Payload || || || ||<br />
|- bgcolor="#eeeeee"<br />
| PAYLOAD_NONE || toplevel || bool || None || <br />
Select this option if you want to create an "empty" coreboot<br />
ROM image for a certain mainboard, i.e. a coreboot ROM image<br />
which does not yet contain a payload.<br />
<br />
For such an image to be useful, you have to use 'cbfstool'<br />
to add a payload to the ROM image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PAYLOAD_ELF || toplevel || bool || An ELF executable payload || <br />
Select this option if you have a payload image (an ELF file)<br />
which coreboot should run as soon as the basic hardware<br />
initialization is completed.<br />
<br />
You will be able to specify the location and file name of the<br />
payload image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PAYLOAD_SEABIOS || toplevel || bool || SeaBIOS || <br />
Select this option if you want to build a coreboot image<br />
with a SeaBIOS payload. If you don't know what this is<br />
about, just leave it enabled.<br />
<br />
See http://coreboot.org/Payloads for more information.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PAYLOAD_FILO || toplevel || bool || FILO || <br />
Select this option if you want to build a coreboot image<br />
with a FILO payload. If you don't know what this is<br />
about, just leave it enabled.<br />
<br />
See http://coreboot.org/Payloads for more information.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SEABIOS_STABLE || toplevel || bool || stable || <br />
Stable SeaBIOS version<br />
||<br />
|- bgcolor="#eeeeee"<br />
| SEABIOS_MASTER || toplevel || bool || master || <br />
Newest SeaBIOS version<br />
||<br />
|- bgcolor="#eeeeee"<br />
| FILO_STABLE || toplevel || bool || 0.6.0 || <br />
Stable FILO version<br />
||<br />
|- bgcolor="#eeeeee"<br />
| FILO_MASTER || toplevel || bool || HEAD || <br />
Newest FILO version<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PAYLOAD_FILE || toplevel || string || Payload path and filename || <br />
The path and filename of the ELF executable file to use as payload.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads || <br />
In order to reduce the size payloads take up in the ROM chip<br />
coreboot can compress them using the LZMA algorithm.<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: VGA BIOS || || || ||<br />
|- bgcolor="#eeeeee"<br />
| VGA_BIOS || toplevel || bool || Add a VGA BIOS image || <br />
Select this option if you have a VGA BIOS image that you would<br />
like to add to your ROM.<br />
<br />
You will be able to specify the location and file name of the<br />
image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename || <br />
The path and filename of the file to use as VGA BIOS.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| VGA_BIOS_ID || toplevel || string || VGA device PCI IDs || <br />
The comma-separated PCI vendor and device ID that would associate<br />
your VGA BIOS to your video card.<br />
<br />
Example: 1106,3230<br />
<br />
In the above example 1106 is the PCI vendor ID (in hex, but without<br />
the "0x" prefix) and 3230 specifies the PCI device ID of the<br />
video card (also in hex, without "0x" prefix).<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| INTEL_MBI || toplevel || bool || Add an MBI image || <br />
Select this option if you have an Intel MBI image that you would<br />
like to add to your ROM.<br />
<br />
You will be able to specify the location and file name of the<br />
image later.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| MBI_FILE || toplevel || string || Intel MBI path and filename || <br />
The path and filename of the file to use as VGA BIOS.<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Bootsplash || || || ||<br />
|- bgcolor="#eeeeee"<br />
| BOOTSPLASH || toplevel || bool || Show graphical bootsplash || <br />
This option shows a graphical bootsplash screen. The grapics are<br />
loaded from the CBFS file bootsplash.jpg.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename || <br />
The path and filename of the file to use as graphical bootsplash<br />
screen. The file format has to be jpg.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| FRAMEBUFFER_VESA_MODE || toplevel || hex || VESA framebuffer video mode || <br />
This option sets the resolution used for the coreboot framebuffer and<br />
bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will<br />
some day make this a "choice".<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| COREBOOT_KEEP_FRAMEBUFFER || toplevel || bool || Keep VESA framebuffer || <br />
This option keeps the framebuffer mode set after coreboot finishes<br />
execution. If this option is enabled, coreboot will pass a<br />
framebuffer entry in its coreboot table and the payload will need a<br />
framebuffer driver. If this option is disabled, coreboot will switch<br />
back to text mode before handing control to a payload.<br />
<br />
||<br />
<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Debugging || || || ||<br />
|- bgcolor="#eeeeee"<br />
| GDB_STUB || toplevel || bool || GDB debugging support || <br />
If enabled, you will be able to set breakpoints for gdb debugging.<br />
See src/arch/x86/lib/c_start.S for details.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages || <br />
This option enables additional RAM init related debug messages.<br />
It is recommended to enable this when debugging issues on your<br />
board which might be RAM init related.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_CAR || toplevel || bool || Output verbose Cache-as-RAM debug messages || <br />
This option enables additional CAR related debug messages.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_PIRQ || toplevel || bool || Check PIRQ table consistency || <br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages || <br />
This option enables additional SMBus (and SPD) debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages || <br />
This option enables additional SMI related debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_SMM_RELOCATION || toplevel || bool || Debug SMM relocation code || <br />
This option enables additional SMM handler relocation related<br />
debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DEBUG_MALLOC || toplevel || bool || Output verbose malloc debug messages || <br />
This option enables additional malloc related debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| REALMODE_DEBUG || toplevel || bool || Enable debug messages for option ROM execution || <br />
This option enables additional x86emu related debug messages.<br />
<br />
Note: This option will increase the time to emulate a ROM.<br />
<br />
If unsure, say N.<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages || <br />
This option enables additional x86emu related debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF || <br />
Print information about JMP and RETF opcodes from x86emu.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes || <br />
Print _all_ opcodes that are executed by x86emu.<br />
<br />
WARNING: This will produce a LOT of output and take a long time.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&amp;Play accesses || <br />
Print Plug And Play accesses made by option ROMs.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O || <br />
Print Disk I/O related messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_PMM || toplevel || bool || Log PMM || <br />
Print messages related to POST Memory Manager (PMM).<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions || <br />
Print messages related to VESA BIOS Extension (VBE) functions.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console || <br />
Let INT10 (i.e. character output) calls print messages to debug output.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls || <br />
Print messages related to interrupt handling.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses || <br />
Print messages related to accesses to certain areas of the virtual<br />
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses || <br />
Print memory accesses made by option ROM.<br />
Note: This also includes accesses to fetch instructions.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses || <br />
Print I/O accesses made by option ROM.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| LLSHELL || toplevel || bool || Built-in low-level shell || <br />
If enabled, you will have a low level shell to examine your machine.<br />
Put llshell() in your (romstage) code to start the shell.<br />
See src/arch/x86/llshell/llshell.inc for details.<br />
<br />
||<br />
<br />
|- bgcolor="#eeeeee"<br />
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || hex || || <br />
Select when the board has a power button which can optionally be<br />
disabled by the user.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || hex || || <br />
Select when the board has a power button which can optionally be<br />
enabled by the user, e.g. when the board ships with a jumper over<br />
the power switch contacts.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| POWER_BUTTON_FORCE_ENABLE || toplevel || hex || || <br />
Select when the board requires that the power button is always<br />
enabled.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| POWER_BUTTON_FORCE_DISABLE || toplevel || hex || || <br />
Select when the board requires that the power button is always<br />
disabled, e.g. when it has been hardwired to ground.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| POWER_BUTTON_IS_OPTIONAL || toplevel || bool || || <br />
Internal option that controls ENABLE_POWER_BUTTON visibility.<br />
<br />
||<br />
|- bgcolor="#6699dd"<br />
! align="left" | Menu: Deprecated || || || ||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_HAS_HARD_RESET || toplevel.deprecated_options || bool || || <br />
This variable specifies whether a given board has a reset.c<br />
file containing a hard_reset() function.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| BOARD_HAS_FADT || toplevel.deprecated_options || bool || || <br />
This variable specifies whether a given board has a board-local<br />
FADT in fadt.c. Long-term, those should be moved to appropriate<br />
chipset components (eg. southbridge).<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| HAVE_BUS_CONFIG || toplevel.deprecated_options || bool || || <br />
This variable specifies whether a given board has a get_bus_conf.c<br />
file containing information about bus routing.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| DRIVERS_PS2_KEYBOARD || toplevel.deprecated_options || bool || PS/2 keyboard init || <br />
Enable this option to initialize PS/2 keyboards found connected<br />
to the PS/2 port.<br />
<br />
Some payloads (eg, filo) require this option. Other payloads<br />
(eg, SeaBIOS, Linux) do not require it.<br />
Initializing a PS/2 keyboard can take several hundred milliseconds.<br />
<br />
If you know you will only use a payload which does not require<br />
this option, then you can say N here to speed up boot time.<br />
Otherwise say Y.<br />
<br />
||<br />
|- bgcolor="#eeeeee"<br />
| PCIE_TUNING || toplevel.deprecated_options || bool || || <br />
This variable enables certain PCIe optimizations. Right now it's<br />
only ASPM and it's untested.<br />
<br />
||<br />
<br />
|}</div>
Uwe
https://www.coreboot.org/index.php?title=Build_HOWTO&diff=10841
Build HOWTO
2011-06-23T15:22:16Z
<p>Uwe: /* Known issue */ Remove .xcompile before rebuild.</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on.<br />
* Enter the '''Payload''' menu.<br />
** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip.<br />
<br />
== Known issue ==<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then remove the '''.xcompile''' file and retry the compilation process:<br />
<br />
$ '''rm .xcompile'''<br />
$ '''make'''<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>
Uwe
https://www.coreboot.org/index.php?title=Build_HOWTO&diff=10840
Build HOWTO
2011-06-23T15:20:23Z
<p>Uwe: Small fixes.</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard.<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot version from [[Git|our git repository]]:<br />
<br />
$ '''git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki>'''<br />
$ '''cd coreboot'''<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on.<br />
* Enter the '''Payload''' menu.<br />
** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip.<br />
<br />
== Known issue ==<br />
<br />
With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:<br />
<br />
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards<br />
<br />
This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run<br />
<br />
$ '''make crossgcc'''<br />
<br />
Then retry the compilation process:<br />
<br />
$ '''make'''<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.</div>
Uwe
https://www.coreboot.org/index.php?title=Datasheets&diff=10820
Datasheets
2011-06-10T07:44:13Z
<p>Uwe: /* AMD */ Fix dead URL.</p>
<hr />
<div></div>
Uwe
https://www.coreboot.org/index.php?title=SeaBIOS&diff=10819
SeaBIOS
2011-06-09T18:56:08Z
<p>Uwe: /* Windows */</p>
<hr />
<div>[http://www.seabios.org '''SeaBIOS'''] is an open-source legacy BIOS implementation which can be used as a coreboot [[Payloads|payload]]. It implements the standard [https://secure.wikimedia.org/wikipedia/en/wiki/BIOS BIOS] calling interfaces that a typical x86 proprietary BIOS implements.<br />
<br />
This page describes using SeaBIOS with coreboot. SeaBIOS can also run natively in [[QEMU]] and [http://bochs.sourceforge.net/ bochs] &mdash; see the [http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=README;hb=HEAD SeaBIOS README] file for information on non-coreboot uses.<br />
<br />
= Use cases =<br />
<br />
Any software requiring 16-bit BIOS services benefits from SeaBIOS (eg, Windows and DOS). SeaBIOS also enables booting Linux out of the box (using standard boot-loaders like GRUB and Syslinux).<br />
<br />
SeaBIOS supports booting from ATA hard drives, ATAPI CDROMs, USB hard drives, USB CDROMs, payloads in flash, and from [http://en.wikipedia.org/wiki/Option_ROM Option ROMs] (eg, SCSI or network cards). SeaBIOS can initialize and use a PS/2 keyboard or USB keyboard.<br />
<br />
== Windows ==<br />
<br />
SeaBIOS has been tested with Windows XP, Windows 2008, Windows Vista (64/32 bit), Windows 7 (32 bit and 64 bit).<br />
<br />
However, Windows has a very strict ACPI interpreter, and many coreboot boards do not have a complete [[ACPI in coreboot|ACPI definition]]. As a result, many coreboot boards will fail during Windows boot (eg, it may fail with a '''STOP 0xA5''' code).<br />
<br />
So far [[ASUS M2V-MX SE]] and [[GIGABYTE GA-M57SLI-S4]] have known good working ACPI and are able to boot XP/Vista/Windows 7. Please ask on the [[Mailinglist|mailing list]] for the status of other boards/chipsets.<br />
<br />
== Linux ==<br />
<br />
SeaBIOS has been tested with GRUB, LILO, and Syslinux. Linux booting works well.<br />
<br />
== Other ==<br />
<br />
SeaBIOS has also been tested with FreeDOS, NetBSD, and OpenBSD.<br />
<br />
Because SeaBIOS implements the standard x86 BIOS interfaces, it is expected many other operating systems and boot-loaders will work.<br />
<br />
= Building =<br />
<br />
== Building via coreboot's menuconfig ==<br />
<br />
Probably the easiest way to use SeaBIOS as coreboot payload is to simply use the coreboot build process, which downloads and builds SeaBIOS as payload by default nowadays. You just have to run the following in your coreboot checkout:<br />
<br />
<source lang="bash"><br />
$ make menuconfig<br />
$ make<br />
</source><br />
<br />
Both SeaBIOS and coreboot will be built, and SeaBIOS will be added as payload to the '''coreboot.rom''' image that is being built.<br />
<br />
== Manual build ==<br />
<br />
One can download the latest version of SeaBIOS through a git repository:<br />
<br />
<source lang="bash"><br />
$ git clone git://git.seabios.org/seabios.git seabios<br />
$ cd seabios<br />
</source><br />
<br />
There's also a [http://code.coreboot.org/p/seabios/source/changes/master/ gitweb] facility to browse the latest source code online.<br />
<br />
Run '''make menuconfig''' and set the following variables:<br />
<br />
* CONFIG_COREBOOT 1<br />
* CONFIG_DEBUG_SERIAL 1<br />
<br />
Then:<br />
<br />
<source lang="bash"><br />
$ make<br />
</source><br />
<br />
The final SeaBIOS payload file is '''out/bios.bin.elf'''.<br />
<br />
== coreboot ==<br />
<br />
For best results, configure coreboot with '''CONFIG_WRITE_HIGH_TABLES''' and '''CONFIG_VGA_BRIDGE_SETUP''' both enabled, and '''CONFIG_VGA_ROM_RUN''' and '''CONFIG_PCI_ROM_RUN''' both disabled.<br />
<br />
Finally, configure the SeaBIOS '''out/bios.bin.elf''' file as the coreboot payload and build coreboot. The resulting '''coreboot.rom''' file will contain both SeaBIOS and coreboot, and it can be flashed to a ROM chip.<br />
<br />
= SeaBIOS and CBFS =<br />
<br />
SeaBIOS can read the coreboot flash filesystem and extract files.<br />
<br />
When SeaBIOS scans the target machine's PCI devices, it will recognize option ROMs in CBFS that have the form '''pciVVVV,DDDD.rom'''. It will also run any file in the directory '''vgaroms/''' as a VGA option ROM not specific to a device and files in '''genroms/''' as a generic option ROM not specific to a device. In the above cases, SeaBIOS will recognize files with a '''.lzma''' suffix, and automatically decompress them (eg, '''pci1106,3344.rom.lzma''' and '''vgaroms/sgabios.bin.lzma''').<br />
<br />
SeaBIOS can also load a graphical bootsplash image from '''bootsplash.jpg''', payloads found in the CBFS directory '''img/''', and floppy images found in the '''floppyimg/''' directory.<br />
<br />
Further, SeaBIOS can obtain configuration information from CBFS. A file '''bootorder''' determines the order of devices and methods to attempt to boot the system from.<br />
<br />
The examples below show some common uses of these features.<br />
<br />
== Adding a VGA option ROM ==<br />
<br />
It is frequently necessary to add a VGA option ROM to CBFS in order to use a VGA adapter that is built-in to a motherboard. Note, VGA adapters on external cards (PCI, AGP, PCIe) do not require this step as SeaBIOS will automatically extract the VGA BIOS directly from the card. For machines without a VGA adapter, please follow the [[#Adding sgabios support|sgabios instructions]] below.<br />
<br />
The first step is to find the vendor and device ID of the built-in VGA adapter. This information can be found from '''lspci''':<br />
<br />
<source lang="bash"><br />
$ lspci -vnn<br />
...<br />
01:00.0 VGA compatible controller [0300]: VIA Technologies, Inc. UniChrome Pro IGP ['''1106:3344'''] (rev 01) (prog-if 00 [VGA controller])<br />
</source><br />
<br />
In the above example, the VGA vendor/device ID is '''1106:3344'''. [[VGA support#How_to_retrieve_a_good_video_bios|Obtain the VGA ROM]] (eg, '''vgabios.bin''') and add it to the ROM with:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add /path/to/vgabios.bin pci1106,3344.rom raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
Alternatively, SeaBIOS supports LZMA compressed option ROMs. Use the following to add a compressed option ROM instead:<br />
<br />
<source lang="bash"><br />
$ lzma -zc /path/to/vgabios.bin > vgabios.bin.lzma<br />
$ ./build/cbfstool coreboot.rom add vgabios.bin.lzma pci1106,3344.rom.lzma raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
After the above is done, one can write the '''coreboot.rom''' file to flash. SeaBIOS will extract the VGA ROM and run it during boot.<br />
<br />
== Adding gpxe support ==<br />
<br />
A [[GPXE|gpxe]] option ROM can nicely complement SeaBIOS and coreboot by adding network boot support. Adding gpxe is similar to [[#Adding a VGA option ROM]]. The first step is to find the Ethernet vendor/device ID. For example:<br />
<br />
<source lang="bash"><br />
$ lspci -vnn<br />
...<br />
00:09.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8110SC/8169SC Gigabit Ethernet ['''10ec:8167'''] (rev 10)<br />
</source><br />
<br />
Then one can build a gpxe option ROM. For example:<br />
<br />
<source lang="bash"><br />
$ cd /path/to/gpxe/src/<br />
$ make bin/10ec8167.rom<br />
</source><br />
<br />
And add it to the coreboot image. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add /path/to/gpxe/src/bin/10ec8167.rom pci10ec,8167.rom raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
As with VGA option ROMs, the gpxe option ROM may be compressed with LZMA. However, compression won't significantly reduce gpxe's size as it implements its own compression.<br />
<br />
In addition to gpxe, other option ROMs can be added in the same manner.<br />
<br />
== Adding sgabios support ==<br />
<br />
An [http://code.google.com/p/sgabios/ sgabios] option ROM can forward many VGA BIOS requests and keyboard events over a serial port. One can deploy it in addition to the primary VGA BIOS or by itself.<br />
<br />
If the target machine does not have a VGA adapter, then one should install sgabios. Most bootloaders (eg, GRUB) require a VGA BIOS in order to function properly &mdash; the sgabios ROM can fill this requirement.<br />
<br />
Place the sgabios ROM file in the '''vgaroms/''' directory of CBFS. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add /path/to/sgabios.bin vgaroms/sgabios.bin raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
When using sgabios, all the characters that SeaBIOS writes to the screen will be seen twice &mdash; once from SeaBIOS sending the character to the serial port and once from sgabios forwarding the character. To prevent the duplicates unset '''CONFIG_SCREEN_AND_DEBUG''' in '''make menuconfig'''.<br />
<br />
== Adding a graphical "bootsplash" image ==<br />
<br />
SeaBIOS can show a custom [http://en.wikipedia.org/wiki/JPEG JPEG] image during bootup. To enable this, add the JPEG file to flash with the name '''bootsplash.jpg'''. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add /path/to/image.jpg bootsplash.jpg raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
The size of the JPEG image determines the video mode to use for showing the image. Make sure the dimensions of the image exactly correspond to an available video mode (eg, 640x480, or 1024x768), otherwise it will not be displayed.<br />
<br />
SeaBIOS will show the image during the wait for the boot menu (if the boot menu has been disabled, users will not see the image). The image should probably have "Press F12 for boot menu" embedded in it so users know they can enter the normal SeaBIOS boot menu. By default, the boot menu prompt (and thus graphical image) is shown for 2.5 seconds. This can be customized by modifying SeaBIOS' '''CONFIG_BOOTMENU_WAIT''' in '''make menuconfig'''.<br />
<br />
The JPEG viewer in SeaBIOS uses a simplified decoding algorithm. It supports most common JPEGs, but does not support all possible formats. Please see the [[#Trouble reporting|Trouble reporting]] section if a valid image isn't displayed properly.<br />
<br />
== Adding payloads ==<br />
<br />
Most [[Payloads|payloads]] can also be launched from SeaBIOS. To add a payload, build the corresponding .elf file and then add it to the '''coreboot.rom''' file in the '''img/''' directory. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add-payload /path/to/payload.elf img/MyPayload l<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
During boot, one can press the '''F12''' key to get a boot menu. SeaBIOS will show all files in the '''img/''' directory, and one can instruct SeaBIOS to run them.<br />
<br />
SeaBIOS supports both uncompressed and LZMA compressed payloads.<br />
<br />
== Adding a floppy image ==<br />
<br />
It is possible to embed an image of a floppy in flash. SeaBIOS can then boot from and redirect floppy BIOS calls to the flash image. This is mainly useful for legacy software (such as DOS utilities). To use this feature, place a floppy image into the CBFS directory '''floppyimg/'''. For example:<br />
<br />
<source lang="bash"><br />
$ lzma -zc /path/to/myfloppy.img > myfloppy.img.lzma<br />
$ ./build/cbfstool coreboot.rom add myfloppy.img.lzma floppyimg/MyFloppy.lzma raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
Both uncompressed and LZMA compressed images are supported. Several floppy formats are available: 360K, 1.2MB, 720K, 1.44MB, 2.88MB, 160K, 180K, 320K.<br />
<br />
The floppy image will appear as writable to the system, however all writes are discarded on reboot.<br />
<br />
When using this system, SeaBIOS reserves high-memory to store the floppy. The reserved memory is then no longer available for OS use, so this feature should only be used when needed.<br />
<br />
== Configuring boot order ==<br />
<br />
Place a file in CBFS with the name '''bootorder''' to configure the boot up order. The file should be ASCII text and contain one line per boot method. The description of each boot method follows an [https://secure.wikimedia.org/wikipedia/en/wiki/Open_firmware Open Firmware] device path format. SeaBIOS will attempt to boot from each item in the file &mdash; first line of the file first.<br />
<br />
The easiest way to find the available boot methods is to look for "Searching bootorder for" in the SeaBIOS serial output. For example, one may see lines similar to:<br />
<br />
Searching bootorder for: /pci@i0cf8/*@f/drive@1/disk@0<br />
Searching bootorder for: /pci@i0cf8/*@f,1/drive@2/disk@1<br />
Searching bootorder for: /pci@i0cf8/usb@10,4/*@2<br />
<br />
The above represents the patterns SeaBIOS will search for in the bootorder file. However, it's safe to just copy and paste the pattern into bootorder. For example, the file:<br />
<br />
/pci@i0cf8/usb@10,4/*@2<br />
/pci@i0cf8/*@f/drive@1/disk@0<br />
<br />
will instruct SeaBIOS to attempt to boot from the given USB drive first and then attempt the given ATA harddrive second.<br />
<br />
Once a file has been created, add it to CBFS with the name '''bootorder'''. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add mybootlist.txt bootorder raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
= Trouble reporting =<br />
<br />
If you are experiencing problems with SeaBIOS, it's useful to increase the debugging level. This is done by running '''make menuconfig''' and setting '''CONFIG_DEBUG_LEVEL''' to a higher value. A debug level of 8 will show a lot of diagnostic information without flooding the serial port (levels above 8 will frequently cause too much data).<br />
<br />
To report an issue, please collect the serial boot log with SeaBIOS set to a debug level of 8 and forward the full log along with a description of the problem to the coreboot [[Mailinglist|mailing list]].</div>
Uwe
https://www.coreboot.org/index.php?title=SeaBIOS&diff=10818
SeaBIOS
2011-06-09T18:27:58Z
<p>Uwe: Small fixes.</p>
<hr />
<div>[http://www.seabios.org '''SeaBIOS'''] is an open-source legacy BIOS implementation which can be used as a coreboot [[Payloads|payload]]. It implements the standard [https://secure.wikimedia.org/wikipedia/en/wiki/BIOS BIOS] calling interfaces that a typical x86 proprietary BIOS implements.<br />
<br />
This page describes using SeaBIOS with coreboot. SeaBIOS can also run natively in [[QEMU]] and [http://bochs.sourceforge.net/ bochs] &mdash; see the [http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=README;hb=HEAD SeaBIOS README] file for information on non-coreboot uses.<br />
<br />
= Use cases =<br />
<br />
Any software requiring 16-bit BIOS services benefits from SeaBIOS (eg, Windows and DOS). SeaBIOS also enables booting Linux out of the box (using standard boot-loaders like GRUB and Syslinux).<br />
<br />
SeaBIOS supports booting from ATA hard drives, ATAPI CDROMs, USB hard drives, USB CDROMs, payloads in flash, and from [http://en.wikipedia.org/wiki/Option_ROM Option ROMs] (eg, SCSI or network cards). SeaBIOS can initialize and use a PS/2 keyboard or USB keyboard.<br />
<br />
== Windows ==<br />
<br />
SeaBIOS has been tested with Windows XP, Windows Vista (64/32 bit), and Windows 7 Beta (64 bit).<br />
<br />
However, Windows has a very strict ACPI interpreter, and many coreboot boards do not have a complete [[ACPI in coreboot|ACPI definition]]. As a result, many coreboot boards will fail during Windows boot (eg, it may fail with a '''STOP 0xA5''' code).<br />
<br />
So far [[ASUS M2V-MX SE]] and [[GIGABYTE GA-M57SLI-S4]] have known good working ACPI and are able to boot XP/Vista/Windows 7. Please ask on the [[Mailinglist|mailing list]] for the status of other boards/chipsets.<br />
<br />
== Linux ==<br />
<br />
SeaBIOS has been tested with GRUB, LILO, and Syslinux. Linux booting works well.<br />
<br />
== Other ==<br />
<br />
SeaBIOS has also been tested with FreeDOS, NetBSD, and OpenBSD.<br />
<br />
Because SeaBIOS implements the standard x86 BIOS interfaces, it is expected many other operating systems and boot-loaders will work.<br />
<br />
= Building =<br />
<br />
== Building via coreboot's menuconfig ==<br />
<br />
Probably the easiest way to use SeaBIOS as coreboot payload is to simply use the coreboot build process, which downloads and builds SeaBIOS as payload by default nowadays. You just have to run the following in your coreboot checkout:<br />
<br />
<source lang="bash"><br />
$ make menuconfig<br />
$ make<br />
</source><br />
<br />
Both SeaBIOS and coreboot will be built, and SeaBIOS will be added as payload to the '''coreboot.rom''' image that is being built.<br />
<br />
== Manual build ==<br />
<br />
One can download the latest version of SeaBIOS through a git repository:<br />
<br />
<source lang="bash"><br />
$ git clone git://git.seabios.org/seabios.git seabios<br />
$ cd seabios<br />
</source><br />
<br />
There's also a [http://code.coreboot.org/p/seabios/source/changes/master/ gitweb] facility to browse the latest source code online.<br />
<br />
Run '''make menuconfig''' and set the following variables:<br />
<br />
* CONFIG_COREBOOT 1<br />
* CONFIG_DEBUG_SERIAL 1<br />
<br />
Then:<br />
<br />
<source lang="bash"><br />
$ make<br />
</source><br />
<br />
The final SeaBIOS payload file is '''out/bios.bin.elf'''.<br />
<br />
== coreboot ==<br />
<br />
For best results, configure coreboot with '''CONFIG_WRITE_HIGH_TABLES''' and '''CONFIG_VGA_BRIDGE_SETUP''' both enabled, and '''CONFIG_VGA_ROM_RUN''' and '''CONFIG_PCI_ROM_RUN''' both disabled.<br />
<br />
Finally, configure the SeaBIOS '''out/bios.bin.elf''' file as the coreboot payload and build coreboot. The resulting '''coreboot.rom''' file will contain both SeaBIOS and coreboot, and it can be flashed to a ROM chip.<br />
<br />
= SeaBIOS and CBFS =<br />
<br />
SeaBIOS can read the coreboot flash filesystem and extract files.<br />
<br />
When SeaBIOS scans the target machine's PCI devices, it will recognize option ROMs in CBFS that have the form '''pciVVVV,DDDD.rom'''. It will also run any file in the directory '''vgaroms/''' as a VGA option ROM not specific to a device and files in '''genroms/''' as a generic option ROM not specific to a device. In the above cases, SeaBIOS will recognize files with a '''.lzma''' suffix, and automatically decompress them (eg, '''pci1106,3344.rom.lzma''' and '''vgaroms/sgabios.bin.lzma''').<br />
<br />
SeaBIOS can also load a graphical bootsplash image from '''bootsplash.jpg''', payloads found in the CBFS directory '''img/''', and floppy images found in the '''floppyimg/''' directory.<br />
<br />
Further, SeaBIOS can obtain configuration information from CBFS. A file '''bootorder''' determines the order of devices and methods to attempt to boot the system from.<br />
<br />
The examples below show some common uses of these features.<br />
<br />
== Adding a VGA option ROM ==<br />
<br />
It is frequently necessary to add a VGA option ROM to CBFS in order to use a VGA adapter that is built-in to a motherboard. Note, VGA adapters on external cards (PCI, AGP, PCIe) do not require this step as SeaBIOS will automatically extract the VGA BIOS directly from the card. For machines without a VGA adapter, please follow the [[#Adding sgabios support|sgabios instructions]] below.<br />
<br />
The first step is to find the vendor and device ID of the built-in VGA adapter. This information can be found from '''lspci''':<br />
<br />
<source lang="bash"><br />
$ lspci -vnn<br />
...<br />
01:00.0 VGA compatible controller [0300]: VIA Technologies, Inc. UniChrome Pro IGP ['''1106:3344'''] (rev 01) (prog-if 00 [VGA controller])<br />
</source><br />
<br />
In the above example, the VGA vendor/device ID is '''1106:3344'''. [[VGA support#How_to_retrieve_a_good_video_bios|Obtain the VGA ROM]] (eg, '''vgabios.bin''') and add it to the ROM with:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add /path/to/vgabios.bin pci1106,3344.rom raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
Alternatively, SeaBIOS supports LZMA compressed option ROMs. Use the following to add a compressed option ROM instead:<br />
<br />
<source lang="bash"><br />
$ lzma -zc /path/to/vgabios.bin > vgabios.bin.lzma<br />
$ ./build/cbfstool coreboot.rom add vgabios.bin.lzma pci1106,3344.rom.lzma raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
After the above is done, one can write the '''coreboot.rom''' file to flash. SeaBIOS will extract the VGA ROM and run it during boot.<br />
<br />
== Adding gpxe support ==<br />
<br />
A [[GPXE|gpxe]] option ROM can nicely complement SeaBIOS and coreboot by adding network boot support. Adding gpxe is similar to [[#Adding a VGA option ROM]]. The first step is to find the Ethernet vendor/device ID. For example:<br />
<br />
<source lang="bash"><br />
$ lspci -vnn<br />
...<br />
00:09.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8110SC/8169SC Gigabit Ethernet ['''10ec:8167'''] (rev 10)<br />
</source><br />
<br />
Then one can build a gpxe option ROM. For example:<br />
<br />
<source lang="bash"><br />
$ cd /path/to/gpxe/src/<br />
$ make bin/10ec8167.rom<br />
</source><br />
<br />
And add it to the coreboot image. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add /path/to/gpxe/src/bin/10ec8167.rom pci10ec,8167.rom raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
As with VGA option ROMs, the gpxe option ROM may be compressed with LZMA. However, compression won't significantly reduce gpxe's size as it implements its own compression.<br />
<br />
In addition to gpxe, other option ROMs can be added in the same manner.<br />
<br />
== Adding sgabios support ==<br />
<br />
An [http://code.google.com/p/sgabios/ sgabios] option ROM can forward many VGA BIOS requests and keyboard events over a serial port. One can deploy it in addition to the primary VGA BIOS or by itself.<br />
<br />
If the target machine does not have a VGA adapter, then one should install sgabios. Most bootloaders (eg, GRUB) require a VGA BIOS in order to function properly &mdash; the sgabios ROM can fill this requirement.<br />
<br />
Place the sgabios ROM file in the '''vgaroms/''' directory of CBFS. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add /path/to/sgabios.bin vgaroms/sgabios.bin raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
When using sgabios, all the characters that SeaBIOS writes to the screen will be seen twice &mdash; once from SeaBIOS sending the character to the serial port and once from sgabios forwarding the character. To prevent the duplicates unset '''CONFIG_SCREEN_AND_DEBUG''' in '''make menuconfig'''.<br />
<br />
== Adding a graphical "bootsplash" image ==<br />
<br />
SeaBIOS can show a custom [http://en.wikipedia.org/wiki/JPEG JPEG] image during bootup. To enable this, add the JPEG file to flash with the name '''bootsplash.jpg'''. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add /path/to/image.jpg bootsplash.jpg raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
The size of the JPEG image determines the video mode to use for showing the image. Make sure the dimensions of the image exactly correspond to an available video mode (eg, 640x480, or 1024x768), otherwise it will not be displayed.<br />
<br />
SeaBIOS will show the image during the wait for the boot menu (if the boot menu has been disabled, users will not see the image). The image should probably have "Press F12 for boot menu" embedded in it so users know they can enter the normal SeaBIOS boot menu. By default, the boot menu prompt (and thus graphical image) is shown for 2.5 seconds. This can be customized by modifying SeaBIOS' '''CONFIG_BOOTMENU_WAIT''' in '''make menuconfig'''.<br />
<br />
The JPEG viewer in SeaBIOS uses a simplified decoding algorithm. It supports most common JPEGs, but does not support all possible formats. Please see the [[#Trouble reporting|Trouble reporting]] section if a valid image isn't displayed properly.<br />
<br />
== Adding payloads ==<br />
<br />
Most [[Payloads|payloads]] can also be launched from SeaBIOS. To add a payload, build the corresponding .elf file and then add it to the '''coreboot.rom''' file in the '''img/''' directory. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add-payload /path/to/payload.elf img/MyPayload l<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
During boot, one can press the '''F12''' key to get a boot menu. SeaBIOS will show all files in the '''img/''' directory, and one can instruct SeaBIOS to run them.<br />
<br />
SeaBIOS supports both uncompressed and LZMA compressed payloads.<br />
<br />
== Adding a floppy image ==<br />
<br />
It is possible to embed an image of a floppy in flash. SeaBIOS can then boot from and redirect floppy BIOS calls to the flash image. This is mainly useful for legacy software (such as DOS utilities). To use this feature, place a floppy image into the CBFS directory '''floppyimg/'''. For example:<br />
<br />
<source lang="bash"><br />
$ lzma -zc /path/to/myfloppy.img > myfloppy.img.lzma<br />
$ ./build/cbfstool coreboot.rom add myfloppy.img.lzma floppyimg/MyFloppy.lzma raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
Both uncompressed and LZMA compressed images are supported. Several floppy formats are available: 360K, 1.2MB, 720K, 1.44MB, 2.88MB, 160K, 180K, 320K.<br />
<br />
The floppy image will appear as writable to the system, however all writes are discarded on reboot.<br />
<br />
When using this system, SeaBIOS reserves high-memory to store the floppy. The reserved memory is then no longer available for OS use, so this feature should only be used when needed.<br />
<br />
== Configuring boot order ==<br />
<br />
Place a file in CBFS with the name '''bootorder''' to configure the boot up order. The file should be ASCII text and contain one line per boot method. The description of each boot method follows an [https://secure.wikimedia.org/wikipedia/en/wiki/Open_firmware Open Firmware] device path format. SeaBIOS will attempt to boot from each item in the file &mdash; first line of the file first.<br />
<br />
The easiest way to find the available boot methods is to look for "Searching bootorder for" in the SeaBIOS serial output. For example, one may see lines similar to:<br />
<br />
Searching bootorder for: /pci@i0cf8/*@f/drive@1/disk@0<br />
Searching bootorder for: /pci@i0cf8/*@f,1/drive@2/disk@1<br />
Searching bootorder for: /pci@i0cf8/usb@10,4/*@2<br />
<br />
The above represents the patterns SeaBIOS will search for in the bootorder file. However, it's safe to just copy and paste the pattern into bootorder. For example, the file:<br />
<br />
/pci@i0cf8/usb@10,4/*@2<br />
/pci@i0cf8/*@f/drive@1/disk@0<br />
<br />
will instruct SeaBIOS to attempt to boot from the given USB drive first and then attempt the given ATA harddrive second.<br />
<br />
Once a file has been created, add it to CBFS with the name '''bootorder'''. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/cbfstool coreboot.rom add mybootlist.txt bootorder raw<br />
$ ./build/cbfstool coreboot.rom print<br />
</source><br />
<br />
= Trouble reporting =<br />
<br />
If you are experiencing problems with SeaBIOS, it's useful to increase the debugging level. This is done by running '''make menuconfig''' and setting '''CONFIG_DEBUG_LEVEL''' to a higher value. A debug level of 8 will show a lot of diagnostic information without flooding the serial port (levels above 8 will frequently cause too much data).<br />
<br />
To report an issue, please collect the serial boot log with SeaBIOS set to a debug level of 8 and forward the full log along with a description of the problem to the coreboot [[Mailinglist|mailing list]].</div>
Uwe
https://www.coreboot.org/index.php?title=ARM&diff=10817
ARM
2011-06-09T18:01:54Z
<p>Uwe: </p>
<hr />
<div></div>
Uwe
https://www.coreboot.org/index.php?title=ARM&diff=10816
ARM
2011-06-09T18:01:45Z
<p>Uwe: </p>
<hr />
<div></div>
Uwe
https://www.coreboot.org/index.php?title=Welcome_to_coreboot&diff=10815
Welcome to coreboot
2011-06-09T17:58:50Z
<p>Uwe: </p>
<hr />
<div><table width="100%" valign="top"><tr valign="top"><td width="80%"><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
'''coreboot''' is a Free Software project aimed at replacing the proprietary [http://wikipedia.org/wiki/BIOS BIOS] (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a [[Payloads|payload]].<br />
<br />
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly from firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like [[SeaBIOS | PC BIOS services]] or [[TianoCore | UEFI]]. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.<br />
<br />
coreboot currently supports over '''[[Supported Motherboards|230]]''' different mainboards. Check the [[Support]] page to see if your system is supported.<br />
<br />
<small><br />
coreboot was formerly known as [http://www.coreboot.org/pipermail/coreboot/2008-January/029133.html LinuxBIOS]. <br />
</small><br />
</div><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
coreboot recently switched to [[git]] and [http://review.coreboot.org gerrit] is now used as patch review tool.<br />
</div><br />
<br />
{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%<br />
|-<br />
|style="vertical-align:top"|<br />
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{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = yellow|<br />
WIDTH = 100%|<br />
ICON = <small>[[Benefits|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Benefits]]</span>|<br />
CONTENT =<br />
<small><br />
* 100% Free Software (GPL), no royalties, no license fees!<br />
* Fast boot times (3 seconds to Linux console)<br />
<!-- * Avoids the need for a slow/buggy/proprietary BIOS --><br />
<!-- * Runs in 32-Bit protected mode almost from the start --><br />
<!-- * Written in C, contains virtually no assembly code --><br />
* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]<br />
<!-- * Further features: netboot, serial console, remote flashing, ... --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = #d1adf6|<br />
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ICON = <small>[[Use Cases|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Use Cases]]</span>|<br />
CONTENT =<br />
<small><br />
* Desktop PCs, servers, [[Laptop|laptops]]<br />
* [[Clusters]]<br />
<!-- * Set-Top-Boxes, thin clients --><br />
* Embedded solutions<br />
<!-- * [http://en.wikipedia.org/wiki/Small_form_factor Small form factor computers], [http://en.wikipedia.org/wiki/Home_theater_PC Home-theater PCs] --><br />
<!-- * No-moving-parts solutions (ROM chip as "disk") --><br />
<!-- * Non-standard scenarios (e.g. FPGA in Opteron socket) --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = lime|<br />
WIDTH = 100%|<br />
ICON = <small>[[Payloads|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Payloads]]</span>|<br />
CONTENT =<br />
<small><br />
* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] <!-- / [[OpenFirmware]] / [[OpenBIOS]] --><br />
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] <!-- / [http://openbsd.org/ OpenBSD]--><br />
* [[Etherboot]] / [[GPXE]] / [[Payloads|...]]<br />
<!--* [[Memtest86]]<br />
* [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]--><br />
</small><br />
}}<br />
<br />
|}<br />
<br />
{| cellspacing=5 cellpadding=15 border=0 valign="top" width=100%<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_cb.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">About</span>'''<br /><small>Find out more about coreboot.</small><small><hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_devel.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Developers</span>'''<br /><small>Get involved! Help us make coreboot better.</small><small><hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://tracker.coreboot.org/trac/coreboot/browser/trunk Browse Source] | [[GSoC]] | [[Flag Days]] | [[Distributed and Automated Testsystem|Testsystem]]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_status.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Status</span>'''<br /><small>Find out whether your hardware is already supported.</small><small><hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [http://qa.coreboot.org Build Status]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_tools.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Related Tools</span>'''<br /><small>Tools and libraries related to coreboot.</small><small><hr />[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [[SerialICE]]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_101.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Getting Started</span>'''<br /><small>Download coreboot and get started.</small><small><hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_support.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Support</span>'''<br /><small>Learn how to contact us and find help and support.</small><small><hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|coreboot Options]]</small><br />
|}<br />
<br />
|}<br />
</td><td width="20%"><br />
<br />
[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]<br />
<br />
<br clear=all /><br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[http://blogs.coreboot.org News (blog)]</span>'''<hr /><br />
<small><br />
<rss max=5>http://blogs.coreboot.org/feed/</rss><br />
</small><br />
<br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[Current events|Upcoming Events]]</span>'''<hr /><br />
<!-- List of upcoming events (remove events after they have taken place). --><br />
<small><br />
<!-- * '''2011/mon/day:''' coreboot event at [[Link]] in somecity --><br />
* '''2011/05/11-14:''' coreboot and [[Flashrom|flashrom]] booths at [http://www.linuxtag.org/ LinuxTag] in Berlin<br />
* [[GSoC|2011 Google Summer of Code]]<br />
</small><br />
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<br />
<br clear=all /><br />
{{#widget:Ohloh Project|id=coreboot|type=partner_badge}}<br />
{{#widget:Ohloh Project|id=coreboot|type=cocomo}}<br />
<br />
<br />
</td></tr></table><br />
<br />
__NOTOC__<br />
__NOEDITSECTION__</div>
Uwe
https://www.coreboot.org/index.php?title=Git&diff=10814
Git
2011-06-09T17:54:46Z
<p>Uwe: /* Pushing changes */</p>
<hr />
<div>= Gerrit =<br />
As part of our move to [https://code.google.com/p/gerrit/ gerrit], [http://gitscm.com/ git] was introduced as primary SCM.<br />
<br />
== Register with gerrit ==<br />
For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br />
You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings.<br />
<br />
=== OpenID ===<br />
It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br />
<br />
== Gerrit workflow ==<br />
Gerrit interprets each Git commit as an individual change. Changes are autobuilt by [http://jenkins-ci.org/ Jenkins], and can be reviewed by developers. Once a change has gotten a positive review and has no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br />
<br />
Reviews grant points on a scale from -2 to 2. The meaning is:<br />
* -2: Do not merge (blocks gerrit from merging)<br />
* -1: I'd prefer you don't merge it<br />
* 0: neutral<br />
* +1: Looks good, but I won't make the last call on it<br />
* +2: Looks good, go ahead and merge (gerrit provides a "submit" function once it has a +2 vote)<br />
<br />
-2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br />
<br />
=== Gerrit and CLI ===<br />
Reviews normally happens through the website.<br />
<br />
Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br />
<br />
=== Gerrit and Email ===<br />
Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br />
<br />
This gateway will provide:<br />
* no patch submission mechanism ("git push" is CLI friendly)<br />
* patch review (maybe openpgp signed "Acked-by" mails)<br />
* patch submission (automatically with Acked-by?)<br />
* maybe patch rejection? (openpgp signed "Nacked-by" mails)<br />
<br />
= Anonymous read access =<br />
Read-only access is available anonymously:<br />
git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki><br />
<br />
= Authenticated read/write access =<br />
<br />
git clone ssh://<username>@review.coreboot.org:29418/coreboot<br />
<br />
Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br />
<br />
wget -O .git/hooks/commit-msg <nowiki>http://review.coreboot.org/tools/hooks/commit-msg</nowiki> && \<br />
chmod +x .git/hooks/commit-msg<br />
<br />
Alternatively, you could also just run<br />
<br />
make gitconfig<br />
<br />
= Working with Git =<br />
<br />
Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br />
<br />
== Commit messages ==<br />
Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br />
<br />
# The first line of the commit message has a short (less than 65 characters, absolute maximum is 75) summary<br />
# The second line is empty (no whitespace at all)<br />
# The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br />
# The next line is empty (no whitespace at all)<br />
# A Change-Id: line to let gerrit track this logical change<br />
# A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br />
<br />
Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running...<br />
<br />
make gitconfig<br />
<br />
...and remember to always use '''git commit -s''' to have git add your Signed-off-by: automatically.<br />
<br />
Here is an example of a well-formatted commit message:<br />
examplecomponent: Refactor duplicated setup into a function.<br />
<br />
Setting up the demo device correctly requires the exact same register<br />
values to be written into each of the PCI device functions. Moving the<br />
writes into a function allows also otherexamplecomponent to use them.<br />
<br />
Signed-off-by: Joe Hacker <joe@hacker.email><br />
<br />
The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|as mentioned above]], which adds a Change-Id: automatically when the commit message is saved.<br />
<br />
== Pushing changes ==<br />
First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see [[Git#Authenticated read/write access|Authenticated read/write access]] above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br />
<br />
git config remote.origin.url ssh://<username>@review.coreboot.org:29418/coreboot<br />
<br />
Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br />
<br />
git config remote.origin.push HEAD:refs/for/master<br />
<br />
After this, the command to push your changes is:<br />
<br />
git push origin<br />
<br />
If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br />
<br />
git config branch.<particularbranchname>.remote origin<br />
<br />
...after which you then push changes with any of the configured branches checked out with a simple:<br />
<br />
git push<br />
<br />
Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br />
<br />
'''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br />
<br />
git log origin/master..<br />
<br />
before '''git push''' to verify which commits you are about to send for review.<br />
<br />
For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of [http://review.coreboot.org/Documentation/user-upload.html#push_create this gerrit documentation].<br />
<br />
== Further Git reading ==<br />
There are tons of git tutorials out there. Take a look at some of these documents:<br />
* http://git-scm.com/<br />
* http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html<br />
* http://git.or.cz/course/svn.html<br />
* and in particular the [http://progit.org/ Pro Git book]<br />
<br />
Please also feel free to ask Git questions in the [[IRC|coreboot IRC channel]] or on the [[Mailinglist|mailing list]].<br />
<br />
= Browsing =<br />
<br />
There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br />
<!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --></div>
Uwe
https://www.coreboot.org/index.php?title=Git&diff=10813
Git
2011-06-09T17:44:56Z
<p>Uwe: /* Authenticated read/write access */ Mention "make gitconfig" in the resp. chapter.</p>
<hr />
<div>= Gerrit =<br />
As part of our move to [https://code.google.com/p/gerrit/ gerrit], [http://gitscm.com/ git] was introduced as primary SCM.<br />
<br />
== Register with gerrit ==<br />
For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br />
You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings.<br />
<br />
=== OpenID ===<br />
It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br />
<br />
== Gerrit workflow ==<br />
Gerrit interprets each Git commit as an individual change. Changes are autobuilt by [http://jenkins-ci.org/ Jenkins], and can be reviewed by developers. Once a change has gotten a positive review and has no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br />
<br />
Reviews grant points on a scale from -2 to 2. The meaning is:<br />
* -2: Do not merge (blocks gerrit from merging)<br />
* -1: I'd prefer you don't merge it<br />
* 0: neutral<br />
* +1: Looks good, but I won't make the last call on it<br />
* +2: Looks good, go ahead and merge (gerrit provides a "submit" function once it has a +2 vote)<br />
<br />
-2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br />
<br />
=== Gerrit and CLI ===<br />
Reviews normally happens through the website.<br />
<br />
Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br />
<br />
=== Gerrit and Email ===<br />
Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br />
<br />
This gateway will provide:<br />
* no patch submission mechanism ("git push" is CLI friendly)<br />
* patch review (maybe openpgp signed "Acked-by" mails)<br />
* patch submission (automatically with Acked-by?)<br />
* maybe patch rejection? (openpgp signed "Nacked-by" mails)<br />
<br />
= Anonymous read access =<br />
Read-only access is available anonymously:<br />
git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki><br />
<br />
= Authenticated read/write access =<br />
<br />
git clone ssh://<username>@review.coreboot.org:29418/coreboot<br />
<br />
Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br />
<br />
wget -O .git/hooks/commit-msg <nowiki>http://review.coreboot.org/tools/hooks/commit-msg</nowiki> && \<br />
chmod +x .git/hooks/commit-msg<br />
<br />
Alternatively, you could also just run<br />
<br />
make gitconfig<br />
<br />
= Working with Git =<br />
<br />
Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br />
<br />
== Commit messages ==<br />
Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br />
<br />
# The first line of the commit message has a short (less than 65 characters, absolute maximum is 75) summary<br />
# The second line is empty (no whitespace at all)<br />
# The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br />
# The next line is empty (no whitespace at all)<br />
# A Change-Id: line to let gerrit track this logical change<br />
# A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br />
<br />
Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running...<br />
<br />
make gitconfig<br />
<br />
...and remember to always use '''git commit -s''' to have git add your Signed-off-by: automatically.<br />
<br />
Here is an example of a well-formatted commit message:<br />
examplecomponent: Refactor duplicated setup into a function.<br />
<br />
Setting up the demo device correctly requires the exact same register<br />
values to be written into each of the PCI device functions. Moving the<br />
writes into a function allows also otherexamplecomponent to use them.<br />
<br />
Signed-off-by: Joe Hacker <joe@hacker.email><br />
<br />
The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|as mentioned above]], which adds a Change-Id: automatically when the commit message is saved.<br />
<br />
== Pushing changes ==<br />
First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see [[#Authenticated read/write access]] above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br />
<br />
git config remote.origin.url ssh://<username>@review.coreboot.org:29418/coreboot<br />
<br />
Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br />
<br />
git config remote.origin.push HEAD:refs/for/master<br />
<br />
After this, the command to push your changes is:<br />
<br />
git push origin<br />
<br />
If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br />
<br />
git config branch.<particularbranchname>.remote origin<br />
<br />
...after which you then push changes with any of the configured branches checked out with a simple:<br />
<br />
git push<br />
<br />
Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br />
<br />
'''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br />
<br />
git log origin/master..<br />
<br />
before '''git push''' to verify which commits you are about to send for review.<br />
<br />
For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of [http://review.coreboot.org/Documentation/user-upload.html#push_create this gerrit documentation].<br />
<br />
== Further Git reading ==<br />
There are tons of git tutorials out there. Take a look at some of these documents:<br />
* http://git-scm.com/<br />
* http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html<br />
* http://git.or.cz/course/svn.html<br />
* and in particular the [http://progit.org/ Pro Git book]<br />
<br />
Please also feel free to ask Git questions in the [[IRC|coreboot IRC channel]] or on the [[Mailinglist|mailing list]].<br />
<br />
= Browsing =<br />
<br />
There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br />
<!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --></div>
Uwe
https://www.coreboot.org/index.php?title=Git&diff=10812
Git
2011-06-09T17:43:47Z
<p>Uwe: Random fixes.</p>
<hr />
<div>= Gerrit =<br />
As part of our move to [https://code.google.com/p/gerrit/ gerrit], [http://gitscm.com/ git] was introduced as primary SCM.<br />
<br />
== Register with gerrit ==<br />
For authenticated access (to submit patches) you'll need a gerrit account which you can register at http://review.coreboot.org/.<br />
You also need to add your ssh key(s) (used for authenticating your connections to the repo) and your email address(es) (used to match up Signed-off-by: statements) to your gerrit user data at http://review.coreboot.org/#settings.<br />
<br />
=== OpenID ===<br />
It seems that gerrit is picky about the OpenID format. Always provide a full URL, including protocol (ie. http:// or https:// prefix). Unfortunately the error messages are non-intuitive.<br />
<br />
== Gerrit workflow ==<br />
Gerrit interprets each Git commit as an individual change. Changes are autobuilt by [http://jenkins-ci.org/ Jenkins], and can be reviewed by developers. Once a change has gotten a positive review and has no build issues, it is applied to the master branch. Thus, no developer directly pushes to master.<br />
<br />
Reviews grant points on a scale from -2 to 2. The meaning is:<br />
* -2: Do not merge (blocks gerrit from merging)<br />
* -1: I'd prefer you don't merge it<br />
* 0: neutral<br />
* +1: Looks good, but I won't make the last call on it<br />
* +2: Looks good, go ahead and merge (gerrit provides a "submit" function once it has a +2 vote)<br />
<br />
-2 and +2 are only available to core developers as it's comparable to commit rights in SVN.<br />
<br />
=== Gerrit and CLI ===<br />
Reviews normally happens through the website.<br />
<br />
Since gerrit exposes an interface through its ssh daemon, it's also possible to do reviews from CLI or mail. Unfortunately there doesn't seem to be any standing tradition on how to build a workflow around these parts, so we'll document our best practices here once they settled.<br />
<br />
=== Gerrit and Email ===<br />
Gerrit has poor email integration (in fact, it doesn't really have any at all). We send a couple of notifications to the mailing list, but that is a coreboot specific extension. Peter intends to build a mail-to-gerrit gateway should the need arise.<br />
<br />
This gateway will provide:<br />
* no patch submission mechanism ("git push" is CLI friendly)<br />
* patch review (maybe openpgp signed "Acked-by" mails)<br />
* patch submission (automatically with Acked-by?)<br />
* maybe patch rejection? (openpgp signed "Nacked-by" mails)<br />
<br />
= Anonymous read access =<br />
Read-only access is available anonymously:<br />
git clone <nowiki>http://review.coreboot.org/p/coreboot</nowiki><br />
<br />
= Authenticated read/write access =<br />
git clone ssh://<username>@review.coreboot.org:29418/coreboot<br />
<br />
Inside the checkout you should install the commit-msg hook which prepares commit messages to fit the style required by gerrit. This needs to happen only once per clone and can be done with<br />
wget -O .git/hooks/commit-msg <nowiki>http://review.coreboot.org/tools/hooks/commit-msg</nowiki> && \<br />
chmod +x .git/hooks/commit-msg<br />
<br />
= Working with Git =<br />
<br />
Git is a distributed version control system. This means that you can manage commits and branches completely without restriction in your local clone of the coreboot repository. Peter wrote [http://www.coreboot.org/pipermail/coreboot/2011-June/065427.html a Git introduction] after the switch to Git had been announced on the mailing list.<br />
<br />
== Commit messages ==<br />
Git does not enforce a commit message style, although perhaps it should. For all aspects of Git to work the best, it's important to follow these simple guidelines for commit messages:<br />
<br />
# The first line of the commit message has a short (less than 65 characters, absolute maximum is 75) summary<br />
# The second line is empty (no whitespace at all)<br />
# The third and any number of following lines contain a longer description of the commit as is neccessary, including relevant background information and quite possibly rationale for why the issue was solved in this particular way. These lines should never be longer than 75 characters.<br />
# The next line is empty (no whitespace at all)<br />
# A Change-Id: line to let gerrit track this logical change<br />
# A Signed-off-by: line according to [[Development_Guidelines#Sign-off_Procedure|the development guidelines]]<br />
<br />
Please do not create Change-Id: and Signed-off-by: manually because it is boring and error-prone. Instead, please install the commit-msg hook as described [[#Authenticated_read/write_access|above]] or by running...<br />
<br />
make gitconfig<br />
<br />
...and remember to always use '''git commit -s''' to have git add your Signed-off-by: automatically.<br />
<br />
Here is an example of a well-formatted commit message:<br />
examplecomponent: Refactor duplicated setup into a function.<br />
<br />
Setting up the demo device correctly requires the exact same register<br />
values to be written into each of the PCI device functions. Moving the<br />
writes into a function allows also otherexamplecomponent to use them.<br />
<br />
Signed-off-by: Joe Hacker <joe@hacker.email><br />
<br />
The example is missing a Change-Id: line. This is OK because Joe Hacker has set up the commit-msg hook [[#Authenticated_read/write_access|as mentioned above]], which adds a Change-Id: automatically when the commit message is saved.<br />
<br />
== Pushing changes ==<br />
First ensure that the git remote you want to use for pushing refers to an ssh:// URL (see [[#Authenticated read/write access]] above). If you need to change this after the fact, ie. if you registered on gerrit only after having cloned anonymously, you can. Assuming that your remote is called ''origin'' (this is the default) you can run:<br />
<br />
git config remote.origin.url ssh://<username>@review.coreboot.org:29418/coreboot<br />
<br />
Then run the following command once, to tell git that by default you want to submit all commits in the currently checked-out branch for review on gerrit:<br />
<br />
git config remote.origin.push HEAD:refs/for/master<br />
<br />
After this, the command to push your changes is:<br />
<br />
git push origin<br />
<br />
If you always push from the same or a few branches the workflow can be simplified further by running once for each branch:<br />
<br />
git config branch.<particularbranchname>.remote origin<br />
<br />
...after which you then push changes with any of the configured branches checked out with a simple:<br />
<br />
git push<br />
<br />
Pushing several commits not yet in the coreboot repository at once will create one review request on gerrit per commit. <br />
<br />
'''NB!''' If you have applied patches from gerrit on a branch and you later push that branch, gerrit will think that you are submitting new versions of the patches that you had applied. This may or may not be what you intend. You can always run<br />
<br />
git log origin/master..<br />
<br />
before '''git push''' to verify which commits you are about to send for review.<br />
<br />
For automating patch submission further (ie. more ways of simplifying the command line), see the last paragraph of [http://review.coreboot.org/Documentation/user-upload.html#push_create this gerrit documentation].<br />
<br />
== Further Git reading ==<br />
There are tons of git tutorials out there. Take a look at some of these documents:<br />
* http://git-scm.com/<br />
* http://www.kernel.org/pub/software/scm/git/docs/v1.7.5.4/gittutorial.html<br />
* http://git.or.cz/course/svn.html<br />
* and in particular the [http://progit.org/ Pro Git book]<br />
<br />
Please also feel free to ask Git questions in the [[IRC|coreboot IRC channel]] or on the [[Mailinglist|mailing list]].<br />
<br />
= Browsing =<br />
<br />
There is no code browser that's properly synced with our gerrit instance at this time. This is a work in progress.<br />
<!-- You can browse the coreboot git repository on [http://code.coreboot.org/p/coreboot-git/source/tree/master/ code.coreboot.org], our indefero system. --></div>
Uwe
https://www.coreboot.org/index.php?title=Superiotool&diff=10772
Superiotool
2011-06-03T20:38:46Z
<p>Uwe: Partial update to r6543: Nuvoton WPCM450, ITE IT8721F, NSC PC87382, ITE IT8720F, SMSC MEC1308, NSC PC87364, W83627DHG-P/-PT, Nuvoton NCT6776F (B/C).</p>
<hr />
<div>'''Superiotool''' is a GPL'd user-space helper tool for coreboot development purposes (but may also be useful for other things). It allows you to detect which [[wikipedia:Super I/O|Super I/O]] you have on your mainboard, and it can provide detailed information about the register contents of the Super I/O.<br />
<br />
This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.<br />
<br />
<gallery><br />
Image:Ite it8705f.jpg|<small>ITE IT8705F</small><br />
Image:Winbond w83977ef.jpg|<small>Winbond W83977EF</small><br />
</gallery><br />
<br />
== Support of various devices ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M1535/M1535D/M1535+/M1535D+<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/048024.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5105<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5107<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5109<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5113<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5119<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M512x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513x<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513xB<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513xF<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M514x<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-September/024916.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-July/050471.html 2], [http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html 3]<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71862FG / F71863FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71889<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71872F/FG / F71806F/FG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71882FG/F71883FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040016.html 1], [http://www.flashrom.org/pipermail/flashrom/2010-August/004390.html 2]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-November/026831.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F8000<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C711<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C712<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C721<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C735<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8228E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8502E/F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8510E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8511E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8512E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8661F/IT8770F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://article.gmane.org/gmane.linux.bios/42100/ 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F/IT8687R<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2010-May/058010.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT86793<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8702F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8703F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8705F/AF / IT8700F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026913.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8706R<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8708F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024879.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8710F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8711F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 2]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024884.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8720F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8721F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8722F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8726F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8761E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8780F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| HMC<br />
| HMC83755<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Holtek<br />
| HT6552IR<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS307<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS308<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS309<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS317<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS338<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS351<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97307<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/047843.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87309<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87360<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026991.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87351<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87364<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87365<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87363<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87366<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87382<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8739x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/043447.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87591x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8741x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87372<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8374L<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071014/19fe07aa/attachment-0001.htm 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87427<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87373<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| WPCE775x / NPCE781x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| WPCM450<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| NCT6776F (B)<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Nuvoton<br />
| NCT6776F (C)<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xFR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N971<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-July/003832.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N972<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N252<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-June/050276.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M172<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xAPM<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C67x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B80x/FDC37M707<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N958FR<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027036.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B77x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B78x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M602<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M60x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B72x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M81x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B27x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027245.html 1]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027248.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B37x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47U33x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B34x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S42x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M10x/112/13x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025451.html 1] <br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B357<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M14x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M15x/192/997<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-December/028269.html 1]<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-February/030897.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S45x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M292<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B387<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B397<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M182<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M584<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| MEC1308<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| DME1737<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5504<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N217<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5514D-NS<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3112<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3114<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3116<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5317<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5027<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH4307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669FR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N237<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N769<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024883.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N3869/FDC37N869<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N227<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025846.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SIO10N268<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C665GT/IR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C666GT<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SIS6801<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SIS950<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686A/VT82C686B<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977CTF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977EF/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040507.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83527HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627SF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697HF/F/HG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-August/004443.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83L517D/D-F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83637HF/HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627THF/THG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment.txt 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025599.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-August/037685.html 3], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 4]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment-0001.txt 1]<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627DHG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-January/029517.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627DHG-P/-PT<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627UHG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83667HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977F-A/G-A/AF-A/AG-A<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977AF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977TF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627HF/F/HG/G<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025453.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025592.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697SF/UF/UG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025914.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627EHF/EF/EHG/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024887.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025284.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-January/029416.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877AF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-February/002119.html]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877TF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| WPCD376I<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-October/053894.html 1]<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM82C862<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8663BF<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8669<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8670<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|}<br />
<br />
|}<br />
<br />
'''Extended dumps (EC, HWM) available for:'''<br />
<br />
Use the '''--extra-dump''' option to see the contents of these registers.<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 1]<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond<br />
| W83627THF/THG HWM<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMSC<br />
| LPC47N227 runtime register block<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
<br />
<small><br />
<sup>1</sup> Previosly National Semiconductor, now bought by Winbond.<br /><br />
<sup>2</sup> Register dump output from a running coreboot system (vs. proprietary BIOS).<br /><br />
</small><br />
<br />
== Installation ==<br />
<br />
'''Manual installation'''<br />
<br />
$ svn co svn://coreboot.org/coreboot/trunk/util/superiotool<br />
$ cd superiotool<br />
$ make<br />
$ sudo make install<br />
<br />
'''Debian / Ubuntu'''<br />
<br />
$ apt-get install superiotool<br />
<br />
'''Fedora'''<br />
<br />
$ yum install superiotool<br />
<br />
== Usage ==<br />
<br />
Probe/detect the Super I/O in your mainboard:<br />
<br />
$ superiotool<br />
<br />
Register dump as table of hex-values (if the Super I/O is detected):<br />
<br />
$ superiotool -d<br />
<br />
Please see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool/README README] for further information.<br />
<br />
{{GPL}}</div>
Uwe
https://www.coreboot.org/index.php?title=Developer_Manual&diff=10750
Developer Manual
2011-05-16T13:25:59Z
<p>Uwe: /* View From The CPU: Intel Architecture */ Fix typo.</p>
<hr />
<div></div>
Uwe
https://www.coreboot.org/index.php?title=SeaBIOS&diff=10297
SeaBIOS
2011-01-03T18:25:17Z
<p>Uwe: Various fixes, esp. location of cbfstool.</p>
<hr />
<div>[http://www.seabios.org '''SeaBIOS'''] is an open-source legacy BIOS implementation which can be used as a coreboot [[Payloads|payload]]. It implements the standard BIOS calling interfaces that a typical x86 proprietary BIOS implements.<br />
<br />
This page describes using SeaBIOS with coreboot. SeaBIOS can also run natively in [[QEMU]] and bochs &mdash; see the [http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=README;hb=HEAD SeaBIOS README] file for information on non-coreboot uses.<br />
<br />
= Use cases =<br />
<br />
Any software requiring 16-bit BIOS services benefits from SeaBIOS (eg, Windows and DOS). SeaBIOS also enables booting Linux out of the box (using standard boot-loaders like GRUB and Syslinux).<br />
<br />
SeaBIOS supports booting from ATA hard drives, ATAPI CDROMs, USB hard drives, USB CDROMs, payloads in flash, and from [http://en.wikipedia.org/wiki/Option_ROM Option ROMs] (eg, SCSI or network cards). SeaBIOS can initialize and use a PS/2 keyboard or USB keyboard.<br />
<br />
== Windows ==<br />
<br />
SeaBIOS has been tested with Windows XP, Windows Vista (64/32 bit), and Windows 7 Beta (64 bit).<br />
<br />
However, Windows has a very strict ACPI interpreter, and many coreboot boards do not have a complete [[ACPI in coreboot|ACPI definition]]. As a result, many coreboot boards will fail during Windows boot (eg, it may fail with a '''STOP 0xA5''' code).<br />
<br />
So far [[ASUS M2V-MX SE]] and [[GIGABYTE GA-M57SLI-S4]] have known good working ACPI and are able to boot XP/Vista/Windows 7. Please ask on the [[Mailinglist|mailing list]] for the status of other boards/chipsets.<br />
<br />
== Linux ==<br />
<br />
SeaBIOS has been tested with GRUB, LILO, and Syslinux. Linux booting works well.<br />
<br />
== Other ==<br />
<br />
SeaBIOS has also been tested with FreeDOS, NetBSD, and OpenBSD.<br />
<br />
Because SeaBIOS implements the standard x86 BIOS interfaces, it is expected many other operating systems and boot-loaders will work.<br />
<br />
= Building =<br />
<br />
== Building via coreboot's menuconfig ==<br />
<br />
Probably the easiest way to use SeaBIOS as coreboot payload is to simply use the coreboot build process, which downloads and builds SeaBIOS as payload by default nowadays. You just have to run the following in your coreboot checkout:<br />
<br />
<source lang="bash"><br />
$ make menuconfig<br />
$ make<br />
</source><br />
<br />
Both SeaBIOS and coreboot will be built, and SeaBIOS will be added as payload to the '''coreboot.rom''' image that is being built.<br />
<br />
== Manual build ==<br />
<br />
One can download the latest version of SeaBIOS through a git repository:<br />
<br />
<source lang="bash"><br />
$ git clone git://git.linuxtogo.org/home/kevin/seabios.git seabios<br />
$ cd seabios<br />
</source><br />
<br />
There's also a [http://git.linuxtogo.org/?p=kevin/seabios.git;a=summary gitweb] facility to browse the latest source code online.<br />
<br />
Edit '''src/config.h''' and set the following values:<br />
<br />
<source lang="C"><br />
#define CONFIG_COREBOOT 1<br />
#define CONFIG_DEBUG_SERIAL 1<br />
#define CONFIG_VGAHOOKS 1<br />
</source><br />
<br />
Then:<br />
<br />
<source lang="bash"><br />
$ make<br />
</source><br />
<br />
The final SeaBIOS payload file is '''out/bios.bin.elf'''.<br />
<br />
=== Compiled SeaBIOS images ===<br />
<br />
It is also possible to download a compiled SeaBIOS image. The latest released version compiled for coreboot is: http://www.linuxtogo.org/~kevin/SeaBIOS/bios.bin.elf-0.6.1<br />
<br />
Other versions are also available at: http://www.linuxtogo.org/~kevin/SeaBIOS/<br />
<br />
== coreboot ==<br />
<br />
For best results, configure coreboot with CONFIG_WRITE_HIGH_TABLES and CONFIG_VGA_BRIDGE_SETUP both enabled, and CONFIG_VGA_ROM_RUN and CONFIG_PCI_ROM_RUN both disabled.<br />
<br />
Finally, configure the SeaBIOS '''out/bios.bin.elf''' file as the coreboot payload and build coreboot. The resulting '''coreboot.rom''' file will contain both SeaBIOS and coreboot, and it can be flashed to a ROM chip.<br />
<br />
= SeaBIOS and CBFS =<br />
<br />
SeaBIOS can read the coreboot flash filesystem and extract files.<br />
<br />
When SeaBIOS scans the target machine's PCI devices, it will recognize option ROMs in CBFS that have the form '''pciVVVV,DDDD.rom'''. It will also run any file in the directory '''vgaroms/''' as a VGA option ROM not specific to a device and files in '''genroms/''' as a generic option ROM not specific to a device. In the above cases, SeaBIOS will recognize files with a '''.lzma''' suffix, and automatically decompress them (eg, '''pci1106,3344.rom.lzma''' and '''vgaroms/sgabios.bin.lzma''').<br />
<br />
SeaBIOS can also load a graphical bootsplash image from '''bootsplash.jpg''', payloads found in the CBFS directory '''img/''', and floppy images found in the '''floppyimg/''' directory.<br />
<br />
The examples below show some common uses of this feature.<br />
<br />
== Adding a VGA option ROM ==<br />
<br />
It is frequently necessary to add a VGA option ROM to CBFS in order to use a VGA adapter that is built-in to a motherboard. Note, VGA adapters on external cards (PCI, AGP, PCIe) do not require this step as SeaBIOS will automatically extract the VGA BIOS directly from the card. For machines without a VGA adapter, please follow the [[#Adding sgabios support|sgabios instructions]] below.<br />
<br />
The first step is to find the vendor and device ID of the built-in VGA adapter. This information can be found from '''lspci''':<br />
<br />
<source lang="bash"><br />
$ lspci -vnn<br />
...<br />
01:00.0 VGA compatible controller [0300]: VIA Technologies, Inc. UniChrome Pro IGP ['''1106:3344'''] (rev 01) (prog-if 00 [VGA controller])<br />
</source><br />
<br />
In the above example, the VGA vendor/device ID is '''1106:3344'''. [[VGA support#How_to_retrieve_a_good_video_bios|Obtain the VGA ROM]] (eg, '''vgabios.bin''') and add it to the ROM with:<br />
<br />
<source lang="bash"><br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add /path/to/vgabios.bin pci1106,3344.rom raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
Alternatively, SeaBIOS supports LZMA compressed option ROMs. Use the following to add a compressed option ROM instead:<br />
<br />
<source lang="bash"><br />
$ lzma -zc /path/to/vgabios.bin > vgabios.bin.lzma<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add vgabios.bin.lzma pci1106,3344.rom.lzma raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
After the above is done, one can write the '''coreboot.rom''' file to flash. SeaBIOS will extract the VGA ROM and run it during boot.<br />
<br />
== Adding gpxe support ==<br />
<br />
A [[GPXE|gpxe]] option ROM can nicely complement SeaBIOS and coreboot by adding network boot support. Adding gpxe is similar to [[#Adding a VGA option ROM]]. The first step is to find the Ethernet vendor/device ID. For example:<br />
<br />
<source lang="bash"><br />
$ lspci -vnn<br />
...<br />
00:09.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8110SC/8169SC Gigabit Ethernet ['''10ec:8167'''] (rev 10)<br />
</source><br />
<br />
Then one can build a gpxe option ROM. For example:<br />
<br />
<source lang="bash"><br />
$ cd /path/to/gpxe/src/<br />
$ make bin/10ec8167.rom<br />
</source><br />
<br />
And add it to the coreboot image. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add /path/to/gpxe/src/bin/10ec8167.rom pci10ec,8167.rom raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
As with VGA option ROMs, the gpxe option ROM may be compressed with LZMA. However, compression won't significantly reduce gpxe's size as it implements its own compression.<br />
<br />
In addition to gpxe, other option ROMs can be added in the same manner.<br />
<br />
== Adding sgabios support ==<br />
<br />
An [http://code.google.com/p/sgabios/ sgabios] option ROM can forward many VGA BIOS requests and keyboard events over a serial port. One can deploy it in addition to the primary VGA BIOS or by itself.<br />
<br />
If the target machine does not have a VGA adapter, then one should install sgabios. Most bootloaders (eg, GRUB) require a VGA BIOS in order to function properly &mdash; the sgabios ROM can fill this requirement.<br />
<br />
The current version of sgabios (as of 20090617) does not implement a proper checksum. As a work around, a tool from the SeaBIOS source repo can fix the checksum:<br />
<source lang="bash"><br />
$ /path/to/seabios/tools/buildrom.py /path/to/sgabios.bin sgabios-fixed.bin<br />
</source><br />
<br />
Once the above is done, place the ROM file in the '''vgaroms/''' directory of CBFS. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add sgabios-fixed.bin vgaroms/sgabios.bin raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
When using sgabios, all the characters that SeaBIOS writes to the screen will be seen twice &mdash; once from SeaBIOS sending the character to the serial port and once from sgabios forwarding the character. To prevent the duplicates one can edit the SeaBIOS '''src/config.h''' file and set the following:<br />
<br />
<source lang="C"><br />
#define CONFIG_SCREEN_AND_DEBUG 0<br />
</source><br />
<br />
== Adding a graphical "bootsplash" image ==<br />
<br />
SeaBIOS can show a custom [http://en.wikipedia.org/wiki/JPEG JPEG] image during bootup. To enable this, add the JPEG file to flash with the name '''bootsplash.jpg'''. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add /path/to/image.jpg bootsplash.jpg raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
The size of the JPEG image determines the video mode to use for showing the image. Make sure the dimensions of the image exactly correspond to an available video mode (eg, 640x480, or 1024x768), otherwise it will not be displayed.<br />
<br />
SeaBIOS will show the image during the wait for the boot menu (if the boot menu has been disabled, users will not see the image). The image should probably have "Press F12 for boot menu" embedded in it so users know they can enter the normal SeaBIOS boot menu. By default, the boot menu prompt (and thus graphical image) is shown for 2.5 seconds. This can be customized by modifying SeaBIOS' '''src/config.h''' file and changing the '''CONFIG_BOOTMENU_WAIT''' setting.<br />
<br />
The JPEG viewer in SeaBIOS uses a simplified decoding algorithm. It supports most common JPEGs, but does not support all possible formats. Please see the [[#Trouble reporting]] section if a valid image isn't displayed properly.<br />
<br />
== Adding payloads ==<br />
<br />
Most [[Payloads|payloads]] can also be launched from SeaBIOS. To add a payload, build the corresponding .elf file and then add it to the '''coreboot.rom''' file in the '''img/''' directory. For example:<br />
<br />
<source lang="bash"><br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add-payload /path/to/payload.elf img/MyPayload l<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
During boot, one can press the '''F12''' key to get a boot menu. SeaBIOS will show all files in the '''img/''' directory, and one can instruct SeaBIOS to run them.<br />
<br />
SeaBIOS supports both uncompressed and LZMA compressed payloads.<br />
<br />
== Adding a floppy image ==<br />
<br />
It is possible to embed an image of a floppy in flash. SeaBIOS can then boot from and redirect floppy BIOS calls to the flash image. This is mainly useful for legacy software (such as DOS utilities). To use this feature, place a floppy image into the CBFS directory '''floppyimg/'''. For example:<br />
<br />
<source lang="bash"><br />
$ lzma -zc /path/to/myfloppy.img > myfloppy.img.lzma<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom add myfloppy.img.lzma floppyimg/MyFloppy.lzma raw<br />
$ ./build/util/cbfstool/cbfstool coreboot.rom print<br />
</source><br />
<br />
Both uncompressed and LZMA compressed images are supported. Several floppy formats are available: 360K, 1.2MB, 720K, 1.44MB, 2.88MB, 160K, 180K, 320K.<br />
<br />
The floppy image will appear as writable to the system, however all writes are discarded on reboot.<br />
<br />
When using this system, SeaBIOS reserves high-memory to store the floppy. The reserved memory is then no longer available for OS use, so this feature should only be used when needed.<br />
<br />
= Trouble reporting =<br />
<br />
If you are experiencing problems with SeaBIOS, it's useful to increase the debugging level. This is done by editing the '''src/config.h''' file and setting the debug level to a higher number (for example '''8'''):<br />
<br />
<source lang="C"><br />
#define CONFIG_DEBUG_LEVEL 8<br />
</source><br />
<br />
A debug level of 8 will show a lot of diagnostic information without flooding the serial port (levels above 8 will frequently cause too much data).<br />
<br />
To report an issue, please collect the serial boot log with SeaBIOS set to a debug level of 8 and forward the full log along with a description of the problem to the coreboot [[Mailinglist|mailing list]].</div>
Uwe
https://www.coreboot.org/index.php?title=Datasheets&diff=10293
Datasheets
2011-01-01T15:47:48Z
<p>Uwe: /* AMD */ AMD SB810/SB850</p>
<hr />
<div></div>
Uwe
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=10249
Board:gigabyte/ga-6bxc
2010-12-24T11:56:40Z
<p>Uwe: </p>
<hr />
<div>This page describes how to use coreboot on the [http://www.gigabyte.com/products/product-page.aspx?pid=1445 GIGABYTE GA-6BXC] mainboard.<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = WIP<br />
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it. <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = WIP<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = Tested: PCI NIC in all PCI slots.<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = WIP<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PP_comments = Doing '''modprobe ppdev''' seems to work, everything else is untested.<br />
|PS2_keyboard_status = WIP<br />
|PS2_keyboard_comments = Doesn't seem to work, yet. This is being investigated.<br />
|PS2_mouse_status = WIP<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|Watchdog_status = N/A<br />
|SMBus_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = N/A<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There is no ACPI implementation for this board, yet.<br />
|Reboot_status = OK<br />
|Poweroff_status = No<br />
|Poweroff_comments = Needs ACPI.<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off.<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
Uwe
https://www.coreboot.org/index.php?title=Welcome_to_coreboot&diff=10246
Welcome to coreboot
2010-12-20T23:54:37Z
<p>Uwe: Intel Poulsbo/SCH/Atom & iWave iW-RainboW-G6 support</p>
<hr />
<div><table width="100%" valign="top"><tr valign="top"><td width="80%"><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
'''coreboot''' (formerly known as LinuxBIOS) is a Free Software project aimed at replacing the proprietary BIOS (firmware) you can find in most of today's computers. It performs just a little bit of hardware initialization and then executes a so-called [[Payloads|payload]].<br />
<br />
<small><br />
With this separation of hardware initialization and later boot logic, coreboot can scale from specialized applications run directly from firmware, operating systems in flash, and custom bootloaders to implementations of firmware standards like PCBIOS and EFI without having to carry features not necessary in the target application, reducing the amount of code and flash space required.<br />
</small><br />
<br />
We currently support '''[[Supported Motherboards|230]]''' different mainboards.<br />
</div><br />
<br />
{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%<br />
|-<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = yellow|<br />
WIDTH = 100%|<br />
ICON = <small>[[Benefits|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Benefits]]</span>|<br />
CONTENT =<br />
<small><br />
* 100% Free Software (GPL), no royalties, no license fees!<br />
* Fast boot times (3 seconds to Linux console)<br />
<!-- * Avoids the need for a slow/buggy/proprietary BIOS --><br />
<!-- * Runs in 32-Bit protected mode almost from the start --><br />
<!-- * Written in C, contains virtually no assembly code --><br />
* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]<br />
<!-- * Further features: netboot, serial console, remote flashing, ... --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = #d1adf6|<br />
WIDTH = 100%|<br />
ICON = <small>[[Use Cases|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Use Cases]]</span>|<br />
CONTENT =<br />
<small><br />
* Desktop PCs, servers, [[Laptop|laptops]]<br />
* [[Clusters]]<br />
<!-- * Set-Top-Boxes, thin clients --><br />
* Embedded solutions<br />
<!-- * [http://en.wikipedia.org/wiki/Small_form_factor Small form factor computers], [http://en.wikipedia.org/wiki/Home_theater_PC Home-theater PCs] --><br />
<!-- * No-moving-parts solutions (ROM chip as "disk") --><br />
<!-- * Non-standard scenarios (e.g. FPGA in Opteron socket) --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = lime|<br />
WIDTH = 100%|<br />
ICON = <small>[[Payloads|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Payloads]]</span>|<br />
CONTENT =<br />
<small><br />
* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] <!-- / [[OpenFirmware]] / [[OpenBIOS]] --><br />
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] <!-- / [http://openbsd.org/ OpenBSD]--><br />
* [[Etherboot]] / [[GPXE]] / [[Payloads|...]]<br />
<!--* [[Memtest86]]<br />
* [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]--><br />
</small><br />
}}<br />
<br />
|}<br />
<br />
{| cellspacing=5 cellpadding=15 border=0 valign="top" width=100%<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_cb.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">About</span>'''<br /><small>Find out more about coreboot.</small><small><hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_devel.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Developers</span>'''<br /><small>Get involved! Help us make coreboot better.</small><small><hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://tracker.coreboot.org/trac/coreboot/browser/trunk Browse Source] | [[GSoC]] | [[Flag Days]]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_status.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Status</span>'''<br /><small>Find out whether your hardware is already supported.</small><small><hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [http://qa.coreboot.org Build Status]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_tools.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Related Tools</span>'''<br /><small>Tools and libraries related to coreboot.</small><small><hr />[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [[SerialICE]]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_101.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Getting Started</span>'''<br /><small>Download coreboot and get started.</small><small><hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_support.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Support</span>'''<br /><small>Learn how to contact us and find help and support.</small><small><hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|coreboot Options]]</small><br />
|}<br />
<br />
|}<br />
</td><td width="20%"><br />
<br />
[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]<br />
<br />
<br clear=all /><br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[News]]</span>'''<hr /><br />
<!-- Please always make this list 7 items long (7 most recent news items). --><br />
<small><br />
* '''2010/12/18:''' [[News#2010.2F12.2F18_Intel_Poulsbo.2FSCH.2FAtom_and_iWave_iW-RainboW-G6_now_supported|Intel Poulsbo/SCH/Atom & iWave iW-RainboW-G6 support]]<br />
* '''2010/12/13:''' [[News#2010.2F12.2F13_ASUS_M2N-E_now_supported|ASUS M2N-E support]]<br />
* '''2010/12/06:''' [[News#2010.2F12.2F06_ASUS_M4A78-EM_now_supported|ASUS M4A78-EM support]]<br />
* '''2010/11/11:''' [[News#2010.2F11.2F11_ASUS_M2V_now_supported|ASUS M2V support]]<br />
* '''2010/09/13:''' [[News#2010.2F09.2F13_ASUS_M4A785-M_now_supported|ASUS M4A785-M support]]<br />
* '''2010/09/10:''' [[News#2010.2F09.2F10_LiPPERT_LiteRunner-LX_and_Hurricane-LX_now_supported|LiPPERT LiteRunner-LX and Hurricane-LX support]]<br />
* '''2010/08/17:''' [[News#2010.2F08.2F17_GIGABYTE_GA-MA785GMT-UD2H_now_supported|GIGABYTE GA-MA785GMT-UD2H support]]<br />
</small><br />
<br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[Current events|Upcoming Events]]</span>'''<hr /><br />
<!-- List of upcoming events (remove events after they have taken place). --><br />
<small><br />
<!-- * '''2010/mon/day:''' coreboot event at [[Link]] in somecity --><br />
* None, currently.<br />
</small><br />
<br />
</td></tr></table><br />
<br />
__NOTOC__<br />
__NOEDITSECTION__</div>
Uwe
https://www.coreboot.org/index.php?title=Board:gigabyte/ga-6bxc&diff=10244
Board:gigabyte/ga-6bxc
2010-12-20T18:37:42Z
<p>Uwe: GA-6BXC updates.</p>
<hr />
<div>This page describes how to use coreboot on the [http://www.gigabyte.com/products/product-page.aspx?pid=1445 GIGABYTE GA-6BXC] mainboard.<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L2_status = WIP<br />
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it. <br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = WIP<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list. <br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|USB_status = OK<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = OK<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = WIP<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PP_comments = Doing '''modprobe ppdev''' seems to work, everything else is untested.<br />
|PS2_keyboard_status = WIP<br />
|PS2_keyboard_comments = Doesn't seem to work, yet. This is being investigated.<br />
|PS2_mouse_status = WIP<br />
|Game_port_status = N/A<br />
|IR_status = Untested<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = Untested<br />
|Watchdog_status = N/A<br />
|SMBus_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = N/A<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There is no ACPI implementation for this board, yet.<br />
|Reboot_status = OK<br />
|Poweroff_status = No<br />
|Poweroff_comments = Needs ACPI.<br />
|LEDs_status = Untested<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = No<br />
|WakeOnLAN_comments = NIC is powered off when the system is off.<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
Uwe
https://www.coreboot.org/index.php?title=Board:asus/m2n-e&diff=10243
Board:asus/m2n-e
2010-12-19T12:19:49Z
<p>Uwe: </p>
<hr />
<div>This page describes how to use coreboot on the '''[http://www.asus.com/product.aspx?P_ID=NFlvt10av3F7ayQ9 ASUS M2N-E]''' mainboard. It is maintained by [[User:Uwe|Uwe Hermann]].<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = I'm using: CPU model AMD Sempron(tm) Processor 3000+<br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = CPU: L2 Cache: 256K (64 bytes/line)<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = Untested<br />
|CPU_multicore_comments = I don't have a multicore CPU to test with, but it should work.<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = OK<br />
|RAM_DDR2_comments = Tested: One 512 MB DIMM in slot DIMM_A2 (see manual).<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = OK<br />
|RAM_dualchannel_comments = Seems to work. Tested: Two 512MB DIMMs (in the DIMM_A2 and DIMM_B2 slots).<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_comments = Tested: Booting from IDE disk (CF card actually).<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = Tested: Booting from a SATA disk in ports SATA1-SATA6 (all of them work).<br />
|USB_status = OK<br />
|USB_comments = Tested: USB keyboard on all 10 USB ports.<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = Tested: PCI graphics card in all three PCI slots.<br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = Tested: PCI-E x1 NIC in both PCI-E x1 slots.<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x4_comments = Tested: PCI-E x1 NIC (which also fits in the x4 slot).<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x16_comments = Tested: PCI-E x16 graphics card.<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = WIP<br />
|Floppy_comments = Doesn't seem to work, yet.<br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = OK<br />
|PP_comments = Tested: '''modprobe ppdev'''.<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments = The '''k8temp''', '''it87''', '''lm85''', '''eeprom''' and '''i2c-nforce2''' / '''i2c-dev''' modules load fine and seem to work.<br />
|Watchdog_status = N/A<br />
|SMBus_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = WIP<br />
|CPUfreq_comments = Doesn't work, yet.<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board, yet.<br />
|Reboot_status = OK<br />
|Poweroff_status = No<br />
|Poweroff_comments = Needs ACPI support.<br />
|LEDs_status = OK<br />
|LEDs_comments = There's a power-on LED on the board PCB, it lights up when the board is powered up.<br />
|HPET_status = WIP<br />
|HPET_comments = Currently not enabled in coreboot, but you can enable it via the '''hpet=force''' Linux kernel cmdline argument. The '''powertop''' tool works fine.<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = WIP<br />
|Flashrom_comments = Works fine with the proprietary BIOS, the may be issues when booted with coreboot though (investigating).<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
Uwe
https://www.coreboot.org/index.php?title=Board:asus/m2n-e&diff=10242
Board:asus/m2n-e
2010-12-19T00:58:48Z
<p>Uwe: More M2N-E updates.</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://www.asus.com/product.aspx?P_ID=NFlvt10av3F7ayQ9 ASUS M2N-E]''' mainboard. It is maintained by [[User:Uwe|Uwe Hermann]].<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = I'm using: CPU model AMD Sempron(tm) Processor 3000+<br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = CPU: L2 Cache: 256K (64 bytes/line)<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = Untested<br />
|CPU_multicore_comments = I don't have a multicore CPU to test with, but it should work.<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = OK<br />
|RAM_DDR2_comments = Tested: One 512 MB DIMM in slot DIMM_A2 (see manual).<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = OK<br />
|RAM_dualchannel_comments = Seems to work. Tested: Two 512MB DIMMs (in the DIMM_A2 and DIMM_B2 slots).<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_comments = Tested: Booting from IDE disk (CF card actually).<br />
|IDE_25_status = N/A<br />
|SATA_status = OK<br />
|SATA_comments = Tested: Booting from a SATA disk in ports SATA1-SATA6 (all of them work).<br />
|USB_status = OK<br />
|USB_comments = Tested: USB keyboard on all 10 USB ports.<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = Tested: PCI graphics card in all three PCI slots.<br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = Tested: PCI-E x1 NIC in both PCI-E x1 slots.<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x4_comments = Tested: PCI-E x1 NIC (which also fits in the x4 slot).<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = OK<br />
|PCIE_x16_comments = Tested: PCI-E x16 graphics card.<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|Floppy_comments = <br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = OK<br />
|PP_comments = Tested: '''modprobe ppdev'''.<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = OK<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments = The '''k8temp''', '''it87''', '''lm85''', '''eeprom''' and '''i2c-nforce2''' / '''i2c-dev''' modules load fine and seem to work.<br />
|Watchdog_status = N/A<br />
|SMBus_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = WIP<br />
|CPUfreq_comments = Doesn't work, yet.<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board, yet.<br />
|Reboot_status = OK<br />
|Poweroff_status = No<br />
|Poweroff_comments = Needs ACPI support.<br />
|LEDs_status = OK<br />
|LEDs_comments = There's a power-on LED on the board PCB, it lights up when the board is powered up.<br />
|HPET_status = WIP<br />
|HPET_comments = Currently not enabled in coreboot, but you can enable it via the '''hpet=force''' Linux kernel cmdline argument. The '''powertop''' tool works fine.<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = WIP<br />
|Flashrom_comments = Works fine with the proprietary BIOS, the may be issues when booted with coreboot though (investigating).<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
Uwe
https://www.coreboot.org/index.php?title=Board:asus/m2n-e&diff=10241
Board:asus/m2n-e
2010-12-18T23:54:12Z
<p>Uwe: Various ASUS M2N-E status updates.</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://www.asus.com/product.aspx?P_ID=NFlvt10av3F7ayQ9 ASUS M2N-E]''' mainboard. It is maintained by [[User:Uwe|Uwe Hermann]].<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = I'm using: CPU model AMD Sempron(tm) Processor 3000+<br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = CPU: L2 Cache: 256K (64 bytes/line)<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = Untested<br />
|CPU_multicore_comments = I don't have a multicore CPU to test with, but it should work.<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = OK<br />
|RAM_DDR2_comments = Tested: One 512 MB DIMM in slot DIMM_A2 (see manual).<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = OK<br />
|RAM_dualchannel_comments = Seems to work. Tested: Two 512MB DIMMs (in the DIMM_A2 and DIMM_B2 slots).<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_comments = Tested: Booting from IDE disk (CF card actually).<br />
|IDE_25_status = N/A<br />
|SATA_status = Untested<br />
|USB_status = OK<br />
|USB_comments = Tested: USB keyboard on all 10 USB ports.<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = Tested: PCI graphics card in all three PCI slots.<br />
|PCIE_x1_status = OK<br />
|PCIE_x1_comments = Tested: PCI-E x1 NIC.<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = OK<br />
|PCIE_x4_comments = Tested: PCI-E x1 NIC (which also fits in x4 slots).<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = Untested<br />
|PCIE_x16_comments = <br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|Floppy_comments = <br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = OK<br />
|PP_comments = Tested: '''modprobe ppdev'''.<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments = The '''k8temp''', '''it87''', '''lm85''', '''eeprom''' and '''i2c-nforce2''' / '''i2c-dev''' modules load fine and seem to work.<br />
|Watchdog_status = Untested<br />
|Watchdog_comments = <br />
|SMBus_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = WIP<br />
|CPUfreq_comments = Doesn't work, yet.<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board, yet.<br />
|Reboot_status = OK<br />
|Poweroff_status = No<br />
|Poweroff_comments = Needs ACPI support.<br />
|LEDs_status = OK<br />
|LEDs_comments = There's a power-on LED on the board PCB, it lights up when the board is powered up.<br />
|HPET_status = Untested<br />
|HPET_comments = <br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = WIP<br />
|Flashrom_comments = Works fine with the proprietary BIOS, the may be issues when booted with coreboot though (investigating).<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
Uwe
https://www.coreboot.org/index.php?title=Datasheets&diff=10239
Datasheets
2010-12-18T13:39:07Z
<p>Uwe: /* Intel */ Intel Atom / SCH</p>
<hr />
<div></div>
Uwe
https://www.coreboot.org/index.php?title=Datasheets&diff=10238
Datasheets
2010-12-18T11:15:08Z
<p>Uwe: /* Intel */ Intel NM10</p>
<hr />
<div></div>
Uwe
https://www.coreboot.org/index.php?title=Supported_Chipsets_and_Devices&diff=10234
Supported Chipsets and Devices
2010-12-16T22:02:10Z
<p>Uwe: /* Devices supported in coreboot v1 */</p>
<hr />
<div>'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards.<br />
* If a device is not supported by coreboot v4, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v3|coreboot v3]] for support.<br />
* In general it is '''not''' recommended to use coreboot v3 &mdash; this was an experimental development tree which is gradually being merged into v4.<br />
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. However, it is definately desirable to port boards from v1 to v4 whereever possible.<br />
<br />
See also [[Supported Motherboards]].<br />
<br />
== Devices supported in coreboot v4 ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam10h<br />
| style="background:lime" | OK<sup>16</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX1<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX&nbsp;(GX2)<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| LX<br />
| style="background: lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7520<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7525<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82810<br />
| style="background:yellow" | WIP<sup>9</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82855<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SiS<br />
| SiS761GX<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601 (PLE133)<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623 (CLE266)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8T890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8M890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN400<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:lime" | OK<sup>14</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CX700<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VX800<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8111<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8131<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8132<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8151<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5530/CS5530A<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5535<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS780/RS785?<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700/SB7x0<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM21000<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5780<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5785<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 6300ESB (ESB6300)<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801AA/AB&nbsp;(ICH/ICH0)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801BA/BAM&nbsp;(ICH2/ICH2-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA/CAM&nbsp;(ICH3-S/ICH3-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB/DBL/DBM<br/>(ICH4/ICH4-L/ICH4-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801EB/ER&nbsp;(ICH5/ICH5R)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PXHD<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| CK804<br />
| style="background:lime" | OK<sup>17</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<sup>17</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Ricoh<br />
| RL5C476<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966(L)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237A<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237S<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | OK<sup>12</sup>, <sup>13</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71859<br />
| style="background:yellow" | OK<sup>19</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71863F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71872F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71889<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8661F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8705F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<sup>15</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<sup>15</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC8374<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87360<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87366<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87417<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87427<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307 <br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ServerEngines<br />
| PILOT<br />
| style="background:yellow" | OK<sup>18</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M70x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B80x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B78x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B72x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B81x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M60x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B27x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M10x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M112<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M13x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M15x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M192<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B397<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| DME1737<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| SCH5307<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47N217<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686(A/B)<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627DHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627UHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627EHG/HF/EHF/THF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83697HF/HG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THF/THG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977TF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:lime" | OK<sup>4</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Emulated<br />
| QEMU<br />
| style="background:lime" | OK<br />
|}<br />
<br />
'''SOCs'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | SOC<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Elan SC520<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background: lime" | OK<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>4</sup> The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least).<br /><br />
<sup>5</sup> Pre-RAM serial output works fine, but nothing else, yet.<br /><br />
<sup>9</sup> Works mostly, but currently there are some limitations as to which RAM DIMMs can be used.<br /><br />
<sup>12</sup> All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though.<br /><br />
<sup>13</sup> The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737.<br /><br />
<sup>14</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
<sup>15</sup> The Intel 3100/EP80579 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far.<br /><br />
<sup>16</sup> Barcelona B0-B3 supported.<br /><br />
<sup>17</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br /><br />
<sup>18</sup> Partially supported, but not all features implemented.<br /><br />
<sup>19</sup> Only support for serial port 1 implemented, everything else is unsupported so far due to lack of datasheet.<br /><br />
</small><br />
<br />
== Devices supported in coreboot v3 ==<br />
<br />
<div style="color: #ff0000">coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 are gradually being merged into v4.</div><br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8111<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8132<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8151<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:orange" | WIP<sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Generic<br />
| i586<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel<br />
| Core Duo / Core 2 Duo<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| C7<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br />
</small><br />
<br />
== Devices supported in coreboot v1 ==<br />
<br />
Not all devices have been ported from coreboot v1 to coreboot v4, yet (check "v4?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1631<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Alpha<br />
| Tsunami<br />
| style="background:#dddddd" | ?<br />
| style="background:#dddddd" | &mdash;<sup>3</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD76x<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 430TX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440BX<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440GX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82815EP<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82860<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7500<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7505<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Micron<br />
| 21PAD<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
| style="background:#dddddd" | &mdash;<sup>3</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC/AMD<br />
| GX1<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT694<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1543<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD766<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD768<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PIIX4E<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC/AMD<br />
| CS5530<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#eeeeee" | ?<br />
| style="background:yellow" | WIP<sup>2</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
| style="background:#dddddd" | &mdash;<sup>3</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:lime" | OK<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 950<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B72X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B78X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B807<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C669<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C67X<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37N769<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | WIP<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83877TF<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<sup>1</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''North-/Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | North/South<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 540<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 550<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 630<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 635<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 730<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 735<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ST<br />
| STPC<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Alpha<br />
| EV6<br />
| style="background:#eeeeee" | ?<br />
| style="background:#eeeeee" | &mdash;<sup>3</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| ?<br />
| style="background:#dddddd" | ?<br />
| style="background:#dddddd" | &mdash;<sup>3</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> The W83977EF works fine with the W83977TF code in coreboot v4 (the pre-RAM serial part at least).<br /><br />
<sup>2</sup> Pre-RAM serial output works in coreboot v4, but the rest is not supported, yet.<br /><br />
<sup>3</sup> Will not be ported anytime soon, we focus on x86 in coreboot v4.<br /><br />
</small><br />
<br />
__FORCETOC__</div>
Uwe
https://www.coreboot.org/index.php?title=Supported_Chipsets_and_Devices&diff=10233
Supported Chipsets and Devices
2010-12-16T21:56:52Z
<p>Uwe: /* Devices supported in coreboot v1 */</p>
<hr />
<div>'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards.<br />
* If a device is not supported by coreboot v4, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v3|coreboot v3]] for support.<br />
* In general it is '''not''' recommended to use coreboot v3 &mdash; this was an experimental development tree which is gradually being merged into v4.<br />
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. However, it is definately desirable to port boards from v1 to v4 whereever possible.<br />
<br />
See also [[Supported Motherboards]].<br />
<br />
== Devices supported in coreboot v4 ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam10h<br />
| style="background:lime" | OK<sup>16</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX1<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX&nbsp;(GX2)<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| LX<br />
| style="background: lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7520<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7525<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82810<br />
| style="background:yellow" | WIP<sup>9</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82855<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SiS<br />
| SiS761GX<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601 (PLE133)<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623 (CLE266)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8T890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8M890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN400<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:lime" | OK<sup>14</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CX700<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VX800<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8111<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8131<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8132<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8151<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5530/CS5530A<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5535<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS780/RS785?<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700/SB7x0<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM21000<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5780<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5785<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 6300ESB (ESB6300)<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801AA/AB&nbsp;(ICH/ICH0)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801BA/BAM&nbsp;(ICH2/ICH2-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA/CAM&nbsp;(ICH3-S/ICH3-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB/DBL/DBM<br/>(ICH4/ICH4-L/ICH4-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801EB/ER&nbsp;(ICH5/ICH5R)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PXHD<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| CK804<br />
| style="background:lime" | OK<sup>17</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<sup>17</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Ricoh<br />
| RL5C476<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966(L)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237A<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237S<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | OK<sup>12</sup>, <sup>13</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71859<br />
| style="background:yellow" | OK<sup>19</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71863F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71872F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71889<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8661F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8705F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<sup>15</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<sup>15</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC8374<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87360<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87366<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87417<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87427<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307 <br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ServerEngines<br />
| PILOT<br />
| style="background:yellow" | OK<sup>18</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M70x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B80x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B78x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B72x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B81x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M60x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B27x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M10x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M112<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M13x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M15x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M192<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B397<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| DME1737<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| SCH5307<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47N217<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686(A/B)<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627DHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627UHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627EHG/HF/EHF/THF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83697HF/HG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THF/THG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977TF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:lime" | OK<sup>4</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Emulated<br />
| QEMU<br />
| style="background:lime" | OK<br />
|}<br />
<br />
'''SOCs'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | SOC<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Elan SC520<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background: lime" | OK<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>4</sup> The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least).<br /><br />
<sup>5</sup> Pre-RAM serial output works fine, but nothing else, yet.<br /><br />
<sup>9</sup> Works mostly, but currently there are some limitations as to which RAM DIMMs can be used.<br /><br />
<sup>12</sup> All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though.<br /><br />
<sup>13</sup> The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737.<br /><br />
<sup>14</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
<sup>15</sup> The Intel 3100/EP80579 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far.<br /><br />
<sup>16</sup> Barcelona B0-B3 supported.<br /><br />
<sup>17</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br /><br />
<sup>18</sup> Partially supported, but not all features implemented.<br /><br />
<sup>19</sup> Only support for serial port 1 implemented, everything else is unsupported so far due to lack of datasheet.<br /><br />
</small><br />
<br />
== Devices supported in coreboot v3 ==<br />
<br />
<div style="color: #ff0000">coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 are gradually being merged into v4.</div><br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8111<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8132<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8151<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:orange" | WIP<sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Generic<br />
| i586<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel<br />
| Core Duo / Core 2 Duo<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| C7<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br />
</small><br />
<br />
== Devices supported in coreboot v1 ==<br />
<br />
Not all devices have been ported from coreboot v1 to coreboot v4, yet (check "v4?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1631<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Alpha<br />
| Tsunami<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD76x<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 430TX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440BX<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440GX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82815EP<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82860<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7500<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7505<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Micron<br />
| 21PAD<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC/AMD<br />
| GX1<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT694<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1543<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD766<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD768<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PIIX4E<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC/AMD<br />
| CS5530<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#eeeeee" | ?<br />
| style="background:yellow" | WIP<sup>2</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:lime" | OK<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 950<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B72X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B78X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B807<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C669<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C67X<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37N769<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | WIP<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83877TF<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<sup>1</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''North-/Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | North/South<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 540<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 550<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 630<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 635<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 730<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 735<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ST<br />
| STPC<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Alpha<br />
| EV6<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| ?<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> The W83977EF works fine with the W83977TF code in coreboot v4 (the pre-RAM serial part at least).<br /><br />
<sup>2</sup> Pre-RAM serial output works in coreboot v4, but the rest is not supported, yet.<br /><br />
<sup>3</sup> Work in progress.<br /><br />
</small><br />
<br />
__FORCETOC__</div>
Uwe
https://www.coreboot.org/index.php?title=Supported_Chipsets_and_Devices&diff=10232
Supported Chipsets and Devices
2010-12-16T21:52:48Z
<p>Uwe: /* Devices supported in coreboot v4 */ Various updates, fixes.</p>
<hr />
<div>'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards.<br />
* If a device is not supported by coreboot v4, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v3|coreboot v3]] for support.<br />
* In general it is '''not''' recommended to use coreboot v3 &mdash; this was an experimental development tree which is gradually being merged into v4.<br />
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. However, it is definately desirable to port boards from v1 to v4 whereever possible.<br />
<br />
See also [[Supported Motherboards]].<br />
<br />
== Devices supported in coreboot v4 ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam10h<br />
| style="background:lime" | OK<sup>16</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX1<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX&nbsp;(GX2)<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| LX<br />
| style="background: lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7520<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7525<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82810<br />
| style="background:yellow" | WIP<sup>9</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82855<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SiS<br />
| SiS761GX<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601 (PLE133)<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623 (CLE266)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8T890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8M890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN400<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:lime" | OK<sup>14</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CX700<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VX800<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8111<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8131<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8132<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8151<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5530/CS5530A<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5535<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS780/RS785?<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700/SB7x0<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM21000<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5780<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5785<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 6300ESB (ESB6300)<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801AA/AB&nbsp;(ICH/ICH0)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801BA/BAM&nbsp;(ICH2/ICH2-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA/CAM&nbsp;(ICH3-S/ICH3-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB/DBL/DBM<br/>(ICH4/ICH4-L/ICH4-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801EB/ER&nbsp;(ICH5/ICH5R)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PXHD<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| CK804<br />
| style="background:lime" | OK<sup>17</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<sup>17</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Ricoh<br />
| RL5C476<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966(L)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237A<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237S<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | OK<sup>12</sup>, <sup>13</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71859<br />
| style="background:yellow" | OK<sup>19</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71863F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71872F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71889<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8661F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8705F<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<sup>15</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<sup>15</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC8374<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:yellow" | OK<sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87360<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87366<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87417<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87427<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307 <br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ServerEngines<br />
| PILOT<br />
| style="background:yellow" | OK<sup>18</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M70x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B80x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B78x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B72x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B81x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M60x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B27x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M10x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M112<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M13x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M15x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M192<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B397<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| DME1737<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| SCH5307<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47N217<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686(A/B)<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627DHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627UHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627EHG/HF/EHF/THF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83697HF/HG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THF/THG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977TF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:lime" | OK<sup>4</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Emulated<br />
| QEMU<br />
| style="background:lime" | OK<br />
|}<br />
<br />
'''SOCs'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | SOC<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Elan SC520<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background: lime" | OK<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>4</sup> The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least).<br /><br />
<sup>5</sup> Pre-RAM serial output works fine, but nothing else, yet.<br /><br />
<sup>9</sup> Works mostly, but currently there are some limitations as to which RAM DIMMs can be used.<br /><br />
<sup>12</sup> All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though.<br /><br />
<sup>13</sup> The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737.<br /><br />
<sup>14</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
<sup>15</sup> The Intel 3100/EP80579 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far.<br /><br />
<sup>16</sup> Barcelona B0-B3 supported.<br /><br />
<sup>17</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br /><br />
<sup>18</sup> Partially supported, but not all features implemented.<br /><br />
<sup>19</sup> Only support for serial port 1 implemented, everything else is unsupported so far due to lack of datasheet.<br /><br />
</small><br />
<br />
== Devices supported in coreboot v3 ==<br />
<br />
<div style="color: #ff0000">coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 are gradually being merged into v4.</div><br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8111<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8132<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8151<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:orange" | WIP<sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Generic<br />
| i586<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel<br />
| Core Duo / Core 2 Duo<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| C7<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br />
</small><br />
<br />
== Devices supported in coreboot v1 ==<br />
<br />
Not all devices have been ported from coreboot v1 to coreboot v4, yet (check "v4?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1631<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Alpha<br />
| Tsunami<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD76x<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 430TX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440BX<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>3</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440GX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82815EP<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82860<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7500<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7505<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Micron<br />
| 21PAD<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC/AMD<br />
| GX1<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT694<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1543<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD766<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD768<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PIIX4E<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC/AMD<br />
| CS5530<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:lime" | OK<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 950<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B72X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B78X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B807<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C669<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C67X<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37N769<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83877TF<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<sup>1</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''North-/Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | North/South<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 540<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 550<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 630<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 635<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 730<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 735<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ST<br />
| STPC<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Alpha<br />
| EV6<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| ?<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> The W83977EF works fine with the W83977TF code in coreboot v4 (the pre-RAM serial part at least).<br /><br />
<sup>2</sup> Pre-RAM serial output works in coreboot v4, but the rest is not supported, yet.<br /><br />
<sup>3</sup> Work in progress.<br /><br />
</small><br />
<br />
__FORCETOC__</div>
Uwe
https://www.coreboot.org/index.php?title=Windows&diff=10231
Windows
2010-12-16T21:39:06Z
<p>Uwe: </p>
<hr />
<div>In order to be able to boot Windows using a coreboot system we recommend to use [[SeaBIOS]] as the payload.<br />
<br />
== ACPI ==<br />
<br />
All Windows versions since Windows Vista require a quite complete ACPI implementation. If you have trouble booting Windows, have a look at [[ACPI|our ACPI page]].<br />
<br />
== Utilities ==<br />
<br />
* [http://jacky5488.myweb.hinet.net/ RW Utility] - Windows hardware query tool<br />
<br />
== Misc == <br />
<br />
* [[Booting Windows using coreboot]] (obsolete, but may be useful)</div>
Uwe
https://www.coreboot.org/index.php?title=Infrastructure_Projects&diff=10230
Infrastructure Projects
2010-12-16T21:37:16Z
<p>Uwe: DONE: Fix ALL build warnings. Other updates.</p>
<hr />
<div>This page collects a list of projects to improve the infrastructure of coreboot v4. Infrastructure means those parts of the code that aren't chipset or mainboard specific, but are used by all of them. The idea is to consolidate a list of things "to do" with their status and responsible developers.<br />
<br />
= In progress =<br />
<br />
== Low/High Tables ==<br />
<br />
SeaBIOS requires a copy of various BIOS tables outside the fseg as it overwrites that segment. Generally clean out the table generation code.<br />
<br />
'''Status:''' Upstream, implemented on some boards. There are problems on some chipsets/boards because of incorrect CONFIG_VIDEO_MB handling. The might be other issues, too (not clear, yet).<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Vendor/chipset<br />
! align="left" | Tested<br />
! align="left" | Comments<br />
<br />
|- bgcolor="#eeeeee"<br />
| amd/amdfam10<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdht<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdk8<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdmct<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/gx1<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/gx2<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/lx<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7501<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7520<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7525<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i3100<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i440bx<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82810<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82830<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i855<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i945<br />
| style="background:lime" | Y<br />
| Tested on Kontron 986LCD-M and Roda RK886EX<br />
|- bgcolor="#eeeeee"<br />
| via/cn400<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/cn700<br />
| style="background:lime" | Y<br />
| Tested on VIA pc2500e.<br />
|- bgcolor="#eeeeee"<br />
| via/cx700<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8601<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8623<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vx800<br />
| ?<br />
| &mdash;<br />
<br />
|}<br />
<br />
'''Developers:''' Stefan<br />
<br />
== CBFS ==<br />
<br />
A filesystem-alike layout for the coreboot image, to enable systems like bayou and to clean up the system in general (eg. no more buildrom).<br />
<br />
'''Status:'''<br />
<br />
Upstream, pre-CBFS infrastructure removed.<br />
<br />
There are places where using CBFS might be a good idea: Everything that makes use of external files, for example the VSA code in the Geode chipset code. VSA is converted, and tested on a couple of configurations, but untested on others.<br />
<br />
Some boards have issues with CBFS because it requires the whole ROM to be accessible at a quite early point in time (compared to the old mechanism). The following table contains validated knowledge if the ROM mapping happens at the right time.<br />
<br />
All boards that manage to boot in a tinybootblock configuration are capable at least for the used ROM size (it might be that larger ROMs would fail because they require mapping the larger space)<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Vendor/chipset<br />
! align="left" | ROM enabled<br />
! align="left" | Tiny bootblock<br />
! align="left" | Status / Comments<br />
<br />
|- bgcolor="#eeeeee"<br />
| amd/amd8111<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5530<br />
| style="background:lime" | Y<br />
| style="background:red" | N<br />
| Not tested on hardware, yet.<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5535<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5536<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/sb600<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/sb700<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd"<br />
| broadcom/bcm5785<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
<br />
|- bgcolor="#eeeeee"<br />
| intel/esb6300<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i3100<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82371eb<br />
| style="background:lime" | Y<br />
| style="background:yellow" | Y<br />
| Build- and runtime-tested on ASUS P2B by [[User:Uwe|Uwe Hermann]].<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801ax<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801bx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801cx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801dx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801ex<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801gx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd"<br />
| nvidia/ck804<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
|- bgcolor="#dddddd"<br />
| nvidia/mcp55<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
<br />
|- bgcolor="#dddddd"<br />
| sis/sis966<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
<br />
|- bgcolor="#eeeeee"<br />
| via/vt8231<br />
| style="background:yellow" | Y<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8235<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8237r<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt82c686<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
<br />
|}<br />
<br />
'''Developers:''' Stefan, Ron, Patrick, Myles, Uwe<br />
<br />
== Tiny Bootblock ==<br />
<br />
Right now, the decision whether to use fallback or normal is in cache_as_ram_auto.c in many boards. Make that generic again (also helps with further CBFSification at some point).<br />
<br />
'''Status:''' Available in Kconfig, works on a couple of boards. Requires per southbridge changes (and northbridge in some cases) on many boards (related to ROM enable, see CBFS section).<br />
<br />
'''Developers:''' Patrick<br />
<br />
== Remove .c includes ==<br />
<br />
Currently we include lots of code in the romstage using the preprocessor. This makes it harder to support new boards (where chipset components are supported already) and maintenance in general. So we should get rid of it where possible, using the linker for CAR boards and the build system for the remaining non-CAR boards appropriately.<br />
<br />
'''Status:''' CAR boards only for now, to keep the project manageable. i945 is modified already, and boards based on it have only one or two remaining source files they include. Interacts with the next project "Move configuration to Kconfig", which ensures that code still sees all configuration when it is compiled separately.<br />
<br />
'''Developers:''' Patrick, Uwe<br />
<br />
== Move configuration to Kconfig ==<br />
<br />
Many boards have lots of <code>#define VAR somevalue</code> statements in their romstage.c which define how certain component drivers are compiled. With Kconfig, there's a better place to store them. This project is about moving all configuration values out of romstage.c (and other places if appropriate) and into Kconfig.<br />
<br />
'''Status:''' Intel and VIA based boards should be mostly configuration free, AMD boards still have defines in their romstage.<br />
<br />
'''Developers:''' Patrick, Uwe<br />
<br />
== Unify ACPI ==<br />
<br />
Every ACPI board has its own routines to compile the ACPI sources. Unify that. Also, figure out generic ACPI code and deduplicate it.<br />
<br />
== Post codes ==<br />
<br />
Find all outb(x, 0x80) and replace them with post_code(). Use common numbers / defines across the boards.<br />
<br />
= More ideas =<br />
<br />
== CMOS layout ==<br />
<br />
Allow (somehow) to define defaults for all CMOS fields, and create a static table from that. Use that at runtime if the CMOS checksum fails.<br />
<br />
== Unify UMA / onboard video code and config ==<br />
<br />
Unify CONFIG_VIDEO_MB, CONFIG_GFXUMA, and similar options and make all code honor them.<br />
<br />
== Add / Unify / Test kconfig compile-time options and runtime CMOS options in coreboot ==<br />
<br />
Some coreboot options are compile-time configurable only at the moment (via kconfig), but should also be runtime-configurable via CMOS/NVRAM options. We should fix this.<br />
<br />
* Make all options (where it makes sense) run-time configurable via CMOS options, in addition to having sane compile-time defaults configured via kconfig.<br />
* This includes many options which are northbridge-specific, many southbridge-specific, and some board-specific ones.<br />
* Example options: Enable/disable IDE channel(s) / SATA / USB / SCSI / etc., enable/disable UDMA on older boards, amount of memory used for IGP/UMA, choice between IDE or NAND flash (on CS5536 boards), IDE 40/80 pin cable selection (VT8237R boards for example), and many more.<br />
* Some of these options are already handled in the code via CMOS options, some are compile-time only so far, so do not yet exist at all.<br />
<br />
== Kconfig TODO ==<br />
<br />
Notes / Style guide:<br />
<br />
* Any bool variables that are (re-)defined to 'y' in Kconfig files can be simplified by using '''select FOO''' instead of the usual paragraph, as long as they're defined globally as '''default n''' boolean elsewhere.<br />
* Use '''bool''' instead of '''boolean'''.<br />
* Use '''default n''' instead of '''default false'''.<br />
<br />
Various post-conversion things to consider:<br />
<br />
* Consider ways to move crt0-y and ldscript-y out of $(src)/arch/i386/Makefile.inc where appropriate (ie. component specific)<br />
* Make various CONFIG_* variable which were in each board's Kconfig file global or per-chipset options (instead of per-board). Examples:<br />
** UDELAY_TSC, TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 (also check UDELAY_IO, APIC, etc.)<br />
** ...<br />
<br />
Stuff to port from v3 to v4:<br />
<br />
* All boards that are in v3 but not in v4 (especially Geode LX stuff. Also check amd/model_gx*).<br />
* Some remaining useful Kconfig options.<br />
<br />
== USB Debug Console ==<br />
<br />
Fix USB debug console and make the Kconfig choice actually work. Right now it's possible to transmit single characters but it's not really hooked up.<br />
<br />
== Clean up Assembler / Linker mess ==<br />
<br />
* Drop / combine / normalize .ld/.lb/.lds linker scripts.<br />
* Move them to a common place.<br />
* Drop / combine / normalize .inc / .S files.<br />
<br />
== Geode issues ==<br />
<br />
* Fix / Unify vsmsetup.c.<br />
* Fix CS5535/CS5536/GX2/LX "chipsetinit" issue.<br />
<br />
== Use central oprom init ==<br />
<br />
* Get rid of all vgabios.c, make all chipsets with own vgabios.c use devices/oprom/x86.c.<br />
* Use the realmode code for vsmsetup too.<br />
<br />
== Stack and Suspend/Resume ==<br />
<br />
* Use CONFIG_RAMBASE + HIGH_MEMORY_SAFE instead of 0x40000 for stack.<br />
<br />
== Fix Suspend/Resume on AMD64 ==<br />
<br />
* Use cbmem in romstage on the AMD64 board(s) that have suspend/resume.<br />
<br />
== printk into buffer ==<br />
<br />
Port the v3 feature that printk can write into a buffer (that might be usable from the client OS, or dumped to output, as soon as output exists).<br />
<br />
Consider use cases first (no need to provide buffer support, if all it would be useful for is buffering pre-CAR messages - which can't be buffered).<br />
<br />
== Global variables ==<br />
<br />
* Port the global variables framework from v3.<br />
* Make use of it where appropriate.<br />
<br />
== Clear phases in romstage ==<br />
<br />
* Split up the code (esp. in romstage) into more sensibly separated phases.<br />
* Maybe use v3 for inspiration where the lines can be drawn.<br />
<br />
= Finished =<br />
<br />
== Port v3 Resource Allocator ==<br />
<br />
The v3 resource allocator should be ported to v4.<br />
<br />
'''Status:''' Upstream. It's limited to one area for resources, that doesn't overlap with fixed resources.<br />
<br />
'''Developers:''' Myles<br />
<br />
== Config & Build System ==<br />
<br />
The current system of generated Makefiles is non-ideal (for too many reasons for this little margin). Fix it, somehow. Use kconfig to improve the configuration management.<br />
<br />
'''Status:''' Upstream, boards are converted. Old system is gone. All boards build. HOWEVER, not all boards have been boot-tested yet, please report any issues you encounter!<br />
<br />
'''Developers:''' Stefan, Ron, Patrick, Uwe, Cristi<br />
<br />
== Unify text printing functions ==<br />
<br />
There are several copies of print_* and printk_* in the code. Unify them so everything is happier than before (because the disjoint features are merged).<br />
<br />
'''Status:''' Finished.<br />
<br />
'''Developers:''' Patrick, Stefan<br />
<br />
== Common payload location ==<br />
<br />
Many boards have different names for the payload in targets/.../Config.lb (payload.elf, filo.elf, etherboot.elf, etc) and locations (../payload.elf, or various absolute paths which only work for one developer). The problem will be fixed with kconfig, where the user specifies a payload manually in "make menuconfig".<br />
<br />
'''Status:''' Finished.<br />
<br />
== Fix ALL build warnings ==<br />
<br />
* Someone has to do the deed.<br />
<br />
'''Status:''' Finished, the build usually issues no warnings. If you see warnings/errors, please report a bug.</div>
Uwe
https://www.coreboot.org/index.php?title=Infrastructure_Projects&diff=10229
Infrastructure Projects
2010-12-16T21:30:17Z
<p>Uwe: /* Remove .c inclues */</p>
<hr />
<div>This page collects a list of projects to improve the infrastructure of coreboot v4. Infrastructure means those parts of the code that aren't chipset or mainboard specific, but are used by all of them. The idea is to consolidate a list of things "to do" with their status and responsible developers.<br />
<br />
= In progress =<br />
<br />
== Low/High Tables ==<br />
<br />
SeaBIOS requires a copy of various BIOS tables outside the fseg as it overwrites that segment. Generally clean out the table generation code.<br />
<br />
'''Status:''' Upstream, implemented on some boards. There are problems on some chipsets/boards because of incorrect CONFIG_VIDEO_MB handling. The might be other issues, too (not clear, yet).<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Vendor/chipset<br />
! align="left" | Tested<br />
! align="left" | Comments<br />
<br />
|- bgcolor="#eeeeee"<br />
| amd/amdfam10<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdht<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdk8<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdmct<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/gx1<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/gx2<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/lx<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7501<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7520<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7525<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i3100<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i440bx<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82810<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82830<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i855<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i945<br />
| style="background:lime" | Y<br />
| Tested on Kontron 986LCD-M and Roda RK886EX<br />
|- bgcolor="#eeeeee"<br />
| via/cn400<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/cn700<br />
| style="background:lime" | Y<br />
| Tested on VIA pc2500e.<br />
|- bgcolor="#eeeeee"<br />
| via/cx700<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8601<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8623<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vx800<br />
| ?<br />
| &mdash;<br />
<br />
|}<br />
<br />
'''Developers:''' Stefan<br />
<br />
== CBFS ==<br />
<br />
A filesystem-alike layout for the coreboot image, to enable systems like bayou and to clean up the system in general (eg. no more buildrom).<br />
<br />
'''Status:'''<br />
<br />
Upstream, pre-CBFS infrastructure removed.<br />
<br />
There are places where using CBFS might be a good idea: Everything that makes use of external files, for example the VSA code in the Geode chipset code. VSA is converted, and tested on a couple of configurations, but untested on others.<br />
<br />
Some boards have issues with CBFS because it requires the whole ROM to be accessible at a quite early point in time (compared to the old mechanism). The following table contains validated knowledge if the ROM mapping happens at the right time.<br />
<br />
All boards that manage to boot in a tinybootblock configuration are capable at least for the used ROM size (it might be that larger ROMs would fail because they require mapping the larger space)<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Vendor/chipset<br />
! align="left" | ROM enabled<br />
! align="left" | Tiny bootblock<br />
! align="left" | Status / Comments<br />
<br />
|- bgcolor="#eeeeee"<br />
| amd/amd8111<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5530<br />
| style="background:lime" | Y<br />
| style="background:red" | N<br />
| Not tested on hardware, yet.<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5535<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5536<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/sb600<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/sb700<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd"<br />
| broadcom/bcm5785<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
<br />
|- bgcolor="#eeeeee"<br />
| intel/esb6300<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i3100<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82371eb<br />
| style="background:lime" | Y<br />
| style="background:yellow" | Y<br />
| Build- and runtime-tested on ASUS P2B by [[User:Uwe|Uwe Hermann]].<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801ax<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801bx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801cx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801dx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801ex<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801gx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd"<br />
| nvidia/ck804<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
|- bgcolor="#dddddd"<br />
| nvidia/mcp55<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
<br />
|- bgcolor="#dddddd"<br />
| sis/sis966<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
<br />
|- bgcolor="#eeeeee"<br />
| via/vt8231<br />
| style="background:yellow" | Y<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8235<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8237r<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt82c686<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
<br />
|}<br />
<br />
'''Developers:''' Stefan, Ron, Patrick, Myles, Uwe<br />
<br />
== Tiny Bootblock ==<br />
<br />
Right now, the decision whether to use fallback or normal is in cache_as_ram_auto.c in many boards. Make that generic again (also helps with further CBFSification at some point).<br />
<br />
'''Status:''' Available in Kconfig, works on a couple of boards. Requires per southbridge changes (and northbridge in some cases) on many boards (related to ROM enable, see CBFS section).<br />
<br />
'''Developers:''' Patrick<br />
<br />
== Remove .c includes ==<br />
<br />
Currently we include lots of code in the romstage using the preprocessor. This makes it harder to support new boards (where chipset components are supported already) and maintenance in general. So we should get rid of it where possible, using the linker for CAR boards and the build system for the remaining non-CAR boards appropriately.<br />
<br />
'''Status:''' CAR boards only for now, to keep the project manageable. i945 is modified already, and boards based on it have only one or two remaining source files they include. Interacts with the next project "Move configuration to Kconfig", which ensures that code still sees all configuration when it is compiled separately.<br />
<br />
'''Developers:''' Patrick, Uwe<br />
<br />
== Move configuration to Kconfig ==<br />
<br />
Many boards have lots of <code>#define VAR somevalue</code> statements in their romstage.c which define how certain component drivers are compiled. With Kconfig, there's a better place to store them. This project is about moving all configuration values out of romstage.c (and other places if appropriate) and into Kconfig.<br />
<br />
'''Status:''' Intel and VIA based boards should be mostly configuration free, AMD boards still have defines in their romstage.<br />
<br />
'''Developers:''' Patrick, Uwe<br />
<br />
= More ideas =<br />
<br />
== Unify ACPI ==<br />
<br />
Every ACPI board has its own routines to compile the ACPI sources. Unify that. Also, figure out generic ACPI code and deduplicate it.<br />
<br />
== CMOS layout ==<br />
<br />
Allow (somehow) to define defaults for all CMOS fields, and create a static table from that. Use that at runtime if the CMOS checksum fails.<br />
<br />
== Unify UMA / onboard video code and config ==<br />
<br />
Unify CONFIG_VIDEO_MB, CONFIG_GFXUMA, and similar options and make all code honor them.<br />
<br />
== Add / Unify / Test kconfig compile-time options and runtime CMOS options in coreboot ==<br />
<br />
Some coreboot options are compile-time configurable only at the moment (via kconfig), but should also be runtime-configurable via CMOS/NVRAM options. We should fix this.<br />
<br />
* Make all options (where it makes sense) run-time configurable via CMOS options, in addition to having sane compile-time defaults configured via kconfig.<br />
* This includes many options which are northbridge-specific, many southbridge-specific, and some board-specific ones.<br />
* Example options: Enable/disable IDE channel(s) / SATA / USB / SCSI / etc., enable/disable UDMA on older boards, amount of memory used for IGP/UMA, choice between IDE or NAND flash (on CS5536 boards), IDE 40/80 pin cable selection (VT8237R boards for example), and many more.<br />
* Some of these options are already handled in the code via CMOS options, some are compile-time only so far, so do not yet exist at all.<br />
<br />
== Kconfig TODO ==<br />
<br />
Notes / Style guide:<br />
<br />
* Any bool variables that are (re-)defined to 'y' in Kconfig files can be simplified by using '''select FOO''' instead of the usual paragraph, as long as they're defined globally as '''default n''' boolean elsewhere.<br />
* Use '''bool''' instead of '''boolean'''.<br />
* Use '''default n''' instead of '''default false'''.<br />
<br />
Various post-conversion things to consider:<br />
<br />
* Consider ways to move crt0-y and ldscript-y out of $(src)/arch/i386/Makefile.inc where appropriate (ie. component specific)<br />
* Make various CONFIG_* variable which were in each board's Kconfig file global or per-chipset options (instead of per-board). Examples:<br />
** UDELAY_TSC, TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 (also check UDELAY_IO, APIC, etc.)<br />
** ...<br />
<br />
Stuff to port from v3 to v4:<br />
<br />
* All boards that are in v3 but not in v4 (especially Geode LX stuff. Also check amd/model_gx*).<br />
* Some remaining useful Kconfig options.<br />
<br />
== USB Debug Console ==<br />
<br />
Fix USB debug console and make the Kconfig choice actually work. Right now it's possible to transmit single characters but it's not really hooked up.<br />
<br />
== Clean up Assembler / Linker mess ==<br />
<br />
* Drop / combine / normalize .ld/.lb/.lds linker scripts.<br />
* Move them to a common place.<br />
* Drop / combine / normalize .inc / .S files.<br />
<br />
== Post codes ==<br />
<br />
* post_code consolidation: find all outb(x, 0x80).<br />
* post_code consolidation: common numbers / defines across the boards.<br />
<br />
== Geode issues ==<br />
<br />
* Fix / Unify vsmsetup.c.<br />
* Fix CS5535/CS5536/GX2/LX "chipsetinit" issue.<br />
<br />
== Use central oprom init ==<br />
<br />
* Get rid of all vgabios.c, make all chipsets with own vgabios.c use devices/oprom/x86.c.<br />
* Use the realmode code for vsmsetup too.<br />
<br />
== Stack and Suspend/Resume ==<br />
<br />
* Use CONFIG_RAMBASE + HIGH_MEMORY_SAFE instead of 0x40000 for stack.<br />
<br />
== Fix Suspend/Resume on AMD64 ==<br />
<br />
* Use cbmem in romstage on the AMD64 board(s) that have suspend/resume.<br />
<br />
== Fix ALL build warnings ==<br />
<br />
* Someone has to do the deed..<br />
<br />
== printk into buffer ==<br />
<br />
Port the v3 feature that printk can write into a buffer (that might be usable from the client OS, or dumped to output, as soon as output exists).<br />
<br />
Consider use cases first (no need to provide buffer support, if all it would be useful for is buffering pre-CAR messages - which can't be buffered).<br />
<br />
== Global variables ==<br />
<br />
* Port the global variables framework from v3.<br />
* Make use of it where appropriate.<br />
<br />
== Clear phases in romstage ==<br />
<br />
* Split up the code (esp. in romstage) into more sensibly separated phases.<br />
* Maybe use v3 for inspiration where the lines can be drawn.<br />
<br />
= Finished =<br />
<br />
== Port v3 Resource Allocator ==<br />
<br />
The v3 resource allocator should be ported to v4.<br />
<br />
'''Status:''' Upstream. It's limited to one area for resources, that doesn't overlap with fixed resources.<br />
<br />
'''Developers:''' Myles<br />
<br />
== Config & Build System ==<br />
<br />
The current system of generated Makefiles is non-ideal (for too many reasons for this little margin). Fix it, somehow. Use kconfig to improve the configuration management.<br />
<br />
'''Status:''' Upstream, boards are converted. Old system is gone. All boards build. HOWEVER, not all boards have been boot-tested yet, please report any issues you encounter!<br />
<br />
'''Developers:''' Stefan, Ron, Patrick, Uwe, Cristi<br />
<br />
== Unify text printing functions ==<br />
<br />
There are several copies of print_* and printk_* in the code. Unify them so everything is happier than before (because the disjoint features are merged).<br />
<br />
'''Developers:''' Patrick, Stefan<br />
<br />
== Common payload location ==<br />
<br />
Many boards have different names for the payload in targets/.../Config.lb (payload.elf, filo.elf, etherboot.elf, etc) and locations (../payload.elf, or various absolute paths which only work for one developer). The problem will be fixed with kconfig, where the user specifies a payload manually in "make menuconfig".</div>
Uwe
https://www.coreboot.org/index.php?title=Infrastructure_Projects&diff=10228
Infrastructure Projects
2010-12-16T21:29:21Z
<p>Uwe: /* CBFS */</p>
<hr />
<div>This page collects a list of projects to improve the infrastructure of coreboot v4. Infrastructure means those parts of the code that aren't chipset or mainboard specific, but are used by all of them. The idea is to consolidate a list of things "to do" with their status and responsible developers.<br />
<br />
= In progress =<br />
<br />
== Low/High Tables ==<br />
<br />
SeaBIOS requires a copy of various BIOS tables outside the fseg as it overwrites that segment. Generally clean out the table generation code.<br />
<br />
'''Status:''' Upstream, implemented on some boards. There are problems on some chipsets/boards because of incorrect CONFIG_VIDEO_MB handling. The might be other issues, too (not clear, yet).<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Vendor/chipset<br />
! align="left" | Tested<br />
! align="left" | Comments<br />
<br />
|- bgcolor="#eeeeee"<br />
| amd/amdfam10<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdht<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdk8<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdmct<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/gx1<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/gx2<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/lx<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7501<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7520<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7525<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i3100<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i440bx<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82810<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82830<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i855<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i945<br />
| style="background:lime" | Y<br />
| Tested on Kontron 986LCD-M and Roda RK886EX<br />
|- bgcolor="#eeeeee"<br />
| via/cn400<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/cn700<br />
| style="background:lime" | Y<br />
| Tested on VIA pc2500e.<br />
|- bgcolor="#eeeeee"<br />
| via/cx700<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8601<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8623<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vx800<br />
| ?<br />
| &mdash;<br />
<br />
|}<br />
<br />
'''Developers:''' Stefan<br />
<br />
== CBFS ==<br />
<br />
A filesystem-alike layout for the coreboot image, to enable systems like bayou and to clean up the system in general (eg. no more buildrom).<br />
<br />
'''Status:'''<br />
<br />
Upstream, pre-CBFS infrastructure removed.<br />
<br />
There are places where using CBFS might be a good idea: Everything that makes use of external files, for example the VSA code in the Geode chipset code. VSA is converted, and tested on a couple of configurations, but untested on others.<br />
<br />
Some boards have issues with CBFS because it requires the whole ROM to be accessible at a quite early point in time (compared to the old mechanism). The following table contains validated knowledge if the ROM mapping happens at the right time.<br />
<br />
All boards that manage to boot in a tinybootblock configuration are capable at least for the used ROM size (it might be that larger ROMs would fail because they require mapping the larger space)<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Vendor/chipset<br />
! align="left" | ROM enabled<br />
! align="left" | Tiny bootblock<br />
! align="left" | Status / Comments<br />
<br />
|- bgcolor="#eeeeee"<br />
| amd/amd8111<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5530<br />
| style="background:lime" | Y<br />
| style="background:red" | N<br />
| Not tested on hardware, yet.<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5535<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5536<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/sb600<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/sb700<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd"<br />
| broadcom/bcm5785<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
<br />
|- bgcolor="#eeeeee"<br />
| intel/esb6300<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i3100<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82371eb<br />
| style="background:lime" | Y<br />
| style="background:yellow" | Y<br />
| Build- and runtime-tested on ASUS P2B by [[User:Uwe|Uwe Hermann]].<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801ax<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801bx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801cx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801dx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801ex<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801gx<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd"<br />
| nvidia/ck804<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
|- bgcolor="#dddddd"<br />
| nvidia/mcp55<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
<br />
|- bgcolor="#dddddd"<br />
| sis/sis966<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| Not tested on hardware, yet.<br />
<br />
|- bgcolor="#eeeeee"<br />
| via/vt8231<br />
| style="background:yellow" | Y<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8235<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8237r<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt82c686<br />
| style="background:red" | N<br />
| style="background:red" | N<br />
| &mdash;<br />
<br />
|}<br />
<br />
'''Developers:''' Stefan, Ron, Patrick, Myles, Uwe<br />
<br />
== Tiny Bootblock ==<br />
<br />
Right now, the decision whether to use fallback or normal is in cache_as_ram_auto.c in many boards. Make that generic again (also helps with further CBFSification at some point).<br />
<br />
'''Status:''' Available in Kconfig, works on a couple of boards. Requires per southbridge changes (and northbridge in some cases) on many boards (related to ROM enable, see CBFS section).<br />
<br />
'''Developers:''' Patrick<br />
<br />
== Remove .c inclues ==<br />
<br />
Currently we include lots of code in the romstage using the preprocessor. This makes it harder to support new boards (where chipset components are supported already) and maintenance in general. So we should get rid of it where possible, using the linker for CAR boards and the build system for the remaining non-CAR boards appropriately.<br />
<br />
'''Status:''' CAR boards only for now, to keep the project manageable. i945 is modified already, and boards based on it have only one or two remaining source files they include. Interacts with the next project "Move configuration to Kconfig", which ensures that code still sees all configuration when it is compiled separately<br />
<br />
'''Developers:''' Patrick, Uwe<br />
<br />
== Move configuration to Kconfig ==<br />
<br />
Many boards have lots of <code>#define VAR somevalue</code> statements in their romstage.c which define how certain component drivers are compiled. With Kconfig, there's a better place to store them. This project is about moving all configuration values out of romstage.c (and other places if appropriate) and into Kconfig.<br />
<br />
'''Status:''' Intel and VIA based boards should be mostly configuration free, AMD boards still have defines in their romstage.<br />
<br />
'''Developers:''' Patrick, Uwe<br />
<br />
= More ideas =<br />
<br />
== Unify ACPI ==<br />
<br />
Every ACPI board has its own routines to compile the ACPI sources. Unify that. Also, figure out generic ACPI code and deduplicate it.<br />
<br />
== CMOS layout ==<br />
<br />
Allow (somehow) to define defaults for all CMOS fields, and create a static table from that. Use that at runtime if the CMOS checksum fails.<br />
<br />
== Unify UMA / onboard video code and config ==<br />
<br />
Unify CONFIG_VIDEO_MB, CONFIG_GFXUMA, and similar options and make all code honor them.<br />
<br />
== Add / Unify / Test kconfig compile-time options and runtime CMOS options in coreboot ==<br />
<br />
Some coreboot options are compile-time configurable only at the moment (via kconfig), but should also be runtime-configurable via CMOS/NVRAM options. We should fix this.<br />
<br />
* Make all options (where it makes sense) run-time configurable via CMOS options, in addition to having sane compile-time defaults configured via kconfig.<br />
* This includes many options which are northbridge-specific, many southbridge-specific, and some board-specific ones.<br />
* Example options: Enable/disable IDE channel(s) / SATA / USB / SCSI / etc., enable/disable UDMA on older boards, amount of memory used for IGP/UMA, choice between IDE or NAND flash (on CS5536 boards), IDE 40/80 pin cable selection (VT8237R boards for example), and many more.<br />
* Some of these options are already handled in the code via CMOS options, some are compile-time only so far, so do not yet exist at all.<br />
<br />
== Kconfig TODO ==<br />
<br />
Notes / Style guide:<br />
<br />
* Any bool variables that are (re-)defined to 'y' in Kconfig files can be simplified by using '''select FOO''' instead of the usual paragraph, as long as they're defined globally as '''default n''' boolean elsewhere.<br />
* Use '''bool''' instead of '''boolean'''.<br />
* Use '''default n''' instead of '''default false'''.<br />
<br />
Various post-conversion things to consider:<br />
<br />
* Consider ways to move crt0-y and ldscript-y out of $(src)/arch/i386/Makefile.inc where appropriate (ie. component specific)<br />
* Make various CONFIG_* variable which were in each board's Kconfig file global or per-chipset options (instead of per-board). Examples:<br />
** UDELAY_TSC, TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 (also check UDELAY_IO, APIC, etc.)<br />
** ...<br />
<br />
Stuff to port from v3 to v4:<br />
<br />
* All boards that are in v3 but not in v4 (especially Geode LX stuff. Also check amd/model_gx*).<br />
* Some remaining useful Kconfig options.<br />
<br />
== USB Debug Console ==<br />
<br />
Fix USB debug console and make the Kconfig choice actually work. Right now it's possible to transmit single characters but it's not really hooked up.<br />
<br />
== Clean up Assembler / Linker mess ==<br />
<br />
* Drop / combine / normalize .ld/.lb/.lds linker scripts.<br />
* Move them to a common place.<br />
* Drop / combine / normalize .inc / .S files.<br />
<br />
== Post codes ==<br />
<br />
* post_code consolidation: find all outb(x, 0x80).<br />
* post_code consolidation: common numbers / defines across the boards.<br />
<br />
== Geode issues ==<br />
<br />
* Fix / Unify vsmsetup.c.<br />
* Fix CS5535/CS5536/GX2/LX "chipsetinit" issue.<br />
<br />
== Use central oprom init ==<br />
<br />
* Get rid of all vgabios.c, make all chipsets with own vgabios.c use devices/oprom/x86.c.<br />
* Use the realmode code for vsmsetup too.<br />
<br />
== Stack and Suspend/Resume ==<br />
<br />
* Use CONFIG_RAMBASE + HIGH_MEMORY_SAFE instead of 0x40000 for stack.<br />
<br />
== Fix Suspend/Resume on AMD64 ==<br />
<br />
* Use cbmem in romstage on the AMD64 board(s) that have suspend/resume.<br />
<br />
== Fix ALL build warnings ==<br />
<br />
* Someone has to do the deed..<br />
<br />
== printk into buffer ==<br />
<br />
Port the v3 feature that printk can write into a buffer (that might be usable from the client OS, or dumped to output, as soon as output exists).<br />
<br />
Consider use cases first (no need to provide buffer support, if all it would be useful for is buffering pre-CAR messages - which can't be buffered).<br />
<br />
== Global variables ==<br />
<br />
* Port the global variables framework from v3.<br />
* Make use of it where appropriate.<br />
<br />
== Clear phases in romstage ==<br />
<br />
* Split up the code (esp. in romstage) into more sensibly separated phases.<br />
* Maybe use v3 for inspiration where the lines can be drawn.<br />
<br />
= Finished =<br />
<br />
== Port v3 Resource Allocator ==<br />
<br />
The v3 resource allocator should be ported to v4.<br />
<br />
'''Status:''' Upstream. It's limited to one area for resources, that doesn't overlap with fixed resources.<br />
<br />
'''Developers:''' Myles<br />
<br />
== Config & Build System ==<br />
<br />
The current system of generated Makefiles is non-ideal (for too many reasons for this little margin). Fix it, somehow. Use kconfig to improve the configuration management.<br />
<br />
'''Status:''' Upstream, boards are converted. Old system is gone. All boards build. HOWEVER, not all boards have been boot-tested yet, please report any issues you encounter!<br />
<br />
'''Developers:''' Stefan, Ron, Patrick, Uwe, Cristi<br />
<br />
== Unify text printing functions ==<br />
<br />
There are several copies of print_* and printk_* in the code. Unify them so everything is happier than before (because the disjoint features are merged).<br />
<br />
'''Developers:''' Patrick, Stefan<br />
<br />
== Common payload location ==<br />
<br />
Many boards have different names for the payload in targets/.../Config.lb (payload.elf, filo.elf, etherboot.elf, etc) and locations (../payload.elf, or various absolute paths which only work for one developer). The problem will be fixed with kconfig, where the user specifies a payload manually in "make menuconfig".</div>
Uwe
https://www.coreboot.org/index.php?title=Infrastructure_Projects&diff=10227
Infrastructure Projects
2010-12-16T21:21:59Z
<p>Uwe: /* CBFS */ TINY_BOOTBLOCK updates.</p>
<hr />
<div>This page collects a list of projects to improve the infrastructure of coreboot v4. Infrastructure means those parts of the code that aren't chipset or mainboard specific, but are used by all of them. The idea is to consolidate a list of things "to do" with their status and responsible developers.<br />
<br />
= In progress =<br />
<br />
== Low/High Tables ==<br />
<br />
SeaBIOS requires a copy of various BIOS tables outside the fseg as it overwrites that segment. Generally clean out the table generation code.<br />
<br />
'''Status:''' Upstream, implemented on some boards. There are problems on some chipsets/boards because of incorrect CONFIG_VIDEO_MB handling. The might be other issues, too (not clear, yet).<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Vendor/chipset<br />
! align="left" | Tested<br />
! align="left" | Comments<br />
<br />
|- bgcolor="#eeeeee"<br />
| amd/amdfam10<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdht<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdk8<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdmct<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/gx1<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/gx2<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/lx<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7501<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7520<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7525<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i3100<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i440bx<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82810<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82830<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i855<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i945<br />
| style="background:lime" | Y<br />
| Tested on Kontron 986LCD-M and Roda RK886EX<br />
|- bgcolor="#eeeeee"<br />
| via/cn400<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/cn700<br />
| style="background:lime" | Y<br />
| Tested on VIA pc2500e.<br />
|- bgcolor="#eeeeee"<br />
| via/cx700<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8601<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8623<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vx800<br />
| ?<br />
| &mdash;<br />
<br />
|}<br />
<br />
'''Developers:''' Stefan<br />
<br />
== CBFS ==<br />
<br />
A filesystem-alike layout for the coreboot image, to enable systems like bayou and to clean up the system in general (eg. no more buildrom).<br />
<br />
'''Status:'''<br />
<br />
Upstream, pre-CBFS infrastructure removed.<br />
<br />
There are places where using CBFS might be a good idea: Everything that makes use of external files, for example the VSA code in the Geode chipset code. VSA is converted, and tested on a couple of configurations, but untested on others.<br />
<br />
Some boards have issues with CBFS because it requires the whole ROM to be accessible at a quite early point in time (compared to the old mechanism). The following table contains validated knowledge if the ROM mapping happens at the right time.<br />
<br />
All boards that manage to boot in a tinybootblock configuration are capable at least for the used ROM size (it might be that larger ROMs would fail because they require mapping the larger space)<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Vendor/chipset<br />
! align="left" | ROM enabled<br />
! align="left" | Tiny bootblock<br />
! align="left" | Status / Comments<br />
<br />
|- bgcolor="#eeeeee"<br />
| amd/amd8111<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5530<br />
| style="background:lime" | Y<br />
| ?<br />
| Not tested on hardware, yet.<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5535<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5536<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/sb600<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/sb700<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd"<br />
| broadcom/bcm5785<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.<br />
<br />
|- bgcolor="#eeeeee"<br />
| intel/esb6300<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i3100<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82371eb<br />
| style="background:lime" | Y<br />
| style="background:yellow" | Y<br />
| Build- and runtime-tested on ASUS P2B by [[User:Uwe|Uwe Hermann]]<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801ax<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801bx<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801cx<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801dx<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801ex<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801gx<br />
| ?<br />
| ?<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd"<br />
| nvidia/ck804<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.<br />
|- bgcolor="#dddddd"<br />
| nvidia/mcp55<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.<br />
<br />
|- bgcolor="#dddddd"<br />
| sis/sis966<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.<br />
<br />
|- bgcolor="#eeeeee"<br />
| via/vt8231<br />
| style="background:yellow" | Y<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8235<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8237r<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt82c686<br />
| ?<br />
| ?<br />
| &mdash;<br />
<br />
|}<br />
<br />
'''Developers:''' Stefan, Ron, Patrick, Myles, Uwe<br />
<br />
== Tiny Bootblock ==<br />
<br />
Right now, the decision whether to use fallback or normal is in cache_as_ram_auto.c in many boards. Make that generic again (also helps with further CBFSification at some point).<br />
<br />
'''Status:''' Available in Kconfig, works on a couple of boards. Requires per southbridge changes (and northbridge in some cases) on many boards (related to ROM enable, see CBFS section).<br />
<br />
'''Developers:''' Patrick<br />
<br />
== Remove .c inclues ==<br />
<br />
Currently we include lots of code in the romstage using the preprocessor. This makes it harder to support new boards (where chipset components are supported already) and maintenance in general. So we should get rid of it where possible, using the linker for CAR boards and the build system for the remaining non-CAR boards appropriately.<br />
<br />
'''Status:''' CAR boards only for now, to keep the project manageable. i945 is modified already, and boards based on it have only one or two remaining source files they include. Interacts with the next project "Move configuration to Kconfig", which ensures that code still sees all configuration when it is compiled separately<br />
<br />
'''Developers:''' Patrick, Uwe<br />
<br />
== Move configuration to Kconfig ==<br />
<br />
Many boards have lots of <code>#define VAR somevalue</code> statements in their romstage.c which define how certain component drivers are compiled. With Kconfig, there's a better place to store them. This project is about moving all configuration values out of romstage.c (and other places if appropriate) and into Kconfig.<br />
<br />
'''Status:''' Intel and VIA based boards should be mostly configuration free, AMD boards still have defines in their romstage.<br />
<br />
'''Developers:''' Patrick, Uwe<br />
<br />
= More ideas =<br />
<br />
== Unify ACPI ==<br />
<br />
Every ACPI board has its own routines to compile the ACPI sources. Unify that. Also, figure out generic ACPI code and deduplicate it.<br />
<br />
== CMOS layout ==<br />
<br />
Allow (somehow) to define defaults for all CMOS fields, and create a static table from that. Use that at runtime if the CMOS checksum fails.<br />
<br />
== Unify UMA / onboard video code and config ==<br />
<br />
Unify CONFIG_VIDEO_MB, CONFIG_GFXUMA, and similar options and make all code honor them.<br />
<br />
== Add / Unify / Test kconfig compile-time options and runtime CMOS options in coreboot ==<br />
<br />
Some coreboot options are compile-time configurable only at the moment (via kconfig), but should also be runtime-configurable via CMOS/NVRAM options. We should fix this.<br />
<br />
* Make all options (where it makes sense) run-time configurable via CMOS options, in addition to having sane compile-time defaults configured via kconfig.<br />
* This includes many options which are northbridge-specific, many southbridge-specific, and some board-specific ones.<br />
* Example options: Enable/disable IDE channel(s) / SATA / USB / SCSI / etc., enable/disable UDMA on older boards, amount of memory used for IGP/UMA, choice between IDE or NAND flash (on CS5536 boards), IDE 40/80 pin cable selection (VT8237R boards for example), and many more.<br />
* Some of these options are already handled in the code via CMOS options, some are compile-time only so far, so do not yet exist at all.<br />
<br />
== Kconfig TODO ==<br />
<br />
Notes / Style guide:<br />
<br />
* Any bool variables that are (re-)defined to 'y' in Kconfig files can be simplified by using '''select FOO''' instead of the usual paragraph, as long as they're defined globally as '''default n''' boolean elsewhere.<br />
* Use '''bool''' instead of '''boolean'''.<br />
* Use '''default n''' instead of '''default false'''.<br />
<br />
Various post-conversion things to consider:<br />
<br />
* Consider ways to move crt0-y and ldscript-y out of $(src)/arch/i386/Makefile.inc where appropriate (ie. component specific)<br />
* Make various CONFIG_* variable which were in each board's Kconfig file global or per-chipset options (instead of per-board). Examples:<br />
** UDELAY_TSC, TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 (also check UDELAY_IO, APIC, etc.)<br />
** ...<br />
<br />
Stuff to port from v3 to v4:<br />
<br />
* All boards that are in v3 but not in v4 (especially Geode LX stuff. Also check amd/model_gx*).<br />
* Some remaining useful Kconfig options.<br />
<br />
== USB Debug Console ==<br />
<br />
Fix USB debug console and make the Kconfig choice actually work. Right now it's possible to transmit single characters but it's not really hooked up.<br />
<br />
== Clean up Assembler / Linker mess ==<br />
<br />
* Drop / combine / normalize .ld/.lb/.lds linker scripts.<br />
* Move them to a common place.<br />
* Drop / combine / normalize .inc / .S files.<br />
<br />
== Post codes ==<br />
<br />
* post_code consolidation: find all outb(x, 0x80).<br />
* post_code consolidation: common numbers / defines across the boards.<br />
<br />
== Geode issues ==<br />
<br />
* Fix / Unify vsmsetup.c.<br />
* Fix CS5535/CS5536/GX2/LX "chipsetinit" issue.<br />
<br />
== Use central oprom init ==<br />
<br />
* Get rid of all vgabios.c, make all chipsets with own vgabios.c use devices/oprom/x86.c.<br />
* Use the realmode code for vsmsetup too.<br />
<br />
== Stack and Suspend/Resume ==<br />
<br />
* Use CONFIG_RAMBASE + HIGH_MEMORY_SAFE instead of 0x40000 for stack.<br />
<br />
== Fix Suspend/Resume on AMD64 ==<br />
<br />
* Use cbmem in romstage on the AMD64 board(s) that have suspend/resume.<br />
<br />
== Fix ALL build warnings ==<br />
<br />
* Someone has to do the deed..<br />
<br />
== printk into buffer ==<br />
<br />
Port the v3 feature that printk can write into a buffer (that might be usable from the client OS, or dumped to output, as soon as output exists).<br />
<br />
Consider use cases first (no need to provide buffer support, if all it would be useful for is buffering pre-CAR messages - which can't be buffered).<br />
<br />
== Global variables ==<br />
<br />
* Port the global variables framework from v3.<br />
* Make use of it where appropriate.<br />
<br />
== Clear phases in romstage ==<br />
<br />
* Split up the code (esp. in romstage) into more sensibly separated phases.<br />
* Maybe use v3 for inspiration where the lines can be drawn.<br />
<br />
= Finished =<br />
<br />
== Port v3 Resource Allocator ==<br />
<br />
The v3 resource allocator should be ported to v4.<br />
<br />
'''Status:''' Upstream. It's limited to one area for resources, that doesn't overlap with fixed resources.<br />
<br />
'''Developers:''' Myles<br />
<br />
== Config & Build System ==<br />
<br />
The current system of generated Makefiles is non-ideal (for too many reasons for this little margin). Fix it, somehow. Use kconfig to improve the configuration management.<br />
<br />
'''Status:''' Upstream, boards are converted. Old system is gone. All boards build. HOWEVER, not all boards have been boot-tested yet, please report any issues you encounter!<br />
<br />
'''Developers:''' Stefan, Ron, Patrick, Uwe, Cristi<br />
<br />
== Unify text printing functions ==<br />
<br />
There are several copies of print_* and printk_* in the code. Unify them so everything is happier than before (because the disjoint features are merged).<br />
<br />
'''Developers:''' Patrick, Stefan<br />
<br />
== Common payload location ==<br />
<br />
Many boards have different names for the payload in targets/.../Config.lb (payload.elf, filo.elf, etherboot.elf, etc) and locations (../payload.elf, or various absolute paths which only work for one developer). The problem will be fixed with kconfig, where the user specifies a payload manually in "make menuconfig".</div>
Uwe
https://www.coreboot.org/index.php?title=Welcome_to_coreboot&diff=10226
Welcome to coreboot
2010-12-14T23:42:02Z
<p>Uwe: ASUS M2N-E</p>
<hr />
<div><table width="100%" valign="top"><tr valign="top"><td width="80%"><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
'''coreboot''' (formerly known as LinuxBIOS) is a Free Software project aimed at replacing the proprietary BIOS (firmware) you can find in most of today's computers. It performs just a little bit of hardware initialization and then executes a so-called [[Payloads|payload]].<br />
<br />
<small><br />
With this separation of hardware initialization and later boot logic, coreboot can scale from specialized applications run directly from firmware, operating systems in flash, and custom bootloaders to implementations of firmware standards like PCBIOS and EFI without having to carry features not necessary in the target application, reducing the amount of code and flash space required.<br />
</small><br />
<br />
We currently support '''[[Supported Motherboards|229]]''' different mainboards.<br />
</div><br />
<br />
{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%<br />
|-<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = yellow|<br />
WIDTH = 100%|<br />
ICON = <small>[[Benefits|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Benefits]]</span>|<br />
CONTENT =<br />
<small><br />
* 100% Free Software (GPL), no royalties, no license fees!<br />
* Fast boot times (3 seconds to Linux console)<br />
<!-- * Avoids the need for a slow/buggy/proprietary BIOS --><br />
<!-- * Runs in 32-Bit protected mode almost from the start --><br />
<!-- * Written in C, contains virtually no assembly code --><br />
* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]<br />
<!-- * Further features: netboot, serial console, remote flashing, ... --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = #d1adf6|<br />
WIDTH = 100%|<br />
ICON = <small>[[Use Cases|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Use Cases]]</span>|<br />
CONTENT =<br />
<small><br />
* Desktop PCs, servers, [[Laptop|laptops]]<br />
* [[Clusters]]<br />
<!-- * Set-Top-Boxes, thin clients --><br />
* Embedded solutions<br />
<!-- * [http://en.wikipedia.org/wiki/Small_form_factor Small form factor computers], [http://en.wikipedia.org/wiki/Home_theater_PC Home-theater PCs] --><br />
<!-- * No-moving-parts solutions (ROM chip as "disk") --><br />
<!-- * Non-standard scenarios (e.g. FPGA in Opteron socket) --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = lime|<br />
WIDTH = 100%|<br />
ICON = <small>[[Payloads|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Payloads]]</span>|<br />
CONTENT =<br />
<small><br />
* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] <!-- / [[OpenFirmware]] / [[OpenBIOS]] --><br />
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] <!-- / [http://openbsd.org/ OpenBSD]--><br />
* [[Etherboot]] / [[GPXE]] / [[Payloads|...]]<br />
<!--* [[Memtest86]]<br />
* [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]--><br />
</small><br />
}}<br />
<br />
|}<br />
<br />
{| cellspacing=5 cellpadding=15 border=0 valign="top" width=100%<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_cb.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">About</span>'''<br /><small>Find out more about coreboot.</small><small><hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_devel.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Developers</span>'''<br /><small>Get involved! Help us make coreboot better.</small><small><hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://tracker.coreboot.org/trac/coreboot/browser/trunk Browse Source] | [[GSoC]] | [[Flag Days]]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_status.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Status</span>'''<br /><small>Find out whether your hardware is already supported.</small><small><hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [http://qa.coreboot.org Build Status]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_tools.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Related Tools</span>'''<br /><small>Tools and libraries related to coreboot.</small><small><hr />[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [[SerialICE]]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_101.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Getting Started</span>'''<br /><small>Download coreboot and get started.</small><small><hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_support.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Support</span>'''<br /><small>Learn how to contact us and find help and support.</small><small><hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|coreboot Options]]</small><br />
|}<br />
<br />
|}<br />
</td><td width="20%"><br />
<br />
[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]<br />
<br />
<br clear=all /><br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[News]]</span>'''<hr /><br />
<!-- Please always make this list 7 items long (7 most recent news items). --><br />
<small><br />
* '''2010/12/13:''' [[News#2010.2F12.2F13_ASUS_M2N-E_now_supported|ASUS M2N-E support]]<br />
* '''2010/12/06:''' [[News#2010.2F12.2F06_ASUS_M4A78-EM_now_supported|ASUS M4A78-EM support]]<br />
* '''2010/11/11:''' [[News#2010.2F11.2F11_ASUS_M2V_now_supported|ASUS M2V support]]<br />
* '''2010/09/13:''' [[News#2010.2F09.2F13_ASUS_M4A785-M_now_supported|ASUS M4A785-M support]]<br />
* '''2010/09/10:''' [[News#2010.2F09.2F10_LiPPERT_LiteRunner-LX_and_Hurricane-LX_now_supported|LiPPERT LiteRunner-LX and Hurricane-LX support]]<br />
* '''2010/08/17:''' [[News#2010.2F08.2F17_GIGABYTE_GA-MA785GMT-UD2H_now_supported|GIGABYTE GA-MA785GMT-UD2H support]]<br />
* '''2010/08/17:''' [[News#2010.2F08.2F17_GIGABYTE_GA-MA78GM-US2H_now_supported|GIGABYTE GA-MA78GM-US2H support]]<br />
</small><br />
<br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[Current events|Upcoming Events]]</span>'''<hr /><br />
<!-- List of upcoming events (remove events after they have taken place). --><br />
<small><br />
<!-- * '''2010/mon/day:''' coreboot event at [[Link]] in somecity --><br />
* None, currently.<br />
</small><br />
<br />
</td></tr></table><br />
<br />
__NOTOC__<br />
__NOEDITSECTION__</div>
Uwe
https://www.coreboot.org/index.php?title=Superiotool&diff=10223
Superiotool
2010-12-13T19:10:35Z
<p>Uwe: Winbond/Nuvoton W83527HG detection.</p>
<hr />
<div>'''Superiotool''' is a GPL'd user-space helper tool for coreboot development purposes (but may also be useful for other things). It allows you to detect which [[wikipedia:Super I/O|Super I/O]] you have on your mainboard, and it can provide detailed information about the register contents of the Super I/O.<br />
<br />
This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.<br />
<br />
<gallery><br />
Image:Ite it8705f.jpg|<small>ITE IT8705F</small><br />
Image:Winbond w83977ef.jpg|<small>Winbond W83977EF</small><br />
</gallery><br />
<br />
== Support of various devices ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M1535/M1535D/M1535+/M1535D+<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/048024.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5105<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5107<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5109<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5113<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5119<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M512x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513x<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513xB<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513xF<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M514x<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-September/024916.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-July/050471.html 2], [http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html 3]<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71862FG / F71863FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71889<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71872F/FG / F71806F/FG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71882FG/F71883FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040016.html 1], [http://www.flashrom.org/pipermail/flashrom/2010-August/004390.html 2]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-November/026831.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F8000<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C711<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C712<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C721<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C735<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8228E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8502E/F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8510E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8511E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8512E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8661F/IT8770F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://article.gmane.org/gmane.linux.bios/42100/ 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F/IT8687R<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2010-May/058010.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT86793<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8702F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8703F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8705F/AF / IT8700F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026913.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8706R<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8708F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024879.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8710F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8711F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 2]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024884.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8720F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8722F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8726F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8761E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8780F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| HMC<br />
| HMC83755<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Holtek<br />
| HT6552IR<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS307<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS308<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS309<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS317<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS338<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS351<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97307<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/047843.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87309<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87360<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026991.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87351<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87364<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87365<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87363<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87366<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8739x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/043447.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87591x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8741x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87372<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8374L<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071014/19fe07aa/attachment-0001.htm 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87427<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87373<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xFR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N971<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-July/003832.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N972<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N252<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-June/050276.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M172<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xAPM<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C67x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B80x/FDC37M707<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N958FR<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027036.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B77x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B78x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M602<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M60x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B72x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M81x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B27x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027245.html 1]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027248.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B37x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47U33x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B34x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S42x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M10x/112/13x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025451.html 1] <br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B357<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M14x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M15x/192/997<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-December/028269.html 1]<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-February/030897.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S45x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M292<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B387<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B397<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M182<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M584<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| DME1737<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5504<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N217<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5514D-NS<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3112<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3114<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3116<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5317<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5027<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH4307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669FR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N237<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N769<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024883.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N3869/FDC37N869<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N227<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025846.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SIO10N268<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C665GT/IR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C666GT<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SIS6801<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SIS950<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686A/VT82C686B<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977CTF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977EF/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040507.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83527HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627SF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697HF/F/HG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-August/004443.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83L517D/D-F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83637HF/HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627THF/THG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment.txt 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025599.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-August/037685.html 3], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 4]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment-0001.txt 1]<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627DHG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-January/029517.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627UHG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83667HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977F-A/G-A/AF-A/AG-A<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977AF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977TF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627HF/F/HG/G<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025453.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025592.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697SF/UF/UG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025914.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627EHF/EF/EHG/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024887.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025284.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-January/029416.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877AF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-February/002119.html]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877TF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| WPCD376I<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-October/053894.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM82C862<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8663BF<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8669<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8670<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|}<br />
<br />
|}<br />
<br />
'''Extended dumps (EC, HWM) available for:'''<br />
<br />
Use the '''--extra-dump''' option to see the contents of these registers.<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 1]<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond<br />
| W83627THF/THG HWM<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMSC<br />
| LPC47N227 runtime register block<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
<br />
<small><br />
<sup>1</sup> Previosly National Semiconductor, now bought by Winbond.<br /><br />
<sup>2</sup> Register dump output from a running coreboot system (vs. proprietary BIOS).<br /><br />
</small><br />
<br />
== Installation ==<br />
<br />
'''Manual installation'''<br />
<br />
$ svn co svn://coreboot.org/coreboot/trunk/util/superiotool<br />
$ cd superiotool<br />
$ make<br />
$ sudo make install<br />
<br />
'''Debian / Ubuntu'''<br />
<br />
$ apt-get install superiotool<br />
<br />
'''Fedora'''<br />
<br />
$ yum install superiotool<br />
<br />
== Usage ==<br />
<br />
Probe/detect the Super I/O in your mainboard:<br />
<br />
$ superiotool<br />
<br />
Register dump as table of hex-values (if the Super I/O is detected):<br />
<br />
$ superiotool -d<br />
<br />
Please see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool/README README] for further information.<br />
<br />
{{GPL}}</div>
Uwe
https://www.coreboot.org/index.php?title=Welcome_to_coreboot&diff=10212
Welcome to coreboot
2010-12-07T19:56:52Z
<p>Uwe: ASUS M4A78-EM</p>
<hr />
<div><table width="100%" valign="top"><tr valign="top"><td width="80%"><br />
<br />
<div style="margin-top:0.5em; margin-bottom:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#efefff; align:right; border:1px solid #aabbcc;"><br />
'''coreboot''' (formerly known as LinuxBIOS) is a Free Software project aimed at replacing the proprietary BIOS (firmware) you can find in most of today's computers. It performs just a little bit of hardware initialization and then executes a so-called [[Payloads|payload]].<br />
<br />
<small><br />
With this separation of hardware initialization and later boot logic, coreboot can scale from specialized applications run directly from firmware, operating systems in flash, and custom bootloaders to implementations of firmware standards like PCBIOS and EFI without having to carry features not necessary in the target application, reducing the amount of code and flash space required.<br />
</small><br />
<br />
We currently support '''[[Supported Motherboards|228]]''' different mainboards.<br />
</div><br />
<br />
{| cellspacing=0 cellpadding=8 border=0 margin=0 padding=0 align="top" width=100%<br />
|-<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = yellow|<br />
WIDTH = 100%|<br />
ICON = <small>[[Benefits|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Benefits]]</span>|<br />
CONTENT =<br />
<small><br />
* 100% Free Software (GPL), no royalties, no license fees!<br />
* Fast boot times (3 seconds to Linux console)<br />
<!-- * Avoids the need for a slow/buggy/proprietary BIOS --><br />
<!-- * Runs in 32-Bit protected mode almost from the start --><br />
<!-- * Written in C, contains virtually no assembly code --><br />
* Supports many [[Supported Motherboards|mainboards]], [[Supported Chipsets and Devices|chipsets]], and [[payloads]]<br />
<!-- * Further features: netboot, serial console, remote flashing, ... --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = #d1adf6|<br />
WIDTH = 100%|<br />
ICON = <small>[[Use Cases|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Use Cases]]</span>|<br />
CONTENT =<br />
<small><br />
* Desktop PCs, servers, [[Laptop|laptops]]<br />
* [[Clusters]]<br />
<!-- * Set-Top-Boxes, thin clients --><br />
* Embedded solutions<br />
<!-- * [http://en.wikipedia.org/wiki/Small_form_factor Small form factor computers], [http://en.wikipedia.org/wiki/Home_theater_PC Home-theater PCs] --><br />
<!-- * No-moving-parts solutions (ROM chip as "disk") --><br />
<!-- * Non-standard scenarios (e.g. FPGA in Opteron socket) --><br />
</small><br />
}}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{{Box|<br />
BORDER = #8898bf|<br />
BACKGROUND = lime|<br />
WIDTH = 100%|<br />
ICON = <small>[[Payloads|More...]]</small>|<br />
HEADING = <span style="font-variant:small-caps; font-size:120%">[[Payloads]]</span>|<br />
CONTENT =<br />
<small><br />
* [[SeaBIOS]] / [[FILO]] / [[GRUB2]] / [[Payloads|...]] <!-- / [[OpenFirmware]] / [[OpenBIOS]] --><br />
* [[Linux]] / [[Windows]] / [[FreeBSD]] / [[NetBSD]] / [[Payloads|...]] <!-- / [http://openbsd.org/ OpenBSD]--><br />
* [[Etherboot]] / [[GPXE]] / [[Payloads|...]]<br />
<!--* [[Memtest86]]<br />
* [[Bayou]] / [[Coreinfo]] / [[Tint]] / [[Libpayload]]--><br />
</small><br />
}}<br />
<br />
|}<br />
<br />
{| cellspacing=5 cellpadding=15 border=0 valign="top" width=100%<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_cb.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">About</span>'''<br /><small>Find out more about coreboot.</small><small><hr />[[Press]] | [[Logo]] | [[History]] | [[Screenshots|Screenshots/Videos]] | [[Contributors]] | [[Sponsors]] | [[Products]] | [[Vendors]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_devel.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Developers</span>'''<br /><small>Get involved! Help us make coreboot better.</small><small><hr />[[Development Guidelines]] | [[Developer Manual]] | [http://qa.coreboot.org/docs/doxygen.php Doxygen] | [http://tracker.coreboot.org/trac/coreboot/browser/trunk Browse Source] | [[GSoC]] | [[Flag Days]]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_status.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Status</span>'''<br /><small>Find out whether your hardware is already supported.</small><small><hr />[[Supported Motherboards|Supported Boards]] | [[Supported Chipsets and Devices|Supported Chipsets]] | [[:Category:Tutorials|Board Status Pages]] | [http://qa.coreboot.org Build Status]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_tools.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Related Tools</span>'''<br /><small>Tools and libraries related to coreboot.</small><small><hr />[[Flashrom]] | [[Superiotool]] | [[Nvramtool]] | [[Buildrom]] | [[Mkelfimage]] | [[Inteltool]] | [[Msrtool]] | [[Ectool]] | [[Developer_Manual/Tools|Hardware tools]] | [[Abuild]] | [[SerialICE]]</small><br />
|}<br />
<br />
|-<br />
| width=50% style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_101.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Getting Started</span>'''<br /><small>Download coreboot and get started.</small><small><hr />[[Build HOWTO]] | [[Download coreboot|Downloads]] | [[Documentation]] | [[QEMU]] | [[AMD SimNow]] | [[Build from Windows]]</small><br />
|}<br />
<br />
|style="vertical-align:top"|<br />
<br />
{|<br />
|style="vertical-align:top"|<br />
[[Image:chip_support.png]]<br />
|style="vertical-align:top"|<br />
'''<span style="font-variant:small-caps; font-size:150%">Support</span>'''<br /><small>Learn how to contact us and find help and support.</small><small><hr />[[FAQ]] | [[Mailinglist]] | [[IRC]] | [http://tracker.coreboot.org/trac/coreboot/ Issue Tracker] | [[Glossary]] | [[coreboot Options|coreboot Options]]</small><br />
|}<br />
<br />
|}<br />
</td><td width="20%"><br />
<br />
[[File:Coreboot menuconfig.png|center|thumb|[[Build HOWTO|make menuconfig]] in coreboot]]<br />
<br />
<br clear=all /><br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[News]]</span>'''<hr /><br />
<!-- Please always make this list 7 items long (7 most recent news items). --><br />
<small><br />
* '''2010/12/06:''' [[News#2010.2F12.2F06_ASUS_M4A78-EM_now_supported|ASUS M4A78-EM support]]<br />
* '''2010/11/11:''' [[News#2010.2F11.2F11_ASUS_M2V_now_supported|ASUS M2V support]]<br />
* '''2010/09/13:''' [[News#2010.2F09.2F13_ASUS_M4A785-M_now_supported|ASUS M4A785-M support]]<br />
* '''2010/09/10:''' [[News#2010.2F09.2F10_LiPPERT_LiteRunner-LX_and_Hurricane-LX_now_supported|LiPPERT LiteRunner-LX and Hurricane-LX support]]<br />
* '''2010/08/17:''' [[News#2010.2F08.2F17_GIGABYTE_GA-MA785GMT-UD2H_now_supported|GIGABYTE GA-MA785GMT-UD2H support]]<br />
* '''2010/08/17:''' [[News#2010.2F08.2F17_GIGABYTE_GA-MA78GM-US2H_now_supported|GIGABYTE GA-MA78GM-US2H support]]<br />
* '''2010/06/22:''' [[News#2010.2F06.2F22_INTEL_D810E2CB_now_supported|Intel D810E2CB support]]<br />
</small><br />
<br />
<br />
'''<span style="font-variant:small-caps; font-size:120%">[[Current events|Upcoming Events]]</span>'''<hr /><br />
<!-- List of upcoming events (remove events after they have taken place). --><br />
<small><br />
<!-- * '''2010/mon/day:''' coreboot event at [[Link]] in somecity --><br />
* None, currently.<br />
</small><br />
<br />
</td></tr></table><br />
<br />
__NOTOC__<br />
__NOEDITSECTION__</div>
Uwe
https://www.coreboot.org/index.php?title=Build_HOWTO&diff=10210
Build HOWTO
2010-12-05T21:20:40Z
<p>Uwe: This is not material for a generic build HOWTO page.</p>
<hr />
<div>[[File:Coreboot menuconfig.png|thumb|right|'''make menuconfig''' in coreboot]]<br />
<br />
This page describes how you can build a coreboot image for your specific mainboard using the '''kconfig''' system (a.k.a. '''make menuconfig''').<br />
<br />
== Requirements ==<br />
<br />
* gcc / g++<br />
* make<br />
* ncurses-dev (for '''make menuconfig''')<br />
<br />
Optional:<br />
<br />
* doxygen (for generating/viewing documentation)<br />
* iasl (for targets with ACPI support)<br />
* gdb (for better debugging facilities on some targets)<br />
* flex and bison (for regenerating parsers)<br />
<br />
== Building a payload ==<br />
<br />
First you need to download the source code for the [[Payloads|payload]] of your choice and build it.<br />
<br />
Instructions for building the various payloads are not covered on this page, please see [[Payloads]] and the wiki page for the respective payload for details.<br />
<br />
The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).<br />
<br />
== Building coreboot ==<br />
<br />
First, get the latest coreboot subversion version:<br />
<br />
$ '''svn co svn://coreboot.org/coreboot/trunk coreboot'''<br />
$ '''cd coreboot'''<br />
<br />
In the coreboot directory you can configure the build-time options of coreboot:<br />
<br />
$ '''make menuconfig'''<br />
<br />
In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:<br />
<br />
* Enter the '''Mainboard''' menu.<br />
** In '''Mainboard vendor''' select the vendor of your board.<br />
** In '''Mainboard model''' select your exact mainboard name.<br />
** In '''ROM chip size''' select the exact size of the flash ROM chip you want to flash the coreboot image on.<br />
* Enter the '''Payload''' menu.<br />
** Set the '''Add a payload''' option to '''An ELF executable payload'''.<br />
** Then, specify the file name and path to your payload file (which you built before).<br />
<br />
That's the bare minimum. Feel free to adjust the other settings to your needs (see [[Coreboot Options]] for the full list), then exit menuconfig and build the coreboot image:<br />
<br />
$ '''make'''<br />
<br />
The file '''build/coreboot.rom''' is your final coreboot image you can flash onto a ROM chip.<br />
<br />
== Flashing coreboot ==<br />
<br />
You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the [http://www.flashrom.org flashrom] user-space utility.<br />
<br />
== Manipulating coreboot images with cbfstool ==<br />
<br />
TODO</div>
Uwe
https://www.coreboot.org/index.php?title=Board:asus/m2n-e&diff=10205
Board:asus/m2n-e
2010-12-05T11:18:10Z
<p>Uwe: ASUS M2N-E status page.</p>
<hr />
<div>This page describes how to use coreboot on the '''[http://www.asus.com/product.aspx?P_ID=NFlvt10av3F7ayQ9 ASUS M2N-E]''' mainboard. It is maintained by [[User:Uwe|Uwe Hermann]].<br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_comments = I'm using: CPU model AMD Sempron(tm) Processor 3000+<br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)<br />
|CPU_L2_status = OK<br />
|CPU_L2_comments = CPU: L2 Cache: 256K (64 bytes/line)<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = Untested<br />
|CPU_multicore_comments = I don't have a multicore CPU to test with, but it should work.<br />
|CPU_virt_status = Untested<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = N/A<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = OK<br />
|RAM_DDR2_comments = Tested: One 512 MB DIMM in slot DIMM_A2 (see manual).<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = Untested<br />
|RAM_ecc_status = Untested<br />
<br />
|IDE_status = OK<br />
|IDE_comments = Tested: Booting from IDE disk (CF card actually).<br />
|IDE_25_status = N/A<br />
|SATA_status = Untested<br />
|SATA_comments = <br />
|USB_status = OK<br />
|USB_comments = Tested: USB keyboard on all 10 USB ports.<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = OK<br />
|Onboard_audio_status = OK<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
<br />
|ISA_cards_status = N/A<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|AGP_cards_status = N/A<br />
|PCI_cards_status = WIP<br />
|PCI_cards_comments = The outermost PCI slot doesn't work yet, the other two work fine. Tested: PCI graphics card.<br />
|PCIE_x1_status = Untested<br />
|PCIE_x1_comments = <br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = Untested<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = Untested<br />
|PCIE_x16_comments = <br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|Floppy_comments = <br />
|COM1_status = OK<br />
|COM2_status = N/A<br />
|PP_status = OK<br />
|PP_comments = Tested: '''modprobe ppdev'''.<br />
|PS2_keyboard_status = OK<br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments = The '''k8temp''', '''it87''', '''lm85''', '''eeprom''' and '''i2c-nforce2''' / '''i2c-dev''' modules load fine and seem to work.<br />
|Watchdog_status = Untested<br />
|Watchdog_comments = <br />
|SMBus_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = WIP<br />
|CPUfreq_comments = Doesn't work, yet.<br />
|Powersave_status = N/A<br />
|ACPI_status = No<br />
|ACPI_comments = There's no ACPI implementation for this board, yet.<br />
|Reboot_status = OK<br />
|Poweroff_status = No<br />
|Poweroff_comments = Needs ACPI support.<br />
|LEDs_status = OK<br />
|LEDs_comments = There's a power-on LED on the board PCB, it lights up when the board is powered up.<br />
|HPET_status = Untested<br />
|HPET_comments = <br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = WIP<br />
|Flashrom_comments = Works fine with the proprietary BIOS, the may be issues when booted with coreboot though (investigating).<br />
<br />
}}<br />
<br />
{{PD-self}}</div>
Uwe
https://www.coreboot.org/index.php?title=Superiotool&diff=10189
Superiotool
2010-11-29T13:54:20Z
<p>Uwe: Fintek F71889</p>
<hr />
<div>'''Superiotool''' is a GPL'd user-space helper tool for coreboot development purposes (but may also be useful for other things). It allows you to detect which [[wikipedia:Super I/O|Super I/O]] you have on your mainboard, and it can provide detailed information about the register contents of the Super I/O.<br />
<br />
This utility should work on most modern UNIX-like operating systems; it has been tested on at least Linux and FreeBSD.<br />
<br />
<gallery><br />
Image:Ite it8705f.jpg|<small>ITE IT8705F</small><br />
Image:Winbond w83977ef.jpg|<small>Winbond W83977EF</small><br />
</gallery><br />
<br />
== Support of various devices ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M1535/M1535D/M1535+/M1535D+<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/048024.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5105<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5107<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5109<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5113<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M5119<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M512x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513x<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513xB<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M513xF<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ALi<br />
| M514x<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-September/024916.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-July/050471.html 2], [http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html 3]<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71862FG / F71863FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71889<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71872F/FG / F71806F/FG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71882FG/F71883FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040016.html 1], [http://www.flashrom.org/pipermail/flashrom/2010-August/004390.html 2]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/linuxbios/2007-November/026831.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F8000<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C711<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C712<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C721<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Chips&Tech<br />
| F82C735<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8228E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8502E/F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8510E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8511E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8512E/TE/G<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8661F/IT8770F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://article.gmane.org/gmane.linux.bios/42100/ 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F/IT8687R<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2010-May/058010.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT86793<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8702F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8703F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8705F/AF / IT8700F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026913.html 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8706R<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8708F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024879.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8710F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8711F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 2]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026957.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024884.html 1], [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8720F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8722F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8726F<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8761E<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8780F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| HMC<br />
| HMC83755<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Holtek<br />
| HT6552IR<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS307<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS308<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS309<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS317<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS338<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| NS351<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97307<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-May/047843.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC97317<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87309<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87360<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/026991.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87351<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87364<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87365<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87363<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87366<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8739x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/043447.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87591x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8741x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87372<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC8374L<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071014/19fe07aa/attachment-0001.htm 1], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 2]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87427<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<sup>1</sup><br />
| PC87373<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xFR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N971<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-July/003832.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N972<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N252<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-June/050276.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M172<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C93xAPM<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C67x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B80x/FDC37M707<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N958FR<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027036.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B77x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B78x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M602<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M60x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37B72x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37M81x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B27x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027245.html 1]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-November/027248.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B37x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47U33x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B34x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S42x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M10x/112/13x<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025451.html 1] <br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B357<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M14x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M15x/192/997<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-December/028269.html 1]<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-February/030897.html 1]<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47S45x<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M292<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B387<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47B397<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M182<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47M584<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| A8000<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| DME1737<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5504<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N217<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5514D-NS<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3112<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3114<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH3116<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5317<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH5027<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SCH4307<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C669FR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N237<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N769<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024883.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37N3869/FDC37N869<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| LPC47N227<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025846.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| SIO10N268<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C665GT/IR<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC<br />
| FDC37C666GT<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SIS6801<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SIS950<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|}<br />
<br />
| valign="top"|<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686A/VT82C686B<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977CTF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977EF/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-October/040507.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627SF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697HF/F/HG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-August/004443.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83L517D/D-F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83637HF/HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627THF/THG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment.txt 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025599.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-August/037685.html 3], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 4]<br />
| [http://www.linuxbios.org/pipermail/linuxbios/attachments/20071009/5c245359/attachment-0001.txt 1]<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627DHG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-January/029517.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627UHG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83667HG<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977F-A/G-A/AF-A/AG-A<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977AF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977TF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83977ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627HF/F/HG/G<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025453.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025592.html 2], [http://www.coreboot.org/pipermail/coreboot/2009-June/050259.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83697SF/UF/UG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025914.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83627EHF/EF/EHG/EG<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.linuxbios.org/pipermail/linuxbios/2007-September/024887.html 1], [http://www.linuxbios.org/pipermail/linuxbios/2007-October/025284.html 2], [http://www.coreboot.org/pipermail/coreboot/2008-January/029416.html 3]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877F<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877AF<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.flashrom.org/pipermail/flashrom/2010-February/002119.html]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877TF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| W83877ATF<br />
| style="background:lime" | Yes<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond<br />
| WPCD376I<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2009-October/053894.html 1]<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM82C862<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8663BF<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8669<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|- bgcolor="#dddddd" valign="top"<br />
| UMC<br />
| UM8670<br />
| style="background:red" | No<br />
| style="background:red" | No<br />
| &mdash;<br />
| &mdash;<br />
|}<br />
<br />
|}<br />
<br />
'''Extended dumps (EC, HWM) available for:'''<br />
<br />
Use the '''--extra-dump''' option to see the contents of these registers.<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super I/O<br />
! align="left" | Detect<br />
! align="left" | Dump<br />
! align="left" | BIOS<br />
! align="left" | CB<sup>2</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-December/042980.html 1]<br />
| &mdash;<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F EC<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| [http://www.coreboot.org/pipermail/coreboot/2008-May/034452.html 1]<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond<br />
| W83627THF/THG HWM<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMSC<br />
| LPC47N227 runtime register block<br />
| style="background:lime" | Yes<br />
| style="background:lime" | Yes<br />
| &mdash;<br />
| &mdash;<br />
<br />
|}<br />
<br />
<br />
<small><br />
<sup>1</sup> Previosly National Semiconductor, now bought by Winbond.<br /><br />
<sup>2</sup> Register dump output from a running coreboot system (vs. proprietary BIOS).<br /><br />
</small><br />
<br />
== Installation ==<br />
<br />
'''Manual installation'''<br />
<br />
$ svn co svn://coreboot.org/coreboot/trunk/util/superiotool<br />
$ cd superiotool<br />
$ make<br />
$ sudo make install<br />
<br />
'''Debian / Ubuntu'''<br />
<br />
$ apt-get install superiotool<br />
<br />
'''Fedora'''<br />
<br />
$ yum install superiotool<br />
<br />
== Usage ==<br />
<br />
Probe/detect the Super I/O in your mainboard:<br />
<br />
$ superiotool<br />
<br />
Register dump as table of hex-values (if the Super I/O is detected):<br />
<br />
$ superiotool -d<br />
<br />
Please see the [http://tracker.coreboot.org/trac/coreboot/browser/trunk/util/superiotool/README README] for further information.<br />
<br />
{{GPL}}</div>
Uwe
https://www.coreboot.org/index.php?title=Board:asus/p2b&diff=10188
Board:asus/p2b
2010-11-29T10:46:46Z
<p>Uwe: </p>
<hr />
<div>[[Image:p2b-1_04.jpg|thumb|The ASUS P2B, rev. 1.04]]<br />
[[File:Asus p2b.jpg|thumb|Another ASUS P2B, rev. 1.04]]<br />
[[Image:Asus-P2B-1_10.jpg|thumb|The ASUS P2B, rev. 1.10]]<br />
<br />
This page lists the coreboot status of the '''[ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b/ ASUS P2B]''' mainboard. It's maintained by [[User:Uwe|Uwe Hermann]].<br />
<br />
<!-- <br clear="all" /> --><br />
<br />
== Status ==<br />
<br />
{{Status|<br />
<br />
|CPU_status = OK<br />
|CPU_L1_status = OK<br />
|CPU_L1_comments = CPU: L1 I cache: 16K, L1 D cache: 16K<br />
|CPU_L2_status = WIP<br />
|CPU_L2_comments = L2 cache is not being enabled at the moment. We're working on fixing it.<br />
|CPU_L3_status = N/A<br />
|CPU_multiple_status = N/A<br />
|CPU_multicore_status = N/A<br />
|CPU_virt_status = N/A<br />
<br />
|RAM_EDO_status = N/A<br />
|RAM_SDRAM_status = OK<br />
|RAM_SODIMM_status = N/A<br />
|RAM_DDR_status = N/A<br />
|RAM_DDR2_status = N/A<br />
|RAM_DDR3_status = N/A<br />
|RAM_dualchannel_status = N/A<br />
|RAM_ecc_status = WIP<br />
|RAM_ecc_comments = Not yet supported by the coreboot 440BX code, but it's on our TODO list.<br />
<br />
|IDE_status = OK<br />
|IDE_25_status = N/A<br />
|SATA_status = N/A<br />
|USB_status = OK<br />
|USB_comments = Tested: USB keyboard in both USB ports.<br />
|Onboard_VGA_status = N/A<br />
|Onboard_ethernet_status = N/A<br />
|Onboard_audio_status = N/A<br />
|Onboard_modem_status = N/A<br />
|Onboard_firewire_status = N/A<br />
|Smartcard_status = N/A<br />
|Onboard_CF_status = N/A<br />
|Onboard_PCMCIA_status = N/A<br />
|Onboard_SCSI_status = N/A<br />
<br />
|ISA_cards_status = Untested<br />
|AMR_cards_status = N/A<br />
|Mini_PCI_cards_status = N/A<br />
|PCIX_cards_status = N/A<br />
|PCI_cards_status = OK<br />
|PCI_cards_comments = Tested: PCI NIC (in all slots); graphics card.<br />
|AGP_cards_status = OK<br />
|AGP_cards_comments = Tested: AGP graphics card.<br />
|PCIE_cards_status = N/A<br />
|PCIE_x1_status = N/A<br />
|PCIE_x2_status = N/A<br />
|PCIE_x4_status = N/A<br />
|PCIE_x8_status = N/A<br />
|PCIE_x16_status = N/A<br />
|PCIE_x32_status = N/A<br />
|HTX_status = N/A<br />
<br />
|Floppy_status = Untested<br />
|COM1_status = OK<br />
|COM2_status = OK<br />
|PP_status = OK<br />
|PP_comments = Doing '''modprobe ppdev''' works, but no further tests were performed.<br />
|PS2_keyboard_status = OK<br />
|PS2_keyboard_comments = <br />
|PS2_mouse_status = Untested<br />
|Game_port_status = N/A<br />
|IR_status = N/A<br />
|Speaker_status = OK<br />
|DiskOnChip_status = N/A<br />
<br />
|Sensors_status = OK<br />
|Sensors_comments = Works fine, you can use the '''w83781d''', '''i2c-piix4''', and '''eeprom''' kernel modules.<br />
|Watchdog_status = N/A<br />
|CAN_bus_status = N/A<br />
|CPUfreq_status = N/A<br />
|Powersave_status = N/A<br />
|ACPI_status = WIP<br />
|ACPI_comments = Poweroff, S1, powerbutton event work. S3 is not implemented yet.<br />
|SMBus_status = Untested<br />
|SMBus_comment = Internal CMBus devices are accessible, so the CMBus header should work.<br />
|Reboot_status = OK<br />
|Poweroff_status = OK<br />
|Poweroff_comments = With ACPI enabled, non-ACPI poweroff would require SMM & [[SeaBIOS]] support.<br />
|LEDs_status = N/A<br />
|LEDs_comments = No special-purpose LEDs available on the board.<br />
|HPET_status = N/A<br />
|RNG_status = N/A<br />
|WakeOnModem_status = Untested<br />
|WakeOnLAN_status = Untested<br />
|WakeOnKeyboard_status = Untested<br />
|WakeOnMouse_status = Untested<br />
|Flashrom_status = OK<br />
<br />
}}<br />
<br />
<br />
{{GPL}}</div>
Uwe
https://www.coreboot.org/index.php?title=Datasheets&diff=10177
Datasheets
2010-11-27T17:37:07Z
<p>Uwe: /* CPU */ Some Pentium III links.</p>
<hr />
<div></div>
Uwe
https://www.coreboot.org/index.php?title=Infrastructure_Projects&diff=10176
Infrastructure Projects
2010-11-26T22:59:20Z
<p>Uwe: /* CBFS */ Add tinybootblock column and some status entries.</p>
<hr />
<div>This page collects a list of projects to improve the infrastructure of coreboot v4. Infrastructure means those parts of the code that aren't chipset or mainboard specific, but are used by all of them. The idea is to consolidate a list of things "to do" with their status and responsible developers.<br />
<br />
= In progress =<br />
<br />
== Low/High Tables ==<br />
<br />
SeaBIOS requires a copy of various BIOS tables outside the fseg as it overwrites that segment. Generally clean out the table generation code.<br />
<br />
'''Status:''' Upstream, implemented on some boards. There are problems on some chipsets/boards because of incorrect CONFIG_VIDEO_MB handling. The might be other issues, too (not clear, yet).<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Vendor/chipset<br />
! align="left" | Tested<br />
! align="left" | Comments<br />
<br />
|- bgcolor="#eeeeee"<br />
| amd/amdfam10<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdht<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdk8<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/amdmct<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/gx1<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/gx2<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/lx<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7501<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7520<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/e7525<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i3100<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i440bx<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82810<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82830<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i855<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i945<br />
| style="background:lime" | Y<br />
| Tested on Kontron 986LCD-M and Roda RK886EX<br />
|- bgcolor="#eeeeee"<br />
| via/cn400<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/cn700<br />
| style="background:lime" | Y<br />
| Tested on VIA pc2500e.<br />
|- bgcolor="#eeeeee"<br />
| via/cx700<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8601<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8623<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vx800<br />
| ?<br />
| &mdash;<br />
<br />
|}<br />
<br />
'''Developers:''' Stefan<br />
<br />
== CBFS ==<br />
<br />
A filesystem-alike layout for the coreboot image, to enable systems like bayou and to clean up the system in general (eg. no more buildrom).<br />
<br />
'''Status:'''<br />
<br />
Upstream, pre-CBFS infrastructure removed.<br />
<br />
There are places where using CBFS might be a good idea: Everything that makes use of external files, for example the VSA code in the Geode chipset code. VSA is converted, and tested on a couple of configurations, but untested on others.<br />
<br />
Some boards have issues with CBFS because it requires the whole ROM to be accessible at a quite early point in time (compared to the old mechanism). The following table contains validated knowledge if the ROM mapping happens at the right time.<br />
<br />
All boards that manage to boot in a tinybootblock configuration are capable at least for the used ROM size (it might be that larger ROMs would fail because they require mapping the larger space)<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699ff"<br />
! align="left" | Vendor/chipset<br />
! align="left" | ROM enabled<br />
! align="left" | Tiny bootblock<br />
! align="left" | Status / Comments<br />
<br />
|- bgcolor="#eeeeee"<br />
| amd/amd8111<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5530<br />
| style="background:lime" | Y<br />
| ?<br />
| Not tested on hardware, yet.<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5535<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/cs5536<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/sb600<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| amd/sb700<br />
| ?<br />
| ?<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd"<br />
| broadcom/bcm5785<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.<br />
<br />
|- bgcolor="#eeeeee"<br />
| intel/esb6300<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i3100<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82371eb<br />
| style="background:lime" | Y<br />
| style="background:yellow" | Y<br />
| Build- and runtime-tested on ASUS P2B by [[User:Uwe|Uwe Hermann]]<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801ax<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801bx<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801cx<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801dx<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801ex<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| intel/i82801gx<br />
| ?<br />
| ?<br />
| &mdash;<br />
<br />
|- bgcolor="#dddddd"<br />
| nvidia/ck804<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.<br />
|- bgcolor="#dddddd"<br />
| nvidia/mcp55<br />
| style="background:yellow" | Y<br />
| style="background:yellow" | Y<br />
| An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.<br />
<br />
|- bgcolor="#dddddd"<br />
| sis/sis966<br />
| style="background:yellow" | Y<br />
| ?<br />
| An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.<br />
<br />
|- bgcolor="#eeeeee"<br />
| via/vt8231<br />
| style="background:yellow" | Y<br />
| style="background:red" | N<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8235<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt8237r<br />
| ?<br />
| ?<br />
| &mdash;<br />
|- bgcolor="#eeeeee"<br />
| via/vt82c686<br />
| ?<br />
| ?<br />
| &mdash;<br />
<br />
|}<br />
<br />
'''Developers:''' Stefan, Ron, Patrick, Myles, Uwe<br />
<br />
== Tiny Bootblock ==<br />
<br />
Right now, the decision whether to use fallback or normal is in cache_as_ram_auto.c in many boards. Make that generic again (also helps with further CBFSification at some point).<br />
<br />
'''Status:''' Available in Kconfig, works on a couple of boards. Requires per southbridge changes (and northbridge in some cases) on many boards (related to ROM enable, see CBFS section).<br />
<br />
'''Developers:''' Patrick<br />
<br />
== Remove .c inclues ==<br />
<br />
Currently we include lots of code in the romstage using the preprocessor. This makes it harder to support new boards (where chipset components are supported already) and maintenance in general. So we should get rid of it where possible, using the linker for CAR boards and the build system for the remaining non-CAR boards appropriately.<br />
<br />
'''Status:''' CAR boards only for now, to keep the project manageable. i945 is modified already, and boards based on it have only one or two remaining source files they include. Interacts with the next project "Move configuration to Kconfig", which ensures that code still sees all configuration when it is compiled separately<br />
<br />
'''Developers:''' Patrick, Uwe<br />
<br />
== Move configuration to Kconfig ==<br />
<br />
Many boards have lots of <code>#define VAR somevalue</code> statements in their romstage.c which define how certain component drivers are compiled. With Kconfig, there's a better place to store them. This project is about moving all configuration values out of romstage.c (and other places if appropriate) and into Kconfig.<br />
<br />
'''Status:''' Intel and VIA based boards should be mostly configuration free, AMD boards still have defines in their romstage.<br />
<br />
'''Developers:''' Patrick, Uwe<br />
<br />
= More ideas =<br />
<br />
== Unify ACPI ==<br />
<br />
Every ACPI board has its own routines to compile the ACPI sources. Unify that. Also, figure out generic ACPI code and deduplicate it.<br />
<br />
== CMOS layout ==<br />
<br />
Allow (somehow) to define defaults for all CMOS fields, and create a static table from that. Use that at runtime if the CMOS checksum fails.<br />
<br />
== Unify UMA / onboard video code and config ==<br />
<br />
Unify CONFIG_VIDEO_MB, CONFIG_GFXUMA, and similar options and make all code honor them.<br />
<br />
== Add / Unify / Test kconfig compile-time options and runtime CMOS options in coreboot ==<br />
<br />
Some coreboot options are compile-time configurable only at the moment (via kconfig), but should also be runtime-configurable via CMOS/NVRAM options. We should fix this.<br />
<br />
* Make all options (where it makes sense) run-time configurable via CMOS options, in addition to having sane compile-time defaults configured via kconfig.<br />
* This includes many options which are northbridge-specific, many southbridge-specific, and some board-specific ones.<br />
* Example options: Enable/disable IDE channel(s) / SATA / USB / SCSI / etc., enable/disable UDMA on older boards, amount of memory used for IGP/UMA, choice between IDE or NAND flash (on CS5536 boards), IDE 40/80 pin cable selection (VT8237R boards for example), and many more.<br />
* Some of these options are already handled in the code via CMOS options, some are compile-time only so far, so do not yet exist at all.<br />
<br />
== Kconfig TODO ==<br />
<br />
Notes / Style guide:<br />
<br />
* Any bool variables that are (re-)defined to 'y' in Kconfig files can be simplified by using '''select FOO''' instead of the usual paragraph, as long as they're defined globally as '''default n''' boolean elsewhere.<br />
* Use '''bool''' instead of '''boolean'''.<br />
* Use '''default n''' instead of '''default false'''.<br />
<br />
Various post-conversion things to consider:<br />
<br />
* Consider ways to move crt0-y and ldscript-y out of $(src)/arch/i386/Makefile.inc where appropriate (ie. component specific)<br />
* Make various CONFIG_* variable which were in each board's Kconfig file global or per-chipset options (instead of per-board). Examples:<br />
** UDELAY_TSC, TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 (also check UDELAY_IO, APIC, etc.)<br />
** ...<br />
<br />
Stuff to port from v3 to v4:<br />
<br />
* All boards that are in v3 but not in v4 (especially Geode LX stuff. Also check amd/model_gx*).<br />
* Some remaining useful Kconfig options.<br />
<br />
== USB Debug Console ==<br />
<br />
Fix USB debug console and make the Kconfig choice actually work. Right now it's possible to transmit single characters but it's not really hooked up.<br />
<br />
== Clean up Assembler / Linker mess ==<br />
<br />
* Drop / combine / normalize .ld/.lb/.lds linker scripts.<br />
* Move them to a common place.<br />
* Drop / combine / normalize .inc / .S files.<br />
<br />
== Post codes ==<br />
<br />
* post_code consolidation: find all outb(x, 0x80).<br />
* post_code consolidation: common numbers / defines across the boards.<br />
<br />
== Geode issues ==<br />
<br />
* Fix / Unify vsmsetup.c.<br />
* Fix CS5535/CS5536/GX2/LX "chipsetinit" issue.<br />
<br />
== Use central oprom init ==<br />
<br />
* Get rid of all vgabios.c, make all chipsets with own vgabios.c use devices/oprom/x86.c.<br />
* Use the realmode code for vsmsetup too.<br />
<br />
== Stack and Suspend/Resume ==<br />
<br />
* Use CONFIG_RAMBASE + HIGH_MEMORY_SAFE instead of 0x40000 for stack.<br />
<br />
== Fix Suspend/Resume on AMD64 ==<br />
<br />
* Use cbmem in romstage on the AMD64 board(s) that have suspend/resume.<br />
<br />
== Fix ALL build warnings ==<br />
<br />
* Someone has to do the deed..<br />
<br />
== printk into buffer ==<br />
<br />
Port the v3 feature that printk can write into a buffer (that might be usable from the client OS, or dumped to output, as soon as output exists).<br />
<br />
Consider use cases first (no need to provide buffer support, if all it would be useful for is buffering pre-CAR messages - which can't be buffered).<br />
<br />
== Global variables ==<br />
<br />
* Port the global variables framework from v3.<br />
* Make use of it where appropriate.<br />
<br />
== Clear phases in romstage ==<br />
<br />
* Split up the code (esp. in romstage) into more sensibly separated phases.<br />
* Maybe use v3 for inspiration where the lines can be drawn.<br />
<br />
= Finished =<br />
<br />
== Port v3 Resource Allocator ==<br />
<br />
The v3 resource allocator should be ported to v4.<br />
<br />
'''Status:''' Upstream. It's limited to one area for resources, that doesn't overlap with fixed resources.<br />
<br />
'''Developers:''' Myles<br />
<br />
== Config & Build System ==<br />
<br />
The current system of generated Makefiles is non-ideal (for too many reasons for this little margin). Fix it, somehow. Use kconfig to improve the configuration management.<br />
<br />
'''Status:''' Upstream, boards are converted. Old system is gone. All boards build. HOWEVER, not all boards have been boot-tested yet, please report any issues you encounter!<br />
<br />
'''Developers:''' Stefan, Ron, Patrick, Uwe, Cristi<br />
<br />
== Unify text printing functions ==<br />
<br />
There are several copies of print_* and printk_* in the code. Unify them so everything is happier than before (because the disjoint features are merged).<br />
<br />
'''Developers:''' Patrick, Stefan<br />
<br />
== Common payload location ==<br />
<br />
Many boards have different names for the payload in targets/.../Config.lb (payload.elf, filo.elf, etherboot.elf, etc) and locations (../payload.elf, or various absolute paths which only work for one developer). The problem will be fixed with kconfig, where the user specifies a payload manually in "make menuconfig".</div>
Uwe
https://www.coreboot.org/index.php?title=Datasheets&diff=10171
Datasheets
2010-11-21T17:37:51Z
<p>Uwe: /* AMD */ AMD 8111</p>
<hr />
<div></div>
Uwe
https://www.coreboot.org/index.php?title=Supported_Chipsets_and_Devices&diff=10170
Supported Chipsets and Devices
2010-11-19T18:20:41Z
<p>Uwe: /* Devices supported in coreboot v4 */ W83627THF/THG</p>
<hr />
<div>'''coreboot v4''' is the current stable coreboot tree recommended for productive use and for porting new boards.<br />
* If a device is not supported by coreboot v4, try [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v1|checking coreboot v1]] or [[Supported_Chipsets_and_Devices#Devices_supported_in_coreboot_v3|coreboot v3]] for support.<br />
* In general it is '''not''' recommended to use coreboot v3 &mdash; this was an experimental development tree which is gradually being merged into v4.<br />
* Also, coreboot v1 should be avoided (if v4 can be used instead for your board), as it has been unmaintained for a long time. However, it is definately desirable to port boards from v1 to v4 whereever possible.<br />
<br />
See also [[Supported Motherboards]].<br />
<br />
== Devices supported in coreboot v4 ==<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Fam10h<br />
| style="background:lime" | OK<sup>16</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX1<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| GX&nbsp;(GX2)<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| LX<br />
| style="background: lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7520<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7525<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82810<br />
| style="background:yellow" | WIP<sup>9</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82855<br />
| style="background:yellow" | ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SiS<br />
| SiS761GX<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601 (PLE133)<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623 (CLE266)<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8T890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| K8M890<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN400<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:lime" | OK<sup>14</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| CX700<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VX800<br />
| style="background:yellow" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8111<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8131<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8132<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD8151<br />
| style="background: lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5530/CS5530A<br />
| style="background:yellow" | WIP<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5535<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS780/RS785?<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB700/SB7x0<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM21000<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5780<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Broadcom<br />
| BCM5785<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 6300ESB (ESB6300)<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:yellow" | WIP<sup>6</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801AA/AB&nbsp;(ICH/ICH0)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801BA/BAM&nbsp;(ICH2/ICH2-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA/CAM&nbsp;(ICH3-S/ICH3-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB/DBL/DBM<br/>(ICH4/ICH4-L/ICH4-M)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801EB/ER&nbsp;(ICH5/ICH5R)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PXHD<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| CK804<br />
| style="background:lime" | OK<sup>17</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:lime" | OK<sup>17</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Ricoh<br />
| RL5C476<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| SiS966(L)<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237A<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8237S<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ASUS<br />
| A8000<br />
| style="background:lime" | OK<sup>12</sup>, <sup>13</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71805F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71859<br />
| style="background:yellow" | OK<sup>19</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71863F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71872F/FG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Fintek<br />
| F71889<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8661F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8673F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8705F<br />
| style="background:yellow" | OK <sup>1</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK <sup>8</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ITE<br />
| IT8718F<br />
| style="background:yellow" | OK <sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 3100<br />
| style="background:lime" | OK <sup>15</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background:lime" | OK <sup>15</sup><br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC8374<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:yellow" | OK <sup>5</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87360<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87366<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87417<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87427<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307 <br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ServerEngines<br />
| PILOT<br />
| style="background:yellow" | OK<sup>18</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M70x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B80x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B78x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B72x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37B81x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| FDC37M60x<br />
| style="background:lime" | OK<sup>3</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B27x<br />
| style="background:lime" | OK<sup>7</sup>,<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M10x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M112<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M13x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M15x<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47M192<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47B397<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| DME1737<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| SCH5307<br />
| style="background:lime" | OK<sup>12</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| SMSC&reg;<br />
| LPC47N217<br />
| style="background:#dddddd" | ?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#eeeeee" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686(A/B)<br />
| style="background:yellow" | OK<sup>5</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627DHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627UHG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627EHG/HF/EHF/THF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83697HF/HG<br />
| ?<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THF/THG<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977TF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:lime" | OK<sup>4</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Emulated<br />
| QEMU<br />
| style="background:lime" | OK<br />
|}<br />
<br />
'''SOCs'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | SOC<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Elan SC520<br />
| style="background: lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| EP80579 (Tolapai)<br />
| style="background: lime" | OK<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> Serial output should work for all ITE Super I/Os (but is only tested on the IT8671F and IT8712F). The rest ''could'' work, but is completely untested.<br /><br />
<sup>3</sup> Serial output on serial port 1 is tested and works, the rest probably not yet (tested on FDC37M602).<br /><br />
<sup>4</sup> The W83977EF works fine with the W83977TF code (the pre-RAM serial part at least).<br /><br />
<sup>5</sup> Pre-RAM serial output works fine, but nothing else, yet.<br /><br />
<sup>6</sup> IDE support is available and tested. SMBus support may work, but is untested. USB support is on our TODO list.<br /><br />
<sup>7</sup> Pre-RAM serial output [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021247.html works fine], everything else is untested.<br /><br />
<sup>8</sup> [http://www.linuxbios.org/pipermail/linuxbios/2007-May/021623.html Works fine] mostly, but support for more obscure features (floppy, game port, MIDI, IR) might need more work.<br /><br />
<sup>9</sup> Works mostly, but currently there are some limitations as to which RAM DIMMs can be used.<br /><br />
<sup>12</sup> All these Super I/O chips should be supported by the "smscsuperio" driver. Only the ASUS A8000 is tested, though. The floppy disk controller, the parallel port, the serial ports (COM1 + COM2), and the keyboard should work for all chips. More advanced stuff may need more work, though.<br /><br />
<sup>13</sup> The ASUS A8000 Super I/O seems to be a rebranded SMSC DME1737.<br /><br />
<sup>14</sup> Working, but not widely tested, yet. Works with single DIMM DDR2.<br /><br />
<sup>15</sup> The Intel 3100/EP80579 UARTs and watchdog timer are integrated as a Super I/O-like device; only the UARTs have been tested so far.<br /><br />
<sup>16</sup> Barcelona B0-B3 supported.<br /><br />
<sup>17</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br /><br />
<sup>18</sup> Partially supported, but not all features implemented.<br /><br />
<sup>19</sup> Only support for serial port 1 implemented, everything else is unsupported so far due to lack of datasheet.<br /><br />
</small><br />
<br />
== Devices supported in coreboot v3 ==<br />
<br />
<div style="color: #ff0000">coreboot v3 was an experimental development tree of coreboot which should not be used anymore (there are only very few exceptions)! Most features from v3 are gradually being merged into v4.</div><br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode&nbsp;K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82443BX&nbsp;(440BX)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 945<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| CN700<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8111<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8132<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD-8151<br />
| style="background:yellow" | ?<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| CS5536<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| RS690<br />
| style="background: lime " | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| SB600<br />
| style="background: lime " | OK<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82371EB&nbsp;(PIIX4E)<br />
| style="background:orange" | WIP<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82801GX&nbsp;(ICH7)<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NVIDIA<br />
| MCP55<br />
| style="background:orange" | WIP<sup>1</sup><br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8237R<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Fintek<br />
| F71805F<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8712F<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8716F<br />
| style="background:lime" | OK<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:lime" | OK<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83627THG<br />
| style="background:lime" | OK<br />
<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| Geode LX<br />
| style="background:lime" | OK<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| K8<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| Generic<br />
| i586<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel<br />
| Core Duo / Core 2 Duo<br />
| style="background:orange" | WIP<br />
<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| C7<br />
| style="background:orange" | WIP<br />
<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> MCP55 and CK804 are supported, but no open documents are available from NVIDIA.<br />
</small><br />
<br />
== Devices supported in coreboot v1 ==<br />
<br />
Not all devices have been ported from coreboot v1 to coreboot v4, yet (check "v4?" field). If you want to work on such a port contact us on the [[Mailinglist|mailing list]].<br />
<br />
{| border="0" valign="top"<br />
| valign="top"|<br />
<br />
'''Northbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Northbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1631<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Alpha<br />
| Tsunami<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| AMD<br />
| AMD76x<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 430TX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440BX<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>3</sup><br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 440GX<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82815EP<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82830<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| 82860<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7500<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7501<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| Intel&reg;<br />
| E7505<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Micron<br />
| 21PAD<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Motorola<br />
| MPC107<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC/AMD<br />
| GX1<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT694<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8601<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8623<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Southbridge<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1543<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD766<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| AMD<br />
| AMD768<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801CA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82801DB<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| 82870<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Intel&reg;<br />
| PIIX4E<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC/AMD<br />
| CS5530<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT8235<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| Winbond&trade;<br />
| W83C553<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''Super I/Os'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | Super&nbsp;I/O<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Acer<br />
| M1535<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| ITE<br />
| IT8671F<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87309<br />
| style="background:lime" | OK<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC87351<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97307<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| PC97317<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 950<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B72X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B78X<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37B807<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C669<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37C67X<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| SMC<br />
| FDC37N769<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT1211<br />
| style="background:#dddddd" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT8231<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| VIA<br />
| VT82C686<br />
| style="background:#dddddd" | ?<br />
| style="background:yellow" | Yes<sup>2</sup><br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83627HF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83877TF<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Winbond&trade;<br />
| W83977EF<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<sup>1</sup><br />
|}<br />
<br />
| valign="top"|<br />
<br />
'''North-/Southbridges'''<br />
<br />
{| border="0" style="font-size: smaller" valign="top"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Vendor<br />
! align="left" | North/South<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| NSC<br />
| SCX200<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 540<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 550<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 630<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 635<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 730<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| SiS<br />
| 735<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| ST<br />
| STPC<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|}<br />
<br />
'''CPUs'''<br />
<br />
{| border="0" style="font-size: smaller"<br />
|- bgcolor="#6699dd"<br />
! align="left" | Type<br />
! align="left" | CPU<br />
! align="left" | Status<br />
! align="left" | v4?<br />
<br />
|- bgcolor="#eeeeee" valign="top"<br />
| Alpha<br />
| EV6<br />
| style="background:#eeeeee" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#dddddd" valign="top"<br />
| PowerPC<br />
| ?<br />
| style="background:#dddddd" | ?<br />
| style="background:red" | No<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| AMD<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| Intel&reg;<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|- bgcolor="#eeeeee" valign="top"<br />
| x86<br />
| VIA<br />
| style="background:#eeeeee" | ?<br />
| style="background:lime" | Yes<br />
|}<br />
<br />
|}<br />
<br />
<small><br />
<sup>1</sup> The W83977EF works fine with the W83977TF code in coreboot v4 (the pre-RAM serial part at least).<br /><br />
<sup>2</sup> Pre-RAM serial output works in coreboot v4, but the rest is not supported, yet.<br /><br />
<sup>3</sup> Work in progress.<br /><br />
</small><br />
<br />
__FORCETOC__</div>
Uwe
https://www.coreboot.org/index.php?title=Datasheets&diff=10168
Datasheets
2010-11-18T21:10:09Z
<p>Uwe: /* AMD */ AMD SB820M public datasheet!</p>
<hr />
<div></div>
Uwe