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| This is an automatically generated list of '''coreboot compile-time options'''.
| | {{#externalredirect: https://coreboot.org/status/kconfig-options.html }} |
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| Last update: 4.7-664-ga6464b7ffd
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| {| border="0" style="font-size: smaller" | |
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| ! align="left" | Option
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| ! align="left" | Source
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| ! align="left" | Format
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| ! align="left" | Short Description
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| ! align="left" | Description
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: General setup || || || ||
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| | LOCALVERSION || toplevel || string || Local version string ||
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| Append an extra string to the end of the coreboot version.
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| This can be useful if, for instance, you want to append the
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| respective board's hostname or some other identifying string to
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| the coreboot version number, so that you can easily distinguish
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| boot logs of different boards from each other.
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| | CBFS_PREFIX || toplevel || string || CBFS prefix to use ||
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| Select the prefix to all files put into the image. It's "fallback"
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| by default, "normal" is a common alternative.
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| | CBFS_PREFIX || toplevel || string || Compiler to use ||
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| This option allows you to select the compiler used for building
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| coreboot.
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| You must build the coreboot crosscompiler for the board that you
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| have selected.
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| To build all the GCC crosscompilers (takes a LONG time), run:
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| make crossgcc
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| For help on individual architectures, run the command:
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| make help_toolchain
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| | COMPILER_GCC || toplevel || bool || GCC ||
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| Use the GNU Compiler Collection (GCC) to build coreboot.
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| For details see http://gcc.gnu.org.
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| | COMPILER_LLVM_CLANG || toplevel || bool || LLVM/clang (TESTING ONLY - Not currently working) ||
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| Use LLVM/clang to build coreboot. To use this, you must build the
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| coreboot version of the clang compiler. Run the command
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| make clang
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| Note that this option is not currently working correctly and should
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| really only be selected if you're trying to work on getting clang
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| operational.
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| For details see http://clang.llvm.org.
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| | ANY_TOOLCHAIN || toplevel || bool || Allow building with any toolchain ||
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| Many toolchains break when building coreboot since it uses quite
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| unusual linker features. Unless developers explicitely request it,
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| we'll have to assume that they use their distro compiler by mistake.
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| Make sure that using patched compilers is a conscious decision.
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| | CCACHE || toplevel || bool || Use ccache to speed up (re)compilation ||
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| Enables the use of ccache for faster builds.
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| Requires the ccache utility in your system $PATH.
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| For details see https://ccache.samba.org.
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| | FMD_GENPARSER || toplevel || bool || Generate flashmap descriptor parser using flex and bison ||
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| Enable this option if you are working on the flashmap descriptor
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| parser and made changes to fmd_scanner.l or fmd_parser.y.
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| Otherwise, say N to use the provided pregenerated scanner/parser.
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| | UTIL_GENPARSER || toplevel || bool || Generate SCONFIG & BINCFG parser using flex and bison ||
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| Enable this option if you are working on the sconfig device tree
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| parser or bincfg and made changes to the .l or .y files.
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| Otherwise, say N to use the provided pregenerated scanner/parser.
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| | USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||
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| Enable this option if coreboot shall read options from the "CMOS"
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| NVRAM instead of using hard-coded values.
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| | STATIC_OPTION_TABLE || toplevel || bool || Load default configuration values into CMOS on each boot ||
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| Enable this option to reset "CMOS" NVRAM values to default on
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| every boot. Use this if you want the NVRAM configuration to
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| never be modified from its default values.
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| | COMPRESS_RAMSTAGE || toplevel || bool || Compress ramstage with LZMA ||
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| Compress ramstage to save memory in the flash image. Note
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| that decompression might slow down booting if the boot flash
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| is connected through a slow link (i.e. SPI).
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| | COMPRESS_PRERAM_STAGES || toplevel || bool || Compress romstage and verstage with LZ4 ||
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| Compress romstage and (if it exists) verstage with LZ4 to save flash
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| space and speed up boot, since the time for reading the image from SPI
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| (and in the vboot case verifying it) is usually much greater than the
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| time spent decompressing. Doesn't work for XIP stages (assume all
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| ARCH_X86 for now) for obvious reasons.
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| | INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot .config file into the ROM image ||
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| Include the .config file that was used to compile coreboot
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| in the (CBFS) ROM image. This is useful if you want to know which
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| options were used to build a specific coreboot.rom image.
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| Saying Y here will increase the image size by 2-3KB.
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| You can use the following command to easily list the options:
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| grep -a CONFIG_ coreboot.rom
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| Alternatively, you can also use cbfstool to print the image
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| contents (including the raw 'config' item we're looking for).
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| Example:
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| $ cbfstool coreboot.rom print
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| coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
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| offset 0x0
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| Alignment: 64 bytes
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| Name Offset Type Size
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| cmos_layout.bin 0x0 cmos layout 1159
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| fallback/romstage 0x4c0 stage 339756
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| fallback/ramstage 0x53440 stage 186664
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| fallback/payload 0x80dc0 payload 51526
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| config 0x8d740 raw 3324
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| (empty) 0x8e480 null 3610440
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| | COLLECT_TIMESTAMPS || toplevel || bool || Create a table of timestamps collected during boot ||
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| Make coreboot create a table of timer-ID/timer-value pairs to
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| allow measuring time spent at different phases of the boot process.
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| | TIMESTAMPS_ON_CONSOLE || toplevel || bool || Print the timestamp values on the console ||
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| Print the timestamps to the debug console if enabled at level spew.
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| | USE_BLOBS || toplevel || bool || Allow use of binary-only repository ||
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| This draws in the blobs repository, which contains binary files that
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| might be required for some chipsets or boards.
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| This flag ensures that a "Free" option remains available for users.
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| | COVERAGE || toplevel || bool || Code coverage support ||
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| Add code coverage support for coreboot. This will store code
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| coverage information in CBMEM for extraction from user space.
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| If unsure, say N.
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| | UBSAN || toplevel || bool || Undefined behavior sanitizer support ||
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| Instrument the code with checks for undefined behavior. If unsure,
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| say N because it adds a small performance penalty and may abort
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| on code that happens to work in spite of the UB.
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| | RELOCATABLE_RAMSTAGE || toplevel || bool || Build the ramstage to be relocatable in 32-bit address space. ||
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| The reloctable ramstage support allows for the ramstage to be built
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| as a relocatable module. The stage loader can identify a place
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| out of the OS way so that copying memory is unnecessary during an S3
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| wake. When selecting this option the romstage is responsible for
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| determing a stack location to use for loading the ramstage.
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| | CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM || toplevel || bool || ||
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| The relocated ramstage is saved in an area specified by the
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| by the board and/or chipset.
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| | UPDATE_IMAGE || toplevel || bool || Update existing coreboot.rom image ||
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| If this option is enabled, no new coreboot.rom file
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| is created. Instead it is expected that there already
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| is a suitable file for further processing.
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| The bootblock will not be modified.
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| If unsure, select 'N'
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| | BOOTSPLASH_IMAGE || toplevel || bool || Add a bootsplash image ||
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| Select this option if you have a bootsplash image that you would
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| like to add to your ROM.
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| This will only add the image to the ROM. To actually run it check
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| options under 'Display' section.
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| | BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||
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| The path and filename of the file to use as graphical bootsplash
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| screen. The file format has to be jpg.
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: Mainboard || || || ||
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| |- bgcolor="#eeeeee"
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| | || || (comment) || || Important: Run 'make distclean' before switching boards ||
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| | VENDOR_WINNET || mainboard/winnet.name || bool || WinNET ||
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| WinNET boards. Used in various thin client appliances.
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| | UART_FOR_CONSOLE || mainboard/intel/mohonpeak || int || ||
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| The Mohon Peak board uses COM2 (2f8) for the serial console.
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| | PAYLOAD_CONFIGFILE || mainboard/intel/mohonpeak || string || ||
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| The Avoton/Rangeley chip does not allow devices to write into the 0xe000
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| segment. This means that USB/SATA devices will not work in SeaBIOS unless
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| we put the SeaBIOS buffer area down in the 0x9000 segment.
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| | ENABLE_FSP_MEMORY_DOWN || mainboard/intel/harcuvar || bool || Enable Memory Down ||
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| Select this option to enable Memory Down function.
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| | SPD_LOC || mainboard/intel/harcuvar || hex || SPD binary location in cbfs ||
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| Location of SPD binary for memory down function.
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| | VBOOT || mainboard/intel/kblrvp || None || TPM to USE ||
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| This option allows you to select the TPM to use.
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| Select whether the board does not have TPM, TPM 1.1 or TPM 2.0
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| | UART_FOR_CONSOLE || mainboard/intel/littleplains || int || ||
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| The Little Plains board uses COM2 (2f8) for the serial console.
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| | PAYLOAD_CONFIGFILE || mainboard/intel/littleplains || string || ||
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| The Avoton/Rangeley chip does not allow devices to write into the 0xe000
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| segment. This means that USB/SATA devices will not work in SeaBIOS unless
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| we put the SeaBIOS buffer area down in the 0x9000 segment.
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| | GALILEO_GEN2 || mainboard/intel/galileo || bool || Board generation: GEN1 (n) or GEN2 (y) ||
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| The coreboot binary will configure only one generation of the Galileo
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| board since coreboot can not determine the board generation at
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| runtime. Select which generation of the Galileo that coreboot
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| should initialize.
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| | FSP_VERSION_1_1 || mainboard/intel/galileo || bool || FSP 1.1 ||
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| Use FSP 1_1 binary
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| | FSP_VERSION_2_0 || mainboard/intel/galileo || bool || FSP 2.0 ||
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| Use FSP 2.0 binary
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| | FSP_BUILD_TYPE_DEBUG || mainboard/intel/galileo || bool || Debug ||
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| Use the debug version of FSP
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| | FSP_BUILD_TYPE_RELEASE || mainboard/intel/galileo || bool || Release ||
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| Use the release version of FSP
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| | FSP_TYPE_1_1 || mainboard/intel/galileo || bool || MemInit subroutine ||
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| FSP 1.1 implemented as subroutines, no EDK-II cores
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| | FSP_TYPE_1_1_PEI || mainboard/intel/galileo || bool || SEC + PEI Core + MemInit PEIM ||
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| FSP 1.1 implemented using SEC and PEI core
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| | FSP_TYPE_2_0 || mainboard/intel/galileo || bool || MemInit subroutine ||
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| FSP 2.0 implemented as subroutines, no EDK-II cores
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| | FSP_TYPE_2_0_PEI || mainboard/intel/galileo || bool || SEC + PEI Core + MemInit PEIM ||
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| FSP 2.0 implemented using SEC and PEI core
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| | FSP_DEBUG_ALL || mainboard/intel/galileo || bool || Enable all FSP debug support ||
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| Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA
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| also turn on FSP 2.0 debug support for ESRAM_LAYOUT,
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| FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS
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| or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS
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| | VBOOT_WITH_CRYPTO_SHIELD || mainboard/intel/galileo || bool || Verified boot using the Crypto Shield board ||
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| Perform a verified boot using the TPM on the Crypto Shield board.
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| | DRIVER_TPM_I2C_ADDR || mainboard/intel/galileo || hex || Address of the I2C TPM chip ||
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| I2C address of the TPM chip on the Crypto Shield board.
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| | FMDFILE || mainboard/intel/galileo || string || FMAP description file in fmd format ||
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| The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
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| but in some cases more complex setups are required.
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| When an FMD descriptionn file is specified, the build system uses it
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| instead of creating a default FMAP file.
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| | BASEBOARD_GLKRVP_LAPTOP || mainboard/intel/glkrvp || None || ON BOARD EC ||
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| This option allows you to select the on board EC to use.
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| Select whether the board has Intel EC or Chrome EC
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: Debugging || || || ||
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| |- bgcolor="#eeeeee"
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| | DISABLE_UART_ON_TESTPADS || mainboard/intel/dcp847ske || bool || Disable UART on testpads ||
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| Serial output requires soldering to the testpad next to
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| NCT5577D pin 18 (txd) and gnd.
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| | VGA_BIOS_FILE || mainboard/intel/strago || string || ||
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| The C0 version of the video bios gets computed from this name
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| so that they can both be added. Only the correct one for the
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| system will be run.
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| |- bgcolor="#eeeeee"
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| | VGA_BIOS_ID || mainboard/intel/strago || string || ||
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| The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
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| in soc/intel/braswell/Makefile.inc as 8086,22b1
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| |- bgcolor="#eeeeee"
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| | BOARD_EMULATION_SPIKE_UCB_RISCV || mainboard/emulation/spike-riscv.name || bool || SPIKE ucb riscv ||
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| To run coreboot in spike:
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| * run "make" as usual
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| * util/riscvtools/make-spike-elf.sh build/coreboot.{rom,elf}
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| * spike -m1024 build/coreboot.elf
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| |- bgcolor="#eeeeee"
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| | HUDSON_LEGACY_FREE || mainboard/bap/ode_e21XX || bool || Select DDR3 clock ||
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| Select your preferenced DDR3 clock setting.
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| Note: This option changes the total power consumption.
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| If unsure, use DDR3-1333.
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| |- bgcolor="#eeeeee"
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| | HUDSON_LEGACY_FREE || mainboard/bap/ode_e20XX || bool || Select DDR3 clock ||
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| Select your preferred DDR3 clock setting.
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| Note: This option changes the total power consumption.
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| If unsure, use DDR3-1066.
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| |- bgcolor="#eeeeee"
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| | ENABLE_DP3_DAUGHTER_CARD_IN_J120 || mainboard/amd/lamar || bool || Use J120 as an additional graphics port ||
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| The PCI Express slot at J120 can be configured as an additional
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| DisplayPort connector using an adapter card from AMD or as a normal
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| PCI Express (x4) slot.
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| By default, the connector is configured as a PCI Express (x4) slot.
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| Select this option to enable the slot for use with one of AMD's
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| passive graphics port expander cards (only available from AMD).
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| | MAINBOARD_PART_NUMBER || mainboard/google/nyan_blaze || string || BCT boot media ||
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| Which boot media to configure the BCT for.
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| | NYAN_BLAZE_BCT_CFG_SPI || mainboard/google/nyan_blaze || bool || SPI ||
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| Configure the BCT for booting from SPI.
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| | NYAN_BLAZE_BCT_CFG_EMMC || mainboard/google/nyan_blaze || bool || eMMC ||
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| Configure the BCT for booting from eMMC.
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| |- bgcolor="#eeeeee"
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| | BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan_blaze || int || SPI bus with boot media ROM ||
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| Which SPI bus the boot media is connected to.
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| |- bgcolor="#eeeeee"
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| | DISPLAY_SPD_DATA || mainboard/google/cyan || bool || Display Memory Serial Presence Detect Data ||
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| When enabled displays the memory configuration data.
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| | VGA_BIOS_FILE || mainboard/google/cyan || string || ||
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| The C0 version of the video bios gets computed from this name
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| so that they can both be added. Only the correct one for the
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| system will be run.
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| |- bgcolor="#eeeeee"
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| | VGA_BIOS_ID || mainboard/google/cyan || string || ||
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| The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
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| in soc/intel/braswell/Makefile.inc as 8086,22b1
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| |- bgcolor="#eeeeee"
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| | FMDFILE || mainboard/google/kahlee || string || ||
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| The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
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| but in some cases more complex setups are required.
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| When an fmd is specified, it overrides the default format.
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| |- bgcolor="#eeeeee"
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| | DRAM_SIZE_MB || mainboard/google/smaug || int || BCT boot media ||
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| Which boot media to configure the BCT for.
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| |- bgcolor="#eeeeee"
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| | SMAUG_BCT_CFG_SPI || mainboard/google/smaug || bool || SPI ||
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| Configure the BCT for booting from SPI.
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| |- bgcolor="#eeeeee"
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| | SMAUG_BCT_CFG_EMMC || mainboard/google/smaug || bool || eMMC ||
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| Configure the BCT for booting from eMMC.
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| |- bgcolor="#eeeeee"
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| | BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/smaug || int || SPI bus with boot media ROM ||
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| Which SPI bus the boot media is connected to.
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| |- bgcolor="#eeeeee"
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| | MAINBOARD_PART_NUMBER || mainboard/google/nyan_big || string || BCT boot media ||
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| Which boot media to configure the BCT for.
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| |- bgcolor="#eeeeee"
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| | NYAN_BIG_BCT_CFG_SPI || mainboard/google/nyan_big || bool || SPI ||
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| Configure the BCT for booting from SPI.
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| ||
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| |- bgcolor="#eeeeee"
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| | NYAN_BIG_BCT_CFG_EMMC || mainboard/google/nyan_big || bool || eMMC ||
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| Configure the BCT for booting from eMMC.
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| ||
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| |- bgcolor="#eeeeee"
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| | BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan_big || int || SPI bus with boot media ROM ||
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| Which SPI bus the boot media is connected to.
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| |- bgcolor="#eeeeee"
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| | DRAM_SIZE_MB || mainboard/google/foster || int || BCT boot media ||
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| Which boot media to configure the BCT for.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FOSTER_BCT_CFG_SPI || mainboard/google/foster || bool || SPI ||
| |
| Configure the BCT for booting from SPI.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FOSTER_BCT_CFG_EMMC || mainboard/google/foster || bool || eMMC ||
| |
| Configure the BCT for booting from eMMC.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/foster || int || SPI bus with boot media ROM ||
| |
| Which SPI bus the boot media is connected to.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_PART_NUMBER || mainboard/google/nyan || string || BCT boot media ||
| |
| Which boot media to configure the BCT for.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NYAN_BCT_CFG_SPI || mainboard/google/nyan || bool || SPI ||
| |
| Configure the BCT for booting from SPI.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NYAN_BCT_CFG_EMMC || mainboard/google/nyan || bool || eMMC ||
| |
| Configure the BCT for booting from eMMC.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan || int || SPI bus with boot media ROM ||
| |
| Which SPI bus the boot media is connected to.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | UART_FOR_CONSOLE || mainboard/adi/rcc-dff || int || ||
| |
| The Mohon Peak board uses COM2 (2f8) for the serial console.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_CONFIGFILE || mainboard/adi/rcc-dff || string || ||
| |
| The Avoton/Rangeley chip does not allow devices to write into the 0xe000
| |
| segment. This means that USB/SATA devices will not work in SeaBIOS unless
| |
| we put the SeaBIOS buffer area down in the 0x9000 segment.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOARD_ASUS_F2A85_M_DDR3_VOLT_135 || mainboard/asus/f2a85-m || bool || 1.35V ||
| |
| Set DRR3 memory voltage to 1.35V
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOARD_ASUS_F2A85_M_DDR3_VOLT_150 || mainboard/asus/f2a85-m || bool || 1.50V ||
| |
| Set DRR3 memory voltage to 1.50V
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOARD_ASUS_F2A85_M_DDR3_VOLT_165 || mainboard/asus/f2a85-m || bool || 1.65V ||
| |
| Set DRR3 memory voltage to 1.65V
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOARD_WINNET_G170 || mainboard/winnet/g170.name || bool || WinNET G170 (Neoware CA19, IGEL 2110) ||
| |
| G170 is a board manufactured by WinNET, used in thin clients including
| |
| HP Neoware CA19 and IGEL 2110.
| |
| | |
| ||
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BMC_INFO_LOC || mainboard/scaleway/tagada || hex || BMC information location in flash ||
| |
| Location of BMC SERIAL information.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_POST || mainboard/purism/librem_skl || int || ||
| |
| This platform does not have any way to see POST codes
| |
| so disable them by default.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_PS2_KEYBOARD || mainboard/purism/librem13v1 || None || ||
| |
| Default PS/2 Keyboard to enabled on this board.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_UART_8250IO || mainboard/purism/librem13v1 || None || ||
| |
| This platform does not have any way to get standard
| |
| serial output so disable it by default.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_POST || mainboard/purism/librem13v1 || int || ||
| |
| This platform does not have any way to see POST codes
| |
| so disable them by default.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || was acquired by ADLINK ||
| |
| |- bgcolor="#eeeeee"
| |
| | ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||
| |
| If selected, both on-board serial ports will operate in RS485 mode
| |
| instead of RS232.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||
| |
| If selected, the on-board SSD will act as IDE Slave instead of Master.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||
| |
| Look on the bottom side for a number like 406-0001-30. The last 2
| |
| digits state the PCB revision (3.0 in this example). For 2.0 or older
| |
| boards choose Y, for 3.0 and newer say N.
| |
| | |
| Old revision boards need a jumper shorting the power button to
| |
| power on automatically. You may enable the button only after this
| |
| jumper has been removed. New revision boards are not restricted
| |
| in this way, and always have the power button enabled.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||
| |
| If selected, both on-board serial ports will operate in RS485 mode
| |
| instead of RS232.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||
| |
| If selected, the first two on-board serial ports will operate in RS485
| |
| mode instead of RS232.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave ||
| |
| If selected, the on-board Compact Flash card socket will act as IDE
| |
| Slave instead of Master.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||
| |
| If selected, both on-board serial ports will operate in RS485 mode
| |
| instead of RS232.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || see under vendor LiPPERT ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || WARNING: This mainboard uses LATE_CBMEM_INIT, which is deprecated ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOARD_ROMSIZE_KB_65536 || mainboard || bool || ROM chip size ||
| |
| Select the size of the ROM chip you intend to flash coreboot on.
| |
| | |
| The build system will take care of creating a coreboot.rom file
| |
| of the matching size.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_64 || mainboard || bool || 64 KB ||
| |
| Choose this option if you have a 64 KB ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||
| |
| Choose this option if you have a 128 KB ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||
| |
| Choose this option if you have a 256 KB ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||
| |
| Choose this option if you have a 512 KB ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||
| |
| Choose this option if you have a 1024 KB (1 MB) ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||
| |
| Choose this option if you have a 2048 KB (2 MB) ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||
| |
| Choose this option if you have a 4096 KB (4 MB) ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||
| |
| Choose this option if you have a 8192 KB (8 MB) ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_10240 || mainboard || bool || 10240 KB (10 MB) ||
| |
| Choose this option if you have a 10240 KB (10 MB) ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_12288 || mainboard || bool || 12288 KB (12 MB) ||
| |
| Choose this option if you have a 12288 KB (12 MB) ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||
| |
| Choose this option if you have a 16384 KB (16 MB) ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_32768 || mainboard || bool || 32768 KB (32 MB) ||
| |
| Choose this option if you have a 32768 KB (32 MB) ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_ROMSIZE_KB_65536 || mainboard || bool || 65536 KB (64 MB) ||
| |
| Choose this option if you have a 65536 KB (64 MB) ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button ||
| |
| The selected mainboard can optionally have the power button tied
| |
| to ground with a jumper so that the button appears to be
| |
| constantly depressed. If this option is enabled and the jumper is
| |
| installed then the board will turn on, but turn off again after a
| |
| short timeout, usually 4 seconds.
| |
| | |
| Select Y here if you have removed the jumper and want to use an
| |
| actual power button. Select N if you have the jumper installed.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEVICETREE || toplevel || string || ||
| |
| This symbol allows mainboards to select a different file under their
| |
| mainboard directory for the devicetree.cb file. This allows the board
| |
| variants that need different devicetrees to be in the same directory.
| |
| | |
| Examples: "devicetree.variant.cb"
| |
| "variant/devicetree.cb"
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CBFS_SIZE || toplevel || hex || Size of CBFS filesystem in ROM ||
| |
| This is the part of the ROM actually managed by CBFS, located at the
| |
| end of the ROM (passed through cbfstool -o) on x86 and at at the start
| |
| of the ROM (passed through cbfstool -s) everywhere else. It defaults
| |
| to span the whole ROM on all but Intel systems that use an Intel Firmware
| |
| Descriptor. It can be overridden to make coreboot live alongside other
| |
| components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
| |
| binaries.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FMDFILE || toplevel || string || fmap description file in fmd format ||
| |
| The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
| |
| but in some cases more complex setups are required.
| |
| When an fmd is specified, it overrides the default format.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#eeeeee"
| |
| | CBFS_AUTOGEN_ATTRIBUTES || toplevel || bool || ||
| |
| If this option is selected, every file in cbfs which has a constraint
| |
| regarding position or alignment will get an additional file attribute
| |
| which describes this constraint.
| |
| | |
| ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Chipset || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || SoC ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_DO_DSI_INIT || soc/nvidia/tegra210 || bool || Use dsi graphics interface ||
| |
| Initialize dsi display
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_DO_SOR_INIT || soc/nvidia/tegra210 || bool || Use dp graphics interface ||
| |
| Initialize dp display
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_TEGRA210_UARTA || soc/nvidia/tegra210 || bool || UARTA ||
| |
| Serial console on UART A.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_TEGRA210_UARTB || soc/nvidia/tegra210 || bool || UARTB ||
| |
| Serial console on UART B.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_TEGRA210_UARTC || soc/nvidia/tegra210 || bool || UARTC ||
| |
| Serial console on UART C.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_TEGRA210_UARTD || soc/nvidia/tegra210 || bool || UARTD ||
| |
| Serial console on UART D.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_TEGRA210_UARTE || soc/nvidia/tegra210 || bool || UARTE ||
| |
| Serial console on UART E.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_TEGRA210_UART_ADDRESS || soc/nvidia/tegra210 || hex || ||
| |
| Map the UART names to the respective MMIO addres.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOTROM_SDRAM_INIT || soc/nvidia/tegra210 || bool || SoC BootROM does SDRAM init with full BCT ||
| |
| Use during Foster LPDDR4 bringup.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TRUSTZONE_CARVEOUT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of Trust Zone region ||
| |
| Size of Trust Zone area in MiB to reserve in memory map.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TTB_SIZE_MB || soc/nvidia/tegra210 || hex || Size of TTB ||
| |
| Maximum size of Translation Table Buffer in MiB.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEC_COMPONENT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of resident EL3 components ||
| |
| Maximum size of resident EL3 components in MiB including BL31 and
| |
| Secure OS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_MTC || soc/nvidia/tegra210 || bool || Add external Memory controller Training Code binary ||
| |
| Select this option to add emc training firmware
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MTC_FILE || soc/nvidia/tegra210 || string || tegra mtc firmware filename ||
| |
| The filename of the mtc firmware
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MTC_DIRECTORY || soc/nvidia/tegra210 || string || Directory where MTC firmware file is located ||
| |
| Path to directory where MTC firmware file is located.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MTC_ADDRESS || soc/nvidia/tegra210 || hex || ||
| |
| The DRAM location where MTC firmware to be loaded in. This location
| |
| needs to be consistent with the location defined in tegra_mtc.ld
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_APOLLOLAKE || soc/intel/apollolake || bool || ||
| |
| Intel Apollolake support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_GLK || soc/intel/apollolake || bool || ||
| |
| Intel GLK support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TPM_ON_FAST_SPI || soc/intel/apollolake || bool || ||
| |
| TPM part is conntected on Fast SPI interface, but the LPC MMIO
| |
| TPM transactions are decoded and serialized over the SPI interface.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCR_BASE_ADDRESS || soc/intel/apollolake || hex || ||
| |
| This option allows you to select MMIO Base Address of sideband bus.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_SIZE || soc/intel/apollolake || hex || ||
| |
| The size of the cache-as-ram region required during bootblock
| |
| and/or romstage.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_BSP_STACK_SIZE || soc/intel/apollolake || hex || ||
| |
| The amount of anticipated stack usage in CAR by bootblock and
| |
| other stages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ROMSTAGE_ADDR || soc/intel/apollolake || hex || ||
| |
| The base address (in CAR) where romstage should be linked
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VERSTAGE_ADDR || soc/intel/apollolake || hex || ||
| |
| The base address (in CAR) where verstage should be linked
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_M_ADDR || soc/intel/apollolake || hex || ||
| |
| The address FSP-M will be relocated to during build time
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NEED_LBP2 || soc/intel/apollolake || bool || Write contents for logical boot partition 2. ||
| |
| Write the contents from a file into the logical boot partition 2
| |
| region defined by LBP2_FMAP_NAME.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LBP2_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to put logical boot partition 2 ||
| |
| Name of FMAP region to write logical boot partition 2 data.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LBP2_FILE_NAME || soc/intel/apollolake || string || Path of file to write to logical boot partition 2 region ||
| |
| Name of file to store in the logical boot partition 2 region.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NEED_IFWI || soc/intel/apollolake || bool || Write content into IFWI region ||
| |
| Write the content from a file into IFWI region defined by
| |
| IFWI_FMAP_NAME.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IFWI_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to pull IFWI into ||
| |
| Name of FMAP region to write IFWI.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IFWI_FILE_NAME || soc/intel/apollolake || string || Path of file to write to IFWI region ||
| |
| Name of file to store in the IFWI region.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DMIC_1CH_16B || soc/intel/apollolake || bool || ||
| |
| Include DSP firmware settings for 1 channel 16B DMIC array.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DMIC_2CH_16B || soc/intel/apollolake || bool || ||
| |
| Include DSP firmware settings for 2 channel 16B DMIC array.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DMIC_4CH_16B || soc/intel/apollolake || bool || ||
| |
| Include DSP firmware settings for 4 channel 16B DMIC array.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_MAX98357 || soc/intel/apollolake || bool || ||
| |
| Include DSP firmware settings for headset codec.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DA7219 || soc/intel/apollolake || bool || ||
| |
| Include DSP firmware settings for headset codec.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DA7219 || soc/intel/apollolake || bool || Cache-as-ram implementation ||
| |
| This option allows you to select how cache-as-ram (CAR) is set up.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CAR_NEM || soc/intel/apollolake || bool || Non-evict mode ||
| |
| Traditionally, CAR is set up by using Non-Evict mode. This method
| |
| does not allow CAR and cache to co-exist, because cache fills are
| |
| block in NEM mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CAR_CQOS || soc/intel/apollolake || bool || Cache Quality of Service ||
| |
| Cache Quality of Service allows more fine-grained control of cache
| |
| usage. As result, it is possible to set up portion of L2 cache for
| |
| CAR and use remainder for actual caching.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_APOLLOLAKE_FSP_CAR || soc/intel/apollolake || bool || Use FSP CAR ||
| |
| Use FSP APIs to initialize & tear down the Cache-As-Ram.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | APL_SKIP_SET_POWER_LIMITS || soc/intel/apollolake || bool || ||
| |
| Some Apollo Lake mainboards do not need the Running Average Power
| |
| Limits (RAPL) algorithm for a constant power management.
| |
| Set this config option to skip the RAPL configuration.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_ESPI || soc/intel/apollolake || bool || ||
| |
| Use eSPI bus instead of LPC
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_BAYTRAIL || soc/intel/baytrail || bool || ||
| |
| Bay Trail M/D part support.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_MRC || soc/intel/baytrail || bool || Add a Memory Reference Code binary ||
| |
| Select this option to add a blob containing
| |
| memory reference code.
| |
| Note: Without this binary coreboot will not work
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MRC_FILE || soc/intel/baytrail || string || Intel memory refeference code path and filename ||
| |
| The path and filename of the file to use as System Agent
| |
| binary. Note that this points to the sandybridge binary file
| |
| which is will not work, but it serves its purpose to do builds.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_SIZE || soc/intel/baytrail || hex || ||
| |
| The size of the cache-as-ram region required during bootblock
| |
| and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
| |
| must add up to a power of 2.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_MRC_VAR_SIZE || soc/intel/baytrail || hex || ||
| |
| The amount of cache-as-ram region required by the reference code.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/baytrail || bool || Reset the system on S3 wake when ramstage cache invalid. ||
| |
| The baytrail romstage code caches the loaded ramstage program
| |
| in SMM space. On S3 wake the romstage will copy over a fresh
| |
| ramstage that was cached in the SMM space. This option determines
| |
| the action to take when the ramstage cache is invalid. If selected
| |
| the system will reset otherwise the ramstage will be reloaded from
| |
| cbfs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_BUILTIN_COM1 || soc/intel/baytrail || bool || Enable builtin COM1 Serial Port ||
| |
| The PMC has a legacy COM1 serial port. Choose this option to
| |
| configure the pads and enable it. This serial port can be used for
| |
| the debug console.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_REFCODE_BLOB || soc/intel/baytrail || bool || An external reference code blob should be put into cbfs. ||
| |
| The reference code blob will be placed into cbfs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | REFCODE_BLOB_FILE || soc/intel/baytrail || string || Path and filename to reference code blob. ||
| |
| The path and filename to the file to be added to cbfs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_BRASWELL || soc/intel/braswell || bool || ||
| |
| Braswell M/D part support.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_SIZE || soc/intel/braswell || hex || ||
| |
| The size of the cache-as-ram region required during bootblock
| |
| and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
| |
| must add up to a power of 2.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/braswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||
| |
| The haswell romstage code caches the loaded ramstage program
| |
| in SMM space. On S3 wake the romstage will copy over a fresh
| |
| ramstage that was cached in the SMM space. This option determines
| |
| the action to take when the ramstage cache is invalid. If selected
| |
| the system will reset otherwise the ramstage will be reloaded from
| |
| cbfs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_BUILTIN_COM1 || soc/intel/braswell || bool || Enable builtin COM1 Serial Port ||
| |
| The PMC has a legacy COM1 serial port. Choose this option to
| |
| configure the pads and enable it. This serial port can be used for
| |
| the debug console.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_BROADWELL || soc/intel/broadwell || bool || ||
| |
| Intel Broadwell and Haswell ULT support.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_SIZE || soc/intel/broadwell || hex || ||
| |
| The size of the cache-as-ram region required during bootblock
| |
| and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
| |
| must add up to a power of 2.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_MRC_VAR_SIZE || soc/intel/broadwell || hex || ||
| |
| The amount of cache-as-ram region required by the reference code.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_MRC || soc/intel/broadwell || bool || Add a Memory Reference Code binary ||
| |
| Select this option to add a Memory Reference Code binary to
| |
| the resulting coreboot image.
| |
| | |
| Note: Without this binary coreboot will not work
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MRC_FILE || soc/intel/broadwell || string || Intel Memory Reference Code path and filename ||
| |
| The filename of the file to use as Memory Reference Code binary.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PRE_GRAPHICS_DELAY || soc/intel/broadwell || int || Graphics initialization delay in ms ||
| |
| On some systems, coreboot boots so fast that connected monitors
| |
| (mostly TVs) won't be able to wake up fast enough to talk to the
| |
| VBIOS. On those systems we need to wait for a bit before executing
| |
| the VBIOS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/broadwell || bool || Reset the system on S3 wake when ramstage cache invalid. ||
| |
| The romstage code caches the loaded ramstage program in SMM space.
| |
| On S3 wake the romstage will copy over a fresh ramstage that was
| |
| cached in the SMM space. This option determines the action to take
| |
| when the ramstage cache is invalid. If selected the system will
| |
| reset otherwise the ramstage will be reloaded from cbfs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIRQ_CONTINUOUS_MODE || soc/intel/broadwell || bool || ||
| |
| If you set this option to y, the serial IRQ machine will be
| |
| operated in continuous mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_REFCODE_BLOB || soc/intel/broadwell || bool || An external reference code blob should be put into cbfs. ||
| |
| The reference code blob will be placed into cbfs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | REFCODE_BLOB_FILE || soc/intel/broadwell || string || Path and filename to reference code blob. ||
| |
| The path and filename to the file to be added to cbfs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_CANNONLAKE || soc/intel/cannonlake || bool || ||
| |
| Intel Cannonlake support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | UART_FOR_CONSOLE || soc/intel/cannonlake || int || Index for LPSS UART port to use for console ||
| |
| Index for LPSS UART port to use for console:
| |
| 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_SIZE || soc/intel/cannonlake || int || ||
| |
| The size of the cache-as-ram region required during bootblock
| |
| and/or romstage.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_BSP_STACK_SIZE || soc/intel/cannonlake || hex || ||
| |
| The amount of anticipated stack usage in CAR by bootblock and
| |
| other stages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DMIC_1CH_16B || soc/intel/cannonlake || bool || ||
| |
| Include DSP firmware settings for 1 channel 16B DMIC array.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DMIC_2CH_16B || soc/intel/cannonlake || bool || ||
| |
| Include DSP firmware settings for 2 channel 16B DMIC array.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DMIC_4CH_16B || soc/intel/cannonlake || bool || ||
| |
| Include DSP firmware settings for 4 channel 16B DMIC array.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_MAX98357 || soc/intel/cannonlake || bool || ||
| |
| Include DSP firmware settings for headset codec.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_MAX98373 || soc/intel/cannonlake || bool || ||
| |
| Include DSP firmware settings for headset codec.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DA7219 || soc/intel/cannonlake || bool || ||
| |
| Include DSP firmware settings for headset codec.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCR_BASE_ADDRESS || soc/intel/cannonlake || hex || ||
| |
| This option allows you to select MMIO Base Address of sideband bus.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | STACK_SIZE || soc/intel/cannonlake || hex || Cache-as-ram implementation ||
| |
| This option allows you to select how cache-as-ram (CAR) is set up.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_CANNONLAKE_CAR_NEM_ENHANCED || soc/intel/cannonlake || bool || Enhanced Non-evict mode ||
| |
| A current limitation of NEM (Non-Evict mode) is that code and data
| |
| sizes are derived from the requirement to not write out any modified
| |
| cache line. With NEM, if there is no physical memory behind the
| |
| cached area, the modified data will be lost and NEM results will be
| |
| inconsistent. ENHANCED NEM guarantees that modified data is always
| |
| kept in cache while clean data is replaced.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_CANNONLAKE_FSP_CAR || soc/intel/cannonlake || bool || Use FSP CAR ||
| |
| Use FSP APIs to initialize and tear down the Cache-As-Ram.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_DENVERTON_NS || soc/intel/denverton_ns || bool || ||
| |
| Intel Denverton-NS SoC support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_T_ADDR || soc/intel/denverton_ns || hex || Intel FSP-T (temp ram init) binary location ||
| |
| The memory location of the Intel FSP-T binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_M_ADDR || soc/intel/denverton_ns || hex || Intel FSP-M (memory init) binary location ||
| |
| The memory location of the Intel FSP-M binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_S_ADDR || soc/intel/denverton_ns || hex || Intel FSP-S (silicon init) binary location ||
| |
| The memory location of the Intel FSP-S binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IQAT_MEMORY_REGION_SIZE || soc/intel/denverton_ns || hex || ||
| |
| Do not change this value
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NON_LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Non Legacy Mode ||
| |
| Disable legacy UART mode
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Legacy Mode ||
| |
| Enable legacy UART mode
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DENVERTON_NS_CAR_NEM_ENHANCED || soc/intel/denverton_ns || bool || Enhanced Non-evict mode ||
| |
| A current limitation of NEM (Non-Evict mode) is that code and data sizes
| |
| are derived from the requirement to not write out any modified cache line.
| |
| With NEM, if there is no physical memory behind the cached area,
| |
| the modified data will be lost and NEM results will be inconsistent.
| |
| ENHANCED NEM guarantees that modified data is always
| |
| kept in cache while clean data is replaced.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_FSP_BAYTRAIL || soc/intel/fsp_baytrail || bool || ||
| |
| Bay Trail I part support using the Intel FSP.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SMM_TSEG_SIZE || soc/intel/fsp_baytrail || hex || ||
| |
| This is set by the FSP
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS_ID || soc/intel/fsp_baytrail || string || ||
| |
| This is the default PCI ID for the Bay Trail graphics
| |
| devices. This string names the vbios ROM in cbfs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_BUILTIN_COM1 || soc/intel/fsp_baytrail || bool || Enable built-in legacy Serial Port ||
| |
| The Baytrail SOC has one legacy serial port. Choose this option to
| |
| configure the pads and enable it. This serial port can be used for
| |
| the debug console.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_FILE || soc/intel/fsp_baytrail/fsp || string || ||
| |
| The path and filename of the Intel FSP binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_LOC || soc/intel/fsp_baytrail/fsp || hex || ||
| |
| The location in CBFS that the FSP is located. This must match the
| |
| value that is set in the FSP binary. If the FSP needs to be moved,
| |
| rebase the FSP with Intel's BCT (tool).
| |
| | |
| The Bay Trail FSP is built with a preferred base address of
| |
| 0xFFFC0000.
| |
| | |
| ||
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_FSP_BROADWELL_DE || soc/intel/fsp_broadwell_de || bool || ||
| |
| Broadwell-DE support using the Intel FSP.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEGRATED_UART || soc/intel/fsp_broadwell_de || bool || Integrated UART ports ||
| |
| Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIRQ_CONTINUOUS_MODE || soc/intel/fsp_broadwell_de || bool || ||
| |
| If you set this option to y, the serial IRQ machine will be
| |
| operated in continuous mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_FILE || soc/intel/fsp_broadwell_de/fsp || string || ||
| |
| The path and filename of the Intel FSP binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_LOC || soc/intel/fsp_broadwell_de/fsp || hex || ||
| |
| The location in CBFS that the FSP is located. This must match the
| |
| value that is set in the FSP binary. If the FSP needs to be moved,
| |
| rebase the FSP with Intel's BCT (tool).
| |
| | |
| The Broadwell-DE FSP is built with a preferred base address of
| |
| 0xffeb0000.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_BASE || soc/intel/fsp_broadwell_de/fsp || hex || ||
| |
| This address needs to match the setup performed inside FSP.
| |
| On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_SIZE || soc/intel/fsp_broadwell_de/fsp || hex || ||
| |
| The DCACHE is shared between FSP itself and the rest of the coreboot
| |
| stages. A size of 0x8000 works fine while providing enough space for
| |
| features like VBOOT in verstage. Further increase to a power of two
| |
| aligned value leads to errors in FSP.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_MEMORY_DOWN || soc/intel/fsp_broadwell_de/fsp || bool || Enable Memory Down ||
| |
| Load SPD data from ROM instead of trying to read from SMBus.
| |
| | |
| If the platform has DIMM sockets, say N. If memory is down, say Y and
| |
| supply the appropriate SPD data for each Channel/DIMM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 0 Present ||
| |
| Select Y if Channel 0, DIMM 0 is present.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 0 SPD File ||
| |
| Path to the file which contains the SPD data for Channel 0, DIMM 0.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 1 Present ||
| |
| Select Y if Channel 0, DIMM 1 is present.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 1 SPD File ||
| |
| Path to the file which contains the SPD data for Channel 0, DIMM 1.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 0 Present ||
| |
| Select Y if Channel 1, DIMM 0 is present.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 0 SPD File ||
| |
| Path to the file which contains the SPD data for Channel 1, DIMM 0.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 1 Present ||
| |
| Select Y if Channel 1, DIMM 1 is present.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 1 SPD File ||
| |
| Path to the file which contains the SPD data for Channel 1, DIMM 1.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_HYPERTHREADING || soc/intel/fsp_broadwell_de/fsp || bool || Enable Hyper-Threading ||
| |
| Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.
| |
| | |
| ||
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_QUARK || soc/intel/quark || bool || ||
| |
| Intel Quark support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_BUILTIN_HSUART0 || soc/intel/quark || bool || Enable built-in HSUART0 ||
| |
| The Quark SoC has two HSUART. Choose this option to configure the pads
| |
| and enable HSUART0, which can be used for the debug console.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_BUILTIN_HSUART1 || soc/intel/quark || bool || Enable built-in HSUART1 ||
| |
| The Quark SoC has two HSUART. Choose this option to configure the pads
| |
| and enable HSUART1, which can be used for the debug console.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TTYS0_BASE || soc/intel/quark || hex || HSUART Base Address ||
| |
| Memory mapped MMIO of HSUART.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_DEBUG_LED || soc/intel/quark || bool || ||
| |
| Enable the use of the SD LED for early debugging before serial output
| |
| is available. Setting this LED indicates that control has reached the
| |
| desired check point.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_DEBUG_LED_ESRAM || soc/intel/quark || bool || SD LED indicates ESRAM initialized ||
| |
| Indicate that ESRAM has been successfully initialized. If the SD LED
| |
| does not light then the ESRAM initialization needs to be debugged.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_DEBUG_LED_FINDFSP || soc/intel/quark || bool || SD LED indicates fsp.bin file was found ||
| |
| Indicate that fsp.bin was found. If the SD LED does not light then
| |
| the code between ESRAM initialization through find_fsp needs to
| |
| debugged. Start by verifying that the correct fsp.bin is in the
| |
| image.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock.c successfully entered ||
| |
| Indicate that bootblock_c_entry was entered. If the SD LED does not
| |
| light then debug the code between ESRAM and bootblock_c_entry. For
| |
| FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully entered ||
| |
| Indicate that bootblock_soc_early_init was entered. If the SD LED
| |
| does not light then debug the code in bootblock_main_with_timestamp.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully exited ||
| |
| Indicate that bootblock_soc_early_init exited. If the SD LED does not
| |
| light then debug the scripts in bootblock_soc_early_init.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_DEBUG_LED_SOC_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_init successfully entered ||
| |
| Indicate that bootblock_soc_init was entered. If the SD LED does not
| |
| light then debug the code in bootblock_mainboard_early_init and
| |
| console_init. If the SD LED does light but there is no serial then
| |
| debug the serial port configuration and initialization.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DISPLAY_ESRAM_LAYOUT || soc/intel/quark || bool || Display ESRAM layout ||
| |
| Select this option to display coreboot's use of ESRAM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CBFS_SIZE || soc/intel/quark || hex || ||
| |
| Specify the size of the coreboot file system in the read-only (recovery)
| |
| portion of the flash part. On Quark systems the firmware image stores
| |
| more than just coreboot, including:
| |
| - The chipset microcode (RMU) binary file located at 0xFFF00000
| |
| - Intel Trusted Execution Engine firmware
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ADD_FSP_RAW_BIN || soc/intel/quark || bool || Add the Intel FSP binary to the flash image without relocation ||
| |
| Select this option to add an Intel FSP binary to
| |
| the resulting coreboot image.
| |
| | |
| Note: Without this binary, coreboot builds relying on the FSP
| |
| will not boot
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_FILE || soc/intel/quark || string || Intel FSP binary path and filename ||
| |
| The path and filename of the Intel FSP binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_LOC || soc/intel/quark || hex || ||
| |
| The location in CBFS that the FSP is located. This must match the
| |
| value that is set in the FSP binary. If the FSP needs to be moved,
| |
| rebase the FSP with Intel's BCT (tool).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_ESRAM_LOC || soc/intel/quark || hex || ||
| |
| The location in ESRAM where a copy of the FSP binary is placed.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RELOCATE_FSP_INTO_DRAM || soc/intel/quark || bool || Relocate FSP into DRAM ||
| |
| Relocate the FSP binary into DRAM before the call to SiliconInit.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ADD_RMU_FILE || soc/intel/quark || bool || Should the RMU binary be added to the flash image? ||
| |
| The RMU file is required to get the chip out of reset.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RMU_FILE || soc/intel/quark || string || ||
| |
| The path and filename of the Intel Quark RMU binary.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RMU_LOC || soc/intel/quark || hex || ||
| |
| The location in CBFS that the RMU is located. It must match the
| |
| strap-determined base address.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | STORAGE_TEST || soc/intel/quark || bool || Test SD/MMC/eMMC card or device access ||
| |
| Read block 0 from each parition of the storage device. User
| |
| must also enable one or both of COMMONLIB_STORAGE_SD or
| |
| COMMONLIB_STORAGE_MMC.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | I2C_DEBUG || soc/intel/quark || bool || Enable I2C debugging ||
| |
| Display the I2C segments and controller errors
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_SKYLAKE || soc/intel/skylake || bool || ||
| |
| Intel Skylake support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_KABYLAKE || soc/intel/skylake || bool || ||
| |
| Intel Kabylake support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_SIZE || soc/intel/skylake || hex || ||
| |
| The size of the cache-as-ram region required during bootblock
| |
| and/or romstage.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_BSP_STACK_SIZE || soc/intel/skylake || hex || ||
| |
| The amount of anticipated stack usage in CAR by bootblock and
| |
| other stages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EXCLUDE_NATIVE_SD_INTERFACE || soc/intel/skylake || bool || ||
| |
| If you set this option to n, will not use native SD controller.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCR_BASE_ADDRESS || soc/intel/skylake || hex || ||
| |
| This option allows you to select MMIO Base Address of sideband bus.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIRQ_CONTINUOUS_MODE || soc/intel/skylake || bool || ||
| |
| If you set this option to y, the serial IRQ machine will be
| |
| operated in continuous mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | UART_FOR_CONSOLE || soc/intel/skylake || int || Index for LPSS UART port to use for console ||
| |
| Index for LPSS UART port to use for console:
| |
| 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SKYLAKE_SOC_PCH_H || soc/intel/skylake || bool || ||
| |
| Choose this option if you have a PCH-H chipset.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DMIC_2CH || soc/intel/skylake || bool || ||
| |
| Include DSP firmware settings for 2 channel DMIC array.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DMIC_4CH || soc/intel/skylake || bool || ||
| |
| Include DSP firmware settings for 4 channel DMIC array.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_NAU88L25 || soc/intel/skylake || bool || ||
| |
| Include DSP firmware settings for nau88l25 headset codec.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_MAX98357 || soc/intel/skylake || bool || ||
| |
| Include DSP firmware settings for max98357 amplifier.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_MAX98373 || soc/intel/skylake || bool || ||
| |
| Include DSP firmware settings for max98373 amplifier.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_SSM4567 || soc/intel/skylake || bool || ||
| |
| Include DSP firmware settings for ssm4567 smart amplifier.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_RT5514 || soc/intel/skylake || bool || ||
| |
| Include DSP firmware settings for rt5514 DSP.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_RT5663 || soc/intel/skylake || bool || ||
| |
| Include DSP firmware settings for rt5663 headset codec.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_MAX98927 || soc/intel/skylake || bool || ||
| |
| Include DSP firmware settings for max98927 amplifier.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DA7219 || soc/intel/skylake || bool || ||
| |
| Include DSP firmware settings for DA7219 headset codec.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NHLT_DA7219 || soc/intel/skylake || bool || Cache-as-ram implementation ||
| |
| This option allows you to select how cache-as-ram (CAR) is set up.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_SKYLAKE_CAR_NEM_ENHANCED || soc/intel/skylake || bool || Enhanced Non-evict mode ||
| |
| A current limitation of NEM (Non-Evict mode) is that code and data
| |
| sizes are derived from the requirement to not write out any modified
| |
| cache line. With NEM, if there is no physical memory behind the
| |
| cached area, the modified data will be lost and NEM results will be
| |
| inconsistent. ENHANCED NEM guarantees that modified data is always
| |
| kept in cache while clean data is replaced.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_SKYLAKE_FSP_CAR || soc/intel/skylake || bool || Use FSP CAR ||
| |
| Use FSP APIs to initialize and tear down the Cache-As-Ram.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SKIP_FSP_CAR || soc/intel/skylake || bool || Skip cache as RAM setup in FSP ||
| |
| Skip Cache as RAM setup in FSP.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_FADT_8042 || soc/intel/skylake || bool || ||
| |
| Choose this option if you want to disable 8042 Keyboard
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON || soc/intel/common || bool || ||
| |
| common code for Intel SOCs
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Intel SoC Common Code ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK || soc/intel/common/block || bool || ||
| |
| SoC driver for intel common IP code
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Intel SoC Common IP Code ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_TIMER || soc/intel/common/block/timer || bool || ||
| |
| Intel Processor common TIMER support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_XDCI || soc/intel/common/block/xdci || bool || ||
| |
| Intel Processor common XDCI support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_SCS || soc/intel/common/block/scs || bool || ||
| |
| Intel Processor common storage and communication subsystem support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_SATA || soc/intel/common/block/sata || bool || ||
| |
| Intel Processor common SATA support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_AHCI_PORT_IMPLEMENTED_INVERT || soc/intel/common/block/sata || bool || ||
| |
| SATA PCI configuration space offset 0x92 Port
| |
| implement register bit 0-2 represents respective
| |
| SATA port enable status as in 0 = Disable; 1 = Enable.
| |
| If this option is selected then port enable status will be
| |
| inverted as in 0 = Enable; 1 = Disable.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_LPC || soc/intel/common/block/lpc || bool || ||
| |
| Use common LPC code for platform. Only soc specific code needs to
| |
| be implemented as per requirement.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE || soc/intel/common/block/lpc || bool || ||
| |
| By default COMA range to LPC is enable. COMB range to LPC is optional
| |
| and should select based on platform dedicated selection.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_SPI || soc/intel/common/block/spi || bool || ||
| |
| Intel Processor common SPI support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_P2SB || soc/intel/common/block/p2sb || bool || ||
| |
| Intel Processor common P2SB driver
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_SMM || soc/intel/common/block/smm || bool || ||
| |
| Intel Processor common SMM support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP || soc/intel/common/block/smm || bool || ||
| |
| Intel Processor trap flag if it is supported
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS || soc/intel/common/block/smm || int || ||
| |
| Time in milliseconds that SLP_SMI for S5 waits for before
| |
| enabling sleep. This is required to avoid any race between
| |
| SLP_SMI and PWRBTN SMI.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_SA || soc/intel/common/block/systemagent || bool || ||
| |
| Intel Processor common System Agent support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SA_PCIEX_LENGTH || soc/intel/common/block/systemagent || hex || ||
| |
| This option allows you to select length of PCIEX region.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SA_ENABLE_IMR || soc/intel/common/block/systemagent || bool || ||
| |
| This option allows you to add the isolated memory ranges (IMRs).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SA_ENABLE_DPR || soc/intel/common/block/systemagent || bool || ||
| |
| This option allows you to add the DMA Protected Range (DPR).
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_HDA || soc/intel/common/block/hda || bool || ||
| |
| Intel Processor common High Definition Audio driver support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_LPSS || soc/intel/common/block/lpss || bool || ||
| |
| Intel Processor common LPSS support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_FAST_SPI || soc/intel/common/block/fast_spi || bool || ||
| |
| Intel Processor common FAST_SPI support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FAST_SPI_DISABLE_WRITE_STATUS || soc/intel/common/block/fast_spi || bool || Disable write status SPI opcode ||
| |
| Disable the write status SPI opcode in Intel Fast SPI block.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_UART || soc/intel/common/block/uart || bool || ||
| |
| Intel Processor common UART support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL || soc/intel/common/block/uart || hex || ||
| |
| Clock m-divisor value for m/n divider
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL || soc/intel/common/block/uart || hex || ||
| |
| Clock m-divisor value for m/n divider
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_GSPI || soc/intel/common/block/gspi || bool || ||
| |
| Intel Processor Common GSPI support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_GSPI_MAX || soc/intel/common/block/gspi || int || ||
| |
| Maximum number of GSPI controllers supported by the PCH. SoC
| |
| must define this config if SOC_INTEL_COMMON_BLOCK_GSPI is
| |
| selected.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 || soc/intel/common/block/gspi || bool || ||
| |
| Intel Processor Common GSPI support with quirks to handle
| |
| SPI_CS_CONTROL changes introduced in CNL.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_XHCI || soc/intel/common/block/xhci || bool || ||
| |
| Intel Processor common XHCI support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_PCIE || soc/intel/common/block/pcie || bool || ||
| |
| Intel Processor common PCIE support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCIE_DEBUG_INFO || soc/intel/common/block/pcie || bool || ||
| |
| Enable debug logs in PCIe module. Allows debug information on memory
| |
| base and limit, prefetchable memory base and limit, prefetchable memory
| |
| base upper 32 bits and prefetchable memory limit upper 32 bits.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_PCR || soc/intel/common/block/pcr || bool || ||
| |
| Intel Processor common Private configuration registers (PCR)
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCR_COMMON_IOSF_1_0 || soc/intel/common/block/pcr || bool || ||
| |
| The mapping of addresses via the SBREG_BAR assumes the IOSF-SB
| |
| agents are using 32-bit aligned accesses for their configuration
| |
| registers. For IOSF versions greater than 1_0, IOSF-SB
| |
| agents can use any access (8/16/32 bit aligned) for their
| |
| configuration registers
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_ACPI || soc/intel/common/block/acpi || bool || ||
| |
| Intel Processor common code for ACPI
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_RTC || soc/intel/common/block/rtc || bool || ||
| |
| Intel Processor common RTC support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_CPU || soc/intel/common/block/cpu || bool || ||
| |
| This option selects Intel Common CPU Model support code
| |
| which provides various CPU related APIs which are common
| |
| between all Intel Processor families. Common CPU code is supported
| |
| for SOCs starting from SKL,KBL,APL, and future.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_CPU_MPINIT || soc/intel/common/block/cpu || bool || ||
| |
| This option selects Intel Common CPU MP Init code. In
| |
| this common MP Init mechanism, the MP Init is occurring before
| |
| calling FSP Silicon Init. Hence, MP Init will be pulled to
| |
| BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is
| |
| ensured that all MTRRs are re-programmed based on the DRAM
| |
| resource settings.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_CAR || soc/intel/common/block/cpu || bool || ||
| |
| This option allows you to select how cache-as-ram (CAR) is set up.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEL_CAR_NEM || soc/intel/common/block/cpu || bool || ||
| |
| Traditionally, CAR is set up by using Non-Evict mode. This method
| |
| does not allow CAR and cache to co-exist, because cache fills are
| |
| blocked in NEM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEL_CAR_CQOS || soc/intel/common/block/cpu || bool || ||
| |
| Cache Quality of Service allows more fine-grained control of cache
| |
| usage. As result, it is possible to set up a portion of L2 cache for
| |
| CAR and use the remainder for actual caching.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEL_CAR_NEM_ENHANCED || soc/intel/common/block/cpu || bool || ||
| |
| A current limitation of NEM (Non-Evict mode) is that code and data sizes
| |
| are derived from the requirement to not write out any modified cache line.
| |
| With NEM, if there is no physical memory behind the cached area,
| |
| the modified data will be lost and NEM results will be inconsistent.
| |
| ENHANCED NEM guarantees that modified data is always
| |
| kept in cache while clean data is replaced.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_CSE || soc/intel/common/block/cse || bool || ||
| |
| Driver for communication with Converged Security Engine (CSE)
| |
| over Host Embedded Controller Interface (HECI)
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_EBDA || soc/intel/common/block/ebda || bool || ||
| |
| Intel Processor common EBDA library support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_PMC || soc/intel/common/block/pmc || bool || ||
| |
| Intel Processor common code for Power Management controller(PMC)
| |
| subsystem
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POWER_STATE_OFF_AFTER_FAILURE || soc/intel/common/block/pmc || bool || S5 Soft Off ||
| |
| Choose this option if you want to keep system into
| |
| S5 after reapplying power after failure
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POWER_STATE_ON_AFTER_FAILURE || soc/intel/common/block/pmc || bool || S0 Full On ||
| |
| Choose this option if you want to keep system into
| |
| S0 after reapplying power after failure
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POWER_STATE_PREVIOUS_AFTER_FAILURE || soc/intel/common/block/pmc || bool || Keep Previous State ||
| |
| Choose this option if you want to keep system into
| |
| same power state as before failure even after reapplying
| |
| power
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PMC_INVALID_READ_AFTER_WRITE || soc/intel/common/block/pmc || bool || ||
| |
| Enable this for PMC devices where a read back of ACPI BAR and
| |
| IO access bit does not return the previously written value.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_SMBUS || soc/intel/common/block/smbus || bool || ||
| |
| Intel Processor common SMBus support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_GPIO || soc/intel/common/block/gpio || bool || ||
| |
| Intel Processor common GPIO support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_SOC_COMMON_BLOCK_GPIO || soc/intel/common/block/gpio || bool || Output verbose GPIO debug messages ||
| |
| This option enables GPIO debug messages
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_SGX || soc/intel/common/block/sgx || bool || ||
| |
| Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU
| |
| instructions that can be used by applications to set aside private
| |
| regions of code and data.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_DSP || soc/intel/common/block/dsp || bool || ||
| |
| Intel Processor common DSP support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_I2C || soc/intel/common/block/i2c || bool || ||
| |
| Intel Processor Common I2C support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_I2C_DEBUG || soc/intel/common/block/i2c || bool || Enable debug output for LPSS I2C transactions ||
| |
| Enable debug output for I2C transactions. This can be useful
| |
| when debugging I2C drivers.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_SRAM || soc/intel/common/block/sram || bool || ||
| |
| Intel Processor common SRAM support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_ITSS || soc/intel/common/block/itss || bool || ||
| |
| Intel Processor common interrupt timer subsystem support
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_BLOCK_GRAPHICS || soc/intel/common/block/graphics || bool || ||
| |
| Intel Processor common Graphics support
| |
| | |
| ||
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ACPI_CONSOLE || soc/intel/common || bool || ||
| |
| Provide a mechanism for serial console based ACPI debug.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_INTEL_COMMON_LPSS_CLOCK_MHZ || soc/intel/common || int || ||
| |
| The clock speed that the controllers in LPSS(GSPI, I2C) are running
| |
| at, in MHz. No default is set here as this is an SOC-specific value
| |
| and must be provided by the SOC.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MMA || soc/intel/common || bool || Enable MMA (Memory Margin Analysis) support for Intel Core ||
| |
| Set this option to y to enable MMA (Memory Margin Analysis) support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TPM_TIS_ACPI_INTERRUPT || soc/intel/common || int || ||
| |
| acpi_get_gpe() is used to provide interrupt status to TPM layer.
| |
| This option specifies the GPE number.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_AMD_STONEYRIDGE_FP4 || soc/amd/stoneyridge || bool || ||
| |
| AMD Stoney Ridge FP4 support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_AMD_STONEYRIDGE_FT4 || soc/amd/stoneyridge || bool || ||
| |
| AMD Stoney Ridge FT4 support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_BSP_STACK_SIZE || soc/amd/stoneyridge || hex || ||
| |
| The amount of anticipated stack usage in CAR by bootblock and
| |
| other stages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PRERAM_CBMEM_CONSOLE_SIZE || soc/amd/stoneyridge || hex || ||
| |
| Increase this value if preram cbmem console is getting truncated
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOTTOMIO_POSITION || soc/amd/stoneyridge || hex || Bottom of 32-bit IO space ||
| |
| If PCI peripherals with big BARs are connected to the system
| |
| the bottom of the IO must be decreased to allocate such
| |
| devices.
| |
| | |
| Declare the beginning of the 128MB-aligned MMIO region. This
| |
| option is useful when PCI peripherals requesting large address
| |
| ranges are present.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS_ID || soc/amd/stoneyridge || string || ||
| |
| The default VGA BIOS PCI vendor/device ID should be set to the
| |
| result of the map_oprom_vendev() function in northbridge.c.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | STONEYRIDGE_XHCI_ENABLE || soc/amd/stoneyridge || bool || Enable Stoney Ridge XHCI Controller ||
| |
| The XHCI controller must be enabled and the XHCI firmware
| |
| must be added in order to have USB 3.0 support configured
| |
| by coreboot. The OS will be responsible for enabling the XHCI
| |
| controller if the the XHCI firmware is available but the
| |
| XHCI controller is not enabled by coreboot.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | STONEYRIDGE_XHCI_FWM || soc/amd/stoneyridge || bool || Add xhci firmware ||
| |
| Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | STONEYRIDGE_IMC_FWM || soc/amd/stoneyridge || bool || Add IMC firmware ||
| |
| Add Stoney Ridge IMC Firmware to support the onboard fan control
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | STONEYRIDGE_GEC_FWM || soc/amd/stoneyridge || bool || ||
| |
| Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC.
| |
| Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | STONEYRIDGE_SATA_MODE || soc/amd/stoneyridge || int || SATA Mode ||
| |
| Select the mode in which SATA should be driven.
| |
| The default is NATIVE.
| |
| 0: NATIVE mode does not require a ROM.
| |
| 2: AHCI may work with or without AHCI ROM. It depends on the payload support.
| |
| For example, seabios does not require the AHCI ROM.
| |
| 3: LEGACY IDE
| |
| 4: IDE to AHCI
| |
| 5: AHCI7804: ROM Required, and AMD driver required in the OS.
| |
| 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || NATIVE ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AHCI ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || LEGACY IDE ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || IDE to AHCI ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AHCI7804 ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || IDE to AHCI7804 ||
| |
| |- bgcolor="#eeeeee"
| |
| | STONEYRIDGE_LEGACY_FREE || soc/amd/stoneyridge || bool || System is legacy free ||
| |
| Select y if there is no keyboard controller in the system.
| |
| This sets variables in AGESA and ACPI.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIRQ_CONTINUOUS_MODE || soc/amd/stoneyridge || bool || ||
| |
| Set this option to y for serial IRQ in continuous mode.
| |
| Otherwise it is in quiet mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | STONEYRIDGE_ACPI_IO_BASE || soc/amd/stoneyridge || hex || ||
| |
| Base address for the ACPI registers.
| |
| This value must match the hardcoded value of AGESA.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | STONEYRIDGE_UART || soc/amd/stoneyridge || bool || UART controller on Stoney Ridge ||
| |
| There are two UART controllers in Stoney Ridge.
| |
| The UART registers are memory-mapped. UART
| |
| controller 0 registers range from FEDC_6000h
| |
| to FEDC_6FFFh. UART controller 1 registers
| |
| range from FEDC_8000h to FEDC_8FFFh.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_PSPSCUREOS || soc/amd/stoneyridge || bool || Include PSP SecureOS blobs in AMD firmware ||
| |
| Include the PspSecureOs, PspTrustlet and TrustletKey binaries
| |
| in the amdfw section.
| |
| | |
| If unsure, answer 'y'
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AMDFW_OUTSIDE_CBFS || soc/amd/stoneyridge || bool || The AMD firmware is outside CBFS ||
| |
| The AMDFW (PSP) is typically locatable in cbfs. Select this
| |
| option to manually attach the generated amdfw.rom outside of
| |
| cbfs. The location is selected by the FWM position.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AMD_FWM_POSITION_INDEX || soc/amd/stoneyridge || int || Firmware Directory Table location (0 to 5) ||
| |
| Typically this is calculated by the ROM size, but there may
| |
| be situations where you want to put the firmware directory
| |
| table in a different location.
| |
| 0: 512 KB - 0xFFFA0000
| |
| 1: 1 MB - 0xFFF20000
| |
| 2: 2 MB - 0xFFE20000
| |
| 3: 4 MB - 0xFFC20000
| |
| 4: 8 MB - 0xFF820000
| |
| 5: 16 MB - 0xFF020000
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AMD Firmware Directory Table set to location for 512KB ROM ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AMD Firmware Directory Table set to location for 1MB ROM ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AMD Firmware Directory Table set to location for 2MB ROM ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AMD Firmware Directory Table set to location for 4MB ROM ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AMD Firmware Directory Table set to location for 8MB ROM ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AMD Firmware Directory Table set to location for 16MB ROM ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_POWER_RESTORE || soc/amd/stoneyridge || int || ||
| |
| This option determines what state to go to once power is restored
| |
| after having been lost in S0. Select this option to automatically
| |
| return to S0. Otherwise the system will remain in S5 once power
| |
| is restored.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_AMD_COMMON || soc/amd/common || bool || ||
| |
| common code for AMD SOCs
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_AMD_COMMON_BLOCK || soc/amd/common/block || bool || ||
| |
| SoC driver for AMD common IP code
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AMD SoC Common IP Code ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_AMD_COMMON_BLOCK_S3 || soc/amd/common/block/s3 || bool || ||
| |
| Select this option to add S3 related functions to the build.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_AMD_COMMON_BLOCK_PI || soc/amd/common/block/pi || bool || ||
| |
| This option builds functions that interface AMD's AGESA.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_AMD_COMMON_BLOCK_PCI || soc/amd/common/block/pci || bool || ||
| |
| This option builds functions used to program PCI interrupt
| |
| routing, both PIC and APIC modes.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_AMD_COMMON_BLOCK_CAR || soc/amd/common/block/cpu || bool || ||
| |
| This option allows the SOC to use a standard AMD cache-as-ram (CAR)
| |
| implementation. CAR setup is built into bootblock and teardown is
| |
| in postcar. The teardown procedure does not preserve the stack so
| |
| it may not be appropriate for a romstage implementation without
| |
| additional consideration. If this option is not used, the SOC must
| |
| implement these functions separately.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_AMD_COMMON_BLOCK_PSP || soc/amd/common/block/psp || bool || ||
| |
| This option builds in the Platform Security Processor initialization
| |
| functions.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_AMD_PSP_SELECTABLE_SMU_FW || soc/amd/common/block/psp || bool || ||
| |
| Some PSP implementations allow storing SMU firmware into cbfs and
| |
| calling the PSP to load the blobs at the proper time.
| |
| | |
| The soc/<codename> should select this if its PSP supports the feature
| |
| and each mainboard can choose to select an appropriate fanless or
| |
| fanned set of blobs. Ask your AMD representative whether your APU
| |
| is considered fanless.
| |
| | |
| ||
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE || soc/broadcom/cygnus || bool || Enable DDR auto self-refresh ||
| |
| Warning: M0 expects that auto self-refresh is enabled. Modify
| |
| with caution.
| |
| | |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_DRAM || soc/mediatek/mt8173 || bool || Output verbose DRAM related debug messages ||
| |
| This option enables additional DRAM related debug messages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_I2C || soc/mediatek/mt8173 || bool || Output verbose I2C related debug messages ||
| |
| This option enables I2C related debug messages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_PMIC || soc/mediatek/mt8173 || bool || Output verbose PMIC related debug messages ||
| |
| This option enables PMIC related debug messages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_PMIC_WRAP || soc/mediatek/mt8173 || bool || Output verbose PMIC WRAP related debug messages ||
| |
| This option enables PMIC WRAP related debug messages.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_MVMAP2315_UART_ADDRESS || soc/marvell/mvmap2315 || hex || ||
| |
| Map the UART to the respective MMIO address
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TTYS0_BAUD || soc/marvell/mvmap2315 || int || ||
| |
| Baud rate for the UART
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IPQ_QFN_PART || soc/qualcomm/ipq40xx || bool || ||
| |
| Is the SoC a QFN part (as opposed to a BGA part)
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SBL_ELF || soc/qualcomm/ipq40xx || string || file name of the QCA SBL ELF ||
| |
| The path and filename of the binary blob containing
| |
| ipq40xx early initialization code, as supplied by the
| |
| vendor.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SBL_UTIL_PATH || soc/qualcomm/ipq40xx || string || Path for utils to combine SBL_ELF and bootblock ||
| |
| Path for utils to combine SBL_ELF and bootblock
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SBL_BLOB || soc/qualcomm/ipq806x || string || file name of the Qualcomm SBL blob ||
| |
| The path and filename of the binary blob containing
| |
| ipq806x early initialization code, as supplied by the
| |
| vendor.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RK3399_SPREAD_SPECTRUM_DDR || soc/rockchip/rk3399 || bool || Spread-spectrum DDR clock ||
| |
| Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit
| |
| used to modulate the frequency of the Silicon Creations’ Fractional
| |
| PLL in order to reduce EMI.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || CPU ||
| |
| |- bgcolor="#eeeeee"
| |
| | RESET_ON_INVALID_RAMSTAGE_CACHE || cpu/intel/haswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||
| |
| The haswell romstage code caches the loaded ramstage program
| |
| in SMM space. On S3 wake the romstage will copy over a fresh
| |
| ramstage that was cached in the SMM space. This option determines
| |
| the action to take when the ramstage cache is invalid. If selected
| |
| the system will reset otherwise the ramstage will be reloaded from
| |
| cbfs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_INTEL_FIRMWARE_INTERFACE_TABLE || cpu/intel/fit || None || ||
| |
| This option selects building a Firmware Interface Table (FIT).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_INTEL_NUM_FIT_ENTRIES || cpu/intel/fit || int || ||
| |
| This option selects the number of empty entries in the FIT table.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED || cpu/intel/turbo || None || ||
| |
| This option indicates that the turbo mode setting is not package
| |
| scoped. i.e. enable_turbo() needs to be called on not just the bsp
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SET_VMX_LOCK_BIT || cpu/intel/common || bool || Set lock bit after configuring VMX ||
| |
| Although the Intel manual says you must set the lock bit in addition
| |
| to the VMX bit in order for VMX to work, this isn't strictly true, so
| |
| we have the option to leave it unlocked and allow the OS (e.g. Linux)
| |
| to manage things itself. This is beneficial for testing purposes as
| |
| there is no need to reflash the firmware just to toggle the lock bit.
| |
| However, leaving the lock bit unset will break Windows' detection of
| |
| VMX support and built-in virtualization features like Hyper-V.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GEODE_VSA_FILE || cpu/amd/geode_lx || bool || Add a VSA image ||
| |
| Select this option if you have an AMD Geode LX vsa that you would
| |
| like to add to your ROM.
| |
| | |
| You will be able to specify the location and file name of the
| |
| image later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VSA_FILENAME || cpu/amd/geode_lx || string || AMD Geode LX VSA path and filename ||
| |
| The path and filename of the file to use as VSA.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | XIP_ROM_SIZE || cpu/amd/agesa || hex || ||
| |
| Overwride the default write through caching size as 1M Bytes.
| |
| On some AMD platforms, one socket supports 2 or more kinds of
| |
| processor family, compiling several CPU families agesa code
| |
| will increase the romstage size.
| |
| In order to execute romstage in place on the flash ROM,
| |
| more space is required to be set as write through caching.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_MRC_CACHE || cpu/amd/agesa || bool || Use cached memory configuration ||
| |
| Try to restore memory training results
| |
| from non-volatile memory.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FORCE_AM1_SOCKET_SUPPORT || cpu/amd/agesa/family16kb || bool || ||
| |
| Force AGESA to ignore package type mismatch between CPU and northbridge
| |
| in memory code. This enables Socket AM1 support with current AGESA
| |
| version for Kabini platform.
| |
| Enable this option only if you have Socket AM1 board.
| |
| Note that the AGESA release shipped with coreboot does not officially
| |
| support the AM1 socket. Selecting this option might damage your hardware.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | XIP_ROM_SIZE || cpu/amd/pi || hex || ||
| |
| Overwride the default write through caching size as 1M Bytes.
| |
| On some AMD platforms, one socket supports 2 or more kinds of
| |
| processor family, compiling several CPU families agesa code
| |
| will increase the romstage size.
| |
| In order to execute romstage in place on the flash ROM,
| |
| more space is required to be set as write through caching.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PARALLEL_MP || cpu/x86 || bool || ||
| |
| This option uses common MP infrastructure for bringing up APs
| |
| in parallel. It additionally provides a more flexible mechanism
| |
| for sequencing the steps of bringing up the APs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PARALLEL_MP_AP_WORK || cpu/x86 || bool || ||
| |
| Allow APs to do other work after initialization instead of going
| |
| to sleep.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LAPIC_MONOTONIC_TIMER || cpu/x86 || bool || ||
| |
| Expose monotonic time using the local APIC.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TSC_CONSTANT_RATE || cpu/x86 || bool || ||
| |
| This option asserts that the TSC ticks at a known constant rate.
| |
| Therefore, no TSC calibration is required.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TSC_MONOTONIC_TIMER || cpu/x86 || bool || ||
| |
| Expose monotonic time using the TSC.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TSC_SYNC_LFENCE || cpu/x86 || bool || ||
| |
| The CPU driver should select this if the CPU needs
| |
| to execute an lfence instruction in order to synchronize
| |
| rdtsc. This is true for all modern AMD CPUs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TSC_SYNC_MFENCE || cpu/x86 || bool || ||
| |
| The CPU driver should select this if the CPU needs
| |
| to execute an mfence instruction in order to synchronize
| |
| rdtsc. This is true for all modern Intel CPUs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_FIXED_XIP_ROM_SIZE || cpu/x86 || bool || ||
| |
| The XIP_ROM_SIZE Kconfig variable is used globally on x86
| |
| with the assumption that all chipsets utilize this value.
| |
| For the chipsets which do not use the variable it can lead
| |
| to unnecessary alignment constraints in cbfs for romstage.
| |
| Therefore, allow those chipsets a path to not be burdened.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SMM_MODULE_HEAP_SIZE || cpu/x86 || hex || ||
| |
| This option determines the size of the heap within the SMM handler
| |
| modules.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIALIZED_SMM_INITIALIZATION || cpu/x86 || bool || ||
| |
| On some CPUs, there is a race condition in SMM.
| |
| This can occur when both hyperthreads change SMM state
| |
| variables in parallel without coordination.
| |
| Setting this option serializes the SMM initialization
| |
| to avoid an ugly hang in the boot process at the cost
| |
| of a slightly longer boot time.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86_AMD_FIXED_MTRRS || cpu/x86 || bool || ||
| |
| This option informs the MTRR code to use the RdMem and WrMem fields
| |
| in the fixed MTRR MSRs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PLATFORM_USES_FSP1_0 || cpu/x86 || bool || ||
| |
| Selected for Intel processors/platform combinations that use the
| |
| Intel Firmware Support Package (FSP) 1.0 for initialization.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING || cpu/x86 || bool || ||
| |
| On certain platforms a boot speed gain can be realized if mirroring
| |
| the payload data stored in non-volatile storage. On x86 systems the
| |
| payload would typically live in a memory-mapped SPI part. Copying
| |
| the SPI contents to RAM before performing the load can speed up
| |
| the boot process.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOC_SETS_MSRS || cpu/x86 || bool || ||
| |
| The SoC requires different access methods for reading and writing
| |
| the MSRs. Use SoC specific routines to handle the MSR access.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_CAR_GLOBAL_MIGRATION || cpu || bool || ||
| |
| This option is selected if there is no need to migrate CAR globals.
| |
| All stages which use CAR globals can directly access the variables
| |
| from their linked addresses.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SMP || cpu || bool || ||
| |
| This option is used to enable certain functions to make coreboot
| |
| work correctly on symmetric multi processor (SMP) systems.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AP_SIPI_VECTOR || cpu || hex || ||
| |
| This must equal address of ap_sipi_vector from bootblock build.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MMX || cpu || bool || ||
| |
| Select MMX in your socket or model Kconfig if your CPU has MMX
| |
| streaming SIMD instructions. ROMCC can build more efficient
| |
| code if it can spill to MMX registers.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SSE || cpu || bool || ||
| |
| Select SSE in your socket or model Kconfig if your CPU has SSE
| |
| streaming SIMD instructions. ROMCC can build more efficient
| |
| code if it can spill to SSE (aka XMM) registers.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SSE2 || cpu || bool || ||
| |
| Select SSE2 in your socket or model Kconfig if your CPU has SSE2
| |
| streaming SIMD instructions. Some parts of coreboot can be built
| |
| with more efficient code if SSE2 instructions are available.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USES_MICROCODE_HEADER_FILES || cpu || bool || ||
| |
| This is selected by a board or chipset to set the default for the
| |
| microcode source choice to a list of external microcode headers
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_MICROCODE_CBFS_GENERATE || cpu || bool || Generate from tree ||
| |
| Select this option if you want microcode updates to be assembled when
| |
| building coreboot and included in the final image as a separate CBFS
| |
| file. Microcode will not be hard-coded into ramstage.
| |
| | |
| The microcode file may be removed from the ROM image at a later
| |
| time with cbfstool, if desired.
| |
| | |
| If unsure, select this option.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_MICROCODE_CBFS_EXTERNAL_HEADER || cpu || bool || Include external microcode header files ||
| |
| Select this option if you want to include external c header files
| |
| containing the CPU microcode. This will be included as a separate
| |
| file in CBFS.
| |
| | |
| A word of caution: only select this option if you are sure the
| |
| microcode that you have is newer than the microcode shipping with
| |
| coreboot.
| |
| | |
| The microcode file may be removed from the ROM image at a later
| |
| time with cbfstool, if desired.
| |
| | |
| If unsure, select "Generate from tree"
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_MICROCODE_CBFS_NONE || cpu || bool || Do not include microcode updates ||
| |
| Select this option if you do not want CPU microcode included in CBFS.
| |
| Note that for some CPUs, the microcode is hard-coded into the source
| |
| tree and is not loaded from CBFS. In this case, microcode will still
| |
| be updated. There is a push to move all microcode to CBFS, but this
| |
| change is not implemented for all CPUs.
| |
| | |
| This option currently applies to:
| |
| - Intel SandyBridge/IvyBridge
| |
| - VIA Nano
| |
| | |
| Microcode may be added to the ROM image at a later time with cbfstool,
| |
| if desired.
| |
| | |
| If unsure, select "Generate from tree"
| |
| | |
| The GOOD:
| |
| Microcode updates intend to solve issues that have been discovered
| |
| after CPU production. The expected effect is that systems work as
| |
| intended with the updated microcode, but we have also seen cases where
| |
| issues were solved by not applying microcode updates.
| |
| | |
| The BAD:
| |
| Note that some operating system include these same microcode patches,
| |
| so you may need to also disable microcode updates in your operating
| |
| system for this option to have an effect.
| |
| | |
| The UGLY:
| |
| A word of CAUTION: some CPUs depend on microcode updates to function
| |
| correctly. Not updating the microcode may leave the CPU operating at
| |
| less than optimal performance, or may cause outright hangups.
| |
| There are CPUs where coreboot cannot properly initialize the CPU
| |
| without microcode updates
| |
| For example, if running with the factory microcode, some Intel
| |
| SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
| |
| will hang when changing the frequency.
| |
| | |
| Make sure you have a way of flashing the ROM externally before
| |
| selecting this option.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_MICROCODE_MULTIPLE_FILES || cpu || bool || ||
| |
| Select this option to install separate microcode container files into
| |
| CBFS instead of using the traditional monolithic microcode file format.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_MICROCODE_HEADER_FILES || cpu || string || List of space separated microcode header files with the path ||
| |
| A list of one or more microcode header files with path from the
| |
| coreboot directory. These should be separated by spaces.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_UCODE_BINARIES || cpu || string || Microcode binary path and filename ||
| |
| Some platforms have microcode in the blobs directory, and these can
| |
| be hardcoded in the makefiles. For platforms with microcode
| |
| binaries that aren't in the makefile, set this option to pull
| |
| in the microcode.
| |
| | |
| This should contain the full path of the file for one or more
| |
| microcode binary files to include, separated by spaces.
| |
| | |
| If unsure, leave this blank.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Northbridge ||
| |
| |- bgcolor="#eeeeee"
| |
| | I945_LVDS || northbridge/intel/i945 || string || ||
| |
| Selected by mainboards that use native graphics initialization
| |
| for the LVDS port. A linear framebuffer is only supported for
| |
| LVDS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || ||
| |
| Usually system firmware turns off system memory clock
| |
| signals to unused SO-DIMM slots to reduce EMI and power
| |
| consumption.
| |
| However, some boards do not like unused clock signals to
| |
| be disabled.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || ||
| |
| If non-zero, this designates the maximum DDR frequency
| |
| the board supports, despite what the chipset should be
| |
| capable of.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CHECK_SLFRCS_ON_RESUME || northbridge/intel/i945 || int || ||
| |
| On some boards it may be neccessary to hard reset early
| |
| during resume from S3 if the SLFRCS register indicates that
| |
| a memory channel is not guaranteed to be in self-refresh.
| |
| On other boards the check always creates a false positive,
| |
| effectively making it impossible to resume.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_NATIVE_RAMINIT || northbridge/intel/sandybridge || bool || Use native raminit ||
| |
| Select if you want to use coreboot implementation of raminit rather than
| |
| System Agent/MRC.bin. You should answer Y.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES || northbridge/intel/sandybridge || bool || Ignore vendor programmed fuses that limit max. DRAM frequency ||
| |
| Ignore the mainboard's vendor programmed fuses that might limit the
| |
| maximum DRAM frequency. By selecting this option the fuses will be
| |
| ignored and the only limits on DRAM frequency are set by RAM's SPD and
| |
| hard fuses in southbridge's clockgen.
| |
| Disabled by default as it might causes system instability.
| |
| Handle with care!
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS || northbridge/intel/sandybridge || bool || Ignore XMP profile max DIMMs per channel ||
| |
| Ignore the max DIMMs per channel restriciton defined in XMP profiles.
| |
| Disabled by default as it might cause system instability.
| |
| Handle with care!
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MMCONF_BASE_ADDRESS || northbridge/intel/sandybridge || hex || ||
| |
| The MRC blob requires it to be at 0xf0000000.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MRC_FILE || northbridge/intel/sandybridge || string || Intel System Agent path and filename ||
| |
| The path and filename of the file to use as System Agent
| |
| binary.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_SIZE || northbridge/intel/haswell || hex || ||
| |
| The size of the cache-as-ram region required during bootblock
| |
| and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
| |
| must add up to a power of 2.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_MRC_VAR_SIZE || northbridge/intel/haswell || hex || ||
| |
| The amount of cache-as-ram region required by the reference code.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DCACHE_RAM_ROMSTAGE_STACK_SIZE || northbridge/intel/haswell || hex || ||
| |
| The amount of anticipated stack usage from the data cache
| |
| during pre-ram ROM stage execution.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_MRC || northbridge/intel/haswell || bool || Add a System Agent binary ||
| |
| Select this option to add a System Agent binary to
| |
| the resulting coreboot image.
| |
| | |
| Note: Without this binary coreboot will not work
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MRC_FILE || northbridge/intel/haswell || string || Intel System Agent path and filename ||
| |
| The path and filename of the file to use as System Agent
| |
| binary.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PRE_GRAPHICS_DELAY || northbridge/intel/haswell || int || Graphics initialization delay in ms ||
| |
| On some systems, coreboot boots so fast that connected monitors
| |
| (mostly TVs) won't be able to wake up fast enough to talk to the
| |
| VBIOS. On those systems we need to wait for a bit before executing
| |
| the VBIOS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS_ID || northbridge/intel/fsp_sandybridge || string || ||
| |
| This is the default PCI ID for the sandybridge/ivybridge graphics
| |
| devices. This string names the vbios ROM in cbfs. The following
| |
| PCI IDs will be remapped to load this ROM:
| |
| 0x80860102, 0x8086010a, 0x80860112, 0x80860116
| |
| 0x80860122, 0x80860126, 0x80860166
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_FILE || northbridge/intel/fsp_sandybridge/fsp || string || ||
| |
| The path and filename of the Intel FSP binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_LOC || northbridge/intel/fsp_sandybridge/fsp || hex || Intel FSP Binary location in CBFS ||
| |
| The location in CBFS that the FSP is located. This must match the
| |
| value that is set in the FSP binary. If the FSP needs to be moved,
| |
| rebase the FSP with the Intel's BCT (tool).
| |
| | |
| The Ivy Bridge Processor/Panther Point FSP is built with a preferred
| |
| base address of 0xFFF80000
| |
| | |
| ||
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool || ||
| |
| This option affects how the SDRAMC register is programmed.
| |
| Memory clock signals will not be routed properly if this option
| |
| is set wrong.
| |
| | |
| If your board has 4 DIMM slots, you must use select this option, in
| |
| your Kconfig file of the board. On boards with 3 DIMM slots,
| |
| do _not_ select this option.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SET_TSEG_1MB || northbridge/intel/fsp_rangeley || bool || 1 MB ||
| |
| Set the TSEG area to 1 MB.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SET_TSEG_2MB || northbridge/intel/fsp_rangeley || bool || 2 MB ||
| |
| Set the TSEG area to 2 MB.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SET_TSEG_4MB || northbridge/intel/fsp_rangeley || bool || 4 MB ||
| |
| Set the TSEG area to 4 MB.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SET_TSEG_8MB || northbridge/intel/fsp_rangeley || bool || 8 MB ||
| |
| Set the TSEG area to 8 MB.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_FILE || northbridge/intel/fsp_rangeley/fsp || string || ||
| |
| The path and filename of the Intel FSP binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_LOC || northbridge/intel/fsp_rangeley/fsp || hex || ||
| |
| The location in CBFS that the FSP is located. This must match the
| |
| value that is set in the FSP binary. If the FSP needs to be moved,
| |
| rebase the FSP with Intel's BCT (tool).
| |
| | |
| The Rangeley FSP is built with a preferred base address of 0xFFF80000
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOTTOMIO_POSITION || northbridge/amd/pi || hex || Bottom of 32-bit IO space ||
| |
| If PCI peripherals with big BARs are connected to the system
| |
| the bottom of the IO must be decreased to allocate such
| |
| devices.
| |
| | |
| Declare the beginning of the 128MB-aligned MMIO region. This
| |
| option is useful when PCI peripherals requesting large address
| |
| ranges are present.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS_ID || northbridge/amd/pi/00630F01 || string || ||
| |
| The default VGA BIOS PCI vendor/device ID should be set to the
| |
| result of the map_oprom_vendev() function in northbridge.c.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS_ID || northbridge/amd/pi/00730F01 || string || ||
| |
| The default VGA BIOS PCI vendor/device ID should be set to the
| |
| result of the map_oprom_vendev() function in northbridge.c.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS_ID || northbridge/amd/pi/00660F01 || string || ||
| |
| The default VGA BIOS PCI vendor/device ID should be set to the
| |
| result of the map_oprom_vendev() function in northbridge.c.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | REDIRECT_NBCIMX_TRACE_TO_SERIAL || northbridge/amd/cimx/rd890 || bool || Redirect AMD Northbridge CIMX Trace to serial console ||
| |
| This Option allows you to redirect the AMD Northbridge CIMX
| |
| Trace debug information to the serial console.
| |
| | |
| Warning: Only enable this option when debuging or tracing AMD CIMX code.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_MMCONF_SUPPORT || northbridge/amd/amdk8 || bool || ||
| |
| If you want to remove this, you need to make sure any access to CPU
| |
| nodes 0:18.0, 0:19.0, ... continue to use PCI IO config access.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS_ID || northbridge/amd/agesa/family16kb || string || ||
| |
| The default VGA BIOS PCI vendor/device ID should be set to the
| |
| result of the map_oprom_vendev() function in northbridge.c.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || ||
| |
| Select this for boards with a Voltage Regulator able to operate
| |
| at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
| |
| | |
| ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: HyperTransport setup || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || HyperTransport downlink width ||
| |
| This option sets the maximum permissible HyperTransport
| |
| downlink width.
| |
| | |
| Use of this option will only limit the autodetected HT width.
| |
| It will not (and cannot) increase the width beyond the autodetected
| |
| limits.
| |
| | |
| This is primarily used to work around poorly designed or laid out HT
| |
| traces on certain motherboards.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd/amdfam10 || bool || HyperTransport uplink width ||
| |
| This option sets the maximum permissible HyperTransport
| |
| uplink width.
| |
| | |
| Use of this option will only limit the autodetected HT width.
| |
| It will not (and cannot) increase the width beyond the autodetected
| |
| limits.
| |
| | |
| This is primarily used to work around poorly designed or laid out HT
| |
| traces on certain motherboards.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Southbridge ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIRQ_CONTINUOUS_MODE || southbridge/intel/ibexpeak || bool || ||
| |
| If you set this option to y, the serial IRQ machine will be
| |
| operated in continuous mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEL_LYNXPOINT_LP || southbridge/intel/lynxpoint || bool || ||
| |
| Set this option to y for Lynxpont LP (Haswell ULT).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIRQ_CONTINUOUS_MODE || southbridge/intel/lynxpoint || bool || ||
| |
| If you set this option to y, the serial IRQ machine will be
| |
| operated in continuous mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ME_MBP_CLEAR_LATE || southbridge/intel/lynxpoint || bool || Defer wait for ME MBP Cleared ||
| |
| If you set this option to y, the Management Engine driver
| |
| will defer waiting for the MBP Cleared indicator until the
| |
| finalize step. This can speed up boot time if the ME takes
| |
| a long time to indicate this status.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FINALIZE_USB_ROUTE_XHCI || southbridge/intel/lynxpoint || bool || Route all ports to XHCI controller in finalize step ||
| |
| If you set this option to y, the USB ports will be routed
| |
| to the XHCI controller during the finalize SMM callback.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIRQ_CONTINUOUS_MODE || southbridge/intel/bd82x6x || bool || ||
| |
| If you set this option to y, the serial IRQ machine will be
| |
| operated in continuous mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LOCK_SPI_FLASH_RO || southbridge/intel/bd82x6x || bool || Write-protect all flash sections ||
| |
| Select this if you want to write-protect the whole firmware flash
| |
| chip. The locking will take place during the chipset lockdown, which
| |
| is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)
| |
| or has to be triggered later (e.g. by the payload or the OS).
| |
| | |
| NOTE: If you trigger the chipset lockdown unconditionally,
| |
| you won't be able to write to the flash chip using the
| |
| internal programmer any more.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LOCK_SPI_FLASH_NO_ACCESS || southbridge/intel/bd82x6x || bool || Write-protect all flash sections and read-protect non-BIOS sections ||
| |
| Select this if you want to protect the firmware flash against all
| |
| further accesses (with the exception of the memory mapped BIOS re-
| |
| gion which is always readable). The locking will take place during
| |
| the chipset lockdown, which is either triggered by coreboot (when
| |
| INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.
| |
| by the payload or the OS).
| |
| | |
| NOTE: If you trigger the chipset lockdown unconditionally,
| |
| you won't be able to write to the flash chip using the
| |
| internal programmer any more.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_bd82x6x || bool || ||
| |
| If you set this option to y, the serial IRQ machine will be
| |
| operated in continuous mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEL_CHIPSET_LOCKDOWN || southbridge/intel/common || bool || Lock down chipset in coreboot ||
| |
| Some registers within host bridge on particular chipsets should be
| |
| locked down on each normal boot path (done by either coreboot or payload)
| |
| and S3 resume (always done by coreboot). Select this to let coreboot
| |
| to do this on normal boot path.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_rangeley || bool || ||
| |
| If you set this option to y, the serial IRQ machine will be
| |
| operated in continuous mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IFD_BIN_PATH || southbridge/intel/fsp_rangeley || string || ||
| |
| The path and filename to the descriptor.bin file.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_i89xx || bool || ||
| |
| If you set this option to y, the serial IRQ machine will be
| |
| operated in continuous mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_XHCI_ENABLE || southbridge/amd/pi/hudson || bool || Enable Hudson XHCI Controller ||
| |
| The XHCI controller must be enabled and the XHCI firmware
| |
| must be added in order to have USB 3.0 support configured
| |
| by coreboot. The OS will be responsible for enabling the XHCI
| |
| controller if the the XHCI firmware is available but the
| |
| XHCI controller is not enabled by coreboot.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_XHCI_FWM || southbridge/amd/pi/hudson || bool || Add xhci firmware ||
| |
| Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_IMC_FWM || southbridge/amd/pi/hudson || bool || Add IMC firmware ||
| |
| Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_GEC_FWM || southbridge/amd/pi/hudson || bool || ||
| |
| Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
| |
| Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_SATA_MODE || southbridge/amd/pi/hudson || int || SATA Mode ||
| |
| Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
| |
| The default is NATIVE.
| |
| 0: NATIVE mode does not require a ROM.
| |
| 1: RAID mode must have the two ROM files.
| |
| 2: AHCI may work with or without AHCI ROM. It depends on the payload support.
| |
| For example, seabios does not require the AHCI ROM.
| |
| 3: LEGACY IDE
| |
| 4: IDE to AHCI
| |
| 5: AHCI7804: ROM Required, and AMD driver required in the OS.
| |
| 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || NATIVE ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || RAID ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AHCI ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || LEGACY IDE ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || IDE to AHCI ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AHCI7804 ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || IDE to AHCI7804 ||
| |
| |- bgcolor="#eeeeee"
| |
| | RAID_ROM_ID || southbridge/amd/pi/hudson || string || RAID device PCI IDs ||
| |
| 1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RAID_MISC_ROM_POSITION || southbridge/amd/pi/hudson || hex || RAID Misc ROM Position ||
| |
| The RAID ROM requires that the MISC ROM is located between the range
| |
| 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
| |
| The CONFIG_ROM_SIZE must be larger than 0x100000.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_LEGACY_FREE || southbridge/amd/pi/hudson || bool || System is legacy free ||
| |
| Select y if there is no keyboard controller in the system.
| |
| This sets variables in AGESA and ACPI.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AZ_PIN || southbridge/amd/pi/hudson || hex || ||
| |
| bit 1,0 - pin 0
| |
| bit 3,2 - pin 1
| |
| bit 5,4 - pin 2
| |
| bit 7,6 - pin 3
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AMDFW_OUTSIDE_CBFS || southbridge/amd/pi/hudson || hex || ||
| |
| The AMDFW (PSP) is typically locatable in cbfs. Select this
| |
| option to manually attach the generated amdfw.rom at an
| |
| offset of 0x20000 from the bottom of the coreboot ROM image.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SERIRQ_CONTINUOUS_MODE || southbridge/amd/pi/hudson || bool || ||
| |
| Set this option to y for serial IRQ in continuous mode.
| |
| Otherwise it is in quiet mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_ACPI_IO_BASE || southbridge/amd/pi/hudson || hex || ||
| |
| Base address for the ACPI registers.
| |
| This value must match the hardcoded value of AGESA.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_UART || southbridge/amd/pi/hudson || bool || UART controller on Kern ||
| |
| There are two UART controllers in Kern.
| |
| The UART registers are memory-mapped. UART
| |
| controller 0 registers range from FEDC_6000h
| |
| to FEDC_6FFFh. UART controller 1 registers
| |
| range from FEDC_8000h to FEDC_8FFFh.
| |
| | |
| ||
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode ||
| |
| If Combined Mode is enabled. IDE controller is exposed and
| |
| SATA controller has control over Port0 through Port3,
| |
| IDE controller has control over Port4 and Port5.
| |
| | |
| If Combined Mode is disabled, IDE controller is hidden and
| |
| SATA controller has full control of all 6 Ports when operating in non-IDE mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||
| |
| Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
| |
| The default is AHCI.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||
| |
| NATIVE does not require a ROM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||
| |
| AHCI is the default and may work with or without AHCI ROM. It depends on the payload support.
| |
| For example, seabios does not require the AHCI ROM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID ||
| |
| sb800 RAID mode must have the two required ROM files.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs ||
| |
| 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position ||
| |
| The RAID ROM requires that the MISC ROM is located between the range
| |
| 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
| |
| The CONFIG_ROM_SIZE must larger than 0x100000.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_IMC_FWM || southbridge/amd/cimx/sb800 || bool || Add IMC firmware ||
| |
| Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_FWM_AT_FFFA0000 || southbridge/amd/cimx/sb800 || bool || 0xFFFA0000 ||
| |
| The IMC and GEC ROMs requires a 'signature' located at one of several
| |
| fixed locations in memory. The location used shouldn't matter, just
| |
| select an area that doesn't conflict with anything else.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_FWM_AT_FFF20000 || southbridge/amd/cimx/sb800 || bool || 0xFFF20000 ||
| |
| The IMC and GEC ROMs requires a 'signature' located at one of several
| |
| fixed locations in memory. The location used shouldn't matter, just
| |
| select an area that doesn't conflict with anything else.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_FWM_AT_FFE20000 || southbridge/amd/cimx/sb800 || bool || 0xFFE20000 ||
| |
| The IMC and GEC ROMs requires a 'signature' located at one of several
| |
| fixed locations in memory. The location used shouldn't matter, just
| |
| select an area that doesn't conflict with anything else.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_FWM_AT_FFC20000 || southbridge/amd/cimx/sb800 || bool || 0xFFC20000 ||
| |
| The IMC and GEC ROMs requires a 'signature' located at one of several
| |
| fixed locations in memory. The location used shouldn't matter, just
| |
| select an area that doesn't conflict with anything else.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_FWM_AT_FF820000 || southbridge/amd/cimx/sb800 || bool || 0xFF820000 ||
| |
| The IMC and GEC ROMs requires a 'signature' located at one of several
| |
| fixed locations in memory. The location used shouldn't matter, just
| |
| select an area that doesn't conflict with anything else.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EHCI_BAR || southbridge/amd/cimx/sb800 || hex || Fan Control ||
| |
| Select the method of SB800 fan control to be used. None would be
| |
| for either fixed maximum speed fans connected to the SB800 or for
| |
| an external chip controlling the fan speeds. Manual control sets
| |
| up the SB800 fan control registers. IMC fan control uses the SB800
| |
| IMC to actively control the fan speeds.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_NO_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || None ||
| |
| No SB800 Fan control - Do not set up the SB800 fan control registers.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_MANUAL_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || Manual ||
| |
| Configure the SB800 fan control registers in devicetree.cb.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SB800_IMC_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || IMC Based ||
| |
| Set up the SB800 to use the IMC based Fan controller. This requires
| |
| the IMC ROM from AMD. Configure the registers in devicetree.cb.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex || ||
| |
| 0x0 = Native IDE mode.
| |
| 0x1 = RAID mode.
| |
| 0x2 = AHCI mode.
| |
| 0x3 = Legacy IDE mode.
| |
| 0x4 = IDE->AHCI mode.
| |
| 0x5 = AHCI mode as 7804 ID (AMD driver).
| |
| 0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool || ||
| |
| n = Disable PCI Bridge Device 14 Function 4.
| |
| y = Enable PCI Bridge Device 14 Function 4.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex || ||
| |
| Set SCI IRQ to 9.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EXT_CONF_SUPPORT || southbridge/amd/sr5650 || bool || Enable PCI-E MMCONFIG support ||
| |
| Select to enable PCI-E MMCONFIG support on the SR5650.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || ||
| |
| Select if RS690 should be setup to support MMCONF.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_XHCI_ENABLE || southbridge/amd/agesa/hudson || bool || Enable Hudson XHCI Controller ||
| |
| The XHCI controller must be enabled and the XHCI firmware
| |
| must be added in order to have USB 3.0 support configured
| |
| by coreboot. The OS will be responsible for enabling the XHCI
| |
| controller if the the XHCI firmware is available but the
| |
| XHCI controller is not enabled by coreboot.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_XHCI_FWM || southbridge/amd/agesa/hudson || bool || Add xhci firmware ||
| |
| Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_IMC_FWM || southbridge/amd/agesa/hudson || bool || Add imc firmware ||
| |
| Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_GEC_FWM || southbridge/amd/agesa/hudson || bool || ||
| |
| Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
| |
| Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_SATA_MODE || southbridge/amd/agesa/hudson || int || SATA Mode ||
| |
| Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
| |
| The default is NATIVE.
| |
| 0: NATIVE mode does not require a ROM.
| |
| 1: RAID mode must have the two ROM files.
| |
| 2: AHCI may work with or without AHCI ROM. It depends on the payload support.
| |
| For example, seabios does not require the AHCI ROM.
| |
| 3: LEGACY IDE
| |
| 4: IDE to AHCI
| |
| 5: AHCI7804: ROM Required, and AMD driver required in the OS.
| |
| 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || NATIVE ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || RAID ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AHCI ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || LEGACY IDE ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || IDE to AHCI ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || AHCI7804 ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || IDE to AHCI7804 ||
| |
| |- bgcolor="#eeeeee"
| |
| | RAID_ROM_ID || southbridge/amd/agesa/hudson || string || RAID device PCI IDs ||
| |
| 1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RAID_MISC_ROM_POSITION || southbridge/amd/agesa/hudson || hex || RAID Misc ROM Position ||
| |
| The RAID ROM requires that the MISC ROM is located between the range
| |
| 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
| |
| The CONFIG_ROM_SIZE must be larger than 0x100000.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HUDSON_LEGACY_FREE || southbridge/amd/agesa/hudson || bool || System is legacy free ||
| |
| Select y if there is no keyboard controller in the system.
| |
| This sets variables in AGESA and ACPI.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AZ_PIN || southbridge/amd/agesa/hudson || hex || ||
| |
| bit 1,0 - pin 0
| |
| bit 3,2 - pin 1
| |
| bit 5,4 - pin 2
| |
| bit 7,6 - pin 3
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOUTHBRIDGE_AMD_SB700_33MHZ_SPI || southbridge/amd/sb700 || bool || Enable high speed SPI clock ||
| |
| When set, the SPI clock will run at 33MHz instead
| |
| of the compatibility mode 16.5MHz. Note that not
| |
| all ROMs are capable of 33MHz operation, so you
| |
| will need to verify this option is appropriate for
| |
| the ROM you are using.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_EARLY_SMBUS || southbridge/amd/cs5536 || bool || ||
| |
| Skip the CS5536 early SMBUS initialization.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EHCI_BAR || southbridge/amd/sb600 || hex || SATA Mode ||
| |
| Select the mode in which SATA should be driven. IDE or AHCI.
| |
| The default is IDE.
| |
| | |
| config SATA_MODE_IDE
| |
| bool "IDE"
| |
| | |
| config SATA_MODE_AHCI
| |
| bool "AHCI"
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Super I/O ||
| |
| |- bgcolor="#eeeeee"
| |
| | SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG || superio/ite/common || bool || ||
| |
| Enable extended, 16-bit wide tacho counters.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SUPERIO_ITE_ENV_CTRL_8BIT_PWM || superio/ite/common || bool || ||
| |
| PWM duty cycles are set in 8-bit registers (instead of 7 bit).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 || superio/ite/common || bool || ||
| |
| The second FAN controller has a separate frequency setting.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Embedded Controllers ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_ACPI || ec/acpi || bool || ||
| |
| ACPI Embedded Controller interface. Mostly found in laptops.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC || ec/google/chromeec || bool || ||
| |
| Google's Chrome EC
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_ACPI_MEMMAP || ec/google/chromeec || bool || ||
| |
| When defined, ACPI accesses EC memmap data on ports 66h/62h. When
| |
| not defined, the memmap data is instead accessed on 900h-9ffh via
| |
| the LPC bus.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_BOARDID || ec/google/chromeec || bool || ||
| |
| Provides common routine for reading boardid from Chrome EC.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_I2C || ec/google/chromeec || bool || ||
| |
| Google's Chrome EC via I2C bus.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_I2C_PROTO3 || ec/google/chromeec || bool || ||
| |
| Use only proto3 for i2c EC communication.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_LPC || ec/google/chromeec || bool || ||
| |
| Google Chrome EC via LPC bus.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_MEC || ec/google/chromeec || bool || ||
| |
| Microchip EC variant for LPC register access.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_PD || ec/google/chromeec || bool || ||
| |
| Indicates that Google's Chrome USB PD chip is present.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_SPI || ec/google/chromeec || bool || ||
| |
| Google's Chrome EC via SPI bus.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US || ec/google/chromeec || int || ||
| |
| Force delay after asserting /CS to allow EC to wakeup.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for EC ||
| |
| The board name used in the Chrome EC code base to build
| |
| the EC firmware. If set, the coreboot build with also
| |
| build the EC firmware and add it to the image.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_PD_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for PD ||
| |
| The board name used in the Chrome EC code base to build
| |
| the PD firmware. If set, the coreboot build with also
| |
| build the EC firmware and add it to the image.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_RTC || ec/google/chromeec || bool || Enable Chrome OS EC RTC ||
| |
| Enable support for the real-time clock on the Chrome OS EC. This
| |
| uses the EC_CMD_RTC_GET_VALUE command to read the current time.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_FIRMWARE_NONE || ec/google/chromeec || bool || No EC firmware is included ||
| |
| Disable building and including any EC firmware in the image.
| |
| | |
| config EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL
| |
| bool "External EC firmware is included"
| |
| help
| |
| Include EC firmware binary in the image from an external source.
| |
| It is expected to be built externally.
| |
| | |
| config EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN
| |
| bool "Builtin EC firmware is included"
| |
| help
| |
| Build and include EC firmware binary in the image.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_FIRMWARE_FILE || ec/google/chromeec || string || Chrome EC firmware path and filename ||
| |
| The path and filename of the EC firmware file to use.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_PD_FIRMWARE_NONE || ec/google/chromeec || bool || No PD firmware is included ||
| |
| Disable building and including any PD firmware in the image.
| |
| | |
| config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_EXTERNAL
| |
| bool "External PD firmware is included"
| |
| help
| |
| Include PD firmware binary in the image from an external source.
| |
| It is expected to be built externally.
| |
| | |
| config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_BUILTIN
| |
| bool "Builtin PD firmware is included"
| |
| help
| |
| Build and include PD firmware binary in the image.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_PD_FIRMWARE_FILE || ec/google/chromeec || string || Chrome EC firmware path and filename for PD ||
| |
| The path and filename of the PD firmware file to use.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_GOOGLE_CHROMEEC_SWITCHES || ec/google/chromeec || bool || ||
| |
| Enable support for Chrome OS mode switches provided by the Chrome OS
| |
| EC.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_QUANTA_IT8518 || ec/quanta/it8518 || bool || ||
| |
| Interface to QUANTA IT8518 Embedded Controller.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_QUANTA_ENE_KB3940Q || ec/quanta/ene_kb3940q || bool || ||
| |
| Interface to QUANTA ENE KB3940Q Embedded Controller.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_HP_KBC1126 || ec/hp/kbc1126 || bool || ||
| |
| Interface to SMSC KBC1126 embedded controller in HP laptops.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Please select the following otherwise your laptop cannot be powered on. ||
| |
| |- bgcolor="#eeeeee"
| |
| | KBC1126_FIRMWARE || ec/hp/kbc1126 || bool || Add firmware images for KBC1126 EC ||
| |
| Select this option to add the two firmware blobs for KBC1126.
| |
| You need these two blobs to power on your machine.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | KBC1126_FW1 || ec/hp/kbc1126 || string || KBC1126 firmware #1 path and filename ||
| |
| The path and filename of the file to use as KBC1126 firmware #1.
| |
| You can use util/kbc1126/kbc1126_ec_dump to dump it from the
| |
| vendor firmware.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | KBC1126_FW2 || ec/hp/kbc1126 || string || KBC1126 filename #2 path and filename ||
| |
| The path and filename of the file to use as KBC1126 firmware #2.
| |
| You can use util/kbc1126/kbc1126_ec_dump to dump it from the
| |
| vendor firmware.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | H8_BEEP_ON_DEATH || ec/lenovo/h8 || bool || Beep on fatal error ||
| |
| Beep when encountered a fatal error.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | H8_FLASH_LEDS_ON_DEATH || ec/lenovo/h8 || bool || Flash LEDs on fatal error ||
| |
| Flash all LEDs when encountered a fatal error.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | H8_SUPPORT_BT_ON_WIFI || ec/lenovo/h8 || bool || Support bluetooth on wifi cards ||
| |
| Disable BDC detection and assume bluetooth is installed. Required for
| |
| bluetooth on wifi cards, as it's not possible to detect it in coreboot.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_RODA_IT8518 || ec/roda/it8518 || bool || ||
| |
| Interface to IT8518 embedded controller in Roda notebooks.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_SMSC_MEC1308 || ec/smsc/mec1308 || bool || ||
| |
| Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_PURISM_LIBREM || ec/purism/librem || bool || ||
| |
| Purism Librem EC
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_COMPAL_ENE932 || ec/compal/ene932 || bool || ||
| |
| Interface to COMPAL ENE932 Embedded Controller.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EC_KONTRON_IT8516E || ec/kontron/it8516e || bool || ||
| |
| Kontron uses an ITE IT8516E on the KTQM77. Its firmware might
| |
| come from Fintek (mentioned as Finte*c* somewhere in their Linux
| |
| driver).
| |
| The KTQM77 is an embedded board and the IT8516E seems to be
| |
| only used for fan control and GPIO.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Intel FSP ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_FSP_BIN || drivers/intel/fsp1_0 || bool || Use Intel Firmware Support Package ||
| |
| Select this option to add an Intel FSP binary to
| |
| the resulting coreboot image.
| |
| | |
| Note: Without this binary, coreboot builds relying on the FSP
| |
| will not boot
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_FILE || drivers/intel/fsp1_0 || string || Intel FSP binary path and filename ||
| |
| The path and filename of the Intel FSP binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_LOC || drivers/intel/fsp1_0 || hex || Intel FSP Binary location in CBFS ||
| |
| The location in CBFS that the FSP is located. This must match the
| |
| value that is set in the FSP binary. If the FSP needs to be moved,
| |
| rebase the FSP with Intel's BCT (tool).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_FSP_FAST_BOOT || drivers/intel/fsp1_0 || bool || Enable Fast Boot ||
| |
| Enabling this feature will force the MRC data to be cached in NV
| |
| storage to be used for speeding up boot time on future reboots
| |
| and/or power cycles.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_MRC_CACHE || drivers/intel/fsp1_0 || bool || ||
| |
| Enabling this feature will cause MRC data to be cached in NV storage.
| |
| This can either be used for fast boot, or just because the FSP wants
| |
| it to be saved.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MRC_CACHE_FMAP || drivers/intel/fsp1_0 || bool || Use MRC Cache in FMAP ||
| |
| Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
| |
| You must define a region in your FMAP named "RW_MRC_CACHE".
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MRC_CACHE_SIZE || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache Size ||
| |
| This is the amount of space in NV storage that is reserved for the
| |
| fast boot data cache storage.
| |
| | |
| WARNING: Because this area will be erased and re-written, the size
| |
| should be a full sector of the flash ROM chip and nothing else should
| |
| be included in CBFS in any sector that the fast boot cache data is in.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VIRTUAL_ROM_SIZE || drivers/intel/fsp1_0 || hex || Virtual ROM Size ||
| |
| This is used to calculate the offset of the MRC data cache in NV
| |
| Storage for fast boot. If in doubt, leave this set to the default
| |
| which sets the virtual size equal to the ROM size.
| |
| | |
| Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are
| |
| loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When
| |
| the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
| |
| size is 16 MB.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CACHE_ROM_SIZE_OVERRIDE || drivers/intel/fsp1_0 || hex || Cache ROM Size ||
| |
| This is the size of the cachable area that is passed into the FSP in
| |
| the early initialization. Typically this should be the size of the CBFS
| |
| area, but the size must be a power of 2 whereas the CBFS size does not
| |
| have this limitation.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_0 || bool || ||
| |
| The chipset can select this to use a generic cache_as_ram.inc file
| |
| that should be good for all FSP based platforms.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_USES_UPD || drivers/intel/fsp1_0 || bool || ||
| |
| If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_INTEL_FIRMWARE || southbridge/intel/common/firmware || bool || ||
| |
| Chipset uses the Intel Firmware Descriptor to describe the
| |
| layout of the SPI ROM chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Intel Firmware ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_IFD_BIN || southbridge/intel/common/firmware || bool || Add Intel descriptor.bin file ||
| |
| The descriptor binary
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EM100 || southbridge/intel/common/firmware || bool || Configure IFD for EM100 usage ||
| |
| Set SPI frequency to 20MHz and disable Dual Output Fast Read Support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_ME_BIN || southbridge/intel/common/firmware || bool || Add Intel ME/TXE firmware ||
| |
| The Intel processor in the selected system requires a special firmware
| |
| for an integrated controller. This might be called the Management
| |
| Engine (ME), the Trusted Execution Engine (TXE) or something else
| |
| depending on the chip. This firmware might or might not be available
| |
| in coreboot's 3rdparty/blobs repository. If it is not and if you don't
| |
| have access to the firmware from elsewhere, you can still build
| |
| coreboot without it. In this case however, you'll have to make sure
| |
| that you don't overwrite your ME/TXE firmware on your flash ROM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CHECK_ME || southbridge/intel/common/firmware || bool || Verify the integrity of the supplied ME/TXE firmware ||
| |
| Verify the integrity of the supplied Intel ME/TXE firmware before
| |
| proceeding with the build, in order to prevent an accidental loading
| |
| of a corrupted ME/TXE image.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_ME_CLEANER || southbridge/intel/common/firmware || bool || Strip down the Intel ME/TXE firmware ||
| |
| Use me_cleaner to remove all the non-fundamental code from the Intel
| |
| ME/TXE firmware.
| |
| The resulting Intel ME/TXE firmware will have only the code
| |
| responsible for the very basic hardware initialization, leaving the
| |
| ME/TXE subsystem essentially in a disabled state.
| |
| | |
| Don't flash a modified ME/TXE firmware and a new coreboot image at the
| |
| same time, test them in two different steps.
| |
| | |
| WARNING: this tool isn't based on any official Intel documentation but
| |
| only on reverse engineering and trial & error.
| |
| | |
| See the project's page
| |
| https://github.com/corna/me_cleaner | |
| or the wiki
| |
| https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner
| |
| https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F
| |
| https://github.com/corna/me_cleaner/wiki/me_cleaner-status
| |
| for more info about this tool
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Please test the modified ME/TXE firmware and coreboot in two steps ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_GBE_BIN || southbridge/intel/common/firmware || bool || Add gigabit ethernet firmware ||
| |
| The integrated gigabit ethernet controller needs a firmware file.
| |
| Select this if you are going to use the PCH integrated controller
| |
| and have the firmware.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_EC_BIN || southbridge/intel/common/firmware || bool || Add EC firmware ||
| |
| The embedded controller needs a firmware file.
| |
| | |
| Select this if you are going to use the PCH integrated controller
| |
| and have the EC firmware. EC firmware will be added to final image
| |
| through ifdtool.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BUILD_WITH_FAKE_IFD || southbridge/intel/common/firmware || bool || Build with a fake IFD ||
| |
| If you don't have an Intel Firmware Descriptor (descriptor.bin) for your
| |
| board, you can select this option and coreboot will build without it.
| |
| The resulting coreboot.rom will not contain all parts required
| |
| to get coreboot running on your board. You can however write only the
| |
| BIOS section to your board's flash ROM and keep the other sections
| |
| untouched. Unfortunately the current version of flashrom doesn't
| |
| support this yet. But there is a patch pending [1].
| |
| | |
| WARNING: Never write a complete coreboot.rom to your flash ROM if it
| |
| was built with a fake IFD. It just won't work.
| |
| | |
| [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IFD_BIOS_SECTION || southbridge/intel/common/firmware || string || BIOS Region Starting:Ending addresses within the ROM ||
| |
| The BIOS region is typically the size of the CBFS area, and is located
| |
| at the end of the ROM space.
| |
| | |
| For an 8MB ROM with a 3MB CBFS area, this would look like:
| |
| 0x00500000:0x007fffff
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IFD_ME_SECTION || southbridge/intel/common/firmware || string || ME/TXE Region Starting:Ending addresses within the ROM ||
| |
| The ME/TXE region typically starts at around 0x1000 and often fills the
| |
| ROM space not used by CBFS.
| |
| | |
| For an 8MB ROM with a 3MB CBFS area, this might look like:
| |
| 0x00001000:0x004fffff
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IFD_GBE_SECTION || southbridge/intel/common/firmware || string || GBE Region Starting:Ending addresses within the ROM ||
| |
| The Gigabit Ethernet ROM region is used when an Intel NIC is built into
| |
| the Southbridge/SOC and the platform uses this device instead of an external
| |
| PCIe NIC. It will be located between the ME/TXE and the BIOS region.
| |
| | |
| Leave this empty if you're unsure.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IFD_PLATFORM_SECTION || southbridge/intel/common/firmware || string || Platform Region Starting:Ending addresses within the Rom ||
| |
| The Platform region is used for platform specific data.
| |
| It will be located between the ME/TXE and the BIOS region.
| |
| | |
| Leave this empty if you're unsure.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LOCK_MANAGEMENT_ENGINE || southbridge/intel/common/firmware || bool || Lock ME/TXE section ||
| |
| The Intel Firmware Descriptor supports preventing write accesses
| |
| from the host to the ME or TXE section in the firmware
| |
| descriptor. If the section is locked, it can only be overwritten
| |
| with an external SPI flash programmer. You will want this if you
| |
| want to increase security of your ROM image once you are sure
| |
| that the ME/TXE firmware is no longer going to change.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CBFS_SIZE || southbridge/intel/common/firmware || hex || ||
| |
| Reduce CBFS size to give room to the IFD blobs.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | UDK_VERSION || vendorcode/intel || int || ||
| |
| UEFI Development Kit version for Platform
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: AMD Platform Initialization || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | None || vendorcode/amd || None || AGESA source ||
| |
| Select the method for including the AMD Platform Initialization
| |
| code into coreboot. Platform Initialization code is required for
| |
| all AMD processors.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_AMD_AGESA_BINARY_PI || vendorcode/amd || bool || binary PI ||
| |
| Use a binary PI package. Generally, these will be stored in the
| |
| "3rdparty/blobs" directory. For some processors, these must be obtained
| |
| directly from AMD Embedded Processors Group
| |
| (http://www.amdcom/embedded).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_AMD_AGESA_OPENSOURCE || vendorcode/amd || bool || open-source AGESA ||
| |
| Build the PI package ("AGESA") from source code in the "vendorcode"
| |
| directory.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AGESA_BINARY_PI_VENDORCODE_PATH || vendorcode/amd/pi || string || AGESA PI directory path ||
| |
| Specify where to find the AGESA header files
| |
| for AMD platform initialization.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AGESA_BINARY_PI_FILE || vendorcode/amd/pi || string || AGESA PI binary file name ||
| |
| Specify the binary file to use for AMD platform initialization.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AGESA_BINARY_PI_AS_STAGE || vendorcode/amd/pi || bool || AGESA Binary PI is added as stage to CBFS. ||
| |
| AGESA will be added as a stage utilizing --xip cbfstool options
| |
| as needed relocating the image to the proper location in memory-mapped
| |
| cpu address space. It's required that the file be in ELF format
| |
| containing the relocations necessary for relocating at runtime.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AGESA_SPLIT_MEMORY_FILES || vendorcode/amd/pi || bool || Split AGESA Binary PI into pre- and post-memory files. ||
| |
| Specifies that AGESA is split into two binaries for pre- and
| |
| post-memory.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AGESA_PRE_MEMORY_BINARY_PI_FILE || vendorcode/amd/pi || string || ||
| |
| Specify the binary file to use for pre-memory AMD platform
| |
| initialization.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AGESA_POST_MEMORY_BINARY_PI_FILE || vendorcode/amd/pi || string || ||
| |
| Specify the binary file to use for post-memory AMD platform
| |
| initialization.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | AGESA_BINARY_PI_LOCATION || vendorcode/amd/pi || hex || AGESA PI binary address in ROM ||
| |
| Specify the ROM address at which to store the binary Platform
| |
| Initialization code.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: ChromeOS || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | CHROMEOS || vendorcode/google/chromeos || bool || Build for ChromeOS ||
| |
| Enable ChromeOS specific features like the GPIO sub table in
| |
| the coreboot table. NOTE: Enabling this option on an unsupported
| |
| board will most likely break your build.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_TPM_RESUME || vendorcode/google/chromeos || bool || ||
| |
| On some boards the TPM stays powered up in S3. On those
| |
| boards, booting Windows will break if the TPM resume command
| |
| is sent during an S3 resume.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_REGULATORY_DOMAIN || vendorcode/google/chromeos || bool || Add regulatory domain methods ||
| |
| This option is needed to add ACPI regulatory domain methods
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME || vendorcode/google/chromeos || bool || ||
| |
| Disable the platform heirarchy on resume path if the firmware
| |
| is involved in resume. The hierarchy is disabled prior to jumping
| |
| to the OS. Note that this option is sepcific to TPM2 boards.
| |
| This option is auto selected if CHROMEOS because it matches with
| |
| vboot_reference model which disables the platform hierarchy in
| |
| the boot loader. However, those operations need to be symmetric
| |
| on normal boot as well as resume and coreboot is only involved
| |
| in the resume piece w.r.t. the platform hierarchy.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#eeeeee"
| |
| | GOOGLE_SMBIOS_MAINBOARD_VERSION || vendorcode/google || bool || ||
| |
| Provide a common implementation for mainboard version,
| |
| which returns a formatted 'rev%d' board_id() string.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ARCH_RISCV_COMPRESSED || arch/riscv || bool || ||
| |
| Enable this option if your RISC-V processor supports compressed
| |
| instructions (RVC). Currently, this enables RVC for all stages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ARCH_ARMV8_EXTENSION || arch/arm64/armv8 || int || ||
| |
| Specify ARMv8 extension, for example '1' for ARMv8.1, to control the
| |
| '-march' option passed into the compiler. Defaults to 0 for vanilla
| |
| ARMv8 but may be overridden in the SoC's Kconfig.
| |
| | |
| All ARMv8 implementations are downwards-compatible, so this does not
| |
| need to be changed unless specific features (e.g. new instructions)
| |
| are used by the SoC's coreboot code.
| |
| | |
| ||
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ARM64_SECURE_OS_FILE || arch/arm64 || string || Secure OS binary file ||
| |
| Secure OS binary file.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ARM64_A53_ERRATUM_843419 || arch/arm64 || bool || ||
| |
| Some early Cortex-A53 revisions had a hardware bug that results in
| |
| incorrect address calculations in rare cases. This option enables a
| |
| linker workaround to avoid those cases if your toolchain supports it.
| |
| Should be selected automatically by SoCs that are affected.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_MARCH_586 || arch/x86 || bool || ||
| |
| Allow a platform or processor to select to be compiled using
| |
| the '-march=i586' option instead of the typical '-march=i686'
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CBMEM_TOP_BACKUP || arch/x86 || bool || ||
| |
| Platform implements non-volatile storage to cache cbmem_top()
| |
| over stage transitions and optionally also over S3 suspend.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LATE_CBMEM_INIT || arch/x86 || bool || ||
| |
| Enable this in chipset's Kconfig if northbridge does not implement
| |
| early cbmem_top() call for romstage. CBMEM tables will be allocated
| |
| late in ramstage, after PCI devices resources are known.
| |
| | |
| WARNING: Late CBMEM initialization is deprecated. Platforms that
| |
| don't support early CBMEM initialization will be removed after
| |
| the release of coreboot 4.7.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PRERAM_CBMEM_CONSOLE_SIZE || arch/x86 || hex || ||
| |
| Increase this value if preram cbmem console is getting truncated
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EARLY_EBDA_INIT || arch/x86 || bool || ||
| |
| Initialize BIOS EBDA area early in romstage to allow bootloader to
| |
| use this region for storing data which can be available across
| |
| various stages. If user is selecting this option then its users
| |
| responsibility to perform EBDA initialization call during romstage.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOTBLOCK_DEBUG_SPINLOOP || arch/x86 || bool || ||
| |
| Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
| |
| for a JTAG debugger to break into the execution sequence.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP || arch/x86 || bool || ||
| |
| Select this value to provide a routine to save the BIST and timestamp
| |
| values. The default code places the BIST value in MM0 and the
| |
| timestamp value in MM2:MM1. Another file is necessary when the CPU
| |
| does not support the MMx register set.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VERSTAGE_DEBUG_SPINLOOP || arch/x86 || bool || ||
| |
| Add a spin (JMP .) in assembly_entry.S during early verstage to wait
| |
| for a JTAG debugger to break into the execution sequence.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ROMSTAGE_DEBUG_SPINLOOP || arch/x86 || bool || ||
| |
| Add a spin (JMP .) in assembly_entry.S during early romstage to wait
| |
| for a JTAG debugger to break into the execution sequence.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SKIP_MAX_REBOOT_CNT_CLEAR || arch/x86 || bool || Do not clear reboot count after successful boot ||
| |
| Do not clear the reboot count immediately after successful boot.
| |
| Set to allow the payload to control normal/fallback image recovery.
| |
| Note that it is the responsibility of the payload to reset the
| |
| normal boot bit to 1 after each successsful boot.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ACPI_CPU_STRING || arch/x86 || string || ||
| |
| Sets the ACPI name string in the processor scope as written by
| |
| the acpigen function. Default is \_PR.CPxx. Note that you need
| |
| the \ escape character in the string.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COLLECT_TIMESTAMPS_NO_TSC || arch/x86 || bool || ||
| |
| Use a non-TSC platform-dependent source for timestamps.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COLLECT_TIMESTAMPS_TSC || arch/x86 || bool || ||
| |
| Use the TSC as the timestamp source.
| |
| | |
| ||
| |
| | |
| ||
| |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Devices || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_VGA_TEXT_FRAMEBUFFER || device || bool || ||
| |
| Selected by graphics drivers that support legacy VGA text mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_VBE_LINEAR_FRAMEBUFFER || device || bool || ||
| |
| Selected by graphics drivers that can set up a VBE linear-framebuffer
| |
| mode.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_LINEAR_FRAMEBUFFER || device || bool || ||
| |
| Selected by graphics drivers that can set up a generic linear
| |
| framebuffer.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_FSP_GOP || device || bool || ||
| |
| Selected by drivers that support to run a blob that implements
| |
| the Graphics Output Protocol (GOP).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_HAS_NATIVE_VGA_INIT || device || bool || ||
| |
| Selected by mainboards / drivers that provide native graphics
| |
| init within coreboot.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_FORCE_NATIVE_VGA_INIT || device || bool || ||
| |
| Selected by mainboards / chipsets whose graphics driver can't or
| |
| shouldn't be disabled.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_HAS_LIBGFXINIT || device || bool || ||
| |
| Selected by mainboards that implement support for `libgfxinit`.
| |
| Usually this requires a list of ports to be probed for displays.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_DO_NATIVE_VGA_INIT || device || bool || Use native graphics init ||
| |
| Some mainboards, such as the Google Link, allow initializing the
| |
| display without the need of a binary only VGA OPROM. Enabling this
| |
| option may be faster, but also lacks flexibility in setting modes.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_USE_LIBGFXINIT || device || bool || Use libgfxinit ||
| |
| Use the SPARK library `libgfxinit` for the native graphics
| |
| initialization. This requires an Ada toolchain.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_ROM_RUN || device || bool || Run VGA Option ROMs ||
| |
| Execute VGA Option ROMs in coreboot if found. This can be used
| |
| to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
| |
| payload.
| |
| | |
| When using a SeaBIOS payload it runs all option ROMs with much
| |
| more complete BIOS interrupt services available than coreboot,
| |
| which some option ROMs require in order to function correctly.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RUN_FSP_GOP || device || bool || Run a GOP driver ||
| |
| Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support
| |
| to run a GOP blob. This option enables graphics initialization with
| |
| such a blob.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_GFX_INIT || device || bool || None ||
| |
| Select this to not perform any graphics initialization in
| |
| coreboot. This is useful if the payload (e.g. SeaBIOS) can
| |
| initialize graphics or if pre-boot graphics are not required.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | S3_VGA_ROM_RUN || device || bool || Re-run VGA Option ROMs on S3 resume ||
| |
| Execute VGA Option ROMs in coreboot when resuming from S3 suspend.
| |
| | |
| When using a SeaBIOS payload it runs all option ROMs with much
| |
| more complete BIOS interrupt services available than coreboot,
| |
| which some option ROMs require in order to function correctly.
| |
| | |
| If unsure, say N when using SeaBIOS as payload, Y otherwise.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ALWAYS_LOAD_OPROM || device || bool || ||
| |
| Always load option ROMs if any are found. The decision to run
| |
| the ROM is still determined at runtime, but the distinction
| |
| between loading and not running comes into play for CHROMEOS.
| |
| | |
| An example where this is required is that VBT (Video BIOS Tables)
| |
| are needed for the kernel's display driver to know how a piece of
| |
| hardware is configured to be used.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ALWAYS_RUN_OPROM || device || bool || ||
| |
| Always uncondtionally run the option regardless of other
| |
| policies.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ON_DEVICE_ROM_LOAD || device || bool || Load Option ROMs on PCI devices ||
| |
| Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot.
| |
| | |
| If disabled, only Option ROMs stored in CBFS will be executed by
| |
| coreboot. If you are concerned about security, you might want to
| |
| disable this option, but it might leave your system in a state of
| |
| degraded functionality.
| |
| | |
| When using a SeaBIOS payload it runs all option ROMs with much
| |
| more complete BIOS interrupt services available than coreboot,
| |
| which some option ROMs require in order to function correctly.
| |
| | |
| If unsure, say N when using SeaBIOS as payload, Y otherwise.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCI_OPTION_ROM_RUN_REALMODE || device || bool || Native mode ||
| |
| If you select this option, PCI Option ROMs will be executed
| |
| natively on the CPU in real mode. No CPU emulation is involved,
| |
| so this is the fastest, but also the least secure option.
| |
| (only works on x86/x64 systems)
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCI_OPTION_ROM_RUN_YABEL || device || bool || Secure mode ||
| |
| If you select this option, the x86emu CPU emulator will be used to
| |
| execute PCI Option ROMs.
| |
| | |
| This option prevents Option ROMs from doing dirty tricks with the
| |
| system (such as installing SMM modules or hypervisors), but it is
| |
| also significantly slower than the native Option ROM initialization
| |
| method.
| |
| | |
| This is the default choice for non-x86 systems.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | YABEL_PCI_ACCESS_OTHER_DEVICES || device || bool || Allow Option ROMs to access other devices ||
| |
| Per default, YABEL only allows Option ROMs to access the PCI device
| |
| that they are associated with. However, this causes trouble for some
| |
| onboard graphics chips whose Option ROM needs to reconfigure the
| |
| north bridge.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG || device || bool || Fake success on writing other device's config space ||
| |
| By default, YABEL aborts when the Option ROM tries to write to other
| |
| devices' config spaces. With this option enabled, the write doesn't
| |
| follow through, but the Option ROM is allowed to go on.
| |
| This can create issues such as hanging Option ROMs (if it depends on
| |
| that other register changing to the written value), so test for
| |
| impact before using this option.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | YABEL_VIRTMEM_LOCATION || device || hex || Location of YABEL's virtual memory ||
| |
| YABEL requires 1MB memory for its CPU emulation. This memory is
| |
| normally located at 16MB.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | YABEL_DIRECTHW || device || bool || Direct hardware access ||
| |
| YABEL consists of two parts: It uses x86emu for the CPU emulation and
| |
| additionally provides a PC system emulation that filters bad device
| |
| and memory access (such as PCI config space access to other devices
| |
| than the initialized one).
| |
| | |
| When choosing this option, x86emu will pass through all hardware
| |
| accesses to memory and I/O devices to the underlying memory and I/O
| |
| addresses. While this option prevents Option ROMs from doing dirty
| |
| tricks with the CPU (such as installing SMM modules or hypervisors),
| |
| they can still access all devices in the system.
| |
| Enable this option for a good compromise between security and speed.
| |
| | |
| ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Display || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | FRAMEBUFFER_SET_VESA_MODE || device || bool || Set framebuffer graphics resolution ||
| |
| Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FRAMEBUFFER_SET_VESA_MODE || device || bool || framebuffer graphics resolution ||
| |
| This option sets the resolution used for the coreboot framebuffer (and
| |
| bootsplash screen).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOTSPLASH || device || bool || Show graphical bootsplash ||
| |
| This option shows a graphical bootsplash screen. The graphics are
| |
| loaded from the CBFS file bootsplash.jpg.
| |
| | |
| You can either specify the location and file name of the
| |
| image in the 'General' section or add it manually to CBFS, using,
| |
| for example, cbfstool.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_TEXT_FRAMEBUFFER || device || bool || Legacy VGA text mode ||
| |
| If this option is enabled, coreboot will initialize graphics in
| |
| legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set,
| |
| switch to text mode before handing control to a payload.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBE_LINEAR_FRAMEBUFFER || device || bool || VESA framebuffer ||
| |
| This option keeps the framebuffer mode set after coreboot finishes
| |
| execution. If this option is enabled, coreboot will pass a
| |
| framebuffer entry in its coreboot table and the payload will need a
| |
| compatible driver.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GENERIC_LINEAR_FRAMEBUFFER || device || bool || Linear \"high-resolution\" framebuffer ||
| |
| This option enables a high-resolution, linear framebuffer. If this
| |
| option is enabled, coreboot will pass a framebuffer entry in its
| |
| coreboot table and the payload will need a compatible driver.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#eeeeee"
| |
| | PCIEXP_COMMON_CLOCK || device || bool || Enable PCIe Common Clock ||
| |
| Detect and enable Common Clock on PCIe links.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCIEXP_ASPM || device || bool || Enable PCIe ASPM ||
| |
| Detect and enable ASPM (Active State Power Management) on PCIe links.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCIEXP_CLK_PM || device || bool || Enable PCIe Clock Power Management ||
| |
| Detect and enable Clock Power Management on PCIe.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCIEXP_L1_SUB_STATE || device || bool || Enable PCIe ASPM L1 SubState ||
| |
| Detect and enable ASPM on PCIe links.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EARLY_PCI_BRIDGE || device || bool || Early PCI bridge ||
| |
| While coreboot is executing code from ROM, the coreboot resource
| |
| allocator has not been running yet. Hence PCI devices living behind
| |
| a bridge are not yet visible to the system.
| |
| | |
| This option enables static configuration for a single pre-defined
| |
| PCI bridge function on bus 0.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SUBSYSTEM_VENDOR_ID || device || hex || Override PCI Subsystem Vendor ID ||
| |
| This config option will override the devicetree settings for
| |
| PCI Subsystem Vendor ID.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SUBSYSTEM_DEVICE_ID || device || hex || Override PCI Subsystem Device ID ||
| |
| This config option will override the devicetree settings for
| |
| PCI Subsystem Device ID.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS || device || bool || Add a VGA BIOS image ||
| |
| Select this option if you have a VGA BIOS image that you would
| |
| like to add to your ROM.
| |
| | |
| You will be able to specify the location and file name of the
| |
| image later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS_FILE || device || string || VGA BIOS path and filename ||
| |
| The path and filename of the file to use as VGA BIOS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS_ID || device || string || VGA device PCI IDs ||
| |
| The comma-separated PCI vendor and device ID that would associate
| |
| your VGA BIOS to your video card.
| |
| | |
| Example: 1106,3230
| |
| | |
| In the above example 1106 is the PCI vendor ID (in hex, but without
| |
| the "0x" prefix) and 3230 specifies the PCI device ID of the
| |
| video card (also in hex, without "0x" prefix).
| |
| | |
| Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEL_GMA_ADD_VBT_DATA_FILE || device || bool || Add a Video Bios Table (VBT) binary to CBFS ||
| |
| Add a VBT data file to CBFS. The VBT describes the integrated
| |
| GPU and connections, and is needed by the GOP driver integrated into
| |
| FSP and the OS driver in order to initialize the display.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEL_GMA_VBT_FILE || device || string || VBT binary path and filename ||
| |
| The path and filename of the VBT binary.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SOFTWARE_I2C || device || bool || Enable I2C controller emulation in software ||
| |
| This config option will enable code to override the i2c_transfer
| |
| routine with a (simple) software emulation of the protocol. This may
| |
| be useful for debugging or on platforms where a driver for the real
| |
| I2C controller is not (yet) available. The platform code needs to
| |
| provide bindings to manually toggle I2C lines.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Generic Drivers || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | ELOG || drivers/elog || bool || Support for flash based event log ||
| |
| Enable support for flash based event logging.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ELOG_CBMEM || drivers/elog || bool || Store a copy of ELOG in CBMEM ||
| |
| This option will have ELOG store a copy of the flash event log
| |
| in a CBMEM region and export that address in SMBIOS to the OS.
| |
| This is useful if the ELOG location is not in memory mapped flash,
| |
| but it means that events added at runtime via the SMI handler
| |
| will not be reflected in the CBMEM copy of the log.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ELOG_GSMI || drivers/elog || bool || SMI interface to write and clear event log ||
| |
| This interface is compatible with the linux kernel driver
| |
| available with CONFIG_GOOGLE_GSMI and can be used to write
| |
| kernel reset/shutdown messages to the event log.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ELOG_BOOT_COUNT || drivers/elog || bool || Maintain a monotonic boot number in CMOS ||
| |
| Store a monotonic boot number in CMOS and provide an interface
| |
| to read the current value and increment the counter. This boot
| |
| counter will be logged as part of the System Boot event.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ELOG_BOOT_COUNT_CMOS_OFFSET || drivers/elog || int || Offset in CMOS to store the boot count ||
| |
| This value must be greater than 16 bytes so as not to interfere
| |
| with the standard RTC region. Requires 8 bytes.
| |
| | |
| ||
| |
| # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USBDEBUG || drivers/usb || bool || USB 2.0 EHCI debug dongle support ||
| |
| This option allows you to use a so-called USB EHCI Debug device
| |
| (such as the Ajays NET20DC, AMIDebug RX, or a system using the
| |
| Linux "EHCI Debug Device gadget" driver found in recent kernel)
| |
| to retrieve the coreboot debug messages (instead, or in addition
| |
| to, a serial port).
| |
| | |
| This feature is NOT supported on all chipsets in coreboot!
| |
| | |
| It also requires a USB2 controller which supports the EHCI
| |
| Debug Port capability.
| |
| | |
| See https://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
| |
| of supported controllers.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USBDEBUG_IN_ROMSTAGE || drivers/usb || bool || Enable early (pre-RAM) usbdebug ||
| |
| Configuring USB controllers in system-agent binary may cause
| |
| problems to usbdebug. Disabling this option delays usbdebug to
| |
| be setup on entry to ramstage.
| |
| | |
| If unsure, say Y.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USBDEBUG_HCD_INDEX || drivers/usb || int || Index for EHCI controller to use with usbdebug ||
| |
| Some boards have multiple EHCI controllers with possibly only
| |
| one having the Debug Port capability on an external USB port.
| |
| | |
| Mapping of this index to PCI device functions is southbridge
| |
| specific and mainboard level Kconfig should already provide
| |
| a working default value here.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USBDEBUG_DEFAULT_PORT || drivers/usb || int || Default USB port to use as Debug Port ||
| |
| Selects which physical USB port usbdebug dongle is connected to.
| |
| Setting of 0 means to scan possible ports starting from 1.
| |
| | |
| Intel platforms have hardwired the debug port location and this
| |
| setting makes no difference there.
| |
| | |
| Hence, if you select the correct port here, you can speed up
| |
| your boot time. Which USB port number refers to which actual
| |
| port on your mainboard (potentially also USB pin headers on
| |
| your mainboard) is highly board-specific, and you'll likely
| |
| have to find out by trial-and-error.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USBDEBUG_DONGLE_STD || drivers/usb || bool || USB gadget driver or Net20DC ||
| |
| Net20DC, BeagleBone Black, Raspberry Pi Zero W
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USBDEBUG_DONGLE_BEAGLEBONE || drivers/usb || bool || BeagleBone ||
| |
| Use this to configure the USB hub on BeagleBone board.
| |
| Do NOT select this for the BeagleBone Black.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USBDEBUG_DONGLE_FTDI_FT232H || drivers/usb || bool || FTDI FT232H UART ||
| |
| Use this with FT232H usb-to-uart. Configuration is hard-coded
| |
| to use 8n1, no flow control.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USBDEBUG_DONGLE_FTDI_FT232H_BAUD || drivers/usb || int || FTDI FT232H baud rate ||
| |
| Select baud rate for FT232H in the range 733..12,000,000. Make
| |
| sure that your receiving side supports the same setting and your
| |
| connection works with it. Multiples of 115,200 seem to be a good
| |
| choice, and EHCI debug usually can't saturate more than 576,000.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COMMON_CBFS_SPI_WRAPPER || drivers/spi || bool || ||
| |
| Use common wrapper to interface CBFS to SPI bootrom.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH || drivers/spi || bool || ||
| |
| Select this option if your chipset driver needs to store certain
| |
| data in the SPI flash.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOT_DEVICE_SPI_FLASH_BUS || drivers/spi || int || ||
| |
| Which SPI bus the boot device is connected to.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOT_DEVICE_SPI_FLASH_RW_NOMMAP || drivers/spi || bool || ||
| |
| Provide common implementation of the RW boot device that
| |
| doesn't provide mmap() operations.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY || drivers/spi || bool || ||
| |
| Include the common implementation in all stages, including the
| |
| early ones.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_SMM || drivers/spi || bool || SPI flash driver support in SMM ||
| |
| Select this option if you want SPI flash support in SMM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_NO_FAST_READ || drivers/spi || bool || Disable Fast Read command ||
| |
| Select this option if your setup requires to avoid "fast read"s
| |
| from the SPI flash parts.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_ADESTO || drivers/spi || bool || ||
| |
| Select this option if your chipset driver needs to store certain
| |
| data in the SPI flash and your SPI flash is made by Adesto Technologies.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_AMIC || drivers/spi || bool || ||
| |
| Select this option if your chipset driver needs to store certain
| |
| data in the SPI flash and your SPI flash is made by AMIC.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_ATMEL || drivers/spi || bool || ||
| |
| Select this option if your chipset driver needs to store certain
| |
| data in the SPI flash and your SPI flash is made by Atmel.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_EON || drivers/spi || bool || ||
| |
| Select this option if your chipset driver needs to store certain
| |
| data in the SPI flash and your SPI flash is made by EON.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_GIGADEVICE || drivers/spi || bool || ||
| |
| Select this option if your chipset driver needs to store certain
| |
| data in the SPI flash and your SPI flash is made by Gigadevice.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_MACRONIX || drivers/spi || bool || ||
| |
| Select this option if your chipset driver needs to store certain
| |
| data in the SPI flash and your SPI flash is made by Macronix.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_SPANSION || drivers/spi || bool || ||
| |
| Select this option if your chipset driver needs to store certain
| |
| data in the SPI flash and your SPI flash is made by Spansion.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_SST || drivers/spi || bool || ||
| |
| Select this option if your chipset driver needs to store certain
| |
| data in the SPI flash and your SPI flash is made by SST.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_STMICRO || drivers/spi || bool || ||
| |
| Select this option if your chipset driver needs to store certain
| |
| data in the SPI flash and your SPI flash is made by ST MICRO.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_WINBOND || drivers/spi || bool || ||
| |
| Select this option if your chipset driver needs to store certain
| |
| data in the SPI flash and your SPI flash is made by Winbond.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B || drivers/spi || bool || ||
| |
| Select this option if your SPI flash supports the fast read dual-
| |
| output command (opcode 0x3b) where the opcode and address are sent
| |
| to the chip on MOSI and data is received on both MOSI and MISO.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_FLASH_HAS_VOLATILE_GROUP || drivers/spi || bool || ||
| |
| Allows chipset to group write/erase operations under a single volatile
| |
| group.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CACHE_MRC_SETTINGS || drivers/mrc_cache || bool || ||
| |
| Save cached MRC settings
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MRC_WRITE_NV_LATE || drivers/mrc_cache || bool || ||
| |
| MRC settings are normally written to NVRAM at BS_DEV_ENUMERATE-EXIT.
| |
| If a platform requires MRC settings written to NVRAM later than
| |
| normal, select this item. This will cause the write to occur at
| |
| BS_OS_RESUME_CHECK-ENTRY.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DIGITIZER_AUTODETECT || drivers/lenovo || bool || Autodetect ||
| |
| The presence of digitizer is inferred from model number stored in
| |
| AT24RF chip.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DIGITIZER_PRESENT || drivers/lenovo || bool || Present ||
| |
| The digitizer is assumed to be present.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DIGITIZER_ABSENT || drivers/lenovo || bool || Absent ||
| |
| The digitizer is assumed to be absent.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | UART_OVERRIDE_INPUT_CLOCK_DIVIDER || drivers/uart || boolean || ||
| |
| Set to "y" when the platform overrides the uart_input_clock_divider
| |
| routine.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | UART_OVERRIDE_REFCLK || drivers/uart || boolean || ||
| |
| Set to "y" when the platform overrides the uart_platform_refclk
| |
| routine.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_UART_OXPCIE || drivers/uart || bool || Oxford OXPCIe952 ||
| |
| Support for Oxford OXPCIe952 serial port PCIe cards.
| |
| Currently only devices with the vendor ID 0x1415 and device ID
| |
| 0xc158 or 0xc11b will work.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | UART_USE_REFCLK_AS_INPUT_CLOCK || drivers/uart || bool || ||
| |
| Use uart_platform_refclk to specify the input clock value.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | UART_PCI_ADDR || drivers/uart || hex || UART's PCI bus, device, function address ||
| |
| Specify zero if the UART is connected to another bus type.
| |
| For PCI based UARTs, build the value as:
| |
| * 1 << 31 - Valid bit, PCI UART in use
| |
| * Bus << 20
| |
| * Device << 15
| |
| * Function << 12
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GIC || drivers/gic || None || ||
| |
| This option enables GIC support, the ARM generic interrupt controller.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | REALTEK_8168_RESET || drivers/net || bool || ||
| |
| This forces a realtek 10ec:8168 card to reset to ensure power state
| |
| is correct at boot.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | REALTEK_8168_MACADDRESS || drivers/net || string || Realtek rt8168 mac address ||
| |
| This is a string to set the mac address on a Realtek rt8168 card.
| |
| It must be in the form of "xx:xx:xx:xx:xx:xx", where x is a
| |
| hexadecimal number for it to be valid. Failing to do so will
| |
| result in the default macaddress being used.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RT8168_SET_LED_MODE || drivers/net || bool || ||
| |
| This is to set a customized LED mode to distinguish 10/100/1000
| |
| link and speed status with limited LEDs avaiable on a board.
| |
| Please refer to RTL811x datasheet section 7.2 Customizable LED
| |
| Configuration for details. With this flag enabled, the
| |
| customized_leds variable will be read from devicetree setting.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_PS2_KEYBOARD || drivers/pc80/pc || bool || PS/2 keyboard init ||
| |
| Enable this option to initialize PS/2 keyboards found connected
| |
| to the PS/2 port.
| |
| | |
| Some payloads (eg, filo) require this option. Other payloads
| |
| (eg, GRUB 2, SeaBIOS, Linux) do not require it.
| |
| Initializing a PS/2 keyboard can take several hundred milliseconds.
| |
| | |
| If you know you will only use a payload which does not require
| |
| this option, then you can say N here to speed up boot time.
| |
| Otherwise say Y.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA || drivers/pc80/vga || bool || ||
| |
| Include legacy VGA support code.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LPC_TPM || drivers/pc80/tpm || bool || Enable TPM support ||
| |
| Enable this option to enable LPC TPM support in coreboot.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TPM_TIS_BASE_ADDRESS || drivers/pc80/tpm || hex || ||
| |
| This can be used to adjust the TPM memory base address.
| |
| The default is specified by the TCG PC Client Specific TPM
| |
| Interface Specification 1.2 and should not be changed unless
| |
| the TPM being used does not conform to TPM TIS 1.2.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TPM_PIRQ || drivers/pc80/tpm || hex || ||
| |
| This can be used to specify a PIRQ to use instead of SERIRQ,
| |
| which is needed for SPI TPM interrupt support on x86.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TPM_INIT_FAILURE_IS_FATAL || drivers/pc80/tpm || bool || ||
| |
| What to do if TPM init failed. If true, force a hard reset,
| |
| otherwise just log error message to console.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SKIP_TPM_STARTUP_ON_NORMAL_BOOT || drivers/pc80/tpm || bool || ||
| |
| Skip TPM init on normal boot. Useful if payload does TPM init.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TPM_DEACTIVATE || drivers/pc80/tpm || bool || Deactivate TPM ||
| |
| Deactivate TPM by issuing deactivate command.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PLATFORM_USES_FSP1_1 || drivers/intel/fsp1_1 || bool || ||
| |
| Does the code require the Intel Firmware Support Package?
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Intel FSP 1.1 ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_FSP_BIN || drivers/intel/fsp1_1 || bool || Should the Intel FSP binary be added to the flash image ||
| |
| Select this option to add an Intel FSP binary to
| |
| the resulting coreboot image.
| |
| | |
| Note: Without this binary, coreboot builds relying on the FSP
| |
| will not boot
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_MICROCODE_CBFS_LEN || drivers/intel/fsp1_1 || hex || Microcode update region length in bytes ||
| |
| The length in bytes of the microcode update region.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CPU_MICROCODE_CBFS_LOC || drivers/intel/fsp1_1 || hex || Microcode update base address in CBFS ||
| |
| The location (base address) in CBFS that contains the microcode update
| |
| binary.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_FILE || drivers/intel/fsp1_1 || string || Intel FSP binary path and filename ||
| |
| The path and filename of the Intel FSP binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_LOC || drivers/intel/fsp1_1 || hex || Intel FSP Binary location in CBFS ||
| |
| The location in CBFS that the FSP is located. This must match the
| |
| value that is set in the FSP binary. If the FSP needs to be moved,
| |
| rebase the FSP with Intel's BCT (tool).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DISPLAY_UPD_DATA || drivers/intel/fsp1_1 || bool || Display UPD data ||
| |
| Display the user specified product data prior to memory
| |
| initialization.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_USES_UPD || drivers/intel/fsp1_1 || bool || ||
| |
| If this FSP uses UPD/VPD data regions, select this in the chipset
| |
| Kconfig.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_1 || bool || ||
| |
| The chipset can select this to use a generic cache_as_ram.inc file
| |
| that should be good for all FSP based platforms.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEL_DDI || drivers/intel/gma || bool || ||
| |
| helper functions for intel DDI operations
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEL_GMA_SSC_ALTERNATE_REF || drivers/intel/gma || bool || ||
| |
| Set when the SSC reference clock for LVDS runs at a different fre-
| |
| quency than the general display reference clock.
| |
| | |
| To be set by northbridge or mainboard Kconfig. For most platforms,
| |
| there is no choice, i.e. for i945 and gm45 the SSC reference always
| |
| differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz
| |
| DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's
| |
| the same frequency for SSC/non-SSC (120MHz). The only, currently
| |
| supported platform with a choice seems to be Pineview, where the
| |
| alternative is 100MHz vs. the default 96MHz.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEL_GMA_SWSMISCI || drivers/intel/gma || bool || ||
| |
| Select this option for Atom-based platforms which use the SWSMISCI
| |
| register (0xe0) rather than the SWSCI register (0xe8).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GFX_GMA_ANALOG_I2C_PORT || drivers/intel/gma || string || ||
| |
| Boards with a DVI-I connector share the I2C pins for both analog and
| |
| digital displays. In that case, the EDID for a VGA display has to be
| |
| read over the I2C interface of the coupled digital port.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_INTEL_MIPI_CAMERA || drivers/intel/mipi_camera || bool || ||
| |
| MIPI CSI I2C camera SSDT generator. Generates SSDB and PWDB
| |
| structures which are used by the Intel kernel drivers.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Intel FSP ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_FSP_BIN || drivers/intel/fsp1_0 || bool || Use Intel Firmware Support Package ||
| |
| Select this option to add an Intel FSP binary to
| |
| the resulting coreboot image.
| |
| | |
| Note: Without this binary, coreboot builds relying on the FSP
| |
| will not boot
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_FILE || drivers/intel/fsp1_0 || string || Intel FSP binary path and filename ||
| |
| The path and filename of the Intel FSP binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_LOC || drivers/intel/fsp1_0 || hex || Intel FSP Binary location in CBFS ||
| |
| The location in CBFS that the FSP is located. This must match the
| |
| value that is set in the FSP binary. If the FSP needs to be moved,
| |
| rebase the FSP with Intel's BCT (tool).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_FSP_FAST_BOOT || drivers/intel/fsp1_0 || bool || Enable Fast Boot ||
| |
| Enabling this feature will force the MRC data to be cached in NV
| |
| storage to be used for speeding up boot time on future reboots
| |
| and/or power cycles.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ENABLE_MRC_CACHE || drivers/intel/fsp1_0 || bool || ||
| |
| Enabling this feature will cause MRC data to be cached in NV storage.
| |
| This can either be used for fast boot, or just because the FSP wants
| |
| it to be saved.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MRC_CACHE_FMAP || drivers/intel/fsp1_0 || bool || Use MRC Cache in FMAP ||
| |
| Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
| |
| You must define a region in your FMAP named "RW_MRC_CACHE".
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MRC_CACHE_SIZE || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache Size ||
| |
| This is the amount of space in NV storage that is reserved for the
| |
| fast boot data cache storage.
| |
| | |
| WARNING: Because this area will be erased and re-written, the size
| |
| should be a full sector of the flash ROM chip and nothing else should
| |
| be included in CBFS in any sector that the fast boot cache data is in.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VIRTUAL_ROM_SIZE || drivers/intel/fsp1_0 || hex || Virtual ROM Size ||
| |
| This is used to calculate the offset of the MRC data cache in NV
| |
| Storage for fast boot. If in doubt, leave this set to the default
| |
| which sets the virtual size equal to the ROM size.
| |
| | |
| Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are
| |
| loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When
| |
| the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
| |
| size is 16 MB.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CACHE_ROM_SIZE_OVERRIDE || drivers/intel/fsp1_0 || hex || Cache ROM Size ||
| |
| This is the size of the cachable area that is passed into the FSP in
| |
| the early initialization. Typically this should be the size of the CBFS
| |
| area, but the size must be a power of 2 whereas the CBFS size does not
| |
| have this limitation.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_0 || bool || ||
| |
| The chipset can select this to use a generic cache_as_ram.inc file
| |
| that should be good for all FSP based platforms.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_USES_UPD || drivers/intel/fsp1_0 || bool || ||
| |
| If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_INTEL_WIFI || drivers/intel/wifi || bool || Support Intel PCI-e WiFi adapters ||
| |
| When enabled, add identifiers in ACPI and SMBIOS tables to
| |
| make OS drivers work with certain Intel PCI-e WiFi chipsets.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USE_SAR || drivers/intel/wifi || bool || ||
| |
| Enable it when wifi driver uses SAR configuration feature.
| |
| VPD entry "wifi_sar" is required to support it.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DSAR_SET_NUM || drivers/intel/wifi || hex || Number of SAR sets when D-SAR is enabled ||
| |
| There can be up to 3 optional SAR table sets.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PLATFORM_USES_FSP2_0 || drivers/intel/fsp2_0 || bool || ||
| |
| Include FSP 2.0 wrappers and functionality
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ADD_FSP_BINARIES || drivers/intel/fsp2_0 || bool || Add Intel FSP 2.0 binaries to CBFS ||
| |
| Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not
| |
| use the FSP-T binary and it is not added.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DISPLAY_FSP_CALLS_AND_STATUS || drivers/intel/fsp2_0 || bool || Display the FSP calls and status ||
| |
| Display the FSP call entry point and parameters prior to calling FSP
| |
| and display the status upon return from FSP.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DISPLAY_FSP_HEADER || drivers/intel/fsp2_0 || bool || Display the FSP header ||
| |
| Display the FSP header information when the FSP file is found.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DISPLAY_HOBS || drivers/intel/fsp2_0 || bool || Display the hand-off-blocks ||
| |
| Display the FSP HOBs which are provided for coreboot.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DISPLAY_UPD_DATA || drivers/intel/fsp2_0 || bool || Display UPD data ||
| |
| Display the user specified product data prior to memory
| |
| initialization.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_T_FILE || drivers/intel/fsp2_0 || string || Intel FSP-T (temp ram init) binary path and filename ||
| |
| The path and filename of the Intel FSP-M binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_M_FILE || drivers/intel/fsp2_0 || string || Intel FSP-M (memory init) binary path and filename ||
| |
| The path and filename of the Intel FSP-M binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_S_FILE || drivers/intel/fsp2_0 || string || Intel FSP-S (silicon init) binary path and filename ||
| |
| The path and filename of the Intel FSP-S binary for this platform.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_CAR || drivers/intel/fsp2_0 || bool || Use FSP TempRamInit & TempRamExit APIs ||
| |
| Use FSP APIs to initialize & Tear Down the Cache-As-Ram
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_M_XIP || drivers/intel/fsp2_0 || bool || Is FSP-M XIP ||
| |
| Select this value when FSP-M is execute-in-place.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VERIFY_HOBS || drivers/intel/fsp2_0 || bool || Verify the FSP hand-off-blocks ||
| |
| Verify that the HOBs required by coreboot are returned by FSP and
| |
| that the resource HOBs are in the correct order and position.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DISPLAY_FSP_VERSION_INFO || drivers/intel/fsp2_0 || bool || Display Firmware Ingredient Version Information ||
| |
| Select this option to display Firmware version information.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS || drivers/intel/fsp2_0 || bool || ||
| |
| This is selected by SoC or mainboard to supply their own
| |
| concept of a version for the memory settings respectively.
| |
| This allows deployed systems to bump their version number
| |
| with the same FSP which will trigger a retrain of the memory.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_SIL_3114 || drivers/sil/3114 || bool || Silicon Image SIL3114 ||
| |
| It sets PCI class to IDE compatible native mode, allowing
| |
| SeaBIOS, FILO etc... to boot from it.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVER_TI_TPS65090 || drivers/ti/tps65090 || bool || ||
| |
| TI TPS65090
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_EMULATION_QEMU_BOCHS || drivers/emulation/qemu || bool || bochs dispi interface vga driver ||
| |
| VGA driver for qemu emulated vga cards supporting
| |
| the bochs dispi interface. This includes
| |
| standard vga, vmware svga and qxl. The default
| |
| vga (cirrus) is *not* supported, so you have to
| |
| pick another one explicitly via 'qemu -vga $card'.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVER_XPOWERS_AXP209 || drivers/xpowers/axp209 || bool || ||
| |
| X-Powers AXP902 Power Management Unit
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVER_XPOWERS_AXP209_BOOTBLOCK || drivers/xpowers/axp209 || bool || ||
| |
| Make AXP209 functionality available in he bootblock.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVER_PARADE_PS8640 || drivers/parade/ps8640 || bool || ||
| |
| Parade PS8640 MIPI DSI to eDP Converter
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVER_PARADE_PS8625 || drivers/parade/ps8625 || bool || ||
| |
| Parade ps8625 display port to lvds bridge
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVER_MAXIM_MAX77686 || drivers/maxim/max77686 || bool || ||
| |
| Maxim MAX77686 power regulator
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_I2C_PCA9538 || drivers/i2c/pca9538 || bool || ||
| |
| Enable support for I2C I/O expander PCA9538.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_I2C_RX6110SA || drivers/i2c/rx6110sa || bool || ||
| |
| Enable support for external RTC chip RX6110 SA.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_I2C_DESIGNWARE || drivers/i2c/designware || bool || ||
| |
| Designware I2C support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ || drivers/i2c/designware || int || ||
| |
| The i2c ip block's clock.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_I2C_RTD2132 || drivers/i2c/rtd2132 || bool || ||
| |
| Enable support for Realtek RTD2132 DisplayPort to LVDS bridge chip.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | STORAGE_ERASE || commonlib/storage || bool || Support SD/MMC erase operations ||
| |
| Select to enable SD/MMC erase oprations
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | STORAGE_WRITE || commonlib/storage || bool || Support SD/MMC write operations ||
| |
| Select to enable SD/MMC write oprations
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SD_MMC_DEBUG || commonlib/storage || bool || Debug SD/MMC card/devices operations ||
| |
| Display overview of SD/MMC card/device operations
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SD_MMC_TRACE || commonlib/storage || bool || Trace SD/MMC card/device operations ||
| |
| Display details of SD/MMC card/device operations
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SDHC_DEBUG || commonlib/storage || bool || Debug SD/MMC controller settings ||
| |
| Display clock speed and bus width settings
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SDHC_TRACE || commonlib/storage || bool || Trace SD/MMC controller operations ||
| |
| Display the operations performed by the SD/MMC controller
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SDHCI_ADMA_IN_BOOTBLOCK || commonlib/storage || bool || ||
| |
| Determine if bootblock is able to use ADMA2 or ADMA64
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SDHCI_ADMA_IN_ROMSTAGE || commonlib/storage || bool || ||
| |
| Determine if romstage is able to use ADMA2 or ADMA64
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SDHCI_ADMA_IN_VERSTAGE || commonlib/storage || bool || ||
| |
| Determine if verstage is able to use ADMA2 or ADMA64
| |
| | |
| ||
| |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Security || || || ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Verified Boot (vboot) || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT || security/vboot || bool || Verify firmware with vboot. ||
| |
| Enabling VBOOT will use vboot to verify the components of the firmware
| |
| (stages, payload, etc).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_VBNV_CMOS || security/vboot || bool || ||
| |
| VBNV is stored in CMOS
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_VBNV_OFFSET || security/vboot || hex || ||
| |
| CMOS offset for VbNv data. This value must match cmos.layout
| |
| in the mainboard directory, minus 14 bytes for the RTC.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_VBNV_CMOS_BACKUP_TO_FLASH || security/vboot || bool || ||
| |
| Vboot non-volatile storage data will be backed up from CMOS to flash
| |
| and restored from flash if the CMOS is invalid due to power loss.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_VBNV_EC || security/vboot || bool || ||
| |
| VBNV is stored in EC
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_VBNV_FLASH || security/vboot || bool || ||
| |
| VBNV is stored in flash storage
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_STARTS_IN_BOOTBLOCK || security/vboot || bool || ||
| |
| Firmware verification happens during the end of or right after the
| |
| bootblock. This implies that a static VBOOT2_WORK() buffer must be
| |
| allocated in memlayout.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_STARTS_IN_ROMSTAGE || security/vboot || bool || ||
| |
| Firmware verification happens during the end of romstage (after
| |
| memory initialization). This implies that vboot working data is
| |
| allocated in CBMEM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_MOCK_SECDATA || security/vboot || bool || Mock secdata for firmware verification ||
| |
| Enabling VBOOT_MOCK_SECDATA will mock secdata for the firmware
| |
| verification to avoid access to a secdata storage (typically TPM).
| |
| All operations for a secdata storage will be successful. This option
| |
| can be used during development when a TPM is not present or broken.
| |
| THIS SHOULD NOT BE LEFT ON FOR PRODUCTION DEVICES.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_DISABLE_DEV_ON_RECOVERY || security/vboot || bool || ||
| |
| When this option is enabled, the Chrome OS device leaves the
| |
| developer mode as soon as recovery request is detected. This is
| |
| handy on embedded devices with limited input capabilities.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_SEPARATE_VERSTAGE || security/vboot || bool || ||
| |
| If this option is set, vboot verification runs in a standalone stage
| |
| that is loaded from the bootblock and exits into romstage. If it is
| |
| not set, the verification code is linked directly into the bootblock
| |
| or the romstage and runs as part of that stage (cf. related options
| |
| VBOOT_STARTS_IN_BOOTBLOCK/_ROMSTAGE and VBOOT_RETURN_FROM_VERSTAGE).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_RETURN_FROM_VERSTAGE || security/vboot || bool || ||
| |
| If this is set, the verstage returns back to the calling stage instead
| |
| of exiting to the succeeding stage so that the verstage space can be
| |
| reused by the succeeding stage. This is useful if a RAM space is too
| |
| small to fit both the verstage and the succeeding stage.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT || security/vboot || bool || ||
| |
| This option ensures that the recovery request is not lost because of
| |
| reboots caused after vboot verification is run. e.g. reboots caused by
| |
| FSP components on Intel platforms.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_OPROM_MATTERS || security/vboot || bool || ||
| |
| Set this option to indicate to vboot that this platform will skip its
| |
| display initialization on a normal (non-recovery, non-developer) boot.
| |
| Vboot calls this "oprom matters" because on x86 devices this
| |
| traditionally meant that the video option ROM will not be loaded, but
| |
| it works functionally the same for other platforms that can skip their
| |
| native display initialization code instead.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_HAS_REC_HASH_SPACE || security/vboot || bool || ||
| |
| Set this option to indicate to vboot that recovery data hash space
| |
| is present in TPM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_EC_SOFTWARE_SYNC || security/vboot || bool || Enable EC software sync ||
| |
| EC software sync is a mechanism where the AP helps the EC verify its
| |
| firmware similar to how vboot verifies the main system firmware. This
| |
| option selects whether vboot should support EC software sync.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_EC_SLOW_UPDATE || security/vboot || bool || ||
| |
| Whether the EC (or PD) is slow to update and needs to display a
| |
| screen that informs the user the update is happening.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_EC_EFS || security/vboot || bool || ||
| |
| CrosEC can support EFS: Early Firmware Selection. If it's enabled,
| |
| software sync need to also support it. This setting tells vboot to
| |
| perform EFS software sync.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_PHYSICAL_DEV_SWITCH || security/vboot || bool || ||
| |
| Whether this platform has a physical developer switch. Note that this
| |
| disables virtual dev switch functionality (through secdata). Operation
| |
| where both a physical pin and the virtual switch get sampled is not
| |
| supported by coreboot.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_PHYSICAL_REC_SWITCH || security/vboot || bool || ||
| |
| Whether this platform has a physical recovery switch.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_LID_SWITCH || security/vboot || bool || ||
| |
| Whether this platform has a lid switch. If it does, vboot will not
| |
| decrement try counters for boot failures if the lid is closed.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_WIPEOUT_SUPPORTED || security/vboot || bool || ||
| |
| When this option is enabled, the firmware provides the ability to
| |
| signal the application the need for factory reset (a.k.a. wipe
| |
| out) of the device
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_FWID_MODEL || security/vboot || string || Firmware ID model ||
| |
| This is the first part of the FWID written to various regions of a
| |
| vboot firmware image to identify its version.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_FWID_VERSION || security/vboot || string || Firmware ID version ||
| |
| This is the second part of the FWID written to various regions of a
| |
| vboot firmware image to identify its version.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VBOOT_NO_BOARD_SUPPORT || security/vboot || bool || Allow the use of vboot without board support ||
| |
| Enable weak functions for get_write_protect_state and
| |
| get_recovery_mode_switch in order to proceed with refactoring
| |
| of the vboot2 code base. Later on this code is removed and replaced
| |
| by interfaces.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RO_REGION_ONLY || security/vboot || string || Additional files that should not be copied to RW ||
| |
| Add a space delimited list of filenames that should only be in the
| |
| RO section.
| |
| | |
| ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: GBB configuration || || || ||
| |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Vboot Keys || || || ||
| |
| | |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Trusted Platform Module || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | TPM || security/tpm || bool || ||
| |
| Enable this option to enable TPM support in coreboot.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TPM2 || security/tpm || bool || ||
| |
| Enable this option to enable TPM2 support in coreboot.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_TPM || security/tpm || bool || Output verbose TPM debug messages ||
| |
| This option enables additional TPM related debug messages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POWER_OFF_ON_CR50_UPDATE || security/tpm || bool || ||
| |
| Power off machine while waiting for CR50 update to take effect.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_HAS_LPC_TPM || security/tpm || bool || ||
| |
| Board has TPM support
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_HAS_TPM2 || security/tpm || bool || ||
| |
| There is a TPM device installed on the mainboard, and it is
| |
| compliant with version 2 TCG TPM specification. Could be connected
| |
| over LPC, SPI or I2C.
| |
| | |
| ||
| |
| | |
| | |
| |- bgcolor="#eeeeee"
| |
| | ACPI_SATA_GENERATOR || acpi || bool || ||
| |
| Use ACPI SATA port generator.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ACPI_INTEL_HARDWARE_SLEEP_VALUES || acpi || bool || ||
| |
| Provide common definitions for Intel hardware PM1_CNT register sleep
| |
| values.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ACPI_AMD_HARDWARE_SLEEP_VALUES || acpi || bool || ||
| |
| Provide common definitions for AMD hardware PM1_CNT register sleep
| |
| values.
| |
| | |
| ||
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOT_DEVICE_MEMORY_MAPPED || toplevel || bool || ||
| |
| Inform system if SPI is memory-mapped or not.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOT_DEVICE_SUPPORTS_WRITES || toplevel || bool || ||
| |
| Indicate that the platform has writable boot device
| |
| support.
| |
| | |
| ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Console || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOTBLOCK_CONSOLE || console || bool || Enable early (bootblock) console output. ||
| |
| Use console during the bootblock if supported
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POSTCAR_CONSOLE || console || bool || Enable console output during postcar. ||
| |
| Use console during the postcar if supported
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SQUELCH_EARLY_SMP || console || bool || Squelch AP CPUs from early console. ||
| |
| When selected only the BSP CPU will output to early console.
| |
| | |
| Console drivers have unpredictable behaviour if multiple threads
| |
| attempt to share the same resources without a spinlock.
| |
| | |
| If unsure, say Y.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL || console || bool || Serial port console output ||
| |
| Send coreboot debug output to a serial port.
| |
| | |
| The type of serial port driver selected based on your configuration is
| |
| shown on the following menu line. Supporting multiple different types
| |
| of UARTs in one build is not supported.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || I/O mapped, 8250-compatible ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || memory mapped, 8250-compatible ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || device-specific UART ||
| |
| |- bgcolor="#eeeeee"
| |
| | UART_FOR_CONSOLE || console || int || Index for UART port to use for console ||
| |
| Select an I/O port to use for serial console:
| |
| 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TTYS0_BASE || console || hex || ||
| |
| Map the COM port number to the respective I/O port.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Serial port base address = 0x3f8 ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Serial port base address = 0x2f8 ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Serial port base address = 0x3e8 ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Serial port base address = 0x2e8 ||
| |
| |- bgcolor="#eeeeee"
| |
| | UART_OVERRIDE_BAUDRATE || console || boolean || ||
| |
| Set to "y" when the platform overrides the baudrate by providing
| |
| a get_uart_baudrate routine.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_921600 || console || bool || 921600 ||
| |
| Set serial port Baud rate to 921600.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_460800 || console || bool || 460800 ||
| |
| Set serial port Baud rate to 460800.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_230400 || console || bool || 230400 ||
| |
| Set serial port Baud rate to 230400.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_115200 || console || bool || 115200 ||
| |
| Set serial port Baud rate to 115200.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_57600 || console || bool || 57600 ||
| |
| Set serial port Baud rate to 57600.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_38400 || console || bool || 38400 ||
| |
| Set serial port Baud rate to 38400.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_19200 || console || bool || 19200 ||
| |
| Set serial port Baud rate to 19200.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_9600 || console || bool || 9600 ||
| |
| Set serial port Baud rate to 9600.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TTYS0_BAUD || console || int || ||
| |
| Map the Baud rates to an integer.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPKMODEM || console || bool || spkmodem (console on speaker) console output ||
| |
| Send coreboot debug output through speaker
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_USB || console || bool || USB dongle console output ||
| |
| Send coreboot debug output to USB.
| |
| | |
| Configuration for USB hardware is under menu Generic Drivers.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ONBOARD_VGA_IS_PRIMARY || console || bool || Use onboard VGA as primary video device ||
| |
| If not selected, the last adapter found will be used.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_NE2K || console || bool || Network console over NE2000 compatible Ethernet adapter ||
| |
| Send coreboot debug output to a Ethernet console, it works
| |
| same way as Linux netconsole, packets are received to UDP
| |
| port 6666 on IP/MAC specified with options bellow.
| |
| Use following netcat command: nc -u -l -p 6666
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_NE2K_DST_MAC || console || string || Destination MAC address of remote system ||
| |
| Type in either MAC address of logging system or MAC address
| |
| of the router.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||
| |
| This is IP address of the system running for example
| |
| netcat command to dump the packets.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_NE2K_SRC_IP || console || string || IP address of coreboot system ||
| |
| This is the IP of the coreboot system
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_NE2K_IO_PORT || console || hex || NE2000 adapter fixed IO port address ||
| |
| This is the IO port address for the IO port
| |
| on the card, please select some non-conflicting region,
| |
| 32 bytes of IO spaces will be used (and align on 32 bytes
| |
| boundary, qemu needs broader align)
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_CBMEM || console || bool || Send console output to a CBMEM buffer ||
| |
| Enable this to save the console output in a CBMEM buffer. This would
| |
| allow to see coreboot console output from Linux space.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_CBMEM_BUFFER_SIZE || console || hex || Room allocated for console output in CBMEM ||
| |
| Space allocated for console output storage in CBMEM. The default
| |
| value (128K or 0x20000 bytes) is large enough to accommodate
| |
| even the BIOS_SPEW level.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_CBMEM_DUMP_TO_UART || console || bool || Dump CBMEM console on resets ||
| |
| Enable this to have CBMEM console buffer contents dumped on the
| |
| serial output in case serial console is disabled and the device
| |
| resets itself while trying to boot the payload.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SPI_FLASH || console || bool || SPI Flash console output ||
| |
| Send coreboot debug output to the SPI Flash in the FMAP CONSOLE area
| |
| | |
| This option can cause premature wear on the SPI flash and should not
| |
| be used as a normal means of debugging. It is only to be enabled and
| |
| used when porting a new motherboard which has no other console
| |
| available (no UART, no POST, no cbmem access(non bootable)). Since
| |
| a non bootable machine will require the use of an external SPI Flash
| |
| programmer, the developer can grab the console log at the same time.
| |
| | |
| The flash console will not be erased on reboot, so once it is full,
| |
| the flashconsole driver will stop writing to it. This is to avoid
| |
| wear on the flash, and to avoid erasing sectors (which may freeze
| |
| the SPI controller on skylake).
| |
| | |
| The 'CONSOLE' area can be extracted from the FMAP with :
| |
| cbfstool rom.bin read -r CONSOLE -f console.log
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SPI_FLASH_BUFFER_SIZE || console || hex || Room allocated for console output in FMAP ||
| |
| Space allocated for console output storage in FMAP. The default
| |
| value (128K or 0x20000 bytes) is large enough to accommodate
| |
| even the BIOS_SPEW level.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_QEMU_DEBUGCON || console || bool || QEMU debug console output ||
| |
| Send coreboot debug output to QEMU's isa-debugcon device:
| |
| | |
| qemu-system-x86_64 \
| |
| -chardev file,id=debugcon,path=/dir/file.log \
| |
| -device isa-debugcon,iobase=0x402,chardev=debugcon
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SPI_CONSOLE || console || bool || SPI debug console output ||
| |
| Enable support for the debug console on the Dediprog EM100Pro.
| |
| This is currently working only in ramstage due to how the spi
| |
| drivers are written.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_OVERRIDE_LOGLEVEL || console || boolean || ||
| |
| Set to "y" when the platform overrides the loglevel by providing
| |
| a get_console_loglevel routine.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
| |
| Way too many details.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
| |
| Debug-level messages.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
| |
| Informational messages.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
| |
| Normal but significant conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
| |
| Warning conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
| |
| Error conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
| |
| Critical conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
| |
| Action must be taken immediately.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
| |
| System is unusable.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL || console || int || ||
| |
| Map the log level config names to an integer.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CMOS_POST || console || bool || Store post codes in CMOS for debugging ||
| |
| If enabled, coreboot will store post codes in CMOS and switch between
| |
| two offsets on each boot so the last post code in the previous boot
| |
| can be retrieved. This uses 3 bytes of CMOS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CMOS_POST_OFFSET || console || hex || Offset into CMOS to store POST codes ||
| |
| If CMOS_POST is enabled then an offset into CMOS must be provided.
| |
| If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
| |
| defined in the mainboard option table.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CMOS_POST_EXTRA || console || bool || Store extra logging info into CMOS ||
| |
| This will enable extra logging of work that happens between post
| |
| codes into CMOS for debug. This uses an additional 8 bytes of CMOS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_POST || console || bool || Show POST codes on the debug console ||
| |
| If enabled, coreboot will additionally print POST codes (which are
| |
| usually displayed using a so-called "POST card" ISA/PCI/PCI-E
| |
| device) on the debug console.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POST_IO || console || bool || Send POST codes to an IO port ||
| |
| If enabled, POST codes will be written to an IO port.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POST_IO_PORT || console || hex || IO port for POST codes ||
| |
| POST codes on x86 are typically written to the LPC bus on port
| |
| 0x80. However, it may be desirable to change the port number
| |
| depending on the presence of coprocessors/microcontrollers or if the
| |
| platform does not support IO in the conventional x86 manner.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_EARLY_BOOTBLOCK_POSTCODES || console || hex || ||
| |
| Some chipsets require that the routing for the port 80h POST
| |
| code be configured before any POST codes are sent out.
| |
| This can be done in the boot block, but there are a couple of
| |
| POST codes that go out before the chipset's bootblock initialization
| |
| can happen. This option suppresses those POST codes.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#eeeeee"
| |
| | ACPI_HUGE_LOWMEM_BACKUP || toplevel || bool || ||
| |
| On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RESUME_PATH_SAME_AS_BOOT || toplevel || bool || ||
| |
| This option indicates that when a system resumes it takes the
| |
| same path as a regular boot. e.g. an x86 system runs from the
| |
| reset vector at 0xfffffff0 on both resume and warm/cold boot.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_HARD_RESET || toplevel || bool || ||
| |
| This variable specifies whether a given board has a hard_reset
| |
| function, no matter if it's provided by board code or chipset code.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK || toplevel || bool || ||
| |
| This should be enabled on certain plaforms, such as the AMD
| |
| SR565x, that cannot handle concurrent CBFS accesses from
| |
| multiple APs during early startup.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_MONOTONIC_TIMER || toplevel || bool || ||
| |
| The board/chipset provides a monotonic timer.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GENERIC_UDELAY || toplevel || bool || ||
| |
| The board/chipset uses a generic udelay function utilizing the
| |
| monotonic timer.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TIMER_QUEUE || toplevel || bool || ||
| |
| Provide a timer queue for performing time-based callbacks.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COOP_MULTITASKING || toplevel || bool || ||
| |
| Cooperative multitasking allows callbacks to be multiplexed on the
| |
| main thread of ramstage. With this enabled it allows for multiple
| |
| execution paths to take place when they have udelay() calls within
| |
| their code.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NUM_THREADS || toplevel || int || ||
| |
| How many execution threads to cooperatively multitask with.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_OPTION_TABLE || toplevel || bool || ||
| |
| This variable specifies whether a given board has a cmos.layout
| |
| file containing NVRAM/CMOS bit definitions.
| |
| It defaults to 'n' but can be selected in mainboard/*/Kconfig.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GFXUMA || toplevel || bool || ||
| |
| Enable Unified Memory Architecture for graphics.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_ACPI_TABLES || toplevel || bool || ||
| |
| This variable specifies whether a given board has ACPI table support.
| |
| It is usually set in mainboard/*/Kconfig.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_MP_TABLE || toplevel || bool || ||
| |
| This variable specifies whether a given board has MP table support.
| |
| It is usually set in mainboard/*/Kconfig.
| |
| Whether or not the MP table is actually generated by coreboot
| |
| is configurable by the user via GENERATE_MP_TABLE.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_PIRQ_TABLE || toplevel || bool || ||
| |
| This variable specifies whether a given board has PIRQ table support.
| |
| It is usually set in mainboard/*/Kconfig.
| |
| Whether or not the PIRQ table is actually generated by coreboot
| |
| is configurable by the user via GENERATE_PIRQ_TABLE.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAX_PIRQ_LINKS || toplevel || int || ||
| |
| This variable specifies the number of PIRQ interrupt links which are
| |
| routable. On most chipsets, this is 4, INTA through INTD. Some
| |
| chipsets offer more than four links, commonly up to INTH. They may
| |
| also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
| |
| table specifies links greater than 4, pirq_route_irqs will not
| |
| function properly, unless this variable is correctly set.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ACPI_NHLT || toplevel || bool || ||
| |
| Build support for NHLT (non HD Audio) ACPI table generation.
| |
| | |
| ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: System tables || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||
| |
| Generate an MP table (conforming to the Intel MultiProcessor
| |
| specification 1.4) for this board.
| |
| | |
| If unsure, say Y.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||
| |
| Generate a PIRQ table for this board.
| |
| | |
| If unsure, say Y.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GENERATE_SMBIOS_TABLES || toplevel || bool || Generate SMBIOS tables ||
| |
| Generate SMBIOS tables for this board.
| |
| | |
| If unsure, say Y.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_SERIAL_NUMBER || toplevel || string || SMBIOS Serial Number ||
| |
| The Serial Number to store in SMBIOS structures.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_VERSION || toplevel || string || SMBIOS Version Number ||
| |
| The Version Number to store in SMBIOS structures.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_SMBIOS_MANUFACTURER || toplevel || string || SMBIOS Manufacturer ||
| |
| Override the default Manufacturer stored in SMBIOS structures.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAINBOARD_SMBIOS_PRODUCT_NAME || toplevel || string || SMBIOS Product name ||
| |
| Override the default Product name stored in SMBIOS structures.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SMBIOS_ENCLOSURE_TYPE || toplevel || hex || ||
| |
| System Enclosure or Chassis Types as defined in SMBIOS specification.
| |
| The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) or
| |
| SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Payload || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_NONE || payloads || bool || None ||
| |
| Select this option if you want to create an "empty" coreboot
| |
| ROM image for a certain mainboard, i.e. a coreboot ROM image
| |
| which does not yet contain a payload.
| |
| | |
| For such an image to be useful, you have to use 'cbfstool'
| |
| to add a payload to the ROM image later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_ELF || payloads || bool || An ELF executable payload ||
| |
| Select this option if you have a payload image (an ELF file)
| |
| which coreboot should run as soon as the basic hardware
| |
| initialization is completed.
| |
| | |
| You will be able to specify the location and file name of the
| |
| payload image later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_BAYOU || payloads || bool || Bayou ||
| |
| Select this option if you want to set bayou as your primary
| |
| payload.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_UBOOT || payloads/external/U-Boot.name || bool || U-Boot (Experimental) ||
| |
| Select this option if you want to build a coreboot image
| |
| with a U-Boot payload.
| |
| | |
| See https://coreboot.org/Payloads and U-Boot's documentation
| |
| at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
| |
| for more information.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_SEABIOS || payloads/external/SeaBIOS.name || bool || SeaBIOS ||
| |
| Select this option if you want to build a coreboot image
| |
| with a SeaBIOS payload. If you don't know what this is
| |
| about, just leave it enabled.
| |
| | |
| See https://coreboot.org/Payloads for more information.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_FILO || payloads/external/FILO.name || bool || FILO ||
| |
| Select this option if you want to build a coreboot image
| |
| with a FILO payload. If you don't know what this is
| |
| about, just leave it enabled.
| |
| | |
| See https://coreboot.org/Payloads for more information.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_LINUX || payloads/external/linux.name || bool || A Linux payload ||
| |
| Select this option if you have a Linux bzImage which coreboot
| |
| should run as soon as the basic hardware initialization
| |
| is completed.
| |
| | |
| You will be able to specify the location and file name of the
| |
| payload image later.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_TIANOCORE || payloads/external/tianocore.name || bool || Tianocore coreboot payload package ||
| |
| Select this option if you want to build a coreboot image
| |
| with a Tianocore payload. If you don't know what this is
| |
| about, just leave it enabled.
| |
| | |
| See https://coreboot.org/Payloads for more information.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_GRUB2 || payloads/external/GRUB2.name || bool || GRUB2 ||
| |
| Select this option if you want to build a coreboot image
| |
| with a GRUB2 payload. If you don't know what this is
| |
| about, just leave it enabled.
| |
| | |
| See https://coreboot.org/Payloads for more information.
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_DEPTHCHARGE || payloads/external/depthcharge.name || bool || Depthcharge ||
| |
| Select this option if you want to build a coreboot image
| |
| with a depthcharge payload.
| |
| | |
| See https://coreboot.org/Payloads for more information.
| |
| | |
| ||
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | UBOOT_STABLE || payloads/external/U-Boot || bool || v2016.1 ||
| |
| Stable U-Boot version
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | UBOOT_MASTER || payloads/external/U-Boot || bool || master ||
| |
| Newest U-Boot version
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_CONFIGFILE || payloads/external/U-Boot || string || U-Boot config file ||
| |
| This option allows a platform to set Kconfig options for a basic
| |
| U-Boot payload. In general, if the option is used, the default
| |
| would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_uboot"
| |
| for a config stored in the coreboot mainboard directory, or
| |
| "$(project_dir)/configs/coreboot-x86_defconfig" to use a config
| |
| from the U-Boot config directory
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEABIOS_STABLE || payloads/external/SeaBIOS || bool || 1.11.1 ||
| |
| Stable SeaBIOS version
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEABIOS_MASTER || payloads/external/SeaBIOS || bool || master ||
| |
| Newest SeaBIOS version
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEABIOS_REVISION || payloads/external/SeaBIOS || bool || git revision ||
| |
| Select this option if you have a specific commit or branch
| |
| that you want to use as the revision from which to
| |
| build SeaBIOS.
| |
| | |
| You will be able to specify the name of a branch or a commit id
| |
| later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEABIOS_REVISION_ID || payloads/external/SeaBIOS || string || Insert a commit's SHA-1 or a branch name ||
| |
| The commit's SHA-1 or branch name of the revision to use.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEABIOS_PS2_TIMEOUT || payloads/external/SeaBIOS || int || PS/2 keyboard controller initialization timeout (milliseconds) ||
| |
| Some PS/2 keyboard controllers don't respond to commands immediately
| |
| after powering on. This specifies how long SeaBIOS will wait for the
| |
| keyboard controller to become ready before giving up.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEABIOS_THREAD_OPTIONROMS || payloads/external/SeaBIOS || bool || Hardware init during option ROM execution ||
| |
| Allow hardware init to run in parallel with optionrom execution.
| |
| | |
| This can reduce boot time, but can cause some timing
| |
| variations during option ROM code execution. It is not
| |
| known if all option ROMs will behave properly with this option.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEABIOS_VGA_COREBOOT || payloads/external/SeaBIOS || bool || Include generated option rom that implements legacy VGA BIOS compatibility ||
| |
| coreboot can initialize the GPU of some mainboards.
| |
| | |
| After initializing the GPU, the information about it can be passed to the payload.
| |
| Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_CONFIGFILE || payloads/external/SeaBIOS || string || SeaBIOS config file ||
| |
| This option allows a platform to set Kconfig options for a basic
| |
| SeaBIOS payload. In general, if the option is used, the default
| |
| would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEABIOS_BOOTORDER_FILE || payloads/external/SeaBIOS || string || SeaBIOS bootorder file ||
| |
| Add a SeaBIOS bootorder file. From the wiki:
| |
| "The bootorder file may be used to configure the boot up order. The file
| |
| should be ASCII text and contain one line per boot method. The description
| |
| of each boot method follows an Open Firmware device path format. SeaBIOS
| |
| will attempt to boot from each item in the file - first line of the file
| |
| first."
| |
| | |
| See: https://www.coreboot.org/SeaBIOS#Configuring_boot_order
| |
| | |
| If used, a typical value would be:
| |
| $(top)/src/mainboard/$(MAINBOARDDIR)/bootorder
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEABIOS_DEBUG_LEVEL || payloads/external/SeaBIOS || int || SeaBIOS debug level (verbosity) ||
| |
| The higher the number, the more verbose SeaBIOS will be. See the table
| |
| below for the current values corresponding to various items as of SeaBIOS
| |
| version 1.10.1. Set this value to -1 to use SeaBIOS' default.
| |
| | |
| Output at various SeaBIOS log levels:
| |
| level 0 - Logging disabled
| |
| level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM
| |
| level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h
| |
| level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts
| |
| level 4 - bios tables, more optionrom
| |
| level 5 - Extra bootsplash, more XHCI
| |
| level 6 - ATA commands, extra optionrom
| |
| level 7 - extra ps2 commands, more OHCI & EHCI
| |
| level 8 - extra malloc info, more AHCI
| |
| level 9 - interrupts 15h, 16h, 1ah, APM, PCI, SMIs, PCIBIOS,
| |
| USB-HID commands, SDcard commands, Floppy commands
| |
| level 10 - interrupt 13h (Drives other than floppy)
| |
| level 20 - interrupt 10h (Display)
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || Using default SeaBIOS log level ||
| |
| |- bgcolor="#eeeeee"
| |
| | || || (comment) || || SeaBIOS logging disabled ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: PXE Options || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | PXE_ROM || payloads/external/iPXE || bool || Add an existing PXE ROM image ||
| |
| Select this option if you have a PXE ROM image that you would
| |
| like to add to your ROM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BUILD_IPXE || payloads/external/iPXE || bool || Build and add an iPXE ROM ||
| |
| Select this option to fetch and build a ROM from the iPXE project.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IPXE_STABLE || payloads/external/iPXE || bool || 2017.3 ||
| |
| iPXE uses a rolling release with no stable version, for
| |
| reproducibility, use the last commit of a given month as the
| |
| 'stable' version.
| |
| This is iPXE from the end of March, 2017.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | IPXE_MASTER || payloads/external/iPXE || bool || master ||
| |
| Newest iPXE version.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PXE_ROM_FILE || payloads/external/iPXE || string || PXE ROM filename ||
| |
| The path and filename of the file to use as PXE ROM.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PXE_ROM_ID || payloads/external/iPXE || string || network card PCI IDs ||
| |
| The comma-separated PCI vendor and device ID that would associate
| |
| your PXE ROM to your network card.
| |
| | |
| Example: 10ec,8168
| |
| | |
| In the above example 10ec is the PCI vendor ID (in hex, but without
| |
| the "0x" prefix) and 8168 specifies the PCI device ID of the
| |
| network card (also in hex, without "0x" prefix).
| |
| | |
| Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#eeeeee"
| |
| | FILO_STABLE || payloads/external/FILO || bool || 0.6.0 ||
| |
| Stable FILO version
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FILO_MASTER || payloads/external/FILO || bool || HEAD ||
| |
| Newest FILO version
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_FILE || payloads/external/linux || string || Linux path and filename ||
| |
| The path and filename of the bzImage kernel to use as payload.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LINUX_COMMAND_LINE || payloads/external/linux || string || Linux command line ||
| |
| A command line to add to the Linux kernel.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LINUX_INITRD || payloads/external/linux || string || Linux initrd ||
| |
| An initrd image to add to the Linux kernel.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_FILE || payloads/external/tianocore || string || Tianocore binary ||
| |
| The result of a corebootPkg build
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_FILE || payloads/external/tianocore || string || Tianocore version ||
| |
| Select which version of Tianocore to build (default is to build stable)
| |
| stable: a version of Tianocore that builds without any errors
| |
| master: most recent version from upstream Tianocore repository
| |
| revision: use specific commit or branch to build Tianocore (specified by user)
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TIANOCORE_STABLE || payloads/external/tianocore || bool || stable ||
| |
| Select this option to build the stable tianocore version
| |
| i.e. a version of Tianocore that builds without any errors
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TIANOCORE_MASTER || payloads/external/tianocore || bool || master ||
| |
| Select this option to build the master tianocore version
| |
| i.e. most recent version from upstream Tianocore repository
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TIANOCORE_REVISION || payloads/external/tianocore || bool || git revision ||
| |
| Select this option if you have a specific commit or branch
| |
| that you want to use as the revision from which to
| |
| build Tianocore.
| |
| | |
| You will be able to specify the name of a branch or a commit id
| |
| later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TIANOCORE_REVISION_ID || payloads/external/tianocore || string || Insert a commit's SHA-1 or a branch name ||
| |
| The commit's SHA-1 or branch name of the revision to use.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TIANOCORE_REVISION_ID || payloads/external/tianocore || string || Target architecture ||
| |
| The Tianocore coreboot Payload Package binary can be
| |
| built for either only IA32 or both X64 and IA32 architectures.
| |
| Select which architecture(s) to build for; default is to build
| |
| for both X64 and IA32.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TIANOCORE_TARGET_IA32 || payloads/external/tianocore || bool || IA32 ||
| |
| By selecting this option, the target architecture will be built
| |
| for only IA32.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TIANOCORE_TARGET_X64 || payloads/external/tianocore || bool || X64 ||
| |
| By selecting this option, the target architecture will be built
| |
| for X64 and IA32.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TIANOCORE_TARGET_X64 || payloads/external/tianocore || bool || Tianocore build ||
| |
| Select whether to generate a debug or release build for
| |
| Tianocore; default is to generate a release build.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TIANOCORE_DEBUG || payloads/external/tianocore || bool || Generate Tianocore debug build ||
| |
| Generate a debug build.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TIANOCORE_RELEASE || payloads/external/tianocore || bool || Generate Tianocore release build ||
| |
| Generate a release build.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GRUB2_STABLE || payloads/external/GRUB2 || bool || 2.02 ||
| |
| Stable GRUB2 version
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GRUB2_MASTER || payloads/external/GRUB2 || bool || HEAD ||
| |
| Newest GRUB2 version
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GRUB2_REVISION || payloads/external/GRUB2 || bool || git revision ||
| |
| Select this option if you have a specific commit or branch
| |
| that you want to use as the revision from which to
| |
| build GRUB2.
| |
| | |
| You will be able to specify the name of a branch or a commit id
| |
| later.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GRUB2_REVISION_ID || payloads/external/GRUB2 || string || Insert a commit's SHA-1 or a branch name ||
| |
| The commit's SHA-1 or branch name of the revision to use.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GRUB2_EXTRA_MODULES || payloads/external/GRUB2 || string || Extra modules to include in GRUB image ||
| |
| Space-separated list of additional modules to include. Few common
| |
| ones:
| |
| * bsd for *BSD
| |
| * png/jpg for PNG/JPG images
| |
| * gfxmenu for graphical menus (you'll need a theme as well)
| |
| * gfxterm_background for setting background
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GRUB2_INCLUDE_RUNTIME_CONFIG_FILE || payloads/external/GRUB2 || bool || Include GRUB2 runtime config file into ROM image ||
| |
| The GRUB2 payload reads its runtime configuration file from etc/grub.cfg
| |
| stored in the CBFS on the flash ROM chip. Without that, it’ll just drop
| |
| into a rescue shell.
| |
| | |
| This configuration may need to be coreboot specific.
| |
| | |
| Select this option, if you want to include the GRUB2 runtime
| |
| configuration file into CBFS as `etc/grub.cfg` automatically.
| |
| | |
| You will be able to specify the path of the configuration file later.
| |
| | |
| Without this option you would need to add this file manually with
| |
| build/cbfstool build/coreboot.rom add -f grub.cfg -n etc/grub.cfg -t raw
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GRUB2_RUNTIME_CONFIG_FILE || payloads/external/GRUB2 || string || Path of grub.cfg ||
| |
| The path of the GRUB2 runtime configuration file to be added to CBFS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEPTHCHARGE_STABLE || payloads/external/depthcharge || bool || stable ||
| |
| Latest stable version.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEPTHCHARGE_MASTER || payloads/external/depthcharge || bool || master ||
| |
| Newest Depthcharge version.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEPTHCHARGE_REVISION || payloads/external/depthcharge || bool || git revision ||
| |
| Select this option if you have a specific commit or branch that
| |
| you want to use as the revision from which to build Depthcharge.
| |
| | |
| You will be able to specify the name of a branch or a commit SHA
| |
| later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEPTHCHARGE_REVISION_ID || payloads/external/depthcharge || string || Insert a commit's SHA-1 or a branch name ||
| |
| The commit's SHA-1 or branch name of the revision to use.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | LP_DEFCONFIG_OVERRIDE || payloads/external/depthcharge || bool || Use default libpayload config ||
| |
| The Depthcharge makefile looks for a file config.<boardname> in the
| |
| libpayload/configs directory. Say Y here to use the file defconfig
| |
| instead. This is can be a convenience for development purposes, or
| |
| if the defaults in defconfig are sufficient for your system.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_FILE || payloads || string || Payload path and filename ||
| |
| The path and filename of the ELF executable file to use as payload.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_FILE || payloads || string || Payload compression algorithm ||
| |
| Choose the compression algorithm for the chosen payloads.
| |
| You can choose between LZMA and LZ4.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COMPRESSED_PAYLOAD_LZMA || payloads || bool || Use LZMA compression for payloads ||
| |
| In order to reduce the size payloads take up in the ROM chip
| |
| coreboot can compress them using the LZMA algorithm.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COMPRESSED_PAYLOAD_LZ4 || payloads || bool || Use LZ4 compression for payloads ||
| |
| In order to reduce the size payloads take up in the ROM chip
| |
| coreboot can compress them using the LZ4 algorithm.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_OPTIONS || payloads || string || ||
| |
| Additional cbfstool options for the payload
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_IS_FLAT_BINARY || payloads || string || ||
| |
| Add the payload to cbfs as a flat binary type instead of as an
| |
| elf payload
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COMPRESS_SECONDARY_PAYLOAD || payloads || bool || Use LZMA compression for secondary payloads ||
| |
| In order to reduce the size secondary payloads take up in the
| |
| ROM chip they can be compressed using the LZMA algorithm.
| |
| | |
| ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Secondary Payloads || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREINFO_SECONDARY_PAYLOAD || payloads || bool || Load coreinfo as a secondary payload ||
| |
| coreinfo can be loaded as a secondary payload under SeaBIOS, GRUB,
| |
| or any other payload that can load additional payloads.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MEMTEST_SECONDARY_PAYLOAD || payloads || bool || Load Memtest86+ as a secondary payload ||
| |
| Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB,
| |
| or any other payload that can load additional payloads.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MEMTEST_STABLE || payloads || bool || Stable ||
| |
| Stable Memtest86+ version.
| |
| | |
| For reproducible builds, this option must be selected.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MEMTEST_MASTER || payloads || bool || Master ||
| |
| Newest Memtest86+ version.
| |
| | |
| This option will fetch the newest version of the Memtest86+ code,
| |
| updating as new changes are committed. This makes the build
| |
| non-reproducible, as it can fetch different code each time.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NVRAMCUI_SECONDARY_PAYLOAD || payloads || bool || Load nvramcui as a secondary payload ||
| |
| nvramcui can be loaded as a secondary payload under SeaBIOS, GRUB,
| |
| or any other payload that can load additional payloads.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TINT_SECONDARY_PAYLOAD || payloads || bool || Load tint as a secondary payload ||
| |
| tint can be loaded as a secondary payload under SeaBIOS, GRUB,
| |
| or any other payload that can load additional payloads.
| |
| | |
| ||
| |
| | |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Debugging || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | GDB_STUB || toplevel || bool || GDB debugging support ||
| |
| If enabled, you will be able to set breakpoints for gdb debugging.
| |
| See src/arch/x86/lib/c_start.S for details.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GDB_WAIT || toplevel || bool || Wait for a GDB connection in the ramstage ||
| |
| If enabled, coreboot will wait for a GDB connection in the ramstage.
| |
| | |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FATAL_ASSERTS || toplevel || bool || Halt when hitting a BUG() or assertion error ||
| |
| If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_CBFS || toplevel || bool || Output verbose CBFS debug messages ||
| |
| This option enables additional CBFS related debug messages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages ||
| |
| This option enables additional RAM init related debug messages.
| |
| It is recommended to enable this when debugging issues on your
| |
| board which might be RAM init related.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_CAR || toplevel || bool || Output verbose Cache-as-RAM debug messages ||
| |
| This option enables additional CAR related debug messages.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_PIRQ || toplevel || bool || Check PIRQ table consistency ||
| |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages ||
| |
| This option enables additional SMBus (and SPD) debug messages.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages ||
| |
| This option enables additional SMI related debug messages.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_SMM_RELOCATION || toplevel || bool || Debug SMM relocation code ||
| |
| This option enables additional SMM handler relocation related
| |
| debug messages.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_MALLOC || toplevel || bool || Output verbose malloc debug messages ||
| |
| This option enables additional malloc related debug messages.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_ACPI || toplevel || bool || Output verbose ACPI debug messages ||
| |
| This option enables additional ACPI related debug messages.
| |
| | |
| Note: This option will slightly increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | REALMODE_DEBUG || toplevel || bool || Enable debug messages for option ROM execution ||
| |
| This option enables additional x86emu related debug messages.
| |
| | |
| Note: This option will increase the time to emulate a ROM.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages ||
| |
| This option enables additional x86emu related debug messages.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF ||
| |
| Print information about JMP and RETF opcodes from x86emu.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes ||
| |
| Print _all_ opcodes that are executed by x86emu.
| |
| | |
| WARNING: This will produce a LOT of output and take a long time.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&Play accesses ||
| |
| Print Plug And Play accesses made by option ROMs.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O ||
| |
| Print Disk I/O related messages.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_PMM || toplevel || bool || Log PMM ||
| |
| Print messages related to POST Memory Manager (PMM).
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions ||
| |
| Print messages related to VESA BIOS Extension (VBE) functions.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console ||
| |
| Let INT10 (i.e. character output) calls print messages to debug output.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls ||
| |
| Print messages related to interrupt handling.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses ||
| |
| Print messages related to accesses to certain areas of the virtual
| |
| memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses ||
| |
| Print memory accesses made by option ROM.
| |
| Note: This also includes accesses to fetch instructions.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses ||
| |
| Print I/O accesses made by option ROM.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | X86EMU_DEBUG_TIMINGS || toplevel || bool || Output timing information ||
| |
| Print timing information needed by i915tool.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_SPI_FLASH || toplevel || bool || Output verbose SPI flash debug messages ||
| |
| This option enables additional SPI flash related debug messages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_USBDEBUG || toplevel || bool || Output verbose USB 2.0 EHCI debug dongle messages ||
| |
| This option enables additional USB 2.0 debug dongle related messages.
| |
| | |
| Select this to debug the connection of usbdebug dongle. Note that
| |
| you need some other working console to receive the messages.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_INTEL_ME || toplevel || bool || Verbose logging for Intel Management Engine ||
| |
| Enable verbose logging for Intel Management Engine driver that
| |
| is present on Intel 6-series chipsets.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TRACE || toplevel || bool || Trace function calls ||
| |
| If enabled, every function will print information to console once
| |
| the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
| |
| the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
| |
| of calling function. Please note some printk related functions
| |
| are omitted from trace to have good looking console dumps.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_COVERAGE || toplevel || bool || Debug code coverage ||
| |
| If enabled, the code coverage hooks in coreboot will output some
| |
| information about the coverage data that is dumped.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_BOOT_STATE || toplevel || bool || Debug boot state machine ||
| |
| Control debugging of the boot state machine. When selected displays
| |
| the state boundaries in ramstage.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_ADA_CODE || toplevel || bool || Compile debug code in Ada sources ||
| |
| Add the compiler switch `-gnata` to compile code guarded by
| |
| `pragma Debug`.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#eeeeee"
| |
| | NO_EDID_FILL_FB || lib || bool || ||
| |
| Don't include default fill_lb_framebuffer() implementation. Select
| |
| this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides
| |
| its own fill_lb_framebuffer() implementation.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RAMSTAGE_ADA || lib || bool || ||
| |
| Selected by features that use Ada code in ramstage.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RAMSTAGE_LIBHWBASE || lib || bool || ||
| |
| Selected by features that require `libhwbase` in ramstage.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POWER_BUTTON_DEFAULT_ENABLE || toplevel || bool || ||
| |
| Select when the board has a power button which can optionally be
| |
| disabled by the user.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POWER_BUTTON_DEFAULT_DISABLE || toplevel || bool || ||
| |
| Select when the board has a power button which can optionally be
| |
| enabled by the user, e.g. when the board ships with a jumper over
| |
| the power switch contacts.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POWER_BUTTON_FORCE_ENABLE || toplevel || bool || ||
| |
| Select when the board requires that the power button is always
| |
| enabled.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POWER_BUTTON_FORCE_DISABLE || toplevel || bool || ||
| |
| Select when the board requires that the power button is always
| |
| disabled, e.g. when it has been hardwired to ground.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | POWER_BUTTON_IS_OPTIONAL || toplevel || bool || ||
| |
| Internal option that controls ENABLE_POWER_BUTTON visibility.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | REG_SCRIPT || toplevel || bool || ||
| |
| Internal option that controls whether we compile in register scripts.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAX_REBOOT_CNT || toplevel || int || ||
| |
| Internal option that sets the maximum number of bootblock executions allowed
| |
| with the normal image enabled before assuming the normal image is defective
| |
| and switching to the fallback image.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CREATE_BOARD_CHECKLIST || toplevel || bool || ||
| |
| When selected, creates a webpage showing the implementation status for
| |
| the board. Routines highlighted in green are complete, yellow are
| |
| optional and red are required and must be implemented. A table is
| |
| produced for each stage of the boot process except the bootblock. The
| |
| red items may be used as an implementation checklist for the board.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAKE_CHECKLIST_PUBLIC || toplevel || bool || ||
| |
| When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
| |
| is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
| |
| directory.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CHECKLIST_DATA_FILE_LOCATION || toplevel || string || ||
| |
| Location of the <stage>_complete.dat and <stage>_optional.dat files
| |
| that are consumed during checklist processing. <stage>_complete.dat
| |
| contains the symbols that are expected to be in the resulting image.
| |
| <stage>_optional.dat is a subset of <stage>_complete.dat and contains
| |
| a list of weak symbols which the resulting image may consume. Other
| |
| symbols contained only in <stage>_complete.dat will be flagged as
| |
| required and not implemented if a weak implementation is found in the
| |
| resulting image.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_XIP_EARLY_STAGES || toplevel || bool || ||
| |
| Identify if early stages are eXecute-In-Place(XIP).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | EARLY_CBMEM_LIST || toplevel || bool || ||
| |
| Enable display of CBMEM during romstage and postcar.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | RELOCATABLE_MODULES || toplevel || bool || ||
| |
| If RELOCATABLE_MODULES is selected then support is enabled for
| |
| building relocatable modules in the RAM stage. Those modules can be
| |
| loaded anywhere and all the relocations are handled automatically.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | NO_STAGE_CACHE || toplevel || bool || ||
| |
| Do not save any component in stage cache for resume path. On resume,
| |
| all components would be read back from CBFS again.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GENERIC_GPIO_LIB || toplevel || bool || ||
| |
| If enabled, compile the generic GPIO library. A "generic" GPIO
| |
| implies configurability usually found on SoCs, particularly the
| |
| ability to control internal pull resistors.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GENERIC_SPD_BIN || toplevel || bool || ||
| |
| If enabled, add support for adding spd.hex files in cbfs as spd.bin
| |
| and locating it runtime to load SPD. Additionally provide provision to
| |
| fetch SPD over SMBus.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DIMM_MAX || toplevel || int || ||
| |
| Total number of memory DIMM slots available on motherboard.
| |
| It is multiplication of number of channel to number of DIMMs per
| |
| channel
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DIMM_SPD_SIZE || toplevel || int || ||
| |
| Total SPD size that will be used for DIMM.
| |
| Ex: DDR3 256, DDR4 512.
| |
| | |
| ||
| |
| |}
| |