Intel Native Raminit
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Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
Status page for all Intel based CPUs and MCHs
Native raminit is to replace the Intel provided closed source binary, that does initialize the memory. This binary is referenced as MRC (Memory Reference Code). Some platforms do support either MRC or native raminit, others only support one of them. In general one can summarize that DDR3 or DDR4 raminit is much more complex that DDR2 raminit, make it more difficult to provide open source and bug free raminit code.
GM45
Status
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Native raminit | yes | yes | yes | |
| MRC raminit | ? |
Native raminit features
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Menu: Supported channels | ||||
| single and dual channel | yes | yes | yes | |
| Up to 4 slots | yes | yes | yes | |
| Up to 4 ranks per channel | yes | yes | yes | |
| Menu: Supported frequencies | ||||
| DDR3-666 (333MHz) | yes | yes | yes | |
| DDR3-800 (400MHz) | yes | yes | yes | |
| DDR3-1066 (533Mhz) | yes | yes | yes | |
| DDR2-800 (400MHz) | yes | no | no | |
| DDR2-666 (333MHz) | yes | no | no | |
| Menu: Supported CAS latencies | ||||
| CL6 | yes | yes | ? | |
| CL7 | yes | yes | ? | |
| CL8 | yes | yes | ? | |
| CL9 | yes | yes | ? | |
| CL10 | yes | yes | ? | |
| CL11 | yes | yes | ? | |
| CL12 | yes | no | ||
| CL13 | yes | no | ||
| CL14 | yes | no | ||
| CL15 | yes | no | ||
| CL16 | yes | no | ||
| Menu: Boot paths | ||||
| Hot reset | yes | yes | yes | |
| Resume from S3 | yes | yes | yes | |
| Menu: MRC cache | ||||
| MRC cache - S3 | yes | no | ||
| MRC cache - normal | yes | no | ||
| Menu: XMP support | ||||
| XMP Profile 1 | yes | no | no | |
| XMP Profile 2 | yes | no | no | |
| Menu: Voltage Support | ||||
| 1.5V | yes | yes | yes | |
| Menu: Manual Overwrites | ||||
| Menu: Overclocking | ||||
| not implemented | no | no | no |
Nehalem
Status
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Native raminit | yes | yes | yes | |
| MRC raminit | ? | ? | ? |
Native raminit features
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Menu: Supported channels | ||||
| single and dual channel | yes | yes | yes | |
| Up to 4 slots | yes | yes | yes | |
| Up to 4 ranks per channel | yes | yes | yes | |
| Menu: Supported frequencies | ||||
| DDR3-800 | yes | yes | ? | |
| DDR3-1066 | yes | yes | ? | |
| DDR3-1333 | yes | yes | ? | |
| Menu: Supported CAS latencies | ||||
| CL6 | yes | yes | ? | |
| CL7 | yes | yes | ? | |
| CL8 | yes | yes | ? | |
| CL9 | yes | yes | ? | |
| CL10 | yes | yes | ? | |
| CL11 | yes | yes | ? | |
| CL12 | yes | no | ||
| CL13 | yes | no | ||
| CL14 | yes | no | ||
| CL15 | yes | no | ||
| CL16 | yes | no | ||
| Menu: MRC cache | ||||
| MRC cache - S3 | yes | yes | yes | |
| MRC cache - normal boot | yes | yes | yes | |
| Menu: XMP support | ||||
| XMP Profile 1 | yes | no | no | |
| XMP Profile 2 | yes | no | no | |
| Menu: Voltage Support | ||||
| 1.5V | yes | yes | yes | |
| 1.35V | ? | no | no | |
| Menu: Manual Overwrites | ||||
| Menu: Overclocking | ||||
| not implemented | no | no | no |
Pineview
Status
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Native raminit | yes | yes | yes | |
| MRC raminit | ? | ? | ? |
Native raminit features
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Menu: Supported channels | ||||
| single and dual channel | yes | yes | yes | |
| Up to 4 slots | yes | yes | yes | |
| Up to 4 ranks per channel | yes | yes | yes | |
| Menu: Supported frequencies | ||||
| DDR2-666 (333Mhz) | yes | yes | yes | |
| DDR2-800 (400Mhz) | yes | yes | yes | |
| Menu: Supported CAS latencies | ||||
| CL4 | yes | yes | yes | |
| CL5 | yes | yes | yes | |
| CL6 | yes | yes | yes | |
| Menu: Boot paths | ||||
| Hot reset | yes | yes | yes | |
| Resume from S3 | yes | no | no | |
| Menu: MRC cache | ||||
| MRC cache - S3 | no | no | no | |
| MRC cache - normal boot | no | no | no | |
| Menu: XMP support | ||||
| XMP Profile 1 | yes | no | no | |
| XMP Profile 2 | yes | no | no | |
| Menu: Voltage Support | ||||
| 1.8V | yes | yes | yes | on ddr2 |
| Menu: Manual Overwrites | ||||
| Menu: Overclocking | ||||
| not implemented | no | no | no |
X4x (Desktop Intel 4 series)
Status
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Native raminit | yes | yes | yes | |
| MRC raminit | ? | ? | ? |
Native raminit features
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Menu: Supported channels | ||||
| single and dual channel | yes | yes | yes | |
| Up to 4 slots | yes | yes | ? | No such board in coreboot |
| Up to 4 ranks per channel | yes | yes | yes | |
| Menu: Supported frequencies | ||||
| DDR2-533 (266Mhz) | yes | no | no | vendor bios bios supports this despite datasheets telling otherwise |
| DDR2-666 (333Mhz) | yes | yes | yes | |
| DDR2-800 (400Mhz) | yes | yes | yes | |
| Menu: Supported CAS latencies | ||||
| CL5 | yes | yes | yes | |
| CL6 | yes | yes | yes | |
| Menu: Supported CPU, FSB | ||||
| 533MHz | yes | no | no | vendor bios bios supports this despite datasheets telling otherwise |
| 800MHz | yes | yes | yes | |
| 1067MHz | yes | yes | yes | |
| 1333MHz | yes | yes | yes | |
| Menu: Boot paths | ||||
| Hot reset | yes | yes | yes | |
| Resume from S3 | yes | yes | yes | |
| Menu: MRC cache | ||||
| MRC cache - S3 | no | no | no | |
| MRC cache - normal boot | no | no | no | |
| Menu: XMP support | ||||
| XMP Profile 1 | yes | no | no | |
| XMP Profile 2 | yes | no | no | |
| Menu: Voltage Support | ||||
| 1.8V | yes | yes | yes | on ddr2 |
| Menu: Manual Overwrites | ||||
| Menu: Overclocking | ||||
| not implemented | no | no | no |
i945
Status
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Native raminit | yes | yes | yes | |
| MRC raminit | ? | ? | ? |
Native raminit features
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Menu: Supported channels | ||||
| single and dual channel | yes | yes | yes | |
| Up to 4 slots | yes | ? | ? | No such board in coreboot and a comment in raminit suggests not |
| Up to 4 ranks per channel | yes | yes | yes | |
| Menu: Supported frequencies | ||||
| DDR2-400 (200Mhz) | yes | yes | yes | |
| DDR2-533 (266Mhz) | yes | yes | yes | |
| DDR2-666 (333Mhz) | yes | yes | yes | |
| Menu: Supported CAS latencies | ||||
| CL3 | yes | yes | yes | |
| CL4 | yes | yes | yes | |
| CL5 | yes | yes | yes | |
| Menu: Boot paths | ||||
| Hot reset | yes | yes | yes | |
| Resume from S3 | yes | yes | yes | |
| Menu: MRC cache | ||||
| MRC cache - S3 | no | no | no | |
| MRC cache - normal boot | no | no | no | |
| Menu: XMP support | ||||
| XMP Profile 1 | yes | no | no | |
| XMP Profile 2 | yes | no | no | |
| Menu: Voltage Support | ||||
| 1.8V | yes | yes | yes | |
| Menu: Manual Overwrites | ||||
| Menu: Overclocking | ||||
| not implemented | no | no | no |
Sandybridge/Ivybridge
Note: If you see only half of the installed memory, there was a memory training error and the emergency fallback has been activated. Please provide raminit logs and file a bug or report it in IRC.
Status
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Native raminit | yes | yes | yes | Native Raminit is working for most frequencies on most boards. There might be errors to fix. |
| MRC raminit | yes | yes | ? |
Native raminit features
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Menu: Supported channels | ||||
| single and dual channel | yes | yes | yes | |
| Up to 4 slots | yes | yes | yes | |
| Up to 4 ranks per channel | yes | yes | yes | |
| Menu: Supported frequencies | ||||
| DDR3-1066 (533Mhz) | yes | yes | yes | |
| DDR3-1333 (666Mhz) | yes | yes | yes | |
| DDR3-1600 (800Mhz) | yes | yes | yes | |
| DDR3-1866 (933Mhz) | yes | yes | yes | |
| DDR3-2133 (1066Mhz) | yes | yes | yes | |
| DDR3-1400 (700Mhz) | yes (Ivybridge only) | no | no | |
| DDR3-1800 (900Mhz) | yes (Ivybridge only) | no | no | |
| DDR3-2000 (1000Mhz) | yes (Ivybridge only) | no | no | |
| DDR3-2200 (1100Mhz) | yes (Ivybridge only) | no | no | |
| DDR3-2400 (1200Mhz) | yes (Ivybridge only) | no | no | |
| Menu: Supported CAS latencies | ||||
| CL6 | yes | yes | ? | |
| CL7 | yes | yes | ? | |
| CL8 | yes | yes | ? | |
| CL9 | yes | yes | ? | |
| CL10 | yes | yes | yes | |
| CL11 | yes | yes | yes | |
| CL12 | yes | yes | ? | Since Coreboot 4.6 |
| CL13 | yes | yes | yes | Since Coreboot 4.6 |
| CL14 | yes | yes | ? | Since Coreboot 4.6 |
| CL15 | yes | yes | ? | Since Coreboot 4.6 |
| Menu: MRC cache | ||||
| MRC cache - S3 | yes | yes | yes | |
| MRC cache - normal boot | yes | yes | yes - reset on SPD CRC16 difference | |
| Menu: XMP support | ||||
| XMP Profile 1 | yes | yes | yes | only 1.5V profiles |
| XMP Profile 2 | yes | yes | no | |
| Menu: Voltage Support | ||||
| 1.5V | yes | yes | yes | |
| 1.35V | depends on board | no | no | needs GPIO to control voltage converter |
| Menu: Manual Overwrites | ||||
| devicetree: cfg_max_mem_clk | yes | yes | yes - limits maximum DDR frequency | |
| Menu: Overclocking | ||||
| not implemented | no | no | no |
Haswell
| Option | Supported | Implemented | Working | Description |
|---|---|---|---|---|
| Native raminit | no | no | no | |
| MRC raminit | yes | yes | yes | No known issues. |