Difference between revisions of "ACPI"

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(More APIC info)
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and also deal with so called IRQ overrides.  
and also deal with so called IRQ overrides.  


Lets look at the figure bellow which explains how the interrupt are routed:[[Image:ApicSystem.svg|thumb|left|A system with 8259s and APICs]]  
look at the figure below which explains how the interrupts are routed:[[Image:ApicSystem.svg|thumb|left|A system with 8259s and APICs]]  


The interrupt sources are on the right side. The legacy IRQs and the PCI IRQs are connected to both APIC and 8259.  
The interrupt sources are on the right side. The legacy IRQs and the PCI IRQs are connected to both APIC and 8259.  


In the legacy case, the APIC is programmed in virtual wire mode. It will just interconnect pin0 of APIC with its output, bypassing APIC completely. OS uses 8259s, and ignores APICs at all.
In the legacy case, the APIC is programmed in virtual wire mode. It will just interconnect pin0 of APIC with its output, bypassing APIC completely. OS uses 8259s, and ignores APICs at all.


The APIC should be in this mode in BIOS, to do that for your SB, check the setup_ioapic in vt8237r_lpc.c. Please note that there is some bit which also says if APIC is delivering through wires, or through FSB messages.
The APIC should be in this mode in BIOS, to do that for your SB, check the setup_ioapic in vt8237r_lpc.c. Please note that there is some bit which also says if APIC is delivering through wires, or through FSB messages.


But back to the table. You need to provide some kind of description of the APICs. Each APIC is identified with its own ID and with the offset where the its IRQ starts. It is called GSI base - Global System Interrupt base. This is just the value which is used in the _PRT entries as offset for IRQ nr. Typically the first SB APIC has offset 0, second APIC starts where the first has finished, so at IRQ 24 if the first has 24 interrupt sources.
But back to the table. You need to provide some kind of description of the APICs. Each APIC is identified with its own ID and with the offset where its IRQ starts. It is called GSI base Global System Interrupt base. This is just the value which is used in the _PRT entries as offset for IRQ nr. Typically the first SB APIC has offset 0, second APIC starts where the first has finished, so at IRQ 24 if the first has 24 interrupt sources.


Last thing in this table are IRQ overrides. Usually there are two IRQ overrides. IRQ0 override means that IRQ0 is not connected to pin 0 on APIC but to another, most likely pin 2. Check the figure above why. Second IRQ override is for ACPI IRQ. This overrides the 'level' of the interrupt to 'active low'.  The rest of the table is filled with NMI entries for the processor.
Last thing in this table are IRQ overrides. Usually there are two IRQ overrides. IRQ0 override means that IRQ0 is not connected to pin 0 on APIC but to another, most likely pin 2. Check the figure above why. Second IRQ override is for ACPI IRQ. This overrides the 'level' of the interrupt to 'active low'.  The rest of the table is filled with NMI entries for the processor.

Revision as of 20:55, 24 February 2009