Difference between revisions of "ACPI"

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For now, you must include your Pstate info yourself using the generator and including that file in DSDT code.
For now, you must include your Pstate info yourself using the generator and including that file in DSDT code.
===== C States =====
C states are processor power states. C1 is mandantory and reached on IA32 compatible processors using the HLT instruction, C2 and C3 are optional and must be configured.
C States can be configured in ACPI using two methods:
1. by defining the P_BLK base address in the Processor() Definition, and P_LVLx_LAT values in the FADT
2. using the _CST Object
P_BLK is easier to configure, if the hardware supports that method. ACPI defines that there must be two registers at P_BLK+4 and P_BLK+5 that initiate a transition to C2 or C3 when the register is read. After sleep, the read returns 0. P_LVLx_LAT define the worst case latency of the state transition.


==== PCI root bus _CRS method ====
==== PCI root bus _CRS method ====

Revision as of 14:15, 16 March 2009