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The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to Contributions welcome!

SPIKE is RISC-V's primary emulator. The Spike support in coreboot is mostly being developed by jn as part of his GSoC 2016.

Build instructions

These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the discussion page or IRC (or just fix it).

Building the toolchain

  • clone the coreboot git repository
  • download and apply this patch and this patch.
  • run make crossgcc-riscv and a have a cup of $BEVERAGE

Building spike

Building coreboot without a payload

For general spike usage, look at its GitHub page.

Building Linux

  • git clone
  • download linux 4.6.x from
  • cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .
  • make ARCH=riscv defconfig
  • make ARCH=riscv menuconfig, configure General setup/Cross-compiler tool prefix
  • make ARCH=riscv

Building bbl

  • TODO: libc stuff
  • TODO: payload linker script foo
  • TODO: patching the console output handler
  • mkdir build
  • cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld
  • make

Building coreboot with bbl

  • apply the same coreboot patches as above, and select Emulation/Spike ucb riscv
  • in the Payload menu of menuconfig, select "ELF Payload" and enter the path to the bbl binary
  • run make and the script as described above

boot log