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The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to Contributions welcome!

This page describes how to use coreboot on the Intel d945gclf mainboard.

The d945gclf2 is almost the same board as the d945gclf, but with a dual core CPU instead of a single core, an extra USB header and a gigabit network card instead of a 10/100. This board also works fine with coreboot.


By default, SeaBIOS uses PIO mode for ATA interfaces. On the ICH7 southbridge, this is very slow. Loading a kernel + initramfs can take up to 20 seconds on this board.

When using ATA DMA mode, this bug disappears. This will have to be set explicitly in the SeaBIOS config file, and selected from coreboot's menuconfig.

From the coreboot root directory, go to payloads/external/SeaBIOS/seabios:

cd payloads/external/SeaBIOS/seabios/

Create a file called .config and add these lines to it:


Then, create a full .config file by running:

make menuconfig

Navigate to General Features and make sure the Build Target is set to Build for coreboot.

Navigate to Hardware support and make sure that ATA DMA is enabled [*].

Navigate to VGA ROM and make sure that VGA Hardware Type is set to coreboot linear framebuffer.

Exit menuconfig and save the changes.

It is probably easiest to move the .config file to the coreboot root directory, under a different name (e.g. .seabiosconfig), as coreboot already has its own .config file.

mv .config ../../../../.seabiosconfig

Finally return to the coreboot root directory:

cd ../../../../

coreboot configuration

Create a file called .config and add at least these lines to it:


In case you do not want CPU microcode updates included in your ROM, add this line:


In case you do want to include CPU microcode updates in your ROM, add these lines:


By default, serial debugging output is enabled. It is very useful for debugging, but also slows down the boot process a lot. If you don't need serial debug or have no idea how to use it, disable it:


Then, create a full .config file by running:

make menuconfig

Navigate to General setup and make sure that Use CMOS for configuration values is enabled [*].

Navigate to Mainboard and make sure the Mainboard vendor is set to INTEL and the Mainboard model to D945GCLF.

Navigate to Chipset and make sure that Include CPU microcode in CBFS is set to either Generate from tree or Do not include microcode updates.

  • In case you selected Generate from tree, make sure that General setup -> Allow use of binary-only repository is enabled [*].

Navigate to Devices and make sure that Use native graphics initialization is enabled [*].

Navigate to Payload and set your SeaBIOS configuration in SeaBIOS config file.

  • This requires a full path. For instance, if your coreboot root directory is in ~/Downloads, set ~/Downloads/coreboot/.seabiosconfig

Exit menuconfig and save the changes.

Now build your ROM:


CMOS default values

By default, the VGA shared RAM on this board is set to 8MB. While this is fine for server use, this is not ideal for desktop or HTPC use.

In order to change CMOS defaults, you will need nvramtool:

cd util/nvramtool/
mv nvramtool ../../nvramtool
cd ../../

The VGA shared RAM can be increased to 16MB, 32MB or 64MB by running:

./nvramtool -C build/coreboot.rom -w gfx_uma_size=16M


./nvramtool -C build/coreboot.rom -w gfx_uma_size=32M


./nvramtool -C build/coreboot.rom -w gfx_uma_size=64M

Backing up the vendor BIOS

This board can be flashed with flashrom, which is in the repositories of nearly every GNU/Linux distribution.

However, the Intel vendor BIOS locks writes to the chip from a running system, so you can only flash internally if you are already running coreboot.

To make a backup of the BIOS chip, run:

sudo flashrom -p internal -r bios.rom

Internal flashing

To flash the BIOS chip, run:

sudo flashrom -p internal -w build/coreboot.rom

As stated above, writing to the chip is only possible when running coreboot. The inital flash will have to be done externally.

External flashing

Chip pinout

-cs          vcc-
-miso           -
-            clk-
-gnd        mosi-

Status (as of commit 5360c7ef94)

Device/functionality Status Comments
CPU works OK
L1 cache enabled OK
L2 cache enabled OK
L3 cache enabled N/A
Multiple CPU support N/A
Multi-core support OK
Hardware virtualization N/A
Dual channel support N/A
ECC support N/A
On-board Hardware
On-board IDE 3.5" Untested
On-board IDE 2.5" N/A
On-board SATA OK
On-board SCSI N/A
On-board USB OK
On-board VGA OK VBIOS works. Only textmode available for native graphic init.
On-board Ethernet OK
On-board Audio OK
On-board Modem N/A
On-board FireWire N/A
On-board Smartcard reader N/A
On-board CompactFlash N/A
On-board PCMCIA N/A
On-board Wifi N/A
On-board Bluetooth N/A
On-board SD card reader N/A
Add-on slots/cards
ISA add-on cards N/A
Audio/Modem-Riser (AMR/CNR) cards N/A
PCI add-on cards OK
Mini-PCI add-on cards N/A
Mini-PCI-Express add-on cards Unknown
PCI-X add-on cards N/A
AGP graphics cards N/A
PCI Express x1 add-on cards N/A
PCI Express x2 add-on cards N/A
PCI Express x4 add-on cards N/A
PCI Express x8 add-on cards N/A
PCI Express x16 add-on cards N/A
PCI Express x32 add-on cards N/A
HTX add-on cards N/A
Legacy / Super I/O
Floppy N/A
Serial port 1 (COM1) OK
Serial port 2 (COM2) N/A
Parallel port Untested
PS/2 keyboard OK
PS/2 mouse Untested
Game port N/A
Infrared N/A
PC speaker N/A
DiskOnChip N/A
Trackpoint N/A
Touchpad N/A
Fn Hotkeys N/A
Fingerprint Reader N/A
Docking VGA N/A
Docking LAN N/A
Docking USB N/A
Docking Audio N/A
Docking Displayport N/A
Thinklight N/A
Webcam N/A
Sensors / fan control OK
Hardware watchdog Unknown
CAN bus N/A
CPU frequency scaling N/A
Other powersaving features N/A
Reboot OK
Poweroff OK
Suspend OK
Nonstandard LEDs OK
High precision event timers (HPET) OK
Random number generator (RNG) N/A
Wake on modem ring N/A
Wake on LAN OK Tested on d945gclf only.
Wake on keyboard Unknown
Wake on mouse Unknown
TPM Unknown
Flashrom OK Needs external flashing from vendor BIOS, internal works fine on coreboot.