Difference between revisions of "Board:jetway/nf81-t56n-lf"

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(get rid of lspci o/p, we should be done with that detail at this stage)
 
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== Known Issues ==
== Known Issues ==


* pcie 06.0 bridge sometimes hangs probing the nic behind it. Linux reports a borked IRQ addr. They are likely connected? (Fix ACPI).
* pcie 06.0 bridge sometimes hangs probing the nic behind it. Linux reports a borked IRQ addr. They are likely connected? (Fix ACPI?).
* superio not controlling fan - fix known, patch WIP!
* suspend/resume could do with some work to clean up nasty warnings.. (Fix ACPI).
* suspend/resume could do with some work to clean up nasty warnings.. (Fix ACPI).
* some werid AGESA issue affects a number of boards
* some werid AGESA issue affects a number of boards


=== pcie 06.0 bridge hang issue ===
== Overview ==


The pcie 06.0 bridge hang issue is the primary remaining issue.
=== Hardware ===


The Interrupt Mask Register (IMR) and Interrupt Service Register (ISR) are responsible for firing up different IRQs. The IMR bits line up with the ISR bits to work in sync. If an IMR bit is low, then the corresponding ISR bit with never fire an IRQ when the time comes for it to happen. The IMR is located at 0x3C and the ISR is located at 0x3E.
* '''AMD Fusion G-series''' AMD Fusion G-T56N (1.65 GHz dual core) APU
* '''AMD A55E''' part of the chipset, AMD A55E (Hudson-E1) southbridge
* '''F71869AD''' Fintek F71869AD Super I/O
* '''RTL8111E''' Twin Realtek RTL8111E network controllers
* '''VT1705''' 6-Channel HD Audio (via VIA VT1705), AC97 AD/DA


=== Details ===


Observe in the vendor bios pci configuration space dump attached below that, indx. 0x3C (IMR) = 0x0b and indx. 0x3E (ISR) = 0x10.
The NF81-T56N-LF is a IPC form factor embedded board:
* AMD Fusion G-T56N (1.65 GHz dual core) APU
** 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V)
** VGA and LVDS (via Analogix ANX3110)
* AMD A55E (Hudson-E1) southbridge
** 6x USB 2.0/1.1 ports
** 5x SATA3 6Gb/s, 1x mSATA socket
** 6-Channel HD Audio (via VIA VT1705)
** PCI and ISA (via ITE IT8888)??
** NEC uPD78F0532 microcontroller on I2C ("SEMA")??
* 2x RJ45 GbE (via Realtek RTL8111E x2)
* Fintek F71869AD Super I/O
** PS/2 KB/MS port
** RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
** GPIO header
** CIR header
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)


IMR val. = 0000 1011 = INTB
Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway '''''lies'''''
ISR val. = 0000 1010
claiming the SPI flash is 16MB. They also use red pen over the chip
====================
so you wont see this deceit.
        &= 0000 1010
====================
 
root@archiso ~ # hexdump -C /sys/bus/pci/devices/0000:00:06.0/config
00000000  22 10 14 15 07 00 10 00  00 00 04 06 10 00 01 00  |"...............|
00000010  00 00 00 00 00 00 00 00  00 02 02 00 e1 e1 00 00  |................|
00000020  f0 ff 00 00 11 d0 11 d0  00 00 00 00 00 00 00 00  |................|
00000030  00 00 00 00 50 00 00 00  00 00 00 00 0b 01 10 00  |....P...........|
00000040  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000050  01 58 03 c8 00 00 00 00  10 a0 42 01 20 80 00 00  |.X........B. ...|
00000060  00 08 00 00 11 0c 30 03  40 00 11 70 80 25 34 00  |......0.@..p.%4.|
00000070  00 00 48 01 00 00 01 00  00 00 00 00 1f 00 00 00  |..H.............|
00000080  06 00 00 00 00 00 00 00  21 00 00 00 00 00 00 00  |........!.......|
00000090  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000000a0  05 b0 80 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000000b0  0d b8 00 00 22 10 34 12  08 00 03 a8 00 00 00 00  |....".4.........|
000000c0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
000000e0  50 00 00 00 02 00 00 00  00 00 00 00 00 00 00 00  |P...............|
000000f0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000100  0b 00 01 00 01 00 01 01  00 00 00 00 00 00 00 00  |................|
00000110  02 00 01 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000120  01 00 00 00 ff 00 00 80  00 00 00 00 01 00 00 00  |................|
00000130  00 00 00 00 00 00 02 00  00 00 00 00 00 00 00 00  |................|
00000140  03 00 01 00 01 00 00 00  00 87 0c 00 00 00 00 00  |................|
00000150  01 00 01 00 00 00 00 00  00 00 00 00 30 20 06 00  |............0 ..|
00000160  00 00 00 00 00 20 00 00  00 00 00 00 00 00 00 00  |..... ..........|
00000170  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00000190  0d 00 01 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000001a0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00001000


Investigate in board support:
=== Building a coreboot image ===
* acpi/routing.asl
* mptable.c


=== weird AGESA issue ===
Make a fresh clone of Coreboot into a empty directory and run:
make crossgcc-i386
Make a cup of tea.. Then run:
make menuconfig
and select Jetway/NF81-t56N-LF under "Mainboard -> Mainboard vendor/model" leaving
everything else as defaults. Then finally do,
make


The function call goes something like this; In
To flash the board with '''flashrom''' run:
mainboard/jetway/nf81-t56n-lf/agesawrapper.c
  flashrom -p ft2232_spi:type=2232H,port=A -c "MX25L1605A/MX25L1606E" -w build/coreboot.rom
the function
''assuming'' you have a SPI flasher setup.
UINT32 agesawrapper_amdinitpost(VOID)
calls
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
this returns a error code of
AGESA_WARNING = 0x4
this triggers
if(status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
giving the resulting message:
 
EventLog:      EventClass = 2, EventInfo = 8040100.
...
 
grep'ing we have that:
AGESA.h:#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT    0x08040100ul
 
However tracing the call back to where '''AGESA_WARNING''' is set goes back to:
  vendor/amd/agesa/f14/Proc/Mem/Main/mmflow.c
line '''290''' here:
Retval = NBPtr[Die].MCTPtr->ErrCode;
with '''Die=0'''.


== Status ==
== Status ==
Line 99: Line 70:
|CPU_multiple_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = N/A
|CPU_multicore_status = N/A
|CPU_virt_status = WIP
|CPU_virt_status = OK


|RAM_EDO_status = N/A
|RAM_EDO_status = N/A
Line 160: Line 131:
|DiskOnChip_status = N/A
|DiskOnChip_status = N/A


|Sensors_status = Pending
|Sensors_status = OK
|Sensors_comments = See Gerrit 5500
|Sensors_comments =
|Watchdog_status = Pending
|Watchdog_status = Pending
|Watchdog_comments = See Gerrit 5500
|Watchdog_comments = What needs to be done here??
|SMBus_status = OK
|SMBus_status = OK
|CAN_bus_status = N/A
|CAN_bus_status = N/A
Line 186: Line 157:
}}
}}


== Hardware ==
== Issue Analysis ==
 
=== pcie 06.0 bridge hang issue ===


=== Overview ===
The pcie 06.0 bridge hang issue is the primary remaining issue.
 
The Interrupt Mask Register (IMR) and Interrupt Service Register (ISR) are responsible for firing up different IRQs. The IMR bits line up with the ISR bits to work in sync. If an IMR bit is low, then the corresponding ISR bit with never fire an IRQ when the time comes for it to happen. The IMR is located at 0x3C and the ISR is located at 0x3E.


* '''AMD Fusion G-series''' AMD Fusion G-T56N (1.65 GHz dual core) APU
* '''AMD A55E''' part of the chipset, AMD A55E (Hudson-E1) southbridge
* '''F71869AD''' Fintek F71869AD Super I/O
* '''RTL8111E''' Twin Realtek RTL8111E network controllers
* '''VT1705''' 6-Channel HD Audio (via VIA VT1705), AC97 AD/DA


=== Details ===
Observe in the vendor bios pci configuration space dump attached below that, indx. 0x3C (IMR) = 0x0b and indx. 0x3E (ISR) = 0x10.


The NF81-T56N-LF is a IPC form factor embedded board:
IMR val. = 0000 1011 = INTB
* AMD Fusion G-T56N (1.65 GHz dual core) APU
ISR val. = 0000 1010
** 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V)
====================
** VGA and LVDS (via Analogix ANX3110)
        &= 0000 1010
* AMD A55E (Hudson-E1) southbridge
====================
** 6x USB 2.0/1.1 ports
** 5x SATA3 6Gb/s, 1x mSATA socket
** 6-Channel HD Audio (via VIA VT1705)
** PCI and ISA (via ITE IT8888)??
** NEC uPD78F0532 microcontroller on I2C ("SEMA")??
* 2x RJ45 GbE (via Realtek RTL8111E x2)
* Fintek F71869AD Super I/O
** PS/2 KB/MS port
** RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
** GPIO header
** CIR header
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)


Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway '''''lies'''''
root@archiso ~ # hexdump -C /sys/bus/pci/devices/0000:00:06.0/config
claiming the SPI flash is 16MB. They also use red pen over the chip
00000000  22 10 14 15 07 00 10 00  00 00 04 06 10 00 01 00  |"...............|
so you wont see this deceit.
00000010  00 00 00 00 00 00 00 00  00 02 02 00 e1 e1 00 00  |................|
00000020  f0 ff 00 00 11 d0 11 d0  00 00 00 00 00 00 00 00  |................|
00000030  00 00 00 00 50 00 00 00  00 00 00 00 0b 01 10 00  |....P...........|
00000040  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000050  01 58 03 c8 00 00 00 00  10 a0 42 01 20 80 00 00  |.X........B. ...|
00000060  00 08 00 00 11 0c 30 03  40 00 11 70 80 25 34 00  |......0.@..p.%4.|
00000070  00 00 48 01 00 00 01 00  00 00 00 00 1f 00 00 00  |..H.............|
00000080  06 00 00 00 00 00 00 00  21 00 00 00 00 00 00 00  |........!.......|
00000090  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000000a0  05 b0 80 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000000b0  0d b8 00 00 22 10 34 12  08 00 03 a8 00 00 00 00  |....".4.........|
000000c0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
000000e0  50 00 00 00 02 00 00 00  00 00 00 00 00 00 00 00  |P...............|
000000f0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000100  0b 00 01 00 01 00 01 01  00 00 00 00 00 00 00 00  |................|
00000110  02 00 01 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000120  01 00 00 00 ff 00 00 80  00 00 00 00 01 00 00 00  |................|
00000130  00 00 00 00 00 00 02 00  00 00 00 00 00 00 00 00  |................|
00000140  03 00 01 00 01 00 00 00  00 87 0c 00 00 00 00 00  |................|
00000150  01 00 01 00 00 00 00 00  00 00 00 00 30 20 06 00  |............0 ..|
00000160  00 00 00 00 00 20 00 00  00 00 00 00 00 00 00 00  |..... ..........|
00000170  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00000190  0d 00 01 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000001a0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00001000


== Building a coreboot image ==
Investigate in board support:
* acpi/routing.asl
* mptable.c


Make a fresh clone of Coreboot into a empty directory and run:
=== weird AGESA issue ===
make crossgcc-i386
Make a cup of tea.. Then run:
make menuconfig
and select Jetway/NF81-t56N-LF under "Mainboard -> Mainboard vendor/model" leaving
everything else as defaults. Then finally do,
make


To flash the board with '''flashrom''' run:
The function call goes something like this; In
  flashrom -p ft2232_spi:type=2232H,port=A -c "MX25L1605A/MX25L1606E" -w build/coreboot.rom
  mainboard/jetway/nf81-t56n-lf/agesawrapper.c
''assuming'' you have a SPI flasher setup.
the function
UINT32 agesawrapper_amdinitpost(VOID)
calls
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
this returns a error code of
AGESA_WARNING = 0x4
this triggers
if(status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
giving the resulting message:


== Various logs ==
EventLog:      EventClass = 2, EventInfo = 8040100.
...


=== SuperI/O tool log ===
grep'ing we have that:
AGESA.h:#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT    0x08040100ul


  superiotool r4.0-5364-gb16690d
However tracing the call back to where '''AGESA_WARNING''' is set goes back to:
Found Fintek F71869AD (vid=0x3419, id=0x0710) at 0x2e
  vendor/amd/agesa/f14/Proc/Mem/Main/mmflow.c
Register dump:
line '''290''' here:
  idx 02 07 20 21 25 26 27 28  29 2a 2b 2c 2d
  Retval = NBPtr[Die].MCTPtr->ErrCode;
val 00 0b 10 07 00 00 a1 01  6f 24 00 60 2f
with '''Die=0'''.
def 00 00 08 14 00 00 MM 38  6f 07 0f 00 28
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f2 f4
val 00 03 f0 06 02 0e ff 00
def 01 03 f0 06 02 0e 03 00
LDN 0x01 (COM1)
idx 30 60 61 70 f0
val 01 03 f8 04 00
def 01 03 f8 04 00
LDN 0x02 (COM2)
idx 30 60 61 70 f0 f1
val 00 02 f8 03 00 44
def 01 02 f8 03 00 04
LDN 0x03 (Parallel port)
idx 30 60 61 70 74 f0
val 00 03 78 07 03 42
def 01 03 78 07 03 42
LDN 0x04 (Hardware monitor)
idx 30 60 61 70
val 01 02 25 00
def 01 02 95 00
LDN 0x05 (Keyboard)
idx 30 60 61 70 72 f0 fe ff
val 01 00 60 01 0c ff 81 29
def 01 00 60 01 0c 83 81 29
LDN 0x06 (GPIO)
idx 30 60 61 70 f0 f1 f2 f3  e0 e1 e2 e3 e4 e5 e6 d0  d1 d2 d3 c0 c1 c2 b0 b1  b2 b3 a0 a1 a2 a3 90 91  92 93
val 01 0a 00 00 00 3f 00 00  20 df 91 00 00 00 05 00  ff a7 00 ff 00 00 00 ff  73 00 00 1f 00 ff 00 ff  00 00
def 00 00 00 00 00 3f NA 00  00 ff NA 00 00 00 00 00  ff NA 00 00 ff NA 00 0f  NA 00 00 1f NA 00 00 3f  NA 00
LDN 0x07 (BSEL)
idx 30 60 61 f0 f2 f3 f4 f5  f6 f7
val 00 00 00 01 ff ff ff 12  0a 01
def 00 00 00 01 00 00 NA 00  0a 00
LDN 0x0a (PME, ACPI)
idx 30 f0 f1 f2 f3 f4 f5 f6  f7 f8 f9 fe ff
val 00 00 6a 00 00 46 1c 1f  86 00 00 00 00
def 00 00 00 NA NA 06 1c 1f  86 00 00 00 00


=== Coreboot S3 resume log ===
=== Coreboot S3 suspend/resume ===


S3 Suspend/Resume works by running:
S3 Suspend/Resume works by running:

Latest revision as of 04:19, 9 June 2014

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