Difference between revisions of "Board:jetway/nf81-t56n-lf"

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This page describes how to use coreboot on the '''[http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T56N-LF Jetway NF81-T56N-LF]''' mainboard.
This page describes how to use coreboot on the '''[http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T56N-LF Jetway NF81-T56N-LF]''' mainboard.


This page is a work in progress. Rows with (WIP)* are high-priority ticket items and shall be addressed soon.
This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.


ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.
== Known Issues ==
 
* pcie 06.0 bridge sometimes hangs probing the nic behind it. Linux reports a borked IRQ addr. They are likely connected? (Fix ACPI?).
* suspend/resume could do with some work to clean up nasty warnings.. (Fix ACPI).
* some werid AGESA issue affects a number of boards
 
== Overview ==
 
=== Hardware ===
 
* '''AMD Fusion G-series''' AMD Fusion G-T56N (1.65 GHz dual core) APU
* '''AMD A55E''' part of the chipset, AMD A55E (Hudson-E1) southbridge
* '''F71869AD''' Fintek F71869AD Super I/O
* '''RTL8111E''' Twin Realtek RTL8111E network controllers
* '''VT1705''' 6-Channel HD Audio (via VIA VT1705), AC97 AD/DA
 
=== Details ===
 
The NF81-T56N-LF is a IPC form factor embedded board:
* AMD Fusion G-T56N (1.65 GHz dual core) APU
** 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V)
** VGA and LVDS (via Analogix ANX3110)
* AMD A55E (Hudson-E1) southbridge
** 6x USB 2.0/1.1 ports
** 5x SATA3 6Gb/s, 1x mSATA socket
** 6-Channel HD Audio (via VIA VT1705)
** PCI and ISA (via ITE IT8888)??
** NEC uPD78F0532 microcontroller on I2C ("SEMA")??
* 2x RJ45 GbE (via Realtek RTL8111E x2)
* Fintek F71869AD Super I/O
** PS/2 KB/MS port
** RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
** GPIO header
** CIR header
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)
 
Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway '''''lies'''''
claiming the SPI flash is 16MB. They also use red pen over the chip
so you wont see this deceit.
 
=== Building a coreboot image ===
 
Make a fresh clone of Coreboot into a empty directory and run:
make crossgcc-i386
Make a cup of tea.. Then run:
make menuconfig
and select Jetway/NF81-t56N-LF under "Mainboard -> Mainboard vendor/model" leaving
everything else as defaults. Then finally do,
make
 
To flash the board with '''flashrom''' run:
flashrom -p ft2232_spi:type=2232H,port=A -c "MX25L1605A/MX25L1606E" -w build/coreboot.rom
''assuming'' you have a SPI flasher setup.


== Status ==
== Status ==
Line 18: Line 70:
|CPU_multiple_status = N/A
|CPU_multiple_status = N/A
|CPU_multicore_status = N/A
|CPU_multicore_status = N/A
|CPU_virt_status = (WIP)*
|CPU_virt_status = OK


|RAM_EDO_status = N/A
|RAM_EDO_status = N/A
Line 34: Line 86:
|IDE_25_status = N/A
|IDE_25_status = N/A
|CDROM_DVD_status = N/A
|CDROM_DVD_status = N/A
|SATA_status = (WIP)*
|SATA_status = OK
|SATA_comments =  
|SATA_comments =  
|Onboard_SCSI_status = N/A
|Onboard_SCSI_status = N/A
|USB_status = (WIP)*
|USB_status = OK
|USB_comments =  
|USB_comments =  
|Onboard_VGA_status = OK
|Onboard_VGA_status = OK
|Onboard_VGA_comments = BIOS/console: works. Used: '''e14jtway.rom''' from original BIOS '''7F4A111.BIN''' (62K) + '''BIOS-bochs-latest''' (64K). X.org (openchrome): works.
|Onboard_VGA_comments = BIOS/console: works.
|Onboard_ethernet_status = OK
|Onboard_ethernet_status = OK
|Onboard_audio_status = Needs work
|Onboard_audio_status = OK
|Onboard_audio_comments = Basic two channel audio works fine.
|Onboard_modem_status = N/A
|Onboard_modem_status = N/A
|Onboard_firewire_status = N/A
|Onboard_firewire_status = N/A
Line 51: Line 104:
|ISA_cards_status = N/A
|ISA_cards_status = N/A
|AMR_cards_status = N/A
|AMR_cards_status = N/A
|Mini_PCI_cards_status = (WIP)*
|Mini_PCI_cards_status = N/A
|Mini_PCI_cards_comments = Testing: with MiniPCI slot with a POST card.
|Mini_PCI_cards_comments =
|PCIX_cards_status = N/A
|PCIX_cards_status = N/A
|AGP_cards_status = N/A
|AGP_cards_status = N/A
|PCI_cards_status = WIP
|PCI_cards_status = OK
|PCI_cards_comments =  
|PCI_cards_comments =  
|mini-PCI_status = (WIP)*
|PCIE_x1_status = OK
|PCIE_x1_status = N/A
|PCIE_x1_comments = miniPCIe slot works, mSATA/miniPCIe slot does not!?
|PCIE_x2_status = N/A
|PCIE_x2_status = N/A
|PCIE_x4_status = N/A
|PCIE_x4_status = N/A
Line 70: Line 123:
|COM2_status = N/A
|COM2_status = N/A
|PP_status = N/A
|PP_status = N/A
|PS2_keyboard_status = Untested
|PS2_keyboard_status = OK
|PS2_mouse_status = Untested
|PS2_mouse_status = OK
|Game_port_status = N/A
|Game_port_status = N/A
|IR_status = N/A
|IR_status = Untested
|IR_comments = CIR header currently turned off in devicetree.cb
|Speaker_status = OK
|Speaker_status = OK
|DiskOnChip_status = N/A
|DiskOnChip_status = N/A


|Sensors_status = (WIP)*
|Sensors_status = OK
|Sensors_comments =  
|Sensors_comments =
|Watchdog_status = (WIP)*
|Watchdog_status = Pending
|Watchdog_comments =  
|Watchdog_comments = What needs to be done here??
|SMBus_status = OK
|SMBus_status = OK
|CAN_bus_status = N/A
|CAN_bus_status = N/A
|CPUfreq_status = OK
|CPUfreq_status = OK
|Powersave_status = N/A
|Powersave_status = N/A
|ACPI_status = (WIP)*
|ACPI_status = WIP
|ACPI_comments =  
|ACPI_comments = Mostly working, needs a good Review!
|Reboot_status = OK
|Reboot_status = OK
|Poweroff_status = No
|Poweroff_status = OK
|Poweroff_comments = Probably needs ACPI.
|Suspend_status = OK
|Poweroff_comments =
|LEDs_status = N/A
|LEDs_status = N/A
|HPET_status = OK  
|HPET_status = OK  
Line 102: Line 157:
}}
}}


== Hardware ==
== Issue Analysis ==
 
=== pcie 06.0 bridge hang issue ===


=== Overview ===
The pcie 06.0 bridge hang issue is the primary remaining issue.


* '''AMD Fusion G-series''' AMD Fusion G-T56N (1.65 GHz dual core) APU
The Interrupt Mask Register (IMR) and Interrupt Service Register (ISR) are responsible for firing up different IRQs. The IMR bits line up with the ISR bits to work in sync. If an IMR bit is low, then the corresponding ISR bit with never fire an IRQ when the time comes for it to happen. The IMR is located at 0x3C and the ISR is located at 0x3E.
* '''AMD A55E''' part of the chipset, AMD A55E (Hudson-E1) southbridge
 
* '''F71869AD''' Fintek F71869AD Super I/O
 
* '''RTL8111E''' Twin Realtek RTL8111E network controllers
Observe in the vendor bios pci configuration space dump attached below that, indx. 0x3C (IMR) = 0x0b and indx. 0x3E (ISR) = 0x10.
* '''VT1705''' 6-Channel HD Audio (via VIA VT1705), AC97 AD/DA
 
IMR val. = 0000 1011 = INTB
ISR val. = 0000 1010
====================
        &= 0000 1010
====================
 
root@archiso ~ # hexdump -C /sys/bus/pci/devices/0000:00:06.0/config
00000000  22 10 14 15 07 00 10 00  00 00 04 06 10 00 01 00  |"...............|
00000010  00 00 00 00 00 00 00 00  00 02 02 00 e1 e1 00 00  |................|
00000020  f0 ff 00 00 11 d0 11 d0  00 00 00 00 00 00 00 00  |................|
00000030  00 00 00 00 50 00 00 00  00 00 00 00 0b 01 10 00  |....P...........|
00000040  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000050  01 58 03 c8 00 00 00 00  10 a0 42 01 20 80 00 00  |.X........B. ...|
00000060  00 08 00 00 11 0c 30 03  40 00 11 70 80 25 34 00  |......0.@..p.%4.|
00000070  00 00 48 01 00 00 01 00  00 00 00 00 1f 00 00 00  |..H.............|
00000080  06 00 00 00 00 00 00 00  21 00 00 00 00 00 00 00  |........!.......|
00000090  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000000a0  05 b0 80 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000000b0  0d b8 00 00 22 10 34 12  08 00 03 a8 00 00 00 00  |....".4.........|
000000c0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
000000e0  50 00 00 00 02 00 00 00  00 00 00 00 00 00 00 00  |P...............|
000000f0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000100  0b 00 01 00 01 00 01 01  00 00 00 00 00 00 00 00  |................|
00000110  02 00 01 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000120  01 00 00 00 ff 00 00 80  00 00 00 00 01 00 00 00  |................|
00000130  00 00 00 00 00 00 02 00  00 00 00 00 00 00 00 00  |................|
00000140  03 00 01 00 01 00 00 00  00 87 0c 00 00 00 00 00  |................|
00000150  01 00 01 00 00 00 00 00  00 00 00 00 30 20 06 00  |............0 ..|
00000160  00 00 00 00 00 20 00 00  00 00 00 00 00 00 00 00  |..... ..........|
00000170  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00000190  0d 00 01 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000001a0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00001000
 
Investigate in board support:
* acpi/routing.asl
* mptable.c
 
=== weird AGESA issue ===
 
The function call goes something like this; In
mainboard/jetway/nf81-t56n-lf/agesawrapper.c
the function
UINT32 agesawrapper_amdinitpost(VOID)
calls
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
this returns a error code of
AGESA_WARNING = 0x4
this triggers
if(status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
giving the resulting message:
 
EventLog:      EventClass = 2, EventInfo = 8040100.
...
 
grep'ing we have that:
AGESA.h:#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT    0x08040100ul
 
However tracing the call back to where '''AGESA_WARNING''' is set goes back to:
vendor/amd/agesa/f14/Proc/Mem/Main/mmflow.c
line '''290''' here:
Retval = NBPtr[Die].MCTPtr->ErrCode;
with '''Die=0'''.
 
=== Coreboot S3 suspend/resume ===
 
S3 Suspend/Resume works by running:
# echo "mem" > /sys/power/state
However a issue remains of wanrings about resources being '''not assigned'''.
 
For details see in '''src/device/pnp_device.c''' the function:
 
static void pnp_set_resource(device_t dev, struct resource *resource)
{
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx "
      "not assigned\n", dev_path(dev), resource->index,
      resource_type(resource), resource->size);
return;
}
  ...
 
and in '''src/device/device_util.c''' the function:
 
const char *resource_type(struct resource *resource)
{
static char buffer[RESOURCE_TYPE_MAX];
snprintf(buffer, sizeof (buffer), "%s%s%s%s",
((resource->flags & IORESOURCE_READONLY) ? "ro" : ""),
((resource->flags & IORESOURCE_PREFETCH) ? "pref" : ""),
((resource->flags == 0) ? "unused" :
  (resource->flags & IORESOURCE_IO) ? "io" :
  (resource->flags & IORESOURCE_DRQ) ? "drq" :
  (resource->flags & IORESOURCE_IRQ) ? "irq" :
  (resource->flags & IORESOURCE_MEM) ? "mem" : "??????"),
((resource->flags & IORESOURCE_PCI64) ? "64" : ""));
return buffer;
}
 
and in '''src/include/device/resource.h''' the struct resource:
 
struct resource {
..
  unsigned long index; /* Bus specific per device resource id */
..


=== Details ===
Analysis:
  ERROR: PCI: 00:18.0 1088 ??????64 size: 0x0000000000 not assigned
        -----------^ ---^ -------^      -----------^
                    |    |        |                  |
                    |    |        |                  +--- resource->size
                    |    |        |
                    |    |        +--- resource_type(resource)
                    |    |
                    |    +--- resource->index
                    |
                    +--- dev_path(dev)


The NF81-T56N-LF is a IPC form factor embedded board:
A '''dev_path''' of type '''DEVICE_PATH_PCI''' (Host Bridge) at 18.0 of '''IORESOURCE_MEM''' type has a bus specific index of '''1088'''.
* AMD Fusion G-T56N (1.65 GHz dual core) APU
  - 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (1.5 or 1.35V)?
  - VGA and LVDS (via Analogix ANX3110)
* AMD A55E (Hudson-E1) southbridge
  - 6x USB 2.0/1.1 ports
  - 5x SATA3 6Gb/s, 1x mSATA socket
  - 6-Channel HD Audio (via VIA VT1705)
  - PCI and ISA (via ITE IT8888)??
  - NEC uPD78F0532 microcontroller on I2C ("SEMA")??
* 2x RJ45 GbE (via Realtek RTL8111E x2)
* Fintek F71869AD Super I/O
  - PS/2 KB/MS port
  - RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
  - GPIO header
  - CIR header
* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)


Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies*
Possibly related to the devicetree.cb ??
claiming the SPI flash is 16MB. They also use red pen over the chip
so you wont see this deceit.


=== lspci -tvnn ===
See log below:


?
Booting from Hard Disk...
Booting from 0000:7c00
coreboot-4.0-5634-gfe71e8b-ap-jupiter-alpha Mon Mar 10 02:01:03 EST 2014 starting...
S3 detected
CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1429552 bytes), entry @ 0x200000
coreboot-4.0-5634-gfe71e8b-ap-jupiter-alpha Mon Mar 10 02:01:03 EST 2014 booting...
Enumerating buses...
Mainboard NF81-T56N-LF Enable.
setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f000000, msr.hi = 0x00000001
setup_uma_memory: uma size 0x18000000, memory start 0xc8000000
PCI: Static device PCI: 00:04.0 not found, disabling it.
sm_init().
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
done
Allocating resources...
Reading resources...
APIC: 00 missing read_resources
APIC: 01 missing read_resources
I2C: 00:50 missing read_resources
I2C: 00:51 missing read_resources
Done reading resources.
Setting resources...
ERROR: PCI: 00:18.0 1080 ??????64 size: 0x0000000000 not assigned
ERROR: PCI: 00:18.0 1088 ??????64 size: 0x0000000000 not assigned
Done setting resources.
Done allocating resources.
Enabling resources...
done.
Initializing devices...
Initializing CPU #0
Enabling cache
Setting up local apic...done.
CPU #0 initialized
Initializing CPU #1
Waiting for 1 CPUS to stop
Enabling cache
Setting up local apic...done.
CPU #1 initialized
Devices initialized
Finalize devices...
Devices finalized


== Building a coreboot image ==
=== Coreboot boot log ===


XXX: to complete..
See [http://www.coreboot.org/Supported_Motherboards#jetway.2Fnf81-t56n-lf] for a recent log.


{{PD-self}}
{{PD-self}}

Latest revision as of 04:19, 9 June 2014

Retrieved from "https://www.coreboot.org/index.php?title=Board:jetway/nf81-t56n-lf&oldid=13759"