The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
Thanks for your interest in Lenovo T420 port. The code has not been merged yet, you can see the code on gerrit.
ATTENTION: You must cherry-pick this patch before building. (It's merged to upstream, you can cherry-picked the T420 port on the upstream coreboot code.)
- The USB beside express card cannot funtion after S3 resume if CONFIG_USBDEBUG is set (work around: reload ehci-pci module)
- Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)
- Boot failure with quad core Ivy Bridge processor with 8G DDR3L module (Bug #6, work around:revert 9f1fbb9a3002e8d74d53d7973bd1c7e3d4879238)
- Ivy Bridge processor (see below)
- RAM module combinations of 2G+0, 4G+0, 8G+0, 0+8G, 4G+8G, 8G+8G
- S3 (Suspend to RAM)
- Video (internal)
- Sound (integrated speakers, integrated mic, external headphones, external mic)
- mini-PCIe slots (wlan)
- Linux (through GRUB-as-payload)
- Windows (through SeaBIOS as payload or chainload SeaBIOS from GRUB payload, using a VGA BIOS)
- DVD-ROM drive
- SD card slot
- Fn hotkeys (backlight control, suspend, thinklight)
- dock (tested with a TYPE 4337)
- Video (VGA and Displayport)
- Expresscard slot (including hotplugging)
- mini pci-e wwan
- Fingerprint reader.
- Thermal management
proprietary components status
- CPU Microcode (optional): you may need it if your system is unstable (especially you're using a ES/QS processor)
- VGA option rom (optional): you need it if you want graphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)
- ME(Management Engine) => you do not have to touch it(just leave it where it is)
- EC(Embedded Controller) => you do not have to touch it(just leave it where it is)
A build instruction has been written on bitbucket.
T420 has an SOIC-8 flash chip of 8M. It's subdivided in roughly in 3 parts:
- Descriptor (12K)
- ME firmware (5M-12K)
- System flash (3M)
ME firmware is not readable. Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).
Proceeds as follows:
- Turn off your laptop, remove battery and AC adapter.
- Disassemble the T420 laptop as the hardware maintenance manual says. You have to take out the mainboard, because the flash chip is under the magnesium stucture frame.
- Connect your external SPI flasher to the SPI chip and flash it. Using an SOIC-8 clip is recommended.
When the laptop is running coreboot, you can reflash the firmware using flashrom:
flashrom -p internal:laptop=force_I_want_a_brick -w <coreboot image>
Ivy Bridge processor support
Sandy Bridge and Ivy Bridge processor use the same socket, so an Ivy Bridge processor can be installed. To use native graphics init, you should use a patch on gerrit so that coreboot can use the correct code for native graphics init. You can also use a VGA option ROM with SeaBIOS, adding VGA option ROMs for both type of graphics manually is recommended (See the build instructionn above).
Up to now, an i5-3340M and an i7-3720QM(QS version) is tested.