Board:lowrisc/nexys4ddr: Difference between revisions

From coreboot
Jump to navigation Jump to search
No edit summary
No edit summary
Line 2: Line 2:


This coreboot port runs on the lowRISC bitstream for the [https://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/ Nexys 4 DDR] FPGA development board.
This coreboot port runs on the lowRISC bitstream for the [https://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/ Nexys 4 DDR] FPGA development board.
== Getting the bitstream ==
The newest bitstream is available at http://www.lowrisc.org/docs/debug-v0.3/fpga/ (you need the "standalone" .bit file). Because this bitstream implements a deprecated page table format (as specified in the RISC-V Privileged Specification 1.7), a new bitstream will be made available.


== Booting coreboot ==
== Booting coreboot ==
Line 9: Line 13:
* convert the board to an ELF file through util/riscvtools/make-spike-elf.sh
* convert the board to an ELF file through util/riscvtools/make-spike-elf.sh
* Copy coreboot.elf on a µSD card as boot.bin
* Copy coreboot.elf on a µSD card as boot.bin
* Attach the Nexys4DDR to a computer over USB. Two serial ports, called /dev/ttyUSB0 and /dev/ttyUSB1 on linux, should appear. Connect to /dev/ttyUSB1 through microcom or a similar program.
* Boot the FPGA board with this µSD card
* Boot the FPGA board with this µSD card

Revision as of 18:42, 22 December 2016

"lowRISC is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. We aim to complete our SoC design this year [2016]."

This coreboot port runs on the lowRISC bitstream for the Nexys 4 DDR FPGA development board.

Getting the bitstream

The newest bitstream is available at http://www.lowrisc.org/docs/debug-v0.3/fpga/ (you need the "standalone" .bit file). Because this bitstream implements a deprecated page table format (as specified in the RISC-V Privileged Specification 1.7), a new bitstream will be made available.

Booting coreboot

  • make crossgcc-riscv
  • select the board in menuconfig
  • convert the board to an ELF file through util/riscvtools/make-spike-elf.sh
  • Copy coreboot.elf on a µSD card as boot.bin
  • Attach the Nexys4DDR to a computer over USB. Two serial ports, called /dev/ttyUSB0 and /dev/ttyUSB1 on linux, should appear. Connect to /dev/ttyUSB1 through microcom or a similar program.
  • Boot the FPGA board with this µSD card