Difference between revisions of "Developer Manual"

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====Supporting a new board with a unsupported cpu, chipset or superIO====
====Supporting a new board with a unsupported cpu, chipset or superIO====


If your new board uses a cpu, chipset or superIO not supported by coreboot then you will have a lot of work in front of you. You will need developer data sheets for the cpu, chipset and superIO. AMD has been releasing data sheets to the public that includes most of the information required to support a new cpu and chipset. AMD has also been releasing complete coreboot patches to many of their recent cpu's and chipsets. Many of the superIO vendors have public documents available. Intel has been closed about releasing specifications at a low enough level to support a new cpu or chipset. Specifications are generally only provided to high volume OEM's. New developers requesting data sheets might have to wait for several months after singing NDA's until they receive the specifications.
If your new board uses a cpu, chipset or superIO not supported by coreboot then you will have a lot of work in front of you. You will need developer data sheets for the cpu, chipset and superIO. AMD has been releasing data sheets to the public that includes most of the information required to support a new cpu and chipset. AMD has also been releasing complete coreboot patches to many of their recent cpu's and chipsets. Many of the superIO vendors have public documents available. Intel has been closed about releasing specifications at a low enough level to support a new cpu or chipset. Specifications are generally only provided to high volume OEM's. New developers requesting data sheets might have to wait for several months after signing NDA's until they receive the specifications.


== Recommended hardware and software tools ==
== Recommended hardware and software tools ==
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# Execution continues with various '''mainboardinit''' fragments:
# Execution continues with various '''mainboardinit''' fragments:
## '''__fpu_start''' from '''cpu/x86/fpu_enable.inc'''.
## '''__fpu_start''' from '''cpu/x86/fpu_enable.inc'''.
## '''(unlabeled)''' from '''cpu/x86/enable_sse.inc'''
## '''(unlabeled)''' from '''cpu/x86/sse_enable.inc'''
## Some CPUs enable their on-chip cache to be used temporarily as a scratch RAM (stack), e.g. '''cpu/amd/model_lx/cache_as_ram.inc'''.
## Some CPUs enable their on-chip cache to be used temporarily as a scratch RAM (stack), e.g. '''cpu/amd/model_lx/cache_as_ram.inc'''.
# The final '''mainboardinit''' fragment is mainboard-specific, in C, called '''romstage.c'''. For non-cache-as-RAM targets, it is compiled with '''romcc'''. It includes and uses other C-code fragments for:
# The final '''mainboardinit''' fragment is mainboard-specific, in C, called '''romstage.c'''. For non-cache-as-RAM targets, it is compiled with '''romcc'''. It includes and uses other C-code fragments for:
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See [[Developer Manual/Bootblock]]
See [[Developer Manual/Bootblock]]
== Reading Coreboot Crash Dumps Overview ==
See [[Developer Manual/Crashdump]]


== Memory map ==
== Memory map ==
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When a device in '''devicetree.cb''' is found during the coreboot PCI/system scan process the functions to do customized initialization are called via the '''device_operations''' and the '''chip_operations''' structures. You will find these structures in the devices source files.
When a device in '''devicetree.cb''' is found during the coreboot PCI/system scan process the functions to do customized initialization are called via the '''device_operations''' and the '''chip_operations''' structures. You will find these structures in the devices source files.
See [[Creating A devicetree.cb]].


=== irq_table.c ===
=== irq_table.c ===

Latest revision as of 16:10, 1 September 2014