Difference between revisions of "Developer Manual"

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# Execution continues with various '''mainboardinit''' fragments:
# Execution continues with various '''mainboardinit''' fragments:
## '''__fpu_start''' from '''cpu/x86/fpu_enable.inc'''.
## '''__fpu_start''' from '''cpu/x86/fpu_enable.inc'''.
## '''(unlabeled)''' from '''cpu/x86/enable_sse.inc'''
## '''(unlabeled)''' from '''cpu/x86/sse_enable.inc'''
## Some CPUs enable their on-chip cache to be used temporarily as a scratch RAM (stack), e.g. '''cpu/amd/model_lx/cache_as_ram.inc'''.
## Some CPUs enable their on-chip cache to be used temporarily as a scratch RAM (stack), e.g. '''cpu/amd/model_lx/cache_as_ram.inc'''.
# The final '''mainboardinit''' fragment is mainboard-specific, in C, called '''romstage.c'''. For non-cache-as-RAM targets, it is compiled with '''romcc'''. It includes and uses other C-code fragments for:
# The final '''mainboardinit''' fragment is mainboard-specific, in C, called '''romstage.c'''. For non-cache-as-RAM targets, it is compiled with '''romcc'''. It includes and uses other C-code fragments for:
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See [[Developer Manual/Bootblock]]
See [[Developer Manual/Bootblock]]
== Reading Coreboot Crash Dumps Overview ==
See [[Developer Manual/Crashdump]]


== Memory map ==
== Memory map ==
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When a device in '''devicetree.cb''' is found during the coreboot PCI/system scan process the functions to do customized initialization are called via the '''device_operations''' and the '''chip_operations''' structures. You will find these structures in the devices source files.
When a device in '''devicetree.cb''' is found during the coreboot PCI/system scan process the functions to do customized initialization are called via the '''device_operations''' and the '''chip_operations''' structures. You will find these structures in the devices source files.
See [[Creating A devicetree.cb]].


=== irq_table.c ===
=== irq_table.c ===

Latest revision as of 16:10, 1 September 2014