Difference between revisions of "Developer Manual"

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(describe the path an Intel architecture mainboard takes from reset to payload execution)
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== Hardware Overview ==
== Hardware Overview ==
=== Intel Architecture ===
==== Hardware Reset ====
{| border="1"
|+Intel 64 and IA-32 Architectures Software Developers Manual, Volume 3A, Section 9.1.4
|
''The first instruction that is fetched and executed following a hardware reset is located at physical address 0xFFFFFFF0. This address is 16 bytes below the processors uppermost physical address.  The EPROM containing the software-initialization code must be located at this address.''
''The address 0xFFFFFFF0 is beyond the 1-MByte addressable range of the processor while in real-address mode. The  processor is initialized to this starting address as follows. The CS register has two parts: the visible segment selector part and the hidden base address part. In real-address mode, the base address is normally formed by shifting the 16-bit segment selector value 4 bits to the left to produce a 20-bit base address. However, during a hardware reset, the segment selector in the CS register is loaded with 0xF000 and the base address is loaded with 0xFFFF0000. The starting address is thus formed by adding the base address to the value in the EIP register (that is, 0xFFFF0000 + 0xFFF0 = 0xFFFFFFF0).''
''The first time the CS register is loaded with a new value after a hardware reset, the processor will follow the normal rule for address translation in real-address mode (that is, [CS base address = CS segment selector * 16]).  To insure that the base address in the CS register remains unchanged until the EPROM based software-initialization code is completed, the code must not contain a far jump or far call or allow an interrupt to occur (which would cause the CS selector value to be changed).''
|}
==== FWH/LPC Flash Memory ====
Modern mainboards are often equipped with Firmware Hub (<code>FWH</code>) or Low Pin Count (<code>LPC</code>) flash memory used to store the system bootloader ("BIOS").  Execution begins by fetching instructions 16 bytes below the flash memory's uppermost physical address.


== coreboot Overview ==
== coreboot Overview ==
=== View From The CPU: Intel Architecture ===
# at <code>0xFFFFFFF0</code>, start execution at <code>reset_vector</code> from src/cpu/x86/16bit/reset16.inc, which simply jumps to <code>_start</code>
# <code>_start</code> from src/cpu/x86/16bit/entry16.inc, invalidates the TLBs, sets up a GDT for selector 0x08 (code) and 0x10 (data), switches to protected mode, and jumps to <code>__protected_start</code> (setting the CS to the new selector 0x08).  The selectors provide full flat access to the entire physical memory map.
# <code>__protected_start</code> from src/cpu/x86/32bit/entry32.inc, sets all other segment registers to the 0x10 selector
# execution continues with various <code>mainboardinit</code> fragments:
## <code>__fpu_start</code> from cpu/x86/fpu/enable_fpu.inc
## <code>(unlabeled)</code> from cpu/x86/sse/enable_sse.inc
## some CPUs enable their on-chip cache to be used temporarily as a scratch RAM (stack), e.g. cpu/amd/model_lx/cache_as_ram.inc
# the final <code>mainboardinit</code> fragment is mainboard-specific, in 'C', called auto.c (or cache_as_ram_auto.c).  It is compiled with 'romcc', and it includes and uses other C-code fragments for:
## initializing MSRs, MTTRs, APIC
## setting up the Southbridge minimally ("early setup")
## setting up SuperIO serial
## initializing the console
## initializing RAM controller and RAM itself
# execution continues at <code>__main</code> from src/arch/i386/init/crt0.S.lb, where the non-romcc 'C' coreboot code is copied (possibly decompressed) to RAM, then the RAM entry point is jumped to.
# the RAM entry point is <code>_start</code> arch/i386/lib/c_start.S, where new descriptor tables are set up, the stack and BSS are cleared, the IDT is initialized, and <code>hardwaremain( )</code> is called (operation is now full 32-bit protected mode 'C' program with stack)
# <code>hardwaremain( )</code> is from boot/hardwaremain.c, the console is initialized, devices are enumerated and initialized, configured and enabled
# the payload is called, either via <code>elfboot( )</code> from boot/elfboot.c, or <code>filo( )</code> from boot/filo.c


== Serial output and the Super I/O ==
== Serial output and the Super I/O ==

Revision as of 21:29, 22 February 2008