Difference between revisions of "Developer Manual"

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## <code>(unlabeled)</code> from cpu/x86/sse/enable_sse.inc
## <code>(unlabeled)</code> from cpu/x86/sse/enable_sse.inc
## some CPUs enable their on-chip cache to be used temporarily as a scratch RAM (stack), e.g. cpu/amd/model_lx/cache_as_ram.inc
## some CPUs enable their on-chip cache to be used temporarily as a scratch RAM (stack), e.g. cpu/amd/model_lx/cache_as_ram.inc
# the final <code>mainboardinit</code> fragment is mainboard-specific, in 'C', called auto.c (or cache_as_ram_auto.c)It is compiled with 'romcc', and it includes and uses other C-code fragments for:
# the final <code>mainboardinit</code> fragment is mainboard-specific, in 'C', called romstage.c.  For non-cache-as-RAM targets, it is compiled with 'romcc'.  It includes and uses other C-code fragments for:
## initializing MSRs, MTTRs, APIC
## initializing MSRs, MTTRs, APIC
## setting up the Southbridge minimally ("early setup")
## setting up the Southbridge minimally ("early setup")

Revision as of 19:50, 13 February 2010