Difference between revisions of "Developer Manual"
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==== FWH/LPC Flash Memory ==== | ==== FWH/LPC Flash Memory ==== | ||
Modern mainboards are often equipped with Firmware Hub (<code>FWH</code>) or Low Pin Count (<code>LPC</code>) flash memory used to store the system bootloader ("BIOS"). Execution begins by fetching instructions 16 bytes below the flash memory's uppermost physical address. | Modern mainboards are often equipped with Firmware Hub (<code>FWH</code>) or Low Pin Count (<code>LPC</code>) flash memory used to store the system bootloader ("BIOS"). Execution begins by fetching instructions 16 bytes below the flash memory's uppermost physical address. | ||
== coreboot Overview == | == coreboot Overview == | ||
=== View From The CPU: Intel Architecture === | === View From The CPU: Intel Architecture === | ||
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# <code>hardwaremain( )</code> is from boot/hardwaremain.c, the console is initialized, devices are enumerated and initialized, configured and enabled | # <code>hardwaremain( )</code> is from boot/hardwaremain.c, the console is initialized, devices are enumerated and initialized, configured and enabled | ||
# the payload is called, either via <code>elfboot( )</code> from boot/elfboot.c, or <code>filo( )</code> from boot/filo.c | # the payload is called, either via <code>elfboot( )</code> from boot/elfboot.c, or <code>filo( )</code> from boot/filo.c | ||
== Memory map== | == Memory map== | ||
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=== Config.lb === | === Config.lb === | ||
The mainboard config.lb contains many build and platform configuration settings. One of the most important items is the mainboard device list. | The mainboard config.lb contains many build and platform configuration settings. One of the most important items is the mainboard device list. | ||
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* Multiple files in src/mainboard/''vendorname''/''mainboardname'' (replace ''vendorname'' and ''mainboardname'', of course). | * Multiple files in src/mainboard/''vendorname''/''mainboardname'' (replace ''vendorname'' and ''mainboardname'', of course). | ||
* A file targets/''vendorname''/''mainboardname''/Config.lb which specifies a few target-specific config options, e.g. the ROM chip size, the payload, etc. | * A file targets/''vendorname''/''mainboardname''/Config.lb which specifies a few target-specific config options, e.g. the ROM chip size, the payload, etc. | ||
== Documentation and datasheets == | == Documentation and datasheets == | ||
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These external documents and slides explain fundamental concepts of hardware that coreboot supports. | These external documents and slides explain fundamental concepts of hardware that coreboot supports. | ||
'''Interrupts''' | |||
* [http://www.bsdcan.org/2007/schedule/attachments/13-PCI_Interrupts_for_x86_Machines_under_FreeBSD_John_Baldwin PCI Interrupts on x86 machines] from John Baldwin | * [http://www.bsdcan.org/2007/schedule/attachments/13-PCI_Interrupts_for_x86_Machines_under_FreeBSD_John_Baldwin PCI Interrupts on x86 machines] from John Baldwin | ||
* [http://www.microsoft.com/whdc/system/CEC/ACPI-MP.mspx PCI IRQ Routing on a Multiprocessor ACPI System] at Microsoft's Windows Hardware Developer Central | * [http://www.microsoft.com/whdc/system/CEC/ACPI-MP.mspx PCI IRQ Routing on a Multiprocessor ACPI System] at Microsoft's Windows Hardware Developer Central | ||
'''System Managment Mode''' | |||
* [http://www.rcollins.org/ddj/Jan97/Jan97.html System Managment Mode Overview] by Robery R. Collins | * [http://www.rcollins.org/ddj/Jan97/Jan97.html System Managment Mode Overview] by Robery R. Collins | ||
=== Specific datasheets === | === Specific datasheets === | ||
See [[Datasheets]]. | |||
{{GPL}} | {{GPL}} | ||