Difference between revisions of "Project Ideas"

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(coreboot Projects: console via SMBus)
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== coreboot on the open source Berkeley RISC V processor ==
We've got a preliminary port of coreboot to the Berkeley RISC V. Much work remains. There are three chips coming out end of 2015 and it would be great to be ready for them.
This work would be to make the build process bullet proof and then show that we can boot linux on RISCV under coreboot.
* http://http://riscv.org/
'''Skill Level'''
* coreboot and firmware: competent
* linux: competent
* LAMP setup
<br/>Ron Minnich<br/>

== coreboot mainboard test result reporting ==
== coreboot mainboard test result reporting ==

Revision as of 04:23, 7 March 2015