# Copyright (C) 2022 - 2025 Advanced Micro Devices, Inc. All rights reserved.

#
#
#

#
#  AMD open Silicon Initialization Library
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#
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# Platform Configuration Settings
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#
# The following items are placed in the platform address map by the
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#
# porting Engineer. These locations must be propagated into openSIL.
#

#
#
#
CONFIG_PLAT_APOB_ADDRESS=0x76B00000
CONFIG_PSP_BIOS_BIN_BASE=0x76C00000
CONFIG_PSP_BIOS_BIN_SIZE=0x400000
# end of Platform Configuration Settings

#
# AMD Processor(s) Selection
#

#
#  This is the list of supported AMD processors for openSIL. Please
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#
#  select the Socket and processor designed into your motherboard.
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#
#
#

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# Show All Configs
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#
#
#

#
#  This configuration is used by CI to ensure all SoC can coexist.
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#  The default value is 'n' and should not be modified manually.
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#  DO NOT MODIFY THIS VALUE
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#
#
#
# CONFIG_HAVE_ALL_YES is not set
# end of Show All Configs

# CONFIG_SOC_F19M10 is not set
CONFIG_SOC_F1AM00=y
# end of AMD Processor(s) Selection

#
# AMD Silicon Feature Settings
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#
#
#

#
#  The available silicon devices and features are dependent upon
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#  which AMD processor(s) have been selected for inclusion into
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#  the platform build.
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#
#

#
# CCX Common - Controls that are common to all versions of IP: CCX
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#
#
#
CONFIG_CCX_APIC_MODE=0xFF
CONFIG_CCX_DOWNCORE_MODE=0
CONFIG_CCX_CCD_MODE=0
CONFIG_CCX_SMT_MODE=1
CONFIG_CCX_CSTATE_ENABLE=1
CONFIG_CCX_CSTATE_IO_ADDR=0x0813
CONFIG_CCX_CSTATE_CC6_ENABLE=1
CONFIG_CCX_CPB_ENABLE=1
CONFIG_CCX_SMEE_ENABLE=0
CONFIG_CCX_HMKEE_ENABLE=0
CONFIG_CCX_FSRM_ENABLE=0
CONFIG_CCX_ERMS_ENABLE=0
CONFIG_CCX_RMSS_ENABLE=0
CONFIG_CCX_P0_SETTING=2
CONFIG_CCX_P0_FREQ=0
CONFIG_CCX_AUTO_FREQ=0xFFFFFFFF
CONFIG_CCX_P0_VID32=0
CONFIG_CCX_AUTO_VID=0xFFFFFFFF
# end of CCX Common Configuration
# end of Compute Core Complex (CCX) Device

CONFIG_IOAPIC_MMIO_ADDRESS_RESERVED_ENABLE=1
CONFIG_IOAPIC_ID_PREDEFINE_EN=0
CONFIG_IOAPIC_ID_BASE=0xF1
CONFIG_NBIO_GLOBAL_CG_OVERRIDE=0x0f
CONFIG_SSTUNL_CLK_GATING=1
CONFIG_NBIF_MGCG_HYSTERESIS=0
CONFIG_SYSHUB_MGCG_CLK_GATING=0
CONFIG_SYSHUB_MGCG_HYSTERESIS=0
CONFIG_IOHC_CLK_GATING_SUPPORT=1
CONFIG_NTB_CLOCK_GATING_ENABLE=1
CONFIG_IOHC_PG_ENABLE=1
CONFIG_IOHC_NONPCI_BAR_INIT_SMU=1
CONFIG_IOHC_NONPCI_BAR_INIT_DBG=0
CONFIG_IOHC_NONPCI_BAR_INIT_FAST_REG=0
CONFIG_IOHC_NONPCI_BAR_INIT_FAST_REGCTL=0
CONFIG_IOMMU_SUPPORT=1
CONFIG_IOMMU_L1_CLOCK_GATING_EN=1
CONFIG_IOMMU_L2_CLOCK_GATING_EN=1
CONFIG_IOMMU_AVIC_SUPPORT=0
CONFIG_IOMMU_MMIO_ADDRESS_RESERVED_ENABLE=1
CONFIG_PCIE_ECRC_ENABLEMENT=1
CONFIG_AUTO_SPEED_CHANGE_EN=0
CONFIG_PCIE_ARI_SUPPORT=1
CONFIG_RX_MARGIN_PERSISTENCE_MODE=1
CONFIG_AER_ENABLE=1
CONFIG_ACS_ENABLE=1
CONFIG_PCIE_LTR_ENABLE=1
CONFIG_TPH_COMPLETER_ENABLE=1
CONFIG_SRIOV_EN_DEV0F1=0
CONFIG_ARI_EN_DEV0F1=0
CONFIG_AER_EN_DEV0F1=0
CONFIG_ACS_EN_DEV0F1=0
CONFIG_ATS_EN_DEV0F1=0
CONFIG_PASID_EN_DEV0F1=0
CONFIG_RTR_EN_DEV0F1=0
CONFIG_PRI_EN_DEV0F1=0
CONFIG_ATC_ENABLE=0
CONFIG_ACS_EN_RCC_DEV0=0
CONFIG_AER_EN_RCC_DEV0=0
CONFIG_ACS_SOURCE_VAL_STRAP5=1
CONFIG_ACS_TRANSLATIONAL_BLOCKING_STRAP5=1
CONFIG_ACS_P2P_REQ_STRAP5=1
CONFIG_ACS_P2P_COMP_STRAP5=1
CONFIG_ACS_UPSTREAM_FWD_STRAP5=1
CONFIG_ACS_P2P_EGRESS_STRAP5=0
CONFIG_ACS_DIRECT_TRANSLATED_STRAP5=1
CONFIG_ACS_SSID_EN_STRAP5=1
CONFIG_DLF_EN_STRAP1=1
CONFIG_PHY_16GT_STRAP1=1
CONFIG_MARGIN_EN_STRAP1=1
CONFIG_PRI_EN_PAGE_REQ=1
CONFIG_PRI_RESET_PAGE_REQ=1
CONFIG_ACS_SOURCE_VAL=1
CONFIG_ACS_TRANSLATIONAL_BLOCKING=0
CONFIG_ACS_P2P_REQ=1
CONFIG_ACS_P2P_COMP=1
CONFIG_ACS_UPSTREAM_FWD=1
CONFIG_ACS_P2P_EGRESS=0
CONFIG_AMD_MASK_DPC_CAPABILITY=0
CONFIG_PCIE_SPEED_CONTROL=0x0F
CONFIG_PWR_EN_DEV0F1=0
CONFIG_TLP_PREFIX_SETTING=0
CONFIG_RCC_DEV0_EXTENDED_FMT_SUPPORTED=0
CONFIG_DLF_CAP_EN=1
CONFIG_DL_FEX_EN=1
CONFIG_PRE_CODE_REQUEST_ENABLE=0
CONFIG_ADVERTISE_EQ_TO_HIGH_RATE_SUPPORT=0
CONFIG_FABRIC_SDXI=0
CONFIG_ESM_EN_ALL_ROOT_PORTS=0
CONFIG_SEV_SNP_SUPPORT=0

#
#
#

#
# IP MPIO Common - Controls that are common to all versions of the IP: MPIO
#
CONFIG_MPIO_CLOCKGATING_ENABLE=1
CONFIG_MPIO_TIMINGCTRL_ENABLE=0
CONFIG_PCIE_LINK_RECEIVER_DETECT_TIMEOUT=0
CONFIG_PCIE_LINK_RESET_TO_TRAINING_TIMEOUT=0
CONFIG_PCIE_LINK_L0_STATE_TIMEOUT=0
CONFIG_MPIO_EXACT_MATCH_ENABLE=0
CONFIG_MPIO_PHY_VALID=1
CONFIG_MPIO_PHY_PROGRAMMING=1
CONFIG_MPIO_SKIP_PSP_MSG=1
CONFIG_MPIO_SAVE_RESTORE_MODE=0xFF
CONFIG_MPIO_ALLOW_PCIE_POLLING=0x00
CONFIG_MPIO_HOT_PLUG_MODE=0xFF

#
# MPIO SIRS Configurations
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#
# The items in this sub-menu are used for configuration of various
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# PCIe Separate Reference Clock with Independent Speed (SIRS)
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#
# options used by the MPIO IP.
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#
#
CONFIG_MPIO_PCIE_SIRS_CONTROL=0xFF
CONFIG_MPIO_PCIE_SIRS_SKIP_INTERVAL=0x00
CONFIG_MPIO_SIRS_SKIP_INTERVAL_SELECT=1
CONFIG_MPIO_SIRS_CONFIG_TYPE=0
CONFIG_MPIO_SIRS_AUTO_DETECT_MODE=0x0F
CONFIG_MPIO_SIRS_AUTODETECT_FACTOR=0
CONFIG_MPIO_PCIE_SIRS_SKP_TRANSMISSION_CONTROL=0x00
CONFIG_MPIO_PCIE_SIRS_SKP_RECPTION_CONTROL=0x00
# end of MPIO SIRS Configurations

CONFIG_MPIO_CXL_PORT_CONTROL=1
CONFIG_MPIO_CXL_CORRECTABLE_ERROR_LOGGING=1
CONFIG_MPIO_CXL_UNCORRECTABLE_ERROR_LOGGING=1
CONFIG_MPIO_ADVANCED_ERROR_REPORTING_ENABLE=1
CONFIG_MPIO_PCIE_MULTICAST_ENABLE=0
CONFIG_MPIO_RECEIVE_ERROR_ENABLE=0
CONFIG_MPIO_EARLY_BMC_LINK_TRAIN_ENABLE=1
CONFIG_MPIO_EARLY_BMC_LINK_SOCKET=0x00
CONFIG_MPIO_EARLY_BMC_LINK_LANE=134
CONFIG_MPIO_EARLY_BMC_LINK_DIE=0x00
CONFIG_MPIO_SURPRISE_DOWN_ENABLE=1
CONFIG_MPIO_PCIE_LINK_TRAINING_SPEED=0
CONFIG_MPIO_RX_MARGIN_ENABLE=1
CONFIG_MPIO_PCIE_CV_TEST_CONFIG=1
CONFIG_MPIO_PCIE_ARI_SUPPORT=1
CONFIG_MPIO_TOGGLE_NBIO_TO_SC=0
CONFIG_MPIO_TOGGLE_NBIO_IGNORE_CTO_ERROR=1

#
# MPIO SSID Settings
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#
# The items in this sub-menu are used for configuration of various
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#
# SSIDs used by the MPIO IP. The SSIDs are used by the PCIE
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#
# interface to configure register settings for different platforms
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#
# after MPIO initialization.
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#
#
#
CONFIG_NBIO_CONTROLLER_SSID=0x00000000
CONFIG_IOMMU_CONTROLLER_SSID=0x00000000
CONFIG_PSP_CCP_CONTROLLER_SSID=0x00000000
CONFIG_NTB_CCP_CONTROLLER_SSID=0x00000000
CONFIG_NBIF0_CONTROLLER_SSID=0x00000000
CONFIG_NTB_CONTROLLER_SSID=0x00000000
# end of MPIO SSID Settings

CONFIG_PCIE_SUBSYSTEM_DEVICE_ID=0
CONFIG_PCIE_SUBSYSTEM_VENDOR_ID=0
CONFIG_MPIO_GPP_ATOMIC_OPS=1
CONFIG_MPIO_GPFXATOMIC_OPS=1
CONFIG_MPIO_EDB_ERROR_REPORTING_ENABLE=0
CONFIG_MPIO_OPN_SPARE=0
CONFIG_AMD_PRE_SIL_CONTROL=0
CONFIG_MPIO_ANCILLARY_DATA_SUPPORT_ENABLE=0
CONFIG_MPIO_AFTER_RESET_DELAY=0
CONFIG_MPIO_EARLY_LINK_TRAINING_ENABLE=0
CONFIG_CHOICE_USE_PLATFORM_CONFIG_DEFAULT=y
CONFIG_MPIO_EXPOSE_UNUSED_PCIE_PORTS=0xFF
CONFIG_CHOICE_NO_LINK_SPEED_LIMIT=y
CONFIG_MPIO_MAX_PCIE_LINK_SPEED=0
CONFIG_MPIO_SATA_PHY_TUNING=0
CONFIG_PCIE_LINK_COMPLIANCE_MODE_ENABLE=1
CONFIG_MPIO_MCTP_SUPPORT_ENABLE=0
CONFIG_SBR_BROKEN_LANE_AVOIDANCE_ENABLE=1
CONFIG_AUTO_FULL_MARGINING_SUPPORT_ENABLE=1
CONFIG_GEN3_PCIE_PRESET_MASK=0xFFFFFFFF
CONFIG_GEN4_PCIE_PRESET_MASK=0xFFFFFFFF
CONFIG_GEN5_PCIE_PRESET_MASK=0xFFFFFFFF
CONFIG_CHOICE_ACTIVE_STATE_PWR_MGMT_AUTO=y
CONFIG_PCIE_LINK_ACTIVE_STATE_PWR_MGMT=0xFF
CONFIG_MCTP_MASTER_PCI_ADDR_SEGMENT=0
CONFIG_MCTP_MASTER_PCI_ADDR=0
CONFIG_CHOICE_PRESENCE_DETECT_AUTO=y
CONFIG_MPIO_HOT_PLUG_PRESENCE_DETECTION_MODE=0xFF
CONFIG_CHOICE_MAX_PAYLOAD_SIZE_DEFAULT=y
CONFIG_PCIE_HOTPLUG_PORT_MAX_PAYLOAD_SIZE=0xFF
CONFIG_MPIO_HOTPLUG_UMB_SUPPORT_ENABLE=1
CONFIG_LINK_DISABLE_AT_POWER_OFF_DELAY=0x00
CONFIG_MPIO_ENABLE_2SPC_GEN4=0
CONFIG_MPIO_NON_PEIE_COMPLIANT_SUPPORT=1
CONFIG_MPIO_SLT_MODE_ENABLE=0
CONFIG_MPIO_FIFO_RD_PTR_OFFSET=0xEC
CONFIG_MPIO_SDXI_ENABLE=1
CONFIG_MPIO_DATA_OBJ_EXCHANGE_ENABLE=1
CONFIG_MPIO_SFI_FEATURES_ENABLE=0
CONFIG_CHOICE_GEN3_UPSTREAM_PRESET_DEFAULT=y
CONFIG_MPIO_GEN3_UPSTREAM_PRESET=0xFF
CONFIG_CHOICE_GEN3_DOWNSTREAM_PRESET_DEFAULT=y
CONFIG_MPIO_GEN3_DOWNSTREAM_PRESET=0xFF
CONFIG_MPIO_GEN3_PRESET_MASK_CONFIG=0xFF
CONFIG_MPIO_GEN3_PCIE_LC_MASK_CONTROL_DEFAULT=0x00000000
CONFIG_CHOICE_GEN4_UPSTREAM_PRESET_DEFAULT=y
CONFIG_MPIO_GEN4_UPSTREAM_PRESET=0xFF
CONFIG_CHOICE_GEN4_DOWNSTREAM_PRESET_DEFAULT=y
CONFIG_MPIO_GEN4_DOWNSTREAM_PRESET=0xFF
CONFIG_MPIO_GEN4_PRESET_MASK_CONFIG=0xFF
CONFIG_MPIO_GEN4_PCIE_LC_MASK_CONTROL_DEFAULT=0x00000000
CONFIG_CHOICE_GEN5_UPSTREAM_PRESET_DEFAULT=y
CONFIG_MPIO_GEN5_UPSTREAM_PRESET=0xFF
CONFIG_CHOICE_GEN5_DOWNSTREAM_PRESET_DEFAULT=y
CONFIG_MPIO_GEN5_DOWNSTREAM_PRESET=0xFF
CONFIG_MPIO_GEN5_PRESET_MASK_CONFIG=0xFF
CONFIG_MPIO_GEN5_PCIE_LC_MASK_CONTROL_DEFAULT=0x00000000
# end of MultiPath Input Output (MPIO)

CONFIG_HAVE_SDXI_BRH=y

#
# Cacheable Direct Memory Access (SDXI)
#

#
#
#

#
#  The SDXI IP adds the capability to
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#  perform certain fabric writes directly
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#  into cache rather than to the DRAM first.
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#

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#
#

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# IP SDXI Common - Controls that are common to all versions of the IP: SDXI
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CONFIG_SDXI_SMART_DATA_CACHE_INJECTION_ENABLE=0
# end of Cacheable Direct Memory Access (SDXI)

CONFIG_HAVE_FCH_KUNLUN=y

#
# FCH Device
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#
#
#

#
# The FCH is a bridge device underwhich many of the
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# legacy and traditional components of a PC are located.
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#
#
#

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# FCH-AB System Bus interface for FCH
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#
#
#

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#  The AB block is the system bus interface for the sub-components
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#  located in the FCH. These include clock gating, reset and
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#
#  DMA control options.
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#
#
#
CONFIG_FCH_ALINK_CLK_GATING=1
CONFIG_FCH_BLINK_CLK_GATING=1
CONFIG_FCH_AB_CLK_GATING=1
CONFIG_FCH_SLOW_BCLOCK=0
CONFIG_FCH_RESET_SYNC_FLOOD=0
CONFIG_FCH_DMA_SIZE=1
CONFIG_FCH_MEM_PWR_SAVING=1
CONFIG_FCH_SDP_PWR_SAVING=1
CONFIG_FCH_SDP_CLK_GATING=1
CONFIG_FCH_XDMA_LIMIT_SIZE=0
CONFIG_FCH_XDMA_PWR_SAVING=0
CONFIG_FCH_XDMA_NPR_COUNT=0
CONFIG_FCH_XDMA_ORDER_DIS=0
CONFIG_FCH_SDP_BYPASS_PACK=0
CONFIG_FCH_SDP_INTERLEAVING=0
# end of FCH-AB System Bus interface for FCH

#
# FCH-ACPI, Power and Misc controls
#

#
#
#

#
#  The HwAcpi component provides controls for ACPI related items,
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#
#  System power options and various platform controls.
#

#
#
#
CONFIG_SPREAD_SPECTRUM=1
CONFIG_CHOICE_PWR_STAY_OFF=y
CONFIG_POWER_FAIL_RETURN_STATE=0
CONFIG_CHOICE_STRESS_DISABLE=y
CONFIG_STRESS_RESET_MODE=0
CONFIG_CLEAR_THRMTRIP_STATUS=0
CONFIG_ENABLE_BOOT_TIMER=1
CONFIG_BOOT_TIMER_RESET=0
CONFIG_TOGGLE_ALL_PWRGOOD=0
CONFIG_RELEASE_SPD_CTL_BMC=1
CONFIG_DIMM_TELEMETRY=0
# end of FCH-ACPI, Power and Misc controls

#
# FCH-ISA Bus interface for FCH
#

#
#
#

#
#  The ISA bus is a legacy system bus for devices
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#
#  such as: LPC, SPI, TPM.
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#
#
#

#
# LPC Bus Configurations
#
CONFIG_LPC_BUS_ENABLE=1
# end of LPC Bus Configurations

#
# SPI Bus Configurations
#
CONFIG_CHOICE_33MHZ_STD=y
CONFIG_SPI_STD_SPEED=2
CONFIG_CHOICE_IGNORE_WRTSPEED=y
CONFIG_SPI_WRT_SPEED=0
CONFIG_CHOICE_IGNORE_TPMSPEED=y
CONFIG_SPI_TPM_SPEED=0
# end of SPI Bus Configurations
# end of FCH-ISA Bus interface for FCH
# end of FCH Device
# end of AMD Silicon Feature Settings

# CONFIG_HAVE_EXAMPLE is not set
