## SPDX-License-Identifier: GPL-2.0-only

config SOC_AMD_COMMON_BLOCK_SPI
	bool
	select SPI_FLASH_SFDP if SPI_FLASH
	help
	  Select this option to add FCH SPI controller functions to the build.
	  This overwrites the structure spi_flash_ops to use FCH SPI code
	  instead of individual SPI specific code.

config SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS
	bool
	depends on SOC_AMD_COMMON_BLOCK_SPI
	help
	  Select this option when the FCH SPI controller MMIO can be written to
	  with DWORDs instead of just BYTEs. This is supported since AMD Familiy
	  17h Model A0h.

config SOC_AMD_COMMON_BLOCK_SPI_DEBUG
	bool "Enable SPI debugging"

config SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST
	bool
	depends on !SOC_AMD_STONEYRIDGE
	help
	  Select this option to keep the 4 DWORD burst support enabled.

config SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3
	bool
	default y if ROM_SIZE > 0x01000000
	depends on !SOC_AMD_PICASSO && !SOC_AMD_STONEYRIDGE
	depends on !SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
	depends on USE_X86_64_SUPPORT
	# Enable X86_CUSTOM_BOOTMEDIA because the fast SPI controller
	# driver provides a custom boot media device when multiple decode
	# windows are used for the BIOS region.
	select X86_CUSTOM_BOOTMEDIA
	help
	  AMD specific SPI flash access. The lower 16MiB of the SPI flash are
	  memory mapped on the ROM2 window and the upper SPI flash is mapped using
	  the ROM3 window in high MMIO. The ROM3 window maps up to 64MiB of the
	  SPI flash. The default address of ROM3 is below 1024GiB address boundary
	  and thus can only be used in x86_64 mode.

config SOC_AMD_COMMON_BLOCK_SPI_MMAP
	def_bool y
	select X86_CUSTOM_BOOTMEDIA
	depends on SOC_AMD_COMMON_BLOCK_SPI
	depends on !SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
	depends on !SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3
	help
	  This option is required when CONFIG_ROM_SIZE is greater than 16 MiB.
	  This flash driver still only mmaps 16 MiB of the flash (depending
	  on SPI straps either the upper or lower part, by default the lower).
	  Developers must take care to place all x86 accessible firmware
	  components in the mmap area.

config EFS_SPI_READ_MODE
	int
	range 0 7
	default 0 if EM100
	default 2
	help
	  SPI read mode to be programmed by the PSP.
	  The numbers in the options below indicate how many wires
	  are utilized for command, address and data. For instance 1-1-2
	  means 1 command, 1 address and 2 data wires.
	    0: Normal Read (up to 33M)
	    1: Reserved
	    2: Dual IO (1-1-2)
	    3: Quad IO (1-1-4)
	    4: Dual IO (1-2-2)
	    5: Quad IO (1-4-4)
	    6: Normal Read (up to 66M)
	    7: Fast Read

config EFS_SPI_SPEED
	int
	range 0 5
	default 3 if EM100
	default 1
	help
	  SPI Fast Speed to be programmed by the PSP.
	    0: 66.66Mhz
	    1: 33.33MHz
	    2: 22.22MHz
	    3: 16.66MHz
	    4: 100MHz
	    5: 800KHz

config EFS_SPI_MICRON_FLAG
	int
	range 0 2
	default 0
	help
	  For Family 17h Model 00h and later SoC the PSP must be aware if a Micron
	  part is present in EFS. Automatic detection (option 2) is available
	  for Family 17h Model 30h-3Fh but is unsupported otherwise.
	    0: Board does not use Micron parts
	    1: Board always uses Micron parts
	    2: Micron parts are optional

config NORMAL_READ_SPI_SPEED
	int
	range 0 5
	default 3 if EM100
	default 1
	help
	  SPI Normal Speed to be programmed by coreboot.
	    0: 66.66Mhz
	    1: 33.33MHz
	    2: 22.22MHz
	    3: 16.66MHz
	    4: 100MHz
	    5: 800KHz

config ALT_SPI_SPEED
	int
	range 0 5
	default 3 if EM100
	default 1
	help
	  SPI ALT Speed to be programmed by coreboot.
	    0: 66.66Mhz
	    1: 33.33MHz
	    2: 22.22MHz
	    3: 16.66MHz
	    4: 100MHz
	    5: 800KHz

config TPM_SPI_SPEED
	int
	range 0 5
	default 3 if EM100
	default 1
	help
	  SPI TPM Speed to be programmed by coreboot.
	    0: 66.66Mhz
	    1: 33.33MHz
	    2: 22.22MHz
	    3: 16.66MHz
	    4: 100MHz
	    5: 800KHz

config SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3
	bool "Enable ROM Armor 3"
	select BOOT_DEVICE_NOT_SPI_FLASH
	select BOOT_DEVICE_MEMORY_MAPPED
	select BOOT_DEVICE_SUPPORTS_WRITES
	select SPI_FLASH
	select SPI_FLASH_SMM
	depends on HAVE_SMI_HANDLER
	depends on SOC_AMD_COMMON_BLOCK_PSP
	depends on SOC_AMD_COMMON_BLOCK_SPI
	depends on !SOC_AMD_COMMON_BLOCK_PSP_SMI
	help
	  Select this option to use PSP ROM Armor3 protocol for SPI flash
	  operations. This routes SPI read/write/erase operations through
	  the SMM PSP firmware mailbox interface instead of direct FCH SPI
	  controller access. After MPinit the SPI will become read only from
	  x86 perspective and the SPI Ctrl interface will be deactived.

	  You will be only able to write SPI regions that are marked 'writable' or
	  are whitelisted by BIOS directory entries 0x6d (AMD_BIOS_NV_ST). To gain
	  direct access to the SPI flash, you must issue a reboot.

	  WARNING: Since the flash access in the SMI handler is a blocking
	  operation during which all cores stay in SMM, an erase operation may
	  lock up the system for a long enough time to be noticeable. Reads and
	  writes with small data sizes are less problematic. This is AMD
	  specific design and should be enabled when you don't want to service
	  PSP SMI requests (see CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI).

config SOC_AMD_PSP_ROM_ARMOR_64K_ERASE
	bool
	depends on SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3
	default n
	help
	  Enable 64KB erase block size support in addition to 4KB blocks.
	  This can improve erase performance when erasing large regions.
	  The PSP firmware must support 64KB erase commands for this to work.

config SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH
	bool
	depends on SOC_AMD_COMMON_BLOCK_SPI
	depends on !SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3 # TODO: remove once this is supported
	help
	  Select this option when there is a second SPI flash
	  which can be booted of when the primary SPI flash is
	  corrupted. The recovery mechanism is board specific.
	  The secondary SPI flash must be of the same type and
	  same size as the primary SPI flash.

config BACKUP_BOOT_DEVICE_SPI_CHIP_SELECT
	int
	depends on SOC_AMD_COMMON_BLOCK_SPI_BACKUP_SPI_FLASH
	default 1
	help
	  Which chip select line the backup boot device is connected to.
	  The assumption here is that chip select 0 and this one have an SPI flash connected to
	  it. Depending on which chip select of these two we booted from, we deem one of them
	  our backup/secondary (the one we didn't boot from) SPI flash.
