Bug Summary

File:home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/PeSmmMsrHandler.c
Warning:line 106, column 3
Value stored to 'SmmCpuState' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-unknown-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name PeSmmMsrHandler.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -fno-jump-tables -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/build/StmPkg/Core/Runtime -resource-dir /opt/xgcc/lib/clang/17 -include PcdData.h -D COREBOOT32 -D RELEASE -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/EDKII/BaseTools/Source/C/Include/X64 -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/EdkII/MdePkg/Include -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/EdkII/MdePkg/Include/X64 -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Include -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Include/x64 -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/../Init -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/. -internal-isystem /opt/xgcc/lib/clang/17/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/13/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -source-date-epoch 1714465709 -Os -fdebug-compilation-dir=/home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/build/StmPkg/Core/Runtime -ferror-limit 19 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-max-loop 10 -analyzer-output=plist-html -faddrsig -o /cb-build/coreboot_scanbuild.0/PURISM_LIBREM15_V4_STM-scanbuildtmp/2024-05-02-081243-2232343-1/report-0T3oXA.plist -x c /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/PeSmmMsrHandler.c
1/** @file
2 SMM MSR handler
3
4 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13**/
14
15// most of this code was borrowed from the Intel driver
16// howver, the only MSR of interest is the EFER MSR since that is needed to configure
17// the guest VM for 64 bit
18
19// may merge this code back into to Intel reference with VM/PE mods
20
21#include "StmRuntime.h"
22#include "PeStm.h"
23
24/**
25
26 This function is RDMSR handler for VM/PE.
27
28 @param Index CPU index
29
30**/
31VOIDvoid
32PeReadMsrHandler (
33 IN UINT32 CpuIndex
34 )
35{
36 UINT64 Data64;
37 UINT32 MsrIndex;
38 X86_REGISTER *Reg;
39 UINT32 VmType = mHostContextCommon.HostContextPerCpu[CpuIndex].GuestVmType;
40
41 UINT32 Index = 0; // PE/VM only has index as 0
42
43 Reg = &mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Register;
44 MsrIndex = ReadUnaligned32 ((UINT32 *)&Reg->Rcx);
45
46 DEBUG ((EFI_D_INFO, "%ld PeReadMsrHandler - 0x%llx\n", CpuIndex, MsrIndex))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld PeReadMsrHandler - 0x%llx\n"
, CpuIndex, MsrIndex); } } while (((BOOLEAN)(0==1)));
47
48 switch (MsrIndex) {
49 case IA32_EFER_MSR_INDEX0xC0000080:
50 Data64 = mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Efer;
51 break;
52#if 0
53 case IA32_SYSENTER_CS_MSR_INDEX0x174:
54 Data64 = (UINT64)VmRead32 (VMCS_32_GUEST_IA32_SYSENTER_CS_INDEX0x482A);
55 break;
56 case IA32_SYSENTER_ESP_MSR_INDEX0x175:
57 Data64 = (UINT64)VmReadN (VMCS_N_GUEST_IA32_SYSENTER_ESP_INDEX0x6824);
58 break;
59 case IA32_SYSENTER_EIP_MSR_INDEX0x176:
60 Data64 = (UINT64)VmReadN (VMCS_N_GUEST_IA32_SYSENTER_EIP_INDEX0x6826);
61 break;
62
63 case IA32_FS_BASE_MSR_INDEX0xC0000100:
64 Data64 = (UINT64)VmReadN (VMCS_N_GUEST_FS_BASE_INDEX0x680E);
65 break;
66 case IA32_GS_BASE_MSR_INDEX0xC0000101:
67 Data64 = (UINT64)VmReadN (VMCS_N_GUEST_GS_BASE_INDEX0x6810);
68 break;
69#endif
70 default:
71 // since we do not allow the VM/PE to generally read MSRs
72 // we return 0 for a read.
73
74 Data64 = 0;
75
76 }
77
78 Reg->Rax = (UINTN)(UINT32)Data64; // HIGH bits are cleared
79 Reg->Rdx = (UINTN)(UINT32)RShiftU64 (Data64, 32); // HIGH bits are cleared
80
81 VmWriteN (VMCS_N_GUEST_RIP_INDEX0x681E, VmReadN(VMCS_N_GUEST_RIP_INDEX0x681E) + VmRead32(VMCS_32_RO_VMEXIT_INSTRUCTION_LENGTH_INDEX0x440C));
82 return ;
83}
84
85/**
86
87 This function is WRMSR handler for SMM.
88
89 @param Index CPU index
90
91**/
92VOIDvoid
93PeWriteMsrHandler (
94 IN UINT32 CpuIndex
95 )
96{
97 UINT64 Data64;
98 UINT32 MsrIndex;
99 VM_ENTRY_CONTROLS VmEntryControls;
100 X86_REGISTER *Reg;
101 STM_SMM_CPU_STATE *SmmCpuState;
102 UINT32 VmType = mHostContextCommon.HostContextPerCpu[CpuIndex].GuestVmType;
103
104 UINT32 Index = 0; // PE VM only Index = 0
105
106 SmmCpuState = mGuestContextCommonSmi.GuestContextPerCpu[Index].SmmCpuState;
Value stored to 'SmmCpuState' is never read
107
108 Reg = &mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Register;
109 MsrIndex = ReadUnaligned32 ((UINT32 *)&Reg->Rcx);
110
111 Data64 = LShiftU64 ((UINT64)ReadUnaligned32 ((UINT32 *)&Reg->Rdx), 32) | (UINT64)ReadUnaligned32 ((UINT32 *)&Reg->Rax);
112 DEBUG ((EFI_D_INFO, "%ld PeWriteMsrHandler - 0x%llx 0x%llx\n", CpuIndex, MsrIndex, Data64))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld PeWriteMsrHandler - 0x%llx 0x%llx\n"
, CpuIndex, MsrIndex, Data64); } } while (((BOOLEAN)(0==1)));
113
114 switch (MsrIndex) {
115 case IA32_EFER_MSR_INDEX0xC0000080:
116#if 0
117 AcquireSpinLock (&mHostContextCommon.DebugLock);
118 if ((Data64 & IA32_EFER_MSR_SCE1u) != 0) {
119 DEBUG ((EFI_D_INFO, "%ld WriteMsrHandler - SCE\n", CpuIndex,))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld WriteMsrHandler - SCE\n"
, CpuIndex,); } } while (((BOOLEAN)(0==1)));
120 }
121 if ((Data64 & IA32_EFER_MSR_XDE(1u << 11)) != 0) {
122 DEBUG ((EFI_D_INFO, "%ld WriteMsrHandler - XDE\n", CpuIndex,))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld WriteMsrHandler - XDE\n"
, CpuIndex,); } } while (((BOOLEAN)(0==1)));
123 }
124 ReleaseSpinLock (&mHostContextCommon.DebugLock);
125#endif
126 mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Efer = Data64;
127 //
128 // Check IA32e mode switch
129 //
130 VmEntryControls.Uint32 = VmRead32 (VMCS_32_CONTROL_VMENTRY_CONTROLS_INDEX0x4012);
131 if ((Data64 & IA32_EFER_MSR_MLE(1u << 8)) != 0) {
132 mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Efer |= IA32_EFER_MSR_MLE(1u << 8);
133 } else {
134 mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Efer &= ~IA32_EFER_MSR_MLE(1u << 8);
135 }
136 if (((mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Efer & IA32_EFER_MSR_MLE(1u << 8)) != 0) &&
137 ((mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Cr0 & CR0_PG(1u << 31)) != 0)) {
138 mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Efer |= IA32_EFER_MSR_MLA(1u << 10);
139 VmEntryControls.Bits.Ia32eGuest = 1;
140 } else {
141 mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Efer &= ~IA32_EFER_MSR_MLA(1u << 10);
142 VmEntryControls.Bits.Ia32eGuest = 0;
143 }
144 VmWrite32 (VMCS_32_CONTROL_VMENTRY_CONTROLS_INDEX0x4012, VmEntryControls.Uint32);
145 VmWrite64 (VMCS_64_GUEST_IA32_EFER_INDEX0x2806, mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Efer);
146
147 break;
148#if 0
149 case IA32_SYSENTER_CS_MSR_INDEX0x174:
150 VmWrite32 (VMCS_32_GUEST_IA32_SYSENTER_CS_INDEX0x482A, (UINT32)Data64);
151 break;
152 case IA32_SYSENTER_ESP_MSR_INDEX0x175:
153 VmWriteN (VMCS_N_GUEST_IA32_SYSENTER_ESP_INDEX0x6824, (UINTN)Data64);
154 break;
155 case IA32_SYSENTER_EIP_MSR_INDEX0x176:
156 VmWriteN (VMCS_N_GUEST_IA32_SYSENTER_EIP_INDEX0x6826, (UINTN)Data64);
157 break;
158
159 case IA32_FS_BASE_MSR_INDEX0xC0000100:
160 VmWriteN (VMCS_N_GUEST_FS_BASE_INDEX0x680E, (UINTN)Data64);
161 // AsmWriteMsr64 (MsrIndex, Data64); // VMM does not use FS
162 break;
163 case IA32_GS_BASE_MSR_INDEX0xC0000101:
164 VmWriteN (VMCS_N_GUEST_GS_BASE_INDEX0x6810, (UINTN)Data64);
165 // AsmWriteMsr64 (MsrIndex, Data64); // VMM does not use GS
166 break;
167 case IA32_KERNAL_GS_BASE_MSR_INDEX0xC0000102:
168 AsmWriteMsr64 (MsrIndex, Data64); // VMM does not use this
169 break;
170 case IA32_STAR_MSR_INDEX0xC0000081:
171 AsmWriteMsr64 (MsrIndex, Data64); // VMM does not use this
172 break;
173 case IA32_LSTAR_MSR_INDEX0xC0000082:
174 AsmWriteMsr64 (MsrIndex, Data64); // VMM does not use this
175 break;
176 case IA32_FMASK_MSR_INDEX0xC0000084:
177 AsmWriteMsr64 (MsrIndex, Data64); // VMM does not use this
178 break;
179#endif
180
181 default:
182 DEBUG ((EFI_D_ERROR, "%ldWriteMsrHandler - VM/PE has no access to this MSR - ignoring\n", CpuIndex))do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ldWriteMsrHandler - VM/PE has no access to this MSR - ignoring\n"
, CpuIndex); } } while (((BOOLEAN)(0==1)));
183 break;
184 }
185
186 VmWriteN (VMCS_N_GUEST_RIP_INDEX0x681E, VmReadN(VMCS_N_GUEST_RIP_INDEX0x681E) + VmRead32(VMCS_32_RO_VMEXIT_INSTRUCTION_LENGTH_INDEX0x440C));
187 return ;
188}