Bug Summary

File:home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/PePciHandler.c
Warning:line 139, column 9
Value stored to 'smi_sts' during its initialization is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-unknown-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name PePciHandler.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -fno-jump-tables -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/build/StmPkg/Core/Runtime -resource-dir /opt/xgcc/lib/clang/17 -include PcdData.h -D COREBOOT32 -D RELEASE -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/EDKII/BaseTools/Source/C/Include/X64 -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/EdkII/MdePkg/Include -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/EdkII/MdePkg/Include/X64 -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Include -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Include/x64 -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/../Init -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/. -internal-isystem /opt/xgcc/lib/clang/17/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/13/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -source-date-epoch 1714465709 -Os -fdebug-compilation-dir=/home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/build/StmPkg/Core/Runtime -ferror-limit 19 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-max-loop 10 -analyzer-output=plist-html -faddrsig -o /cb-build/coreboot_scanbuild.0/PURISM_LIBREM15_V4_STM-scanbuildtmp/2024-05-02-081243-2232343-1/report-1gUYdd.plist -x c /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/PePciHandler.c
1/** @file
2
3PE PCI Handler
4
5This program and the accompanying materials
6are licensed and made available under the terms and conditions of the BSD License
7which accompanies this distribution. The full text of the license may be found at
8http://opensource.org/licenses/bsd-license.php.
9
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13**/
14
15#include "StmRuntime.h"
16#include "PeStm.h"
17
18void SetTimerRate(UINT16 value);
19
20// interval timer support
21
22//#define CONFIG_MMCONF_BASE_ADDRESS 0xF8000000///
23//#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS // frm sandybridge.h
24
25
26// from pci_devs.h
27#define PCU_DEV0x1F 0x1F
28
29// from lcp.h
30
31/* D30:F0 LPC bridge */
32#define D31F0_PMBASE0x40 0x40
33#define D31F0_GEN_PMCON_10xA0 0xA0
34#define D31F0_GEN_PMCON_30xA4 0xA4
35
36#define SMI_EN0x30 0x30 /* SMI Control and Enable Register */
37#define SWSMI_TMR_EN(1<<6) (1<<6) // start software timer on bit set
38#define PERIODIC_EN(1<<14) (1<<14)
39#define EOS_EN(1<<1) (1<<1) /* End of SMI */
40
41#define SMI_STS0x34 0x34 /* SMI Status Register */
42
43// SMI STATUS BITS
44
45#define SWSMI_TMR_STS(1<<6) (1<<6)
46#define PERIODIC_STS(1<<14) (1<<14)
47
48
49// from arch/io.h
50#define PCI_DEV(SEGBUS, DEV, FN)( (((SEGBUS) & 0xFFF) << 20) | (((DEV) & 0x1F) <<
15) | (((FN) & 0x07) <<12)) ( \
51 (((SEGBUS) & 0xFFF) << 20) | \
52 (((DEV) & 0x1F) << 15) | \
53 (((FN) & 0x07) <<12))
54
55void PrintSmiEnRegister(UINT32 Index);
56extern STM_GUEST_CONTEXT_COMMON mGuestContextCommonSmm[];
57
58typedef int device_t;
59
60static UINT16 pmbase = 0x0;
61
62static UINT16 read16(UINTN addr)
63{
64 return *((volatile UINT16 *) (addr));
65}
66
67static void write16(UINTN addr, UINT16 Reg16)
68{
69 *((volatile UINT16 *) (addr)) = Reg16;
70}
71
72static UINT32 read32(UINTN addr)
73{
74 return *((volatile UINT32 *) (addr));
75}
76
77static UINT16 pcie_read_config16(device_t dev, unsigned int whereat)
78{
79 UINTN addr;
80
81 addr = ((UINTN) mHostContextCommon.PciExpressBaseAddress) | dev | whereat;
82 //DEBUG((EFI_D_DEBUG, "pcie_read_config16 %x\n", addr));
83 return read16(addr);
84}
85
86static UINT32 pcie_read_config32(device_t dev, unsigned int whereat)
87{
88 UINTN addr;
89
90 addr = ((UINTN) mHostContextCommon.PciExpressBaseAddress) | dev | whereat;
91 //DEBUG((EFI_D_DEBUG, "pcie_read_config32 %x\n", addr));
92 return read32(addr);
93}
94
95static void pcie_write_config16(device_t dev, unsigned int whereat, UINT16 Reg16)
96{
97 UINTN addr;
98
99 addr = ((UINTN) mHostContextCommon.PciExpressBaseAddress) | dev | whereat;
100 write16(addr, Reg16);
101 return;
102}
103
104static device_t get_pcu_dev(void)
105{
106 //DEBUG((EFI_D_DEBUG, "get_pcu_dev - return %x\n", PCI_DEV(0, PCU_DEV, 0)));
107 return PCI_DEV(0, PCU_DEV, 0)( (((0) & 0xFFF) << 20) | (((0x1F) & 0x1F) <<
15) | (((0) & 0x07) <<12));
108}
109
110UINT16 get_pmbase(void)
111{
112 if (pmbase == 0)
113 {
114 // find the pmbase in the BIOS resource list
115
116 STM_RSC *Resource;
117
118 // the pmbase is the first IO resource
119 Resource = GetStmFirstResource (
120 (STM_RSC *)mGuestContextCommonSmm[SMI_HANDLER0].BiosHwResourceRequirementsPtr,
121 IO_RANGE2);
122 if(Resource == NULL((void *) 0))
123 DEBUG((EFI_D_ERROR,do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "get_pmbase - Error pmbase not found in resource list\n"
); } } while (((BOOLEAN)(0==1)))
124 "get_pmbase - Error pmbase not found in resource list\n"))do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "get_pmbase - Error pmbase not found in resource list\n"
); } } while (((BOOLEAN)(0==1)));
125 else
126 {
127 pmbase = Resource->Io.Base;
128 DEBUG((EFI_D_INFO,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "get_pmbase - pmbase set at 0x%x\n"
, pmbase); } } while (((BOOLEAN)(0==1)))
129 "get_pmbase - pmbase set at 0x%x\n", pmbase))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "get_pmbase - pmbase set at 0x%x\n"
, pmbase); } } while (((BOOLEAN)(0==1)));
130 }
131 }
132 return pmbase;
133}
134
135void StartTimer(void)
136{
137 UINT16 pmbase = get_pmbase();
138 UINT32 smi_en = IoRead32(pmbase + SMI_EN0x30);
139 UINT32 smi_sts = IoRead32(pmbase + SMI_STS0x34);
Value stored to 'smi_sts' during its initialization is never read
140
141 smi_en |= PERIODIC_EN(1<<14);
142#if 0
143 DEBUG((EFI_D_INFO,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "StartTimer - smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, smi_en, smi_sts); } } while (((BOOLEAN)(0==1)))
144 "StartTimer - smi_en: 0x%08lx smi_sts: 0x%08lx\n",do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "StartTimer - smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, smi_en, smi_sts); } } while (((BOOLEAN)(0==1)))
145 smi_en,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "StartTimer - smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, smi_en, smi_sts); } } while (((BOOLEAN)(0==1)))
146 smi_sts))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "StartTimer - smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, smi_en, smi_sts); } } while (((BOOLEAN)(0==1)));
147#endif
148 IoWrite32(pmbase + SMI_STS0x34, PERIODIC_STS(1<<14));
149 IoWrite32(pmbase + SMI_EN0x30, smi_en);
150}
151
152void SetEndOfSmi(void)
153{
154
155 UINT16 pmbase = get_pmbase();
156 UINT32 smi_en = IoRead32(pmbase + SMI_EN0x30);
157 smi_en |= EOS_EN(1<<1); // set the bit
158#if 0
159 DEBUG((EFI_D_INFO,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "-- SetEndOfSmi pmbase: %x smi_en: %x \n"
, pmbase, smi_en); } } while (((BOOLEAN)(0==1)))
160 "-- SetEndOfSmi pmbase: %x smi_en: %x \n",do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "-- SetEndOfSmi pmbase: %x smi_en: %x \n"
, pmbase, smi_en); } } while (((BOOLEAN)(0==1)))
161 pmbase,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "-- SetEndOfSmi pmbase: %x smi_en: %x \n"
, pmbase, smi_en); } } while (((BOOLEAN)(0==1)))
162 smi_en))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "-- SetEndOfSmi pmbase: %x smi_en: %x \n"
, pmbase, smi_en); } } while (((BOOLEAN)(0==1)));
163#endif
164 IoWrite32(pmbase + SMI_EN0x30, smi_en);
165#if 0
166 DEBUG((EFI_D_INFO,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "SetEndOfSmi smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); } } while
(((BOOLEAN)(0==1)))
167 "SetEndOfSmi smi_en: 0x%08lx smi_sts: 0x%08lx\n",do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "SetEndOfSmi smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); } } while
(((BOOLEAN)(0==1)))
168 IoRead32(pmbase + SMI_EN),do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "SetEndOfSmi smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); } } while
(((BOOLEAN)(0==1)))
169 IoRead32(pmbase + SMI_STS)))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "SetEndOfSmi smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); } } while
(((BOOLEAN)(0==1)));
170#endif
171}
172
173void PrintSmiEnRegister(UINT32 Index)
174{
175 UINT16 pmbase = get_pmbase();
176 DEBUG((EFI_D_INFO,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld PrintSmiEnRegister smi_en: 0x%08x smi_sts: 0x%08x\n"
, Index, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); }
} while (((BOOLEAN)(0==1)))
177 "%ld PrintSmiEnRegister smi_en: 0x%08x smi_sts: 0x%08x\n",do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld PrintSmiEnRegister smi_en: 0x%08x smi_sts: 0x%08x\n"
, Index, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); }
} while (((BOOLEAN)(0==1)))
178 Index,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld PrintSmiEnRegister smi_en: 0x%08x smi_sts: 0x%08x\n"
, Index, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); }
} while (((BOOLEAN)(0==1)))
179 IoRead32(pmbase + SMI_EN),do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld PrintSmiEnRegister smi_en: 0x%08x smi_sts: 0x%08x\n"
, Index, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); }
} while (((BOOLEAN)(0==1)))
180 IoRead32(pmbase + SMI_STS)))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld PrintSmiEnRegister smi_en: 0x%08x smi_sts: 0x%08x\n"
, Index, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); }
} while (((BOOLEAN)(0==1)));
181}
182
183void AckTimer(void)
184{
185 UINT16 pmbase = get_pmbase();
186
187 IoWrite32(pmbase + SMI_STS0x34, PERIODIC_STS(1<<14));
188#if 0
189 DEBUG((EFI_D_INFO,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "AckTimer - smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); } } while
(((BOOLEAN)(0==1)))
190 "AckTimer - smi_en: 0x%08lx smi_sts: 0x%08lx\n",do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "AckTimer - smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); } } while
(((BOOLEAN)(0==1)))
191 IoRead32(pmbase + SMI_EN),do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "AckTimer - smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); } } while
(((BOOLEAN)(0==1)))
192 IoRead32(pmbase + SMI_STS)))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "AckTimer - smi_en: 0x%08lx smi_sts: 0x%08lx\n"
, IoRead32(pmbase + 0x30), IoRead32(pmbase + 0x34)); } } while
(((BOOLEAN)(0==1)));
193#endif
194}
195
196void StopSwTimer(void)
197{
198 UINT16 pmbase = get_pmbase();
199 UINT32 smi_en = IoRead32(pmbase + SMI_EN0x30);
200
201 smi_en &= ~PERIODIC_EN(1<<14);
202 IoWrite32(pmbase + SMI_EN0x30, smi_en);
203}
204
205/*
206 * CheckTimerSTS
207 * Input:
208 * Index - cpu number
209 *
210 * Output:
211 * 0 - No timer interrupt detected
212 * 1 - Timer interrupt detected
213 * 2 - Timer interrupt plus additional SMI
214 */
215
216int CheckTimerSTS(UINT32 Index)
217{
218 UINT16 pmbase = get_pmbase();
219 UINT32 smi_sts = IoRead32(pmbase + SMI_STS0x34);
220#if 0
221 DEBUG((EFI_D_ERROR, "%ld CheckTimerSTS - 0x%08lx\n", Index, smi_sts))do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld CheckTimerSTS - 0x%08lx\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)));
222#endif
223 if((smi_sts & PERIODIC_STS(1<<14)) == PERIODIC_STS(1<<14))
224 {
225 UINT32 smi_en = IoRead32(pmbase + SMI_EN0x30);
226 UINT32 other_smi = (smi_en & smi_sts) & ~PERIODIC_STS(1<<14);
227
228 if(other_smi == 0)
229 {
230 DEBUG((EFI_D_INFO,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - Timer Interrupt Detected\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)))
231 "%ld CheckTimerSTS - Timer Interrupt Detected\n",do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - Timer Interrupt Detected\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)))
232 Index,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - Timer Interrupt Detected\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)))
233 smi_sts))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - Timer Interrupt Detected\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)));
234 return 1;
235 }
236 else
237 {
238 DEBUG((EFI_D_INFO,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - Timer + other SMI found\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)))
239 "%ld CheckTimerSTS - Timer + other SMI found\n",do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - Timer + other SMI found\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)))
240 Index,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - Timer + other SMI found\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)))
241 smi_sts))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - Timer + other SMI found\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)));
242 return 2;
243 }
244 }
245 else
246 {
247#if 0
248 DEBUG((EFI_D_INFO,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - No Timer Interrupt Detected\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)))
249 "%ld CheckTimerSTS - No Timer Interrupt Detected\n",do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - No Timer Interrupt Detected\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)))
250 Index,do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - No Timer Interrupt Detected\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)))
251 smi_sts))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld CheckTimerSTS - No Timer Interrupt Detected\n"
, Index, smi_sts); } } while (((BOOLEAN)(0==1)));
252#endif
253 return 0;
254 }
255}
256
257void ClearTimerSTS()
258{
259 UINT16 pmbase = get_pmbase();
260
261 // just want to clear the status - do not touch the rest
262 IoWrite32(pmbase + SMI_STS0x34, PERIODIC_STS(1<<14));
263}
264
265void SetMaxSwTimerInt()
266{
267 SetTimerRate(3);
268}
269
270void SetMinSwTimerInt()
271{
272 SetTimerRate(0);
273}
274
275void SetTimerRate(UINT16 value)
276{
277 UINT16 Reg16;
278 UINT16 TimeOut;
279 device_t PcuDev = get_pcu_dev();
280
281 if( value > 3)
282 {
283 value = 3;
284 }
285 TimeOut = (value << 0);
286
287 Reg16 = pcie_read_config16(PcuDev, D31F0_GEN_PMCON_10xA0);
288 pcie_write_config16(PcuDev, D31F0_GEN_PMCON_10xA0, Reg16|TimeOut);
289}