Bug Summary

File:home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/SmmIoHandler.c
Warning:line 231, column 4
Value stored to 'LinearAddr' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-unknown-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name SmmIoHandler.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -fno-jump-tables -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/build/StmPkg/Core/Runtime -resource-dir /opt/xgcc/lib/clang/17 -include PcdData.h -D COREBOOT32 -D RELEASE -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/EDKII/BaseTools/Source/C/Include/X64 -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/EdkII/MdePkg/Include -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/EdkII/MdePkg/Include/X64 -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Include -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Include/x64 -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/../Init -I /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/. -internal-isystem /opt/xgcc/lib/clang/17/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/13/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -source-date-epoch 1714465709 -Os -fdebug-compilation-dir=/home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/build/StmPkg/Core/Runtime -ferror-limit 19 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-max-loop 10 -analyzer-output=plist-html -faddrsig -o /cb-build/coreboot_scanbuild.0/PURISM_LIBREM15_V4_STM-scanbuildtmp/2024-05-02-081243-2232343-1/report-9k_eM_.plist -x c /home/coreboot/node-root/workspace/coreboot_scanbuild/3rdparty/stm/Stm/StmPkg/Core/Runtime/SmmIoHandler.c
1/** @file
2 SMM IO handler
3
4 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13**/
14
15#include "StmRuntime.h"
16#include "PeStm.h"
17
18#define BUS_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x00FF0000) >> 16) (UINT8)(((UINTN)(PciAddress) & 0x00FF0000) >> 16)
19#define DEVICE_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x0000F800) >> 13) (UINT8)(((UINTN)(PciAddress) & 0x0000F800) >> 13)
20#define FUNCTION_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x00000700) >> 8) (UINT8)(((UINTN)(PciAddress) & 0x00000700) >> 8)
21#define REGISTER_FROM_CF8_ADDRESS(PciAddress)(UINT16)((UINTN)(PciAddress) & 0x000000FC) (UINT16)((UINTN)(PciAddress) & 0x000000FC)
22
23/**
24
25 This function translate guest linear address to host address.
26
27 @param CpuIndex CPU index
28 @param GuestLinearAddress Guest linear address
29
30 @return Host physical address
31**/
32UINTN
33GuestLinearToHostPhysical (
34 UINT32 CpuIndex,
35 UINTN GuestLinearAddress
36 );
37
38/**
39
40 This function is IO instruction handler for SMM.
41
42 @param Index CPU index
43
44**/
45VOIDvoid
46SmmIoHandler (
47 IN UINT32 Index
48 )
49{
50 VM_EXIT_QUALIFICATION Qualification;
51 UINT16 Port;
52 UINTN *DataPtr;
53 UINTN LinearAddr;
54 X86_REGISTER *Reg;
55 STM_RSC_IO_DESC *IoDesc;
56 STM_RSC_PCI_CFG_DESC *PciCfgDesc;
57 UINT32 PciAddress;
58 STM_RSC_IO_DESC LocalIoDesc;
59 STM_RSC_PCI_CFG_DESC *LocalPciCfgDescPtr;
60 UINT8 LocalPciCfgDescBuf[STM_LOG_ENTRY_SIZE256];
61 UINT32 VmType = SMI_HANDLER0;
62
63 Reg = &mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Register;
64
65 Qualification.UintN = VmReadN (VMCS_N_RO_EXIT_QUALIFICATION_INDEX0x6400);
66 if (Qualification.IoInstruction.Operand != 0) {
67 Port = (UINT16)Qualification.IoInstruction.PortNum;
68 } else {
69 Port = (UINT16)Reg->Rdx;
70 }
71 DataPtr = (UINTN *)&Reg->Rax;
72
73 // DEBUG ((EFI_D_ERROR, "%ld SmmIoHandler - Port 0x%x DataPtr 0x%x\n", Index, Port, DataPtr));
74 //
75 // We need handle case that CF9 is protected, but CF8, CFC need to be pass-through.
76 // But DWORD CF8 programming will be caught here.
77 // So add check here. CF8 will be bypassed, because it does not in CF9 scope.
78 //
79 IoDesc = GetStmResourceIo (mHostContextCommon.MleProtectedResource.Base, Port);
80 if (IoDesc != NULL((void *) 0)) {
81 DEBUG ((EFI_D_ERROR, "%ld SmmIoHandler - IO violation!\n", Index))do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld SmmIoHandler - IO violation!\n"
, Index); } } while (((BOOLEAN)(0==1)));
82 AddEventLogForResource (EvtHandledProtectionException, (STM_RSC *)IoDesc);
83 SmmExceptionHandler (Index);
84 CpuDeadLoop ();
85 }
86
87 IoDesc = GetStmResourceIo ((STM_RSC *)(UINTN)mGuestContextCommonSmm[VmType].BiosHwResourceRequirementsPtr, Port);
88 if (IoDesc == NULL((void *) 0)) {
89 DEBUG ((EFI_D_ERROR, "%ld SmmIoHandler - IODesc is NULL - BIOS did not claim\n", Index))do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld SmmIoHandler - IODesc is NULL - BIOS did not claim\n"
, Index); } } while (((BOOLEAN)(0==1)));
90 ZeroMem (&LocalIoDesc, sizeof(LocalIoDesc));
91 LocalIoDesc.Hdr.RscType = IO_RANGE2;
92 LocalIoDesc.Hdr.Length = sizeof(LocalIoDesc);
93 LocalIoDesc.Base = Port;
94 LocalIoDesc.Length = (UINT16)(Qualification.IoInstruction.Size + 1);
95 AddEventLogForResource (EvtBiosAccessToUnclaimedResource, (STM_RSC *)&LocalIoDesc);
96 }
97
98 //
99 // Check PCI - 0xCF8, 0xCFC~0xCFF access
100 //
101 if (Port == 0xCF8) {
102 // Access PciAddress
103
104 //
105 // We need make sure PciAddress access and PciData access is atomic.
106 //
107 AcquireSpinLock (&mHostContextCommon.PciLock);
108 }
109 if ((Port >= 0xCFC) && (Port <= 0xCFF)) {
110 // Access PciData
111
112 //
113 // AcquireLock to prevent 0xCF8 access
114 //
115 AcquireSpinLock (&mHostContextCommon.PciLock);
116 PciAddress = IoRead32 (0xCF8);
117 PciCfgDesc = GetStmResourcePci (
118 mHostContextCommon.MleProtectedResource.Base,
119 BUS_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x00FF0000) >> 16),
120 DEVICE_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x0000F800) >> 13),
121 FUNCTION_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x00000700) >> 8),
122 REGISTER_FROM_CF8_ADDRESS(PciAddress)(UINT16)((UINTN)(PciAddress) & 0x000000FC) + (Port & 0x3),
123 (Qualification.IoInstruction.Direction != 0) ? STM_RSC_PCI_CFG_R0x1 : STM_RSC_PCI_CFG_W0x2
124 );
125 if (PciCfgDesc != NULL((void *) 0)) {
126 DEBUG ((EFI_D_ERROR, "IO (PCI) violation!\n"))do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "IO (PCI) violation!\n"
); } } while (((BOOLEAN)(0==1)));
127 AddEventLogForResource (EvtHandledProtectionException, (STM_RSC *)PciCfgDesc);
128 ReleaseSpinLock (&mHostContextCommon.PciLock);
129 SmmExceptionHandler (Index);
130 CpuDeadLoop ();
131 }
132
133 PciCfgDesc = GetStmResourcePci (
134 (STM_RSC *)(UINTN)mGuestContextCommonSmm[VmType].BiosHwResourceRequirementsPtr,
135 BUS_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x00FF0000) >> 16),
136 DEVICE_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x0000F800) >> 13),
137 FUNCTION_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x00000700) >> 8),
138 REGISTER_FROM_CF8_ADDRESS(PciAddress)(UINT16)((UINTN)(PciAddress) & 0x000000FC) + (Port & 0x3),
139 (Qualification.IoInstruction.Direction != 0) ? STM_RSC_PCI_CFG_R0x1 : STM_RSC_PCI_CFG_W0x2
140 );
141 if (PciCfgDesc == NULL((void *) 0)) {
142#if 0 // StmReseource.c does not create an entry for this - leave out because it generates a lot of output
143 DEBUG((EFI_D_ERROR, "%ld - Add unclaimed PCI_RSC!: Port: 0x%x PciAddress 0x%x Bus: 0x%x Device: 0x%x Function: 0x%x Register: 0x%x Direction: 0x%x\n",do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld - Add unclaimed PCI_RSC!: Port: 0x%x PciAddress 0x%x Bus: 0x%x Device: 0x%x Function: 0x%x Register: 0x%x Direction: 0x%x\n"
, Index, Port, PciAddress, (UINT8)(((UINTN)(PciAddress) &
0x00FF0000) >> 16), (UINT8)(((UINTN)(PciAddress) &
0x0000F800) >> 13), (UINT8)(((UINTN)(PciAddress) &
0x00000700) >> 8), (UINT16)((UINTN)(PciAddress) & 0x000000FC
) + (Port & 0x3), (Qualification.IoInstruction.Direction !=
0) ? 0x1 : 0x2); } } while (((BOOLEAN)(0==1)))
144 Index,do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld - Add unclaimed PCI_RSC!: Port: 0x%x PciAddress 0x%x Bus: 0x%x Device: 0x%x Function: 0x%x Register: 0x%x Direction: 0x%x\n"
, Index, Port, PciAddress, (UINT8)(((UINTN)(PciAddress) &
0x00FF0000) >> 16), (UINT8)(((UINTN)(PciAddress) &
0x0000F800) >> 13), (UINT8)(((UINTN)(PciAddress) &
0x00000700) >> 8), (UINT16)((UINTN)(PciAddress) & 0x000000FC
) + (Port & 0x3), (Qualification.IoInstruction.Direction !=
0) ? 0x1 : 0x2); } } while (((BOOLEAN)(0==1)))
145 Port,do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld - Add unclaimed PCI_RSC!: Port: 0x%x PciAddress 0x%x Bus: 0x%x Device: 0x%x Function: 0x%x Register: 0x%x Direction: 0x%x\n"
, Index, Port, PciAddress, (UINT8)(((UINTN)(PciAddress) &
0x00FF0000) >> 16), (UINT8)(((UINTN)(PciAddress) &
0x0000F800) >> 13), (UINT8)(((UINTN)(PciAddress) &
0x00000700) >> 8), (UINT16)((UINTN)(PciAddress) & 0x000000FC
) + (Port & 0x3), (Qualification.IoInstruction.Direction !=
0) ? 0x1 : 0x2); } } while (((BOOLEAN)(0==1)))
146 PciAddress,do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld - Add unclaimed PCI_RSC!: Port: 0x%x PciAddress 0x%x Bus: 0x%x Device: 0x%x Function: 0x%x Register: 0x%x Direction: 0x%x\n"
, Index, Port, PciAddress, (UINT8)(((UINTN)(PciAddress) &
0x00FF0000) >> 16), (UINT8)(((UINTN)(PciAddress) &
0x0000F800) >> 13), (UINT8)(((UINTN)(PciAddress) &
0x00000700) >> 8), (UINT16)((UINTN)(PciAddress) & 0x000000FC
) + (Port & 0x3), (Qualification.IoInstruction.Direction !=
0) ? 0x1 : 0x2); } } while (((BOOLEAN)(0==1)))
147 BUS_FROM_CF8_ADDRESS(PciAddress),do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld - Add unclaimed PCI_RSC!: Port: 0x%x PciAddress 0x%x Bus: 0x%x Device: 0x%x Function: 0x%x Register: 0x%x Direction: 0x%x\n"
, Index, Port, PciAddress, (UINT8)(((UINTN)(PciAddress) &
0x00FF0000) >> 16), (UINT8)(((UINTN)(PciAddress) &
0x0000F800) >> 13), (UINT8)(((UINTN)(PciAddress) &
0x00000700) >> 8), (UINT16)((UINTN)(PciAddress) & 0x000000FC
) + (Port & 0x3), (Qualification.IoInstruction.Direction !=
0) ? 0x1 : 0x2); } } while (((BOOLEAN)(0==1)))
148 DEVICE_FROM_CF8_ADDRESS(PciAddress),do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld - Add unclaimed PCI_RSC!: Port: 0x%x PciAddress 0x%x Bus: 0x%x Device: 0x%x Function: 0x%x Register: 0x%x Direction: 0x%x\n"
, Index, Port, PciAddress, (UINT8)(((UINTN)(PciAddress) &
0x00FF0000) >> 16), (UINT8)(((UINTN)(PciAddress) &
0x0000F800) >> 13), (UINT8)(((UINTN)(PciAddress) &
0x00000700) >> 8), (UINT16)((UINTN)(PciAddress) & 0x000000FC
) + (Port & 0x3), (Qualification.IoInstruction.Direction !=
0) ? 0x1 : 0x2); } } while (((BOOLEAN)(0==1)))
149 FUNCTION_FROM_CF8_ADDRESS(PciAddress),do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld - Add unclaimed PCI_RSC!: Port: 0x%x PciAddress 0x%x Bus: 0x%x Device: 0x%x Function: 0x%x Register: 0x%x Direction: 0x%x\n"
, Index, Port, PciAddress, (UINT8)(((UINTN)(PciAddress) &
0x00FF0000) >> 16), (UINT8)(((UINTN)(PciAddress) &
0x0000F800) >> 13), (UINT8)(((UINTN)(PciAddress) &
0x00000700) >> 8), (UINT16)((UINTN)(PciAddress) & 0x000000FC
) + (Port & 0x3), (Qualification.IoInstruction.Direction !=
0) ? 0x1 : 0x2); } } while (((BOOLEAN)(0==1)))
150 REGISTER_FROM_CF8_ADDRESS(PciAddress) + (Port & 0x3),do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld - Add unclaimed PCI_RSC!: Port: 0x%x PciAddress 0x%x Bus: 0x%x Device: 0x%x Function: 0x%x Register: 0x%x Direction: 0x%x\n"
, Index, Port, PciAddress, (UINT8)(((UINTN)(PciAddress) &
0x00FF0000) >> 16), (UINT8)(((UINTN)(PciAddress) &
0x0000F800) >> 13), (UINT8)(((UINTN)(PciAddress) &
0x00000700) >> 8), (UINT16)((UINTN)(PciAddress) & 0x000000FC
) + (Port & 0x3), (Qualification.IoInstruction.Direction !=
0) ? 0x1 : 0x2); } } while (((BOOLEAN)(0==1)))
151 (Qualification.IoInstruction.Direction != 0) ? STM_RSC_PCI_CFG_R : STM_RSC_PCI_CFG_W))do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld - Add unclaimed PCI_RSC!: Port: 0x%x PciAddress 0x%x Bus: 0x%x Device: 0x%x Function: 0x%x Register: 0x%x Direction: 0x%x\n"
, Index, Port, PciAddress, (UINT8)(((UINTN)(PciAddress) &
0x00FF0000) >> 16), (UINT8)(((UINTN)(PciAddress) &
0x0000F800) >> 13), (UINT8)(((UINTN)(PciAddress) &
0x00000700) >> 8), (UINT16)((UINTN)(PciAddress) & 0x000000FC
) + (Port & 0x3), (Qualification.IoInstruction.Direction !=
0) ? 0x1 : 0x2); } } while (((BOOLEAN)(0==1)));
152#endif
153 LocalPciCfgDescPtr = (STM_RSC_PCI_CFG_DESC *)LocalPciCfgDescBuf;
154 ZeroMem (LocalPciCfgDescBuf, sizeof(LocalPciCfgDescBuf));
155 LocalPciCfgDescPtr->Hdr.RscType = PCI_CFG_RANGE5;
156 LocalPciCfgDescPtr->Hdr.Length = sizeof(STM_RSC_PCI_CFG_DESC); // BUGBUG: Just report this PCI device, it is hard to create PCI hierachy here.
157 LocalPciCfgDescPtr->RWAttributes = (Qualification.IoInstruction.Direction != 0) ? STM_RSC_PCI_CFG_R0x1 : STM_RSC_PCI_CFG_W0x2;
158 LocalPciCfgDescPtr->Base = REGISTER_FROM_CF8_ADDRESS(PciAddress)(UINT16)((UINTN)(PciAddress) & 0x000000FC) + (Port & 0x3);
159 LocalPciCfgDescPtr->Length = (UINT16)(Qualification.IoInstruction.Size + 1);
160 LocalPciCfgDescPtr->OriginatingBusNumber = BUS_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x00FF0000) >> 16);
161 LocalPciCfgDescPtr->LastNodeIndex = 0;
162 LocalPciCfgDescPtr->PciDevicePath[0].Type = 1;
163 LocalPciCfgDescPtr->PciDevicePath[0].Subtype = 1;
164 LocalPciCfgDescPtr->PciDevicePath[0].Length = sizeof(STM_PCI_DEVICE_PATH_NODE);
165 LocalPciCfgDescPtr->PciDevicePath[0].PciFunction = FUNCTION_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x00000700) >> 8);
166 LocalPciCfgDescPtr->PciDevicePath[0].PciDevice = DEVICE_FROM_CF8_ADDRESS(PciAddress)(UINT8)(((UINTN)(PciAddress) & 0x0000F800) >> 13);
167 AddEventLogForResource (EvtBiosAccessToUnclaimedResource, (STM_RSC *)LocalPciCfgDescPtr);
168 // give it BIOS since the MLE did not claim
169 //bug,bug need to officially add it to the BIOS resource list
170
171 SetIoBitmapRange (0xCF8, 1);
172 SetIoBitmapRange (0xCFC, 4);
173
174 if(EPTSetPageAttributeRange (
175 mGuestContextCommonSmm[SMI_HANDLER0].EptPointer.Uint64,
176 PciAddress & ~(0x00000FFF),
177 SIZE_4KB0x00001000,
178 PciAddress & ~(0x00000FFF),
179 ((LocalPciCfgDescPtr->RWAttributes & STM_RSC_MEM_R0x1) != 0) ? 0 : 1,
180 ((LocalPciCfgDescPtr->RWAttributes & STM_RSC_MEM_W0x2) != 0) ? 0 : 1,
181 0,
182 EptPageAttributeSet,
183 0 // uncachable
184 ) != 0)
185 {
186 DEBUG((EFI_D_ERROR, "%ld SmmEPTViolationHandler - STM ERROR unable to add resource to EPT map\n", Index))do { if (DebugPrintEnabled ()) { DebugPrint (0x80000000, "%ld SmmEPTViolationHandler - STM ERROR unable to add resource to EPT map\n"
, Index); } } while (((BOOLEAN)(0==1)));
187 CpuDeadLoop ();
188 }
189 }
190 }
191
192 if (Qualification.IoInstruction.Rep != 0) {
193 UINT64 RcxMask;
194
195 RcxMask = 0xFFFFFFFFFFFFFFFFull;
196 if ((mGuestContextCommonSmm[VmType].GuestContextPerCpu[Index].Efer & IA32_EFER_MSR_MLA(1u << 10)) == 0) {
197 RcxMask = 0xFFFFFFFFull;
198 }
199 if ((Reg->Rcx & RcxMask) == 0) {
200 // Skip
201 if ((Port == 0xCF8) || ((Port >= 0xCFC) && (Port <= 0xCFF))) {
202 ReleaseSpinLock (&mHostContextCommon.PciLock);
203 }
204 VmWriteN (VMCS_N_GUEST_RIP_INDEX0x681E, VmReadN(VMCS_N_GUEST_RIP_INDEX0x681E) + VmRead32(VMCS_32_RO_VMEXIT_INSTRUCTION_LENGTH_INDEX0x440C));
205 return ;
206 }
207 }
208
209 if (Qualification.IoInstruction.String != 0) {
210 LinearAddr = VmReadN (VMCS_N_RO_GUEST_LINEAR_ADDR_INDEX0x640A);
211 if (VmReadN (VMCS_N_GUEST_CR0_INDEX0x6800) & CR0_PG(1u << 31)) {
212 DataPtr = (UINTN *)(UINTN)GuestLinearToHostPhysical (Index, LinearAddr);
213 } else {
214 DataPtr = (UINTN *)LinearAddr;
215 }
216 if ((VmReadN (VMCS_N_GUEST_RFLAGS_INDEX0x6820) & RFLAGS_DF(1u << 10)) != 0) {
217 if (Qualification.IoInstruction.Direction != 0) {
218 Reg->Rdi -= Qualification.IoInstruction.Size + 1;
219 } else {
220 Reg->Rsi -= Qualification.IoInstruction.Size + 1;
221 }
222 } else {
223 if (Qualification.IoInstruction.Direction != 0) {
224 Reg->Rdi += Qualification.IoInstruction.Size + 1;
225 } else {
226 Reg->Rsi += Qualification.IoInstruction.Size + 1;
227 }
228 }
229 }
230 if (Qualification.IoInstruction.Direction != 0) {
231 LinearAddr = VmReadN (VMCS_N_RO_GUEST_LINEAR_ADDR_INDEX0x640A);
Value stored to 'LinearAddr' is never read
232 switch (Qualification.IoInstruction.Size) {
233 case 0:
234 *(UINT8 *)DataPtr = IoRead8 (Port);
235 goto Ret;
236 break;
237 case 1:
238 *(UINT16 *)DataPtr = IoRead16 (Port);
239 goto Ret;
240 break;
241 case 3:
242 *(UINT32 *)DataPtr = IoRead32 (Port);
243 goto Ret;
244 break;
245 default:
246 break;
247 }
248 } else { // OUT
249 switch (Qualification.IoInstruction.Size) {
250 case 0:
251 IoWrite8 (Port, (UINT8)*DataPtr);
252 goto Ret;
253 break;
254 case 1:
255 IoWrite16 (Port, (UINT16)*DataPtr);
256 goto Ret;
257 break;
258 case 3:
259 IoWrite32 (Port, (UINT32)*DataPtr);
260 goto Ret;
261 break;
262 default:
263 break;
264 }
265 }
266 if ((Port == 0xCF8) || ((Port >= 0xCFC) && (Port <= 0xCFF))) {
267 ReleaseSpinLock (&mHostContextCommon.PciLock);
268 }
269 DEBUG ((EFI_D_INFO, "%ld - !!!IoHandler error !!!\n", Index))do { if (DebugPrintEnabled ()) { DebugPrint (0x00000040, "%ld - !!!IoHandler error !!!\n"
, Index); } } while (((BOOLEAN)(0==1)));
270 DumpVmcsAllField (Index);
271
272 CpuDeadLoop ();
273
274Ret:
275 if ((Port == 0xCF8) || ((Port >= 0xCFC) && (Port <= 0xCFF))) {
276 ReleaseSpinLock (&mHostContextCommon.PciLock);
277 }
278 if (Qualification.IoInstruction.Rep != 0) {
279 // replay
280 Reg->Rcx --;
281 return ;
282 }
283 VmWriteN (VMCS_N_GUEST_RIP_INDEX0x681E, VmReadN(VMCS_N_GUEST_RIP_INDEX0x681E) + VmRead32(VMCS_32_RO_VMEXIT_INSTRUCTION_LENGTH_INDEX0x440C));
284 return ;
285}