This is an automatically generated list of '''coreboot compile-time options'''.

Last update: 4.8-543-g635e512be3
<table border="0" style="font-size: smaller">
<tr bgcolor="#6699dd">
<td align="left">Option</td>
<td align="left">Source</td>
<td align="left">Format</td>
<td align="left">Short&nbsp;Description</td>
<td align="left">Description</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: General setup</td></tr>
<tr bgcolor="#eeeeee">
<td>LOCALVERSION</td><td>toplevel</td><td>string</td><td>Local version string</td><td>
Append an extra string to the end of the coreboot version.<br />
<br />
This can be useful if, for instance, you want to append the<br />
respective board's hostname or some other identifying string to<br />
the coreboot version number, so that you can easily distinguish<br />
boot logs of different boards from each other.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CBFS_PREFIX</td><td>toplevel</td><td>string</td><td>CBFS prefix to use</td><td>
Select the prefix to all files put into the image. It's "fallback"<br />
by default, "normal" is a common alternative.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CBFS_PREFIX</td><td>toplevel</td><td>string</td><td>Compiler to use</td><td>
This option allows you to select the compiler used for building<br />
coreboot.<br />
You must build the coreboot crosscompiler for the board that you<br />
have selected.<br />
<br />
To build all the GCC crosscompilers (takes a LONG time), run:<br />
make crossgcc<br />
<br />
For help on individual architectures, run the command:<br />
make help_toolchain<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COMPILER_GCC</td><td>toplevel</td><td>bool</td><td>GCC</td><td>
Use the GNU Compiler Collection (GCC) to build coreboot.<br />
<br />
For details see http://gcc.gnu.org.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COMPILER_LLVM_CLANG</td><td>toplevel</td><td>bool</td><td>LLVM/clang (TESTING ONLY - Not currently working)</td><td>
Use LLVM/clang to build coreboot.  To use this, you must build the<br />
coreboot version of the clang compiler.  Run the command<br />
make clang<br />
Note that this option is not currently working correctly and should<br />
really only be selected if you're trying to work on getting clang<br />
operational.<br />
<br />
For details see http://clang.llvm.org.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ANY_TOOLCHAIN</td><td>toplevel</td><td>bool</td><td>Allow building with any toolchain</td><td>
Many toolchains break when building coreboot since it uses quite<br />
unusual linker features. Unless developers explicitely request it,<br />
we'll have to assume that they use their distro compiler by mistake.<br />
Make sure that using patched compilers is a conscious decision.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CCACHE</td><td>toplevel</td><td>bool</td><td>Use ccache to speed up (re)compilation</td><td>
Enables the use of ccache for faster builds.<br />
<br />
Requires the ccache utility in your system $PATH.<br />
<br />
For details see https://ccache.samba.org.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FMD_GENPARSER</td><td>toplevel</td><td>bool</td><td>Generate flashmap descriptor parser using flex and bison</td><td>
Enable this option if you are working on the flashmap descriptor<br />
parser and made changes to fmd_scanner.l or fmd_parser.y.<br />
<br />
Otherwise, say N to use the provided pregenerated scanner/parser.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UTIL_GENPARSER</td><td>toplevel</td><td>bool</td><td>Generate SCONFIG &amp; BINCFG parser using flex and bison</td><td>
Enable this option if you are working on the sconfig device tree<br />
parser or bincfg and made changes to the .l or .y files.<br />
<br />
Otherwise, say N to use the provided pregenerated scanner/parser.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_OPTION_TABLE</td><td>toplevel</td><td>bool</td><td>Use CMOS for configuration values</td><td>
Enable this option if coreboot shall read options from the "CMOS"<br />
NVRAM instead of using hard-coded values.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>STATIC_OPTION_TABLE</td><td>toplevel</td><td>bool</td><td>Load default configuration values into CMOS on each boot</td><td>
Enable this option to reset "CMOS" NVRAM values to default on<br />
every boot.  Use this if you want the NVRAM configuration to<br />
never be modified from its default values.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COMPRESS_RAMSTAGE</td><td>toplevel</td><td>bool</td><td>Compress ramstage with LZMA</td><td>
Compress ramstage to save memory in the flash image. Note<br />
that decompression might slow down booting if the boot flash<br />
is connected through a slow link (i.e. SPI).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COMPRESS_PRERAM_STAGES</td><td>toplevel</td><td>bool</td><td>Compress romstage and verstage with LZ4</td><td>
Compress romstage and (if it exists) verstage with LZ4 to save flash<br />
space and speed up boot, since the time for reading the image from SPI<br />
(and in the vboot case verifying it) is usually much greater than the<br />
time spent decompressing. Doesn't work for XIP stages (assume all<br />
ARCH_X86 for now) for obvious reasons.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COMPRESS_BOOTBLOCK</td><td>toplevel</td><td>bool</td><td></td><td>
This option can be used to compress the bootblock with LZ4 and attach<br />
a small self-decompression stub to its front. This can drastically<br />
reduce boot time on platforms where the bootblock is loaded over a<br />
very slow connection and bootblock size trumps all other factors for<br />
speed. Since this using this option usually requires changes to the<br />
SoC memlayout and possibly extra support code, it should not be<br />
user-selectable. (There's no real point in offering this to the user<br />
anyway... if it works and saves boot time, you would always want it.)<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INCLUDE_CONFIG_FILE</td><td>toplevel</td><td>bool</td><td>Include the coreboot .config file into the ROM image</td><td>
Include the .config file that was used to compile coreboot<br />
in the (CBFS) ROM image. This is useful if you want to know which<br />
options were used to build a specific coreboot.rom image.<br />
<br />
Saying Y here will increase the image size by 2-3KB.<br />
<br />
You can use the following command to easily list the options:<br />
<br />
grep -a CONFIG_ coreboot.rom<br />
<br />
Alternatively, you can also use cbfstool to print the image<br />
contents (including the raw 'config' item we're looking for).<br />
<br />
Example:<br />
<br />
$ cbfstool coreboot.rom print<br />
coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,<br />
offset 0x0<br />
Alignment: 64 bytes<br />
<br />
Name                           Offset     Type         Size<br />
cmos_layout.bin                0x0        cmos layout  1159<br />
fallback/romstage              0x4c0      stage        339756<br />
fallback/ramstage              0x53440    stage        186664<br />
fallback/payload               0x80dc0    payload      51526<br />
config                         0x8d740    raw          3324<br />
(empty)                        0x8e480    null         3610440<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COLLECT_TIMESTAMPS</td><td>toplevel</td><td>bool</td><td>Create a table of timestamps collected during boot</td><td>
Make coreboot create a table of timer-ID/timer-value pairs to<br />
allow measuring time spent at different phases of the boot process.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIMESTAMPS_ON_CONSOLE</td><td>toplevel</td><td>bool</td><td>Print the timestamp values on the console</td><td>
Print the timestamps to the debug console if enabled at level spew.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_BLOBS</td><td>toplevel</td><td>bool</td><td>Allow use of binary-only repository</td><td>
This draws in the blobs repository, which contains binary files that<br />
might be required for some chipsets or boards.<br />
This flag ensures that a "Free" option remains available for users.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COVERAGE</td><td>toplevel</td><td>bool</td><td>Code coverage support</td><td>
Add code coverage support for coreboot. This will store code<br />
coverage information in CBMEM for extraction from user space.<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UBSAN</td><td>toplevel</td><td>bool</td><td>Undefined behavior sanitizer support</td><td>
Instrument the code with checks for undefined behavior. If unsure,<br />
say N because it adds a small performance penalty and may abort<br />
on code that happens to work in spite of the UB.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RELOCATABLE_RAMSTAGE</td><td>toplevel</td><td>bool</td><td></td><td>
The reloctable ramstage support allows for the ramstage to be built<br />
as a relocatable module. The stage loader can identify a place<br />
out of the OS way so that copying memory is unnecessary during an S3<br />
wake. When selecting this option the romstage is responsible for<br />
determing a stack location to use for loading the ramstage.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</td><td>toplevel</td><td>bool</td><td></td><td>
The relocated ramstage is saved in an area specified by the<br />
by the board and/or chipset.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UPDATE_IMAGE</td><td>toplevel</td><td>bool</td><td>Update existing coreboot.rom image</td><td>
If this option is enabled, no new coreboot.rom file<br />
is created. Instead it is expected that there already<br />
is a suitable file for further processing.<br />
The bootblock will not be modified.<br />
<br />
If unsure, select 'N'<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOTSPLASH_IMAGE</td><td>toplevel</td><td>bool</td><td>Add a bootsplash image</td><td>
Select this option if you have a bootsplash image that you would<br />
like to add to your ROM.<br />
<br />
This will only add the image to the ROM. To actually run it check<br />
options under 'Display' section.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOTSPLASH_FILE</td><td>toplevel</td><td>string</td><td>Bootsplash path and filename</td><td>
The path and filename of the file to use as graphical bootsplash<br />
screen. The file format has to be jpg.<br />
<br />
</td></tr>

<tr bgcolor="#6699dd">
<td colspan=5>Menu: Mainboard</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard</td><td>(comment)</td><td></td><td>Important: Run 'make distclean' before switching boards</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/lippert</td><td>(comment)</td><td></td><td>was acquired by ADLINK</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/adlink</td><td>(comment)</td><td></td><td>see under vendor LiPPERT</td></tr>
<tr bgcolor="#eeeeee">
<td>BOARD_ASUS_F2A85_M_DDR3_VOLT_135</td><td>mainboard/asus/f2a85-m</td><td>bool</td><td>1.35V</td><td>
Set DRR3 memory voltage to 1.35V<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOARD_ASUS_F2A85_M_DDR3_VOLT_150</td><td>mainboard/asus/f2a85-m</td><td>bool</td><td>1.50V</td><td>
Set DRR3 memory voltage to 1.50V<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOARD_ASUS_F2A85_M_DDR3_VOLT_165</td><td>mainboard/asus/f2a85-m</td><td>bool</td><td>1.65V</td><td>
Set DRR3 memory voltage to 1.65V<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NO_POST</td><td>mainboard/purism/librem_skl</td><td>int</td><td></td><td>
This platform does not have any way to see POST codes<br />
so disable them by default.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_PS2_KEYBOARD</td><td>mainboard/purism/librem_bdw</td><td>string</td><td></td><td>
Default PS/2 Keyboard to enabled on this board.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_UART_8250IO</td><td>mainboard/purism/librem_bdw</td><td>string</td><td></td><td>
This platform does not have any way to get standard<br />
serial output so disable it by default.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NO_POST</td><td>mainboard/purism/librem_bdw</td><td>int</td><td></td><td>
This platform does not have any way to see POST codes<br />
so disable them by default.<br />
<br />
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: Debugging</td></tr>
<tr bgcolor="#eeeeee">
<td>DISABLE_UART_ON_TESTPADS</td><td>mainboard/intel/dcp847ske</td><td>bool</td><td>Disable UART on testpads</td><td>
Serial output requires soldering to the testpad next to<br />
NCT5577D pin 18 (txd) and gnd.<br />
<br />
</td></tr>

<tr bgcolor="#eeeeee">
<td>UART_FOR_CONSOLE</td><td>mainboard/intel/mohonpeak</td><td>int</td><td></td><td>
The Mohon Peak board uses COM2 (2f8) for the serial console.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_CONFIGFILE</td><td>mainboard/intel/mohonpeak</td><td>string</td><td></td><td>
The Avoton/Rangeley chip does not allow devices to write into the 0xe000<br />
segment.  This means that USB/SATA devices will not work in SeaBIOS unless<br />
we put the SeaBIOS buffer area down in the 0x9000 segment.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BASEBOARD_GLKRVP_LAPTOP</td><td>mainboard/intel/glkrvp</td><td>None</td><td>ON BOARD EC</td><td>
This option allows you to select the on board EC to use.<br />
Select whether the board  has Intel EC or Chrome EC<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GALILEO_GEN2</td><td>mainboard/intel/galileo</td><td>bool</td><td>Board generation: GEN1 (n) or GEN2 (y)</td><td>
The coreboot binary will configure only one generation of the Galileo<br />
board since coreboot can not determine the board generation at<br />
runtime.  Select which generation of the Galileo that coreboot<br />
should initialize.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_VERSION_1_1</td><td>mainboard/intel/galileo</td><td>bool</td><td>FSP 1.1</td><td>
Use FSP 1_1 binary<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_VERSION_2_0</td><td>mainboard/intel/galileo</td><td>bool</td><td>FSP 2.0</td><td>
Use FSP 2.0 binary<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_BUILD_TYPE_DEBUG</td><td>mainboard/intel/galileo</td><td>bool</td><td>Debug</td><td>
Use the debug version of FSP<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_BUILD_TYPE_RELEASE</td><td>mainboard/intel/galileo</td><td>bool</td><td>Release</td><td>
Use the release version of FSP<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_TYPE_1_1</td><td>mainboard/intel/galileo</td><td>bool</td><td>MemInit subroutine</td><td>
FSP 1.1 implemented as subroutines, no EDK-II cores<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_TYPE_1_1_PEI</td><td>mainboard/intel/galileo</td><td>bool</td><td>SEC + PEI Core + MemInit PEIM</td><td>
FSP 1.1 implemented using SEC and PEI core<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_TYPE_2_0</td><td>mainboard/intel/galileo</td><td>bool</td><td>MemInit subroutine</td><td>
FSP 2.0 implemented as subroutines, no EDK-II cores<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_TYPE_2_0_PEI</td><td>mainboard/intel/galileo</td><td>bool</td><td>SEC + PEI Core + MemInit PEIM</td><td>
FSP 2.0 implemented using SEC and PEI core<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_DEBUG_ALL</td><td>mainboard/intel/galileo</td><td>bool</td><td>Enable all FSP debug support</td><td>
Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA<br />
also turn on FSP 2.0 debug support for ESRAM_LAYOUT,<br />
FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS<br />
or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_WITH_CRYPTO_SHIELD</td><td>mainboard/intel/galileo</td><td>bool</td><td>Verified boot using the Crypto Shield board</td><td>
Perform a verified boot using the TPM on the Crypto Shield board.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVER_TPM_I2C_ADDR</td><td>mainboard/intel/galileo</td><td>hex</td><td>Address of the I2C TPM chip</td><td>
I2C address of the TPM chip on the Crypto Shield board.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FMDFILE</td><td>mainboard/intel/galileo</td><td>string</td><td>FMAP description file in fmd format</td><td>
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,<br />
but in some cases more complex setups are required.<br />
<br />
When an FMD descriptionn file is specified, the build system uses it<br />
instead of creating a default FMAP file.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UART_FOR_CONSOLE</td><td>mainboard/intel/littleplains</td><td>int</td><td></td><td>
The Little Plains board uses COM2 (2f8) for the serial console.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_CONFIGFILE</td><td>mainboard/intel/littleplains</td><td>string</td><td></td><td>
The Avoton/Rangeley chip does not allow devices to write into the 0xe000<br />
segment.  This means that USB/SATA devices will not work in SeaBIOS unless<br />
we put the SeaBIOS buffer area down in the 0x9000 segment.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_FILE</td><td>mainboard/intel/strago</td><td>string</td><td></td><td>
The C0 version of the video bios gets computed from this name<br />
so that they can both be added.  Only the correct one for the<br />
system will be run.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_ID</td><td>mainboard/intel/strago</td><td>string</td><td></td><td>
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded<br />
in soc/intel/braswell/Makefile.inc as 8086,22b1<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_FSP_MEMORY_DOWN</td><td>mainboard/intel/harcuvar</td><td>bool</td><td>Enable Memory Down</td><td>
Select this option to enable Memory Down function.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPD_LOC</td><td>mainboard/intel/harcuvar</td><td>hex</td><td>SPD binary location in cbfs</td><td>
Location of SPD binary for memory down function.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOARD_EMULATION_SPIKE_UCB_RISCV</td><td>mainboard/emulation/spike-riscv.name</td><td>bool</td><td>SPIKE ucb riscv</td><td>
To run coreboot in spike:<br />
* run "make" as usual<br />
* util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}<br />
* spike -m1024 build/coreboot.elf<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/poppy.name</td><td>(comment)</td><td></td><td>Poppy</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/cyan.name</td><td>(comment)</td><td></td><td>Cyan</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/gru.name</td><td>(comment)</td><td></td><td>Gru</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/octopus.name</td><td>(comment)</td><td></td><td>Octopus</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/reef.name</td><td>(comment)</td><td></td><td>Reef</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/veyron.name</td><td>(comment)</td><td></td><td>Veyron</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/oak.name</td><td>(comment)</td><td></td><td>Oak</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/jecht.name</td><td>(comment)</td><td></td><td>Jecht</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/rambi.name</td><td>(comment)</td><td></td><td>Rambi</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/beltino.name</td><td>(comment)</td><td></td><td>Beltino</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/zoombini.name</td><td>(comment)</td><td></td><td>Zoombini</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/kahlee.name</td><td>(comment)</td><td></td><td>Kahlee</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/slippy.name</td><td>(comment)</td><td></td><td>Slippy</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard/google/auron.name</td><td>(comment)</td><td></td><td>Auron</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_PART_NUMBER</td><td>mainboard/google/nyan_big</td><td>string</td><td>BCT boot media</td><td>
Which boot media to configure the BCT for.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NYAN_BIG_BCT_CFG_SPI</td><td>mainboard/google/nyan_big</td><td>bool</td><td>SPI</td><td>
Configure the BCT for booting from SPI.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NYAN_BIG_BCT_CFG_EMMC</td><td>mainboard/google/nyan_big</td><td>bool</td><td>eMMC</td><td>
Configure the BCT for booting from eMMC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOT_DEVICE_SPI_FLASH_BUS</td><td>mainboard/google/nyan_big</td><td>int</td><td>SPI bus with boot media ROM</td><td>
Which SPI bus the boot media is connected to.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DISPLAY_SPD_DATA</td><td>mainboard/google/cyan</td><td>bool</td><td>Display Memory Serial Presence Detect Data</td><td>
When enabled displays the memory configuration data.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_FILE</td><td>mainboard/google/cyan</td><td>string</td><td></td><td>
The C0 version of the video bios gets computed from this name<br />
so that they can both be added.  Only the correct one for the<br />
system will be run.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_ID</td><td>mainboard/google/cyan</td><td>string</td><td></td><td>
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded<br />
in soc/intel/braswell/Makefile.inc as 8086,22b1<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_PART_NUMBER</td><td>mainboard/google/nyan_blaze</td><td>string</td><td>BCT boot media</td><td>
Which boot media to configure the BCT for.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NYAN_BLAZE_BCT_CFG_SPI</td><td>mainboard/google/nyan_blaze</td><td>bool</td><td>SPI</td><td>
Configure the BCT for booting from SPI.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NYAN_BLAZE_BCT_CFG_EMMC</td><td>mainboard/google/nyan_blaze</td><td>bool</td><td>eMMC</td><td>
Configure the BCT for booting from eMMC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOT_DEVICE_SPI_FLASH_BUS</td><td>mainboard/google/nyan_blaze</td><td>int</td><td>SPI bus with boot media ROM</td><td>
Which SPI bus the boot media is connected to.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRAM_SIZE_MB</td><td>mainboard/google/foster</td><td>int</td><td>BCT boot media</td><td>
Which boot media to configure the BCT for.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FOSTER_BCT_CFG_SPI</td><td>mainboard/google/foster</td><td>bool</td><td>SPI</td><td>
Configure the BCT for booting from SPI.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FOSTER_BCT_CFG_EMMC</td><td>mainboard/google/foster</td><td>bool</td><td>eMMC</td><td>
Configure the BCT for booting from eMMC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOT_DEVICE_SPI_FLASH_BUS</td><td>mainboard/google/foster</td><td>int</td><td>SPI bus with boot media ROM</td><td>
Which SPI bus the boot media is connected to.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_PART_NUMBER</td><td>mainboard/google/nyan</td><td>string</td><td>BCT boot media</td><td>
Which boot media to configure the BCT for.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NYAN_BCT_CFG_SPI</td><td>mainboard/google/nyan</td><td>bool</td><td>SPI</td><td>
Configure the BCT for booting from SPI.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NYAN_BCT_CFG_EMMC</td><td>mainboard/google/nyan</td><td>bool</td><td>eMMC</td><td>
Configure the BCT for booting from eMMC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOT_DEVICE_SPI_FLASH_BUS</td><td>mainboard/google/nyan</td><td>int</td><td>SPI bus with boot media ROM</td><td>
Which SPI bus the boot media is connected to.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRAM_SIZE_MB</td><td>mainboard/google/smaug</td><td>int</td><td>BCT boot media</td><td>
Which boot media to configure the BCT for.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SMAUG_BCT_CFG_SPI</td><td>mainboard/google/smaug</td><td>bool</td><td>SPI</td><td>
Configure the BCT for booting from SPI.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SMAUG_BCT_CFG_EMMC</td><td>mainboard/google/smaug</td><td>bool</td><td>eMMC</td><td>
Configure the BCT for booting from eMMC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOT_DEVICE_SPI_FLASH_BUS</td><td>mainboard/google/smaug</td><td>int</td><td>SPI bus with boot media ROM</td><td>
Which SPI bus the boot media is connected to.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FMDFILE</td><td>mainboard/google/kahlee</td><td>string</td><td></td><td>
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,<br />
but in some cases more complex setups are required.<br />
When an fmd is specified, it overrides the default format.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BMC_INFO_LOC</td><td>mainboard/scaleway/tagada</td><td>hex</td><td>BMC information location in flash</td><td>
Location of BMC SERIAL information.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_DP3_DAUGHTER_CARD_IN_J120</td><td>mainboard/amd/lamar</td><td>bool</td><td>Use J120 as an additional graphics port</td><td>
The PCI Express slot at J120 can be configured as an additional<br />
DisplayPort connector using an adapter card from AMD or as a normal<br />
PCI Express (x4) slot.<br />
<br />
By default, the connector is configured as a PCI Express (x4) slot.<br />
<br />
Select this option to enable the slot for use with one of AMD's<br />
passive graphics port expander cards (only available from AMD).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UART_FOR_CONSOLE</td><td>mainboard/adi/rcc-dff</td><td>int</td><td></td><td>
The Mohon Peak board uses COM2 (2f8) for the serial console.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_CONFIGFILE</td><td>mainboard/adi/rcc-dff</td><td>string</td><td></td><td>
The Avoton/Rangeley chip does not allow devices to write into the 0xe000<br />
segment.  This means that USB/SATA devices will not work in SeaBIOS unless<br />
we put the SeaBIOS buffer area down in the 0x9000 segment.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_LEGACY_FREE</td><td>mainboard/bap/ode_e21XX</td><td>bool</td><td>Select DDR3 clock</td><td>
Select your preferenced DDR3 clock setting.<br />
<br />
Note: This option changes the total power consumption.<br />
<br />
If unsure, use DDR3-1333.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_LEGACY_FREE</td><td>mainboard/bap/ode_e20XX</td><td>bool</td><td>Select DDR3 clock</td><td>
Select your preferred DDR3 clock setting.<br />
<br />
Note: This option changes the total power consumption.<br />
<br />
If unsure, use DDR3-1066.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>mainboard</td><td>(comment)</td><td></td><td>WARNING: This mainboard uses LATE_CBMEM_INIT, which is deprecated</td></tr>
<tr bgcolor="#eeeeee">
<td>BOARD_ROMSIZE_KB_65536</td><td>mainboard</td><td>bool</td><td>ROM chip size</td><td>
Select the size of the ROM chip you intend to flash coreboot on.<br />
<br />
The build system will take care of creating a coreboot.rom file<br />
of the matching size.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_64</td><td>mainboard</td><td>bool</td><td>64 KB</td><td>
Choose this option if you have a 64 KB ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_128</td><td>mainboard</td><td>bool</td><td>128 KB</td><td>
Choose this option if you have a 128 KB ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_256</td><td>mainboard</td><td>bool</td><td>256 KB</td><td>
Choose this option if you have a 256 KB ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_512</td><td>mainboard</td><td>bool</td><td>512 KB</td><td>
Choose this option if you have a 512 KB ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_1024</td><td>mainboard</td><td>bool</td><td>1024 KB (1 MB)</td><td>
Choose this option if you have a 1024 KB (1 MB) ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_2048</td><td>mainboard</td><td>bool</td><td>2048 KB (2 MB)</td><td>
Choose this option if you have a 2048 KB (2 MB) ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_4096</td><td>mainboard</td><td>bool</td><td>4096 KB (4 MB)</td><td>
Choose this option if you have a 4096 KB (4 MB) ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_8192</td><td>mainboard</td><td>bool</td><td>8192 KB (8 MB)</td><td>
Choose this option if you have a 8192 KB (8 MB) ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_10240</td><td>mainboard</td><td>bool</td><td>10240 KB (10 MB)</td><td>
Choose this option if you have a 10240 KB (10 MB) ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_12288</td><td>mainboard</td><td>bool</td><td>12288 KB (12 MB)</td><td>
Choose this option if you have a 12288 KB (12 MB) ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_16384</td><td>mainboard</td><td>bool</td><td>16384 KB (16 MB)</td><td>
Choose this option if you have a 16384 KB (16 MB) ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_32768</td><td>mainboard</td><td>bool</td><td>32768 KB (32 MB)</td><td>
Choose this option if you have a 32768 KB (32 MB) ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COREBOOT_ROMSIZE_KB_65536</td><td>mainboard</td><td>bool</td><td>65536 KB (64 MB)</td><td>
Choose this option if you have a 65536 KB (64 MB) ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_POWER_BUTTON</td><td>mainboard</td><td>bool</td><td>Enable the power button</td><td>
The selected mainboard can optionally have the power button tied<br />
to ground with a jumper so that the button appears to be<br />
constantly depressed. If this option is enabled and the jumper is<br />
installed then the board will turn on, but turn off again after a<br />
short timeout, usually 4 seconds.<br />
<br />
Select Y here if you have removed the jumper and want to use an<br />
actual power button. Select N if you have the jumper installed.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEVICETREE</td><td>toplevel</td><td>string</td><td></td><td>
This symbol allows mainboards to select a different file under their<br />
mainboard directory for the devicetree.cb file.  This allows the board<br />
variants that need different devicetrees to be in the same directory.<br />
<br />
Examples: "devicetree.variant.cb"<br />
"variant/devicetree.cb"<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CBFS_SIZE</td><td>toplevel</td><td>hex</td><td>Size of CBFS filesystem in ROM</td><td>
This is the part of the ROM actually managed by CBFS, located at the<br />
end of the ROM (passed through cbfstool -o) on x86 and at at the start<br />
of the ROM (passed through cbfstool -s) everywhere else. It defaults<br />
to span the whole ROM on all but Intel systems that use an Intel Firmware<br />
Descriptor.  It can be overridden to make coreboot live alongside other<br />
components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE<br />
binaries.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FMDFILE</td><td>toplevel</td><td>string</td><td>fmap description file in fmd format</td><td>
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,<br />
but in some cases more complex setups are required.<br />
When an fmd is specified, it overrides the default format.<br />
<br />
</td></tr>

<tr bgcolor="#eeeeee">
<td>CBFS_AUTOGEN_ATTRIBUTES</td><td>toplevel</td><td>bool</td><td></td><td>
If this option is selected, every file in cbfs which has a constraint<br />
regarding position or alignment will get an additional file attribute<br />
which describes this constraint.<br />
<br />
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: Chipset</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>toplevel</td><td>(comment)</td><td></td><td>SoC</td></tr>
<tr bgcolor="#eeeeee">
<td>SBL_BLOB</td><td>soc/qualcomm/ipq806x</td><td>string</td><td>file name of the Qualcomm SBL blob</td><td>
The path and filename of the binary blob containing<br />
ipq806x early initialization code, as supplied by the<br />
vendor.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IPQ_QFN_PART</td><td>soc/qualcomm/ipq40xx</td><td>bool</td><td></td><td>
Is the SoC a QFN part (as opposed to a BGA part)<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SBL_ELF</td><td>soc/qualcomm/ipq40xx</td><td>string</td><td>file name of the QCA SBL ELF</td><td>
The path and filename of the binary blob containing<br />
ipq40xx early initialization code, as supplied by the<br />
vendor.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SBL_UTIL_PATH</td><td>soc/qualcomm/ipq40xx</td><td>string</td><td>Path for utils to combine SBL_ELF and bootblock</td><td>
Path for utils to combine SBL_ELF and bootblock<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_MVMAP2315_UART_ADDRESS</td><td>soc/marvell/mvmap2315</td><td>hex</td><td></td><td>
Map the UART to the respective MMIO address<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TTYS0_BAUD</td><td>soc/marvell/mvmap2315</td><td>int</td><td></td><td>
Baud rate for the UART<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_APOLLOLAKE</td><td>soc/intel/apollolake</td><td>bool</td><td></td><td>
Intel Apollolake support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_GLK</td><td>soc/intel/apollolake</td><td>bool</td><td></td><td>
Intel GLK support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TPM_ON_FAST_SPI</td><td>soc/intel/apollolake</td><td>bool</td><td></td><td>
TPM part is conntected on Fast SPI interface, but the LPC MMIO<br />
TPM transactions are decoded and serialized over the SPI interface.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCR_BASE_ADDRESS</td><td>soc/intel/apollolake</td><td>hex</td><td></td><td>
This option allows you to select MMIO Base Address of sideband bus.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_SIZE</td><td>soc/intel/apollolake</td><td>hex</td><td></td><td>
The size of the cache-as-ram region required during bootblock<br />
and/or romstage.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_BSP_STACK_SIZE</td><td>soc/intel/apollolake</td><td>hex</td><td></td><td>
The amount of anticipated stack usage in CAR by bootblock and<br />
other stages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ROMSTAGE_ADDR</td><td>soc/intel/apollolake</td><td>hex</td><td></td><td>
The base address (in CAR) where romstage should be linked<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VERSTAGE_ADDR</td><td>soc/intel/apollolake</td><td>hex</td><td></td><td>
The base address (in CAR) where verstage should be linked<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_M_ADDR</td><td>soc/intel/apollolake</td><td>hex</td><td></td><td>
The address FSP-M will be relocated to during build time<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NEED_LBP2</td><td>soc/intel/apollolake</td><td>bool</td><td>Write contents for logical boot partition 2.</td><td>
Write the contents from a file into the logical boot partition 2<br />
region defined by LBP2_FMAP_NAME.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LBP2_FMAP_NAME</td><td>soc/intel/apollolake</td><td>string</td><td>Name of FMAP region to put logical boot partition 2</td><td>
Name of FMAP region to write logical boot partition 2 data.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LBP2_FILE_NAME</td><td>soc/intel/apollolake</td><td>string</td><td>Path of file to write to logical boot partition 2 region</td><td>
Name of file to store in the logical boot partition 2 region.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NEED_IFWI</td><td>soc/intel/apollolake</td><td>bool</td><td>Write content into IFWI region</td><td>
Write the content from a file into IFWI region defined by<br />
IFWI_FMAP_NAME.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IFWI_FMAP_NAME</td><td>soc/intel/apollolake</td><td>string</td><td>Name of FMAP region to pull IFWI into</td><td>
Name of FMAP region to write IFWI.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IFWI_FILE_NAME</td><td>soc/intel/apollolake</td><td>string</td><td>Path of file to write to IFWI region</td><td>
Name of file to store in the IFWI region.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DMIC_1CH_16B</td><td>soc/intel/apollolake</td><td>bool</td><td></td><td>
Include DSP firmware settings for 1 channel 16B DMIC array.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DMIC_2CH_16B</td><td>soc/intel/apollolake</td><td>bool</td><td></td><td>
Include DSP firmware settings for 2 channel 16B DMIC array.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DMIC_4CH_16B</td><td>soc/intel/apollolake</td><td>bool</td><td></td><td>
Include DSP firmware settings for 4 channel 16B DMIC array.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_MAX98357</td><td>soc/intel/apollolake</td><td>bool</td><td></td><td>
Include DSP firmware settings for headset codec.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DA7219</td><td>soc/intel/apollolake</td><td>bool</td><td></td><td>
Include DSP firmware settings for headset codec.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_RT5682</td><td>soc/intel/apollolake</td><td>bool</td><td></td><td>
Include DSP firmware settings for headset codec.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_RT5682</td><td>soc/intel/apollolake</td><td>bool</td><td>Cache-as-ram implementation</td><td>
This option allows you to select how cache-as-ram (CAR) is set up.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CAR_NEM</td><td>soc/intel/apollolake</td><td>bool</td><td>Non-evict mode</td><td>
Traditionally, CAR is set up by using Non-Evict mode. This method<br />
does not allow CAR and cache to co-exist, because cache fills are<br />
block in NEM mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CAR_CQOS</td><td>soc/intel/apollolake</td><td>bool</td><td>Cache Quality of Service</td><td>
Cache Quality of Service allows more fine-grained control of cache<br />
usage. As result, it is possible to set up portion of L2 cache for<br />
CAR and use remainder for actual caching.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_APOLLOLAKE_FSP_CAR</td><td>soc/intel/apollolake</td><td>bool</td><td>Use FSP CAR</td><td>
Use FSP APIs to initialize &amp; tear down the Cache-As-Ram.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>APL_SKIP_SET_POWER_LIMITS</td><td>soc/intel/apollolake</td><td>bool</td><td></td><td>
Some Apollo Lake mainboards do not need the Running Average Power<br />
Limits (RAPL) algorithm for a constant power management.<br />
Set this config option to skip the RAPL configuration.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_ESPI</td><td>soc/intel/apollolake</td><td>bool</td><td></td><td>
Use eSPI bus instead of LPC<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_BAYTRAIL</td><td>soc/intel/baytrail</td><td>bool</td><td></td><td>
Bay Trail M/D part support.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_MRC</td><td>soc/intel/baytrail</td><td>bool</td><td>Add a Memory Reference Code binary</td><td>
Select this option to add a blob containing<br />
memory reference code.<br />
Note: Without this binary coreboot will not work<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MRC_FILE</td><td>soc/intel/baytrail</td><td>string</td><td>Intel memory refeference code path and filename</td><td>
The path and filename of the file to use as System Agent<br />
binary. Note that this points to the sandybridge binary file<br />
which is will not work, but it serves its purpose to do builds.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_SIZE</td><td>soc/intel/baytrail</td><td>hex</td><td></td><td>
The size of the cache-as-ram region required during bootblock<br />
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE<br />
must add up to a power of 2.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_MRC_VAR_SIZE</td><td>soc/intel/baytrail</td><td>hex</td><td></td><td>
The amount of cache-as-ram region required by the reference code.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RESET_ON_INVALID_RAMSTAGE_CACHE</td><td>soc/intel/baytrail</td><td>bool</td><td>Reset the system on S3 wake when ramstage cache invalid.</td><td>
The baytrail romstage code caches the loaded ramstage program<br />
in SMM space. On S3 wake the romstage will copy over a fresh<br />
ramstage that was cached in the SMM space. This option determines<br />
the action to take when the ramstage cache is invalid. If selected<br />
the system will reset otherwise the ramstage will be reloaded from<br />
cbfs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_BUILTIN_COM1</td><td>soc/intel/baytrail</td><td>bool</td><td>Enable builtin COM1 Serial Port</td><td>
The PMC has a legacy COM1 serial port. Choose this option to<br />
configure the pads and enable it. This serial port can be used for<br />
the debug console.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_REFCODE_BLOB</td><td>soc/intel/baytrail</td><td>bool</td><td>An external reference code blob should be put into cbfs.</td><td>
The reference code blob will be placed into cbfs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>REFCODE_BLOB_FILE</td><td>soc/intel/baytrail</td><td>string</td><td>Path and filename to reference code blob.</td><td>
The path and filename to the file to be added to cbfs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_BRASWELL</td><td>soc/intel/braswell</td><td>bool</td><td></td><td>
Braswell M/D part support.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_SIZE</td><td>soc/intel/braswell</td><td>hex</td><td></td><td>
The size of the cache-as-ram region required during bootblock<br />
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE<br />
must add up to a power of 2.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RESET_ON_INVALID_RAMSTAGE_CACHE</td><td>soc/intel/braswell</td><td>bool</td><td>Reset the system on S3 wake when ramstage cache invalid.</td><td>
The haswell romstage code caches the loaded ramstage program<br />
in SMM space. On S3 wake the romstage will copy over a fresh<br />
ramstage that was cached in the SMM space. This option determines<br />
the action to take when the ramstage cache is invalid. If selected<br />
the system will reset otherwise the ramstage will be reloaded from<br />
cbfs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_BUILTIN_COM1</td><td>soc/intel/braswell</td><td>bool</td><td>Enable builtin COM1 Serial Port</td><td>
The PMC has a legacy COM1 serial port. Choose this option to<br />
configure the pads and enable it. This serial port can be used for<br />
the debug console.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_BROADWELL</td><td>soc/intel/broadwell</td><td>bool</td><td></td><td>
Intel Broadwell and Haswell ULT support.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_SIZE</td><td>soc/intel/broadwell</td><td>hex</td><td></td><td>
The size of the cache-as-ram region required during bootblock<br />
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE<br />
must add up to a power of 2.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_MRC_VAR_SIZE</td><td>soc/intel/broadwell</td><td>hex</td><td></td><td>
The amount of cache-as-ram region required by the reference code.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_MRC</td><td>soc/intel/broadwell</td><td>bool</td><td>Add a Memory Reference Code binary</td><td>
Select this option to add a Memory Reference Code binary to<br />
the resulting coreboot image.<br />
<br />
Note: Without this binary coreboot will not work<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MRC_FILE</td><td>soc/intel/broadwell</td><td>string</td><td>Intel Memory Reference Code path and filename</td><td>
The filename of the file to use as Memory Reference Code binary.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PRE_GRAPHICS_DELAY</td><td>soc/intel/broadwell</td><td>int</td><td>Graphics initialization delay in ms</td><td>
On some systems, coreboot boots so fast that connected monitors<br />
(mostly TVs) won't be able to wake up fast enough to talk to the<br />
VBIOS. On those systems we need to wait for a bit before executing<br />
the VBIOS.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RESET_ON_INVALID_RAMSTAGE_CACHE</td><td>soc/intel/broadwell</td><td>bool</td><td>Reset the system on S3 wake when ramstage cache invalid.</td><td>
The romstage code caches the loaded ramstage program in SMM space.<br />
On S3 wake the romstage will copy over a fresh ramstage that was<br />
cached in the SMM space. This option determines the action to take<br />
when the ramstage cache is invalid. If selected the system will<br />
reset otherwise the ramstage will be reloaded from cbfs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIRQ_CONTINUOUS_MODE</td><td>soc/intel/broadwell</td><td>bool</td><td></td><td>
If you set this option to y, the serial IRQ machine will be<br />
operated in continuous mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_REFCODE_BLOB</td><td>soc/intel/broadwell</td><td>bool</td><td>An external reference code blob should be put into cbfs.</td><td>
The reference code blob will be placed into cbfs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>REFCODE_BLOB_FILE</td><td>soc/intel/broadwell</td><td>string</td><td>Path and filename to reference code blob.</td><td>
The path and filename to the file to be added to cbfs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_CANNONLAKE</td><td>soc/intel/cannonlake</td><td>bool</td><td></td><td>
Intel Cannonlake support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UART_FOR_CONSOLE</td><td>soc/intel/cannonlake</td><td>int</td><td>Index for LPSS UART port to use for console</td><td>
Index for LPSS UART port to use for console:<br />
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_SIZE</td><td>soc/intel/cannonlake</td><td>int</td><td></td><td>
The size of the cache-as-ram region required during bootblock<br />
and/or romstage.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_BSP_STACK_SIZE</td><td>soc/intel/cannonlake</td><td>hex</td><td></td><td>
The amount of anticipated stack usage in CAR by bootblock and<br />
other stages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DMIC_1CH_16B</td><td>soc/intel/cannonlake</td><td>bool</td><td></td><td>
Include DSP firmware settings for 1 channel 16B DMIC array.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DMIC_2CH_16B</td><td>soc/intel/cannonlake</td><td>bool</td><td></td><td>
Include DSP firmware settings for 2 channel 16B DMIC array.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DMIC_4CH_16B</td><td>soc/intel/cannonlake</td><td>bool</td><td></td><td>
Include DSP firmware settings for 4 channel 16B DMIC array.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_MAX98357</td><td>soc/intel/cannonlake</td><td>bool</td><td></td><td>
Include DSP firmware settings for headset codec.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_MAX98373</td><td>soc/intel/cannonlake</td><td>bool</td><td></td><td>
Include DSP firmware settings for headset codec.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DA7219</td><td>soc/intel/cannonlake</td><td>bool</td><td></td><td>
Include DSP firmware settings for headset codec.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCR_BASE_ADDRESS</td><td>soc/intel/cannonlake</td><td>hex</td><td></td><td>
This option allows you to select MMIO Base Address of sideband bus.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>C_ENV_BOOTBLOCK_SIZE</td><td>soc/intel/cannonlake</td><td>hex</td><td>Cache-as-ram implementation</td><td>
This option allows you to select how cache-as-ram (CAR) is set up.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_CANNONLAKE_CAR_NEM_ENHANCED</td><td>soc/intel/cannonlake</td><td>bool</td><td>Enhanced Non-evict mode</td><td>
A current limitation of NEM (Non-Evict mode) is that code and data<br />
sizes are derived from the requirement to not write out any modified<br />
cache line. With NEM, if there is no physical memory behind the<br />
cached area, the modified data will be lost and NEM results will be<br />
inconsistent. ENHANCED NEM guarantees that modified data is always<br />
kept in cache while clean data is replaced.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_CANNONLAKE_FSP_CAR</td><td>soc/intel/cannonlake</td><td>bool</td><td>Use FSP CAR</td><td>
Use FSP APIs to initialize and tear down the Cache-As-Ram.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_DENVERTON_NS</td><td>soc/intel/denverton_ns</td><td>bool</td><td></td><td>
Intel Denverton-NS SoC support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_T_ADDR</td><td>soc/intel/denverton_ns</td><td>hex</td><td>Intel FSP-T (temp ram init) binary location</td><td>
The memory location of the Intel FSP-T binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_M_ADDR</td><td>soc/intel/denverton_ns</td><td>hex</td><td>Intel FSP-M (memory init) binary location</td><td>
The memory location of the Intel FSP-M binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_S_ADDR</td><td>soc/intel/denverton_ns</td><td>hex</td><td>Intel FSP-S (silicon init) binary location</td><td>
The memory location of the Intel FSP-S binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCR_BASE_ADDRESS</td><td>soc/intel/denverton_ns</td><td>hex</td><td></td><td>
This option allows you to select MMIO Base Address of sideband bus.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IQAT_MEMORY_REGION_SIZE</td><td>soc/intel/denverton_ns</td><td>hex</td><td></td><td>
Do not change this value<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NON_LEGACY_UART_MODE</td><td>soc/intel/denverton_ns</td><td>bool</td><td>Non Legacy Mode</td><td>
Disable legacy UART mode<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LEGACY_UART_MODE</td><td>soc/intel/denverton_ns</td><td>bool</td><td>Legacy Mode</td><td>
Enable legacy UART mode<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DENVERTON_NS_CAR_NEM_ENHANCED</td><td>soc/intel/denverton_ns</td><td>bool</td><td>Enhanced Non-evict mode</td><td>
A current limitation of NEM (Non-Evict mode) is that code and data sizes<br />
are derived from the requirement to not write out any modified cache line.<br />
With NEM, if there is no physical memory behind the cached area,<br />
the modified data will be lost and NEM results will be inconsistent.<br />
ENHANCED NEM guarantees that modified data is always<br />
kept in cache while clean data is replaced.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_FSP_BAYTRAIL</td><td>soc/intel/fsp_baytrail</td><td>bool</td><td></td><td>
Bay Trail I part support using the Intel FSP.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SMM_TSEG_SIZE</td><td>soc/intel/fsp_baytrail</td><td>hex</td><td></td><td>
This is set by the FSP<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_ID</td><td>soc/intel/fsp_baytrail</td><td>string</td><td></td><td>
This is the default PCI ID for the Bay Trail graphics<br />
devices.  This string names the vbios ROM in cbfs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_BUILTIN_COM1</td><td>soc/intel/fsp_baytrail</td><td>bool</td><td>Enable built-in legacy Serial Port</td><td>
The Baytrail SOC has one legacy serial port. Choose this option to<br />
configure the pads and enable it. This serial port can be used for<br />
the debug console.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_FILE</td><td>soc/intel/fsp_baytrail/fsp</td><td>string</td><td></td><td>
The path and filename of the Intel FSP binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_LOC</td><td>soc/intel/fsp_baytrail/fsp</td><td>hex</td><td></td><td>
The location in CBFS that the FSP is located. This must match the<br />
value that is set in the FSP binary.  If the FSP needs to be moved,<br />
rebase the FSP with Intel's BCT (tool).<br />
<br />
The Bay Trail FSP is built with a preferred base address of<br />
0xFFFC0000.<br />
<br />
</td></tr>
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_FSP_BROADWELL_DE</td><td>soc/intel/fsp_broadwell_de</td><td>bool</td><td></td><td>
Broadwell-DE support using the Intel FSP.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEGRATED_UART</td><td>soc/intel/fsp_broadwell_de</td><td>bool</td><td>Integrated UART ports</td><td>
Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIRQ_CONTINUOUS_MODE</td><td>soc/intel/fsp_broadwell_de</td><td>bool</td><td></td><td>
If you set this option to y, the serial IRQ machine will be<br />
operated in continuous mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_FILE</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>string</td><td></td><td>
The path and filename of the Intel FSP binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_LOC</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>hex</td><td></td><td>
The location in CBFS that the FSP is located. This must match the<br />
value that is set in the FSP binary.  If the FSP needs to be moved,<br />
rebase the FSP with Intel's BCT (tool).<br />
<br />
The Broadwell-DE FSP is built with a preferred base address of<br />
0xffeb0000.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_BASE</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>hex</td><td></td><td>
This address needs to match the setup performed inside FSP.<br />
On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_SIZE</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>hex</td><td></td><td>
The DCACHE is shared between FSP itself and the rest of the coreboot<br />
stages. A size of 0x8000 works fine while providing enough space for<br />
features like VBOOT in verstage. Further increase to a power of two<br />
aligned value leads to errors in FSP.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_MEMORY_DOWN</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>bool</td><td>Enable Memory Down</td><td>
Load SPD data from ROM instead of trying to read from SMBus.<br />
<br />
If the platform has DIMM sockets, say N. If memory is down, say Y and<br />
supply the appropriate SPD data for each Channel/DIMM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>bool</td><td>Channel 0, DIMM 0 Present</td><td>
Select Y if Channel 0, DIMM 0 is present.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>string</td><td>Channel 0, DIMM 0 SPD File</td><td>
Path to the file which contains the SPD data for Channel 0, DIMM 0.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>bool</td><td>Channel 0, DIMM 1 Present</td><td>
Select Y if Channel 0, DIMM 1 is present.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>string</td><td>Channel 0, DIMM 1 SPD File</td><td>
Path to the file which contains the SPD data for Channel 0, DIMM 1.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>bool</td><td>Channel 1, DIMM 0 Present</td><td>
Select Y if Channel 1, DIMM 0 is present.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>string</td><td>Channel 1, DIMM 0 SPD File</td><td>
Path to the file which contains the SPD data for Channel 1, DIMM 0.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>bool</td><td>Channel 1, DIMM 1 Present</td><td>
Select Y if Channel 1, DIMM 1 is present.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>string</td><td>Channel 1, DIMM 1 SPD File</td><td>
Path to the file which contains the SPD data for Channel 1, DIMM 1.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_HYPERTHREADING</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>bool</td><td>Enable Hyper-Threading</td><td>
Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_EHCI1_ENABLE</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>bool</td><td>EHCI1 Enable</td><td>
Enable EHCI controller 1<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_EHCI2_ENABLE</td><td>soc/intel/fsp_broadwell_de/fsp</td><td>bool</td><td>EHCI2 Enable</td><td>
Enable EHCI controller 2<br />
<br />
</td></tr>
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_QUARK</td><td>soc/intel/quark</td><td>bool</td><td></td><td>
Intel Quark support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_BUILTIN_HSUART0</td><td>soc/intel/quark</td><td>bool</td><td>Enable built-in HSUART0</td><td>
The Quark SoC has two HSUART. Choose this option to configure the pads<br />
and enable HSUART0, which can be used for the debug console.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_BUILTIN_HSUART1</td><td>soc/intel/quark</td><td>bool</td><td>Enable built-in HSUART1</td><td>
The Quark SoC has two HSUART. Choose this option to configure the pads<br />
and enable HSUART1, which can be used for the debug console.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TTYS0_BASE</td><td>soc/intel/quark</td><td>hex</td><td>HSUART Base Address</td><td>
Memory mapped MMIO of HSUART.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_DEBUG_LED</td><td>soc/intel/quark</td><td>bool</td><td></td><td>
Enable the use of the SD LED for early debugging before serial output<br />
is available.  Setting this LED indicates that control has reached the<br />
desired check point.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_DEBUG_LED_ESRAM</td><td>soc/intel/quark</td><td>bool</td><td>SD LED indicates ESRAM initialized</td><td>
Indicate that ESRAM has been successfully initialized.  If the SD LED<br />
does not light then the ESRAM initialization needs to be debugged.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_DEBUG_LED_FINDFSP</td><td>soc/intel/quark</td><td>bool</td><td>SD LED indicates fsp.bin file was found</td><td>
Indicate that fsp.bin was found.  If the SD LED does not light then<br />
the code between ESRAM initialization through find_fsp needs to<br />
debugged.  Start by verifying that the correct fsp.bin is in the<br />
image.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY</td><td>soc/intel/quark</td><td>bool</td><td>SD LED indicates bootblock.c successfully entered</td><td>
Indicate that bootblock_c_entry was entered.  If the SD LED does not<br />
light then debug the code between ESRAM and bootblock_c_entry.  For<br />
FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY</td><td>soc/intel/quark</td><td>bool</td><td>SD LED indicates bootblock_soc_early_init successfully entered</td><td>
Indicate that bootblock_soc_early_init was entered.  If the SD LED<br />
does not light then debug the code in bootblock_main_with_timestamp.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT</td><td>soc/intel/quark</td><td>bool</td><td>SD LED indicates bootblock_soc_early_init successfully exited</td><td>
Indicate that bootblock_soc_early_init exited.  If the SD LED does not<br />
light then debug the scripts in bootblock_soc_early_init.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_DEBUG_LED_SOC_INIT_ENTRY</td><td>soc/intel/quark</td><td>bool</td><td>SD LED indicates bootblock_soc_init successfully entered</td><td>
Indicate that bootblock_soc_init was entered.  If the SD LED does not<br />
light then debug the code in bootblock_mainboard_early_init and<br />
console_init.  If the SD LED does light but there is no serial then<br />
debug the serial port configuration and initialization.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DISPLAY_ESRAM_LAYOUT</td><td>soc/intel/quark</td><td>bool</td><td>Display ESRAM layout</td><td>
Select this option to display coreboot's use of ESRAM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CBFS_SIZE</td><td>soc/intel/quark</td><td>hex</td><td></td><td>
Specify the size of the coreboot file system in the read-only (recovery)<br />
portion of the flash part.  On Quark systems the firmware image stores<br />
more than just coreboot, including:<br />
- The chipset microcode (RMU) binary file located at 0xFFF00000<br />
- Intel Trusted Execution Engine firmware<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ADD_FSP_RAW_BIN</td><td>soc/intel/quark</td><td>bool</td><td>Add the Intel FSP binary to the flash image without relocation</td><td>
Select this option to add an Intel FSP binary to<br />
the resulting coreboot image.<br />
<br />
Note: Without this binary, coreboot builds relying on the FSP<br />
will not boot<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_FILE</td><td>soc/intel/quark</td><td>string</td><td>Intel FSP binary path and filename</td><td>
The path and filename of the Intel FSP binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_LOC</td><td>soc/intel/quark</td><td>hex</td><td></td><td>
The location in CBFS that the FSP is located. This must match the<br />
value that is set in the FSP binary.  If the FSP needs to be moved,<br />
rebase the FSP with Intel's BCT (tool).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_ESRAM_LOC</td><td>soc/intel/quark</td><td>hex</td><td></td><td>
The location in ESRAM where a copy of the FSP binary is placed.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RELOCATE_FSP_INTO_DRAM</td><td>soc/intel/quark</td><td>bool</td><td>Relocate FSP into DRAM</td><td>
Relocate the FSP binary into DRAM before the call to SiliconInit.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ADD_RMU_FILE</td><td>soc/intel/quark</td><td>bool</td><td>Should the RMU binary be added to the flash image?</td><td>
The RMU file is required to get the chip out of reset.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RMU_FILE</td><td>soc/intel/quark</td><td>string</td><td></td><td>
The path and filename of the Intel Quark RMU binary.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RMU_LOC</td><td>soc/intel/quark</td><td>hex</td><td></td><td>
The location in CBFS that the RMU is located. It must match the<br />
strap-determined base address.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>STORAGE_TEST</td><td>soc/intel/quark</td><td>bool</td><td>Test SD/MMC/eMMC card or device access</td><td>
Read block 0 from each parition of the storage device.  User<br />
must also enable one or both of COMMONLIB_STORAGE_SD or<br />
COMMONLIB_STORAGE_MMC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>I2C_DEBUG</td><td>soc/intel/quark</td><td>bool</td><td>Enable I2C debugging</td><td>
Display the I2C segments and controller errors<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_SKYLAKE</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Intel Skylake support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_KABYLAKE</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Intel Kabylake support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_SIZE</td><td>soc/intel/skylake</td><td>hex</td><td></td><td>
The size of the cache-as-ram region required during bootblock<br />
and/or romstage.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_BSP_STACK_SIZE</td><td>soc/intel/skylake</td><td>hex</td><td></td><td>
The amount of anticipated stack usage in CAR by bootblock and<br />
other stages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EXCLUDE_NATIVE_SD_INTERFACE</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
If you set this option to n, will not use native SD controller.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCR_BASE_ADDRESS</td><td>soc/intel/skylake</td><td>hex</td><td></td><td>
This option allows you to select MMIO Base Address of sideband bus.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIRQ_CONTINUOUS_MODE</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
If you set this option to y, the serial IRQ machine will be<br />
operated in continuous mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UART_FOR_CONSOLE</td><td>soc/intel/skylake</td><td>int</td><td>Index for LPSS UART port to use for console</td><td>
Index for LPSS UART port to use for console:<br />
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SKYLAKE_SOC_PCH_H</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Choose this option if you have a PCH-H chipset.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DMIC_2CH</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Include DSP firmware settings for 2 channel DMIC array.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DMIC_4CH</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Include DSP firmware settings for 4 channel DMIC array.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_NAU88L25</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Include DSP firmware settings for nau88l25 headset codec.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_MAX98357</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Include DSP firmware settings for max98357 amplifier.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_MAX98373</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Include DSP firmware settings for max98373 amplifier.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_SSM4567</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Include DSP firmware settings for ssm4567 smart amplifier.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_RT5514</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Include DSP firmware settings for rt5514 DSP.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_RT5663</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Include DSP firmware settings for rt5663 headset codec.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_MAX98927</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Include DSP firmware settings for max98927 amplifier.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DA7219</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Include DSP firmware settings for DA7219 headset codec.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NHLT_DA7219</td><td>soc/intel/skylake</td><td>bool</td><td>Cache-as-ram implementation</td><td>
This option allows you to select how cache-as-ram (CAR) is set up.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_SKYLAKE_CAR_NEM_ENHANCED</td><td>soc/intel/skylake</td><td>bool</td><td>Enhanced Non-evict mode</td><td>
A current limitation of NEM (Non-Evict mode) is that code and data<br />
sizes are derived from the requirement to not write out any modified<br />
cache line. With NEM, if there is no physical memory behind the<br />
cached area, the modified data will be lost and NEM results will be<br />
inconsistent. ENHANCED NEM guarantees that modified data is always<br />
kept in cache while clean data is replaced.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_SKYLAKE_FSP_CAR</td><td>soc/intel/skylake</td><td>bool</td><td>Use FSP CAR</td><td>
Use FSP APIs to initialize and tear down the Cache-As-Ram.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SKIP_FSP_CAR</td><td>soc/intel/skylake</td><td>bool</td><td>Skip cache as RAM setup in FSP</td><td>
Skip Cache as RAM setup in FSP.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NO_FADT_8042</td><td>soc/intel/skylake</td><td>bool</td><td></td><td>
Choose this option if you want to disable 8042 Keyboard<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON</td><td>soc/intel/common</td><td>bool</td><td></td><td>
common code for Intel SOCs<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/intel/common</td><td>(comment)</td><td></td><td>Intel SoC Common Code</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK</td><td>soc/intel/common/block</td><td>bool</td><td></td><td>
SoC driver for intel common IP code<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/intel/common/block</td><td>(comment)</td><td></td><td>Intel SoC Common IP Code</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_GRAPHICS</td><td>soc/intel/common/block/graphics</td><td>bool</td><td></td><td>
Intel Processor common Graphics support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_P2SB</td><td>soc/intel/common/block/p2sb</td><td>bool</td><td></td><td>
Intel Processor common P2SB driver<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_SMM</td><td>soc/intel/common/block/smm</td><td>bool</td><td></td><td>
Intel Processor common SMM support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP</td><td>soc/intel/common/block/smm</td><td>bool</td><td></td><td>
Intel Processor trap flag if it is supported<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS</td><td>soc/intel/common/block/smm</td><td>int</td><td></td><td>
Time in milliseconds that SLP_SMI for S5 waits for before<br />
enabling sleep. This is required to avoid any race between<br />
SLP_SMI and PWRBTN SMI.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_RTC</td><td>soc/intel/common/block/rtc</td><td>bool</td><td></td><td>
Intel Processor common RTC support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_UART</td><td>soc/intel/common/block/uart</td><td>bool</td><td></td><td>
Intel Processor common UART support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL</td><td>soc/intel/common/block/uart</td><td>hex</td><td></td><td>
Clock m-divisor value for m/n divider<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL</td><td>soc/intel/common/block/uart</td><td>hex</td><td></td><td>
Clock m-divisor value for m/n divider<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_ITSS</td><td>soc/intel/common/block/itss</td><td>bool</td><td></td><td>
Intel Processor common interrupt timer subsystem support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_PMC</td><td>soc/intel/common/block/pmc</td><td>bool</td><td></td><td>
Intel Processor common code for Power Management controller(PMC)<br />
subsystem<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>POWER_STATE_OFF_AFTER_FAILURE</td><td>soc/intel/common/block/pmc</td><td>bool</td><td>S5 Soft Off</td><td>
Choose this option if you want to keep system into<br />
S5 after reapplying power after failure<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>POWER_STATE_ON_AFTER_FAILURE</td><td>soc/intel/common/block/pmc</td><td>bool</td><td>S0 Full On</td><td>
Choose this option if you want to keep system into<br />
S0 after reapplying power after failure<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>POWER_STATE_PREVIOUS_AFTER_FAILURE</td><td>soc/intel/common/block/pmc</td><td>bool</td><td>Keep Previous State</td><td>
Choose this option if you want to keep system into<br />
same power state as before failure even after reapplying<br />
power<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PMC_INVALID_READ_AFTER_WRITE</td><td>soc/intel/common/block/pmc</td><td>bool</td><td></td><td>
Enable this for PMC devices where a read back of ACPI BAR and<br />
IO access bit does not return the previously written value.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_PCR</td><td>soc/intel/common/block/pcr</td><td>bool</td><td></td><td>
Intel Processor common Private configuration registers (PCR)<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCR_COMMON_IOSF_1_0</td><td>soc/intel/common/block/pcr</td><td>bool</td><td></td><td>
The mapping of addresses via the SBREG_BAR assumes the IOSF-SB<br />
agents are using 32-bit aligned accesses for their configuration<br />
registers. For IOSF versions greater than 1_0, IOSF-SB<br />
agents can use any access (8/16/32 bit aligned) for their<br />
configuration registers<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_LPSS</td><td>soc/intel/common/block/lpss</td><td>bool</td><td></td><td>
Intel Processor common LPSS support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_GSPI</td><td>soc/intel/common/block/gspi</td><td>bool</td><td></td><td>
Intel Processor Common GSPI support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ</td><td>soc/intel/common/block/gspi</td><td>int</td><td></td><td>
The input clock speed into the SPI controller IP block, in MHz.<br />
No default is set here as this is an SOC-specific value<br />
and must be provided by the SOC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_GSPI_MAX</td><td>soc/intel/common/block/gspi</td><td>int</td><td></td><td>
Maximum number of GSPI controllers supported by the PCH. SoC<br />
must define this config if SOC_INTEL_COMMON_BLOCK_GSPI is<br />
selected.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2</td><td>soc/intel/common/block/gspi</td><td>bool</td><td></td><td>
Intel Processor Common GSPI support with quirks to handle<br />
SPI_CS_CONTROL changes introduced in CNL.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_SCS</td><td>soc/intel/common/block/scs</td><td>bool</td><td></td><td>
Intel Processor common storage and communication subsystem support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_XHCI</td><td>soc/intel/common/block/xhci</td><td>bool</td><td></td><td>
Intel Processor common XHCI support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_I2C</td><td>soc/intel/common/block/i2c</td><td>bool</td><td></td><td>
Intel Processor Common I2C support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_I2C_DEBUG</td><td>soc/intel/common/block/i2c</td><td>bool</td><td>Enable debug output for LPSS I2C transactions</td><td>
Enable debug output for I2C transactions.  This can be useful<br />
when debugging I2C drivers.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_SA</td><td>soc/intel/common/block/systemagent</td><td>bool</td><td></td><td>
Intel Processor common System Agent support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SA_PCIEX_LENGTH</td><td>soc/intel/common/block/systemagent</td><td>hex</td><td></td><td>
This option allows you to select length of PCIEX region.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SA_ENABLE_IMR</td><td>soc/intel/common/block/systemagent</td><td>bool</td><td></td><td>
This option allows you to add the isolated memory ranges (IMRs).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SA_ENABLE_DPR</td><td>soc/intel/common/block/systemagent</td><td>bool</td><td></td><td>
This option allows you to add the DMA Protected Range (DPR).<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_TIMER</td><td>soc/intel/common/block/timer</td><td>bool</td><td></td><td>
Intel Processor common TIMER support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_XDCI</td><td>soc/intel/common/block/xdci</td><td>bool</td><td></td><td>
Intel Processor common XDCI support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_SPI</td><td>soc/intel/common/block/spi</td><td>bool</td><td></td><td>
Intel Processor common SPI support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_LPC</td><td>soc/intel/common/block/lpc</td><td>bool</td><td></td><td>
Use common LPC code for platform. Only soc specific code needs to<br />
be implemented as per requirement.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE</td><td>soc/intel/common/block/lpc</td><td>bool</td><td></td><td>
By default COMA range to LPC is enable. COMB range to LPC is optional<br />
and should select based on platform dedicated selection.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_SRAM</td><td>soc/intel/common/block/sram</td><td>bool</td><td></td><td>
Intel Processor common SRAM support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG</td><td>soc/intel/common/block/chip</td><td>bool</td><td></td><td>
Intel Processor common soc/ chip configuration support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_SMBUS</td><td>soc/intel/common/block/smbus</td><td>bool</td><td></td><td>
Intel Processor common SMBus support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_GPIO</td><td>soc/intel/common/block/gpio</td><td>bool</td><td></td><td>
Intel Processor common GPIO support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_SOC_COMMON_BLOCK_GPIO</td><td>soc/intel/common/block/gpio</td><td>bool</td><td>Output verbose GPIO debug messages</td><td>
This option enables GPIO debug messages<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_HDA</td><td>soc/intel/common/block/hda</td><td>bool</td><td></td><td>
Intel Processor common High Definition Audio driver support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_EBDA</td><td>soc/intel/common/block/ebda</td><td>bool</td><td></td><td>
Intel Processor common EBDA library support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_SGX</td><td>soc/intel/common/block/sgx</td><td>bool</td><td></td><td>
Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU<br />
instructions that can be used by applications to set aside private<br />
regions of code and data.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_ACPI</td><td>soc/intel/common/block/acpi</td><td>bool</td><td></td><td>
Intel Processor common code for ACPI<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_DSP</td><td>soc/intel/common/block/dsp</td><td>bool</td><td></td><td>
Intel Processor common DSP support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_PCIE</td><td>soc/intel/common/block/pcie</td><td>bool</td><td></td><td>
Intel Processor common PCIE support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCIE_DEBUG_INFO</td><td>soc/intel/common/block/pcie</td><td>bool</td><td></td><td>
Enable debug logs in PCIe module. Allows debug information on memory<br />
base and limit, prefetchable memory base and limit, prefetchable memory<br />
base upper 32 bits and prefetchable memory limit upper 32 bits.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_CSE</td><td>soc/intel/common/block/cse</td><td>bool</td><td></td><td>
Driver for communication with Converged Security Engine (CSE)<br />
over Host Embedded Controller Interface (HECI)<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_FAST_SPI</td><td>soc/intel/common/block/fast_spi</td><td>bool</td><td></td><td>
Intel Processor common FAST_SPI support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FAST_SPI_DISABLE_WRITE_STATUS</td><td>soc/intel/common/block/fast_spi</td><td>bool</td><td>Disable write status SPI opcode</td><td>
Disable the write status SPI opcode in Intel Fast SPI block.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_SATA</td><td>soc/intel/common/block/sata</td><td>bool</td><td></td><td>
Intel Processor common SATA support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_AHCI_PORT_IMPLEMENTED_INVERT</td><td>soc/intel/common/block/sata</td><td>bool</td><td></td><td>
SATA PCI configuration space offset 0x92 Port<br />
implement register bit 0-2 represents respective<br />
SATA port enable status as in 0 = Disable; 1 = Enable.<br />
If this option is selected then port enable status will be<br />
inverted as in 0 = Enable; 1 = Disable.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_CPU</td><td>soc/intel/common/block/cpu</td><td>bool</td><td></td><td>
This option selects Intel Common CPU Model support code<br />
which provides various CPU related APIs which are common<br />
between all Intel Processor families. Common CPU code is supported<br />
for SOCs starting from SKL,KBL,APL, and future.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_CPU_MPINIT</td><td>soc/intel/common/block/cpu</td><td>bool</td><td></td><td>
This option selects Intel Common CPU MP Init code. In<br />
this common MP Init mechanism, the MP Init is occurring before<br />
calling FSP Silicon Init. Hence, MP Init will be pulled to<br />
BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is<br />
ensured that all MTRRs are re-programmed based on the DRAM<br />
resource settings.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_BLOCK_CAR</td><td>soc/intel/common/block/cpu</td><td>bool</td><td></td><td>
This option allows you to select how cache-as-ram (CAR) is set up.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEL_CAR_NEM</td><td>soc/intel/common/block/cpu</td><td>bool</td><td></td><td>
Traditionally, CAR is set up by using Non-Evict mode. This method<br />
does not allow CAR and cache to co-exist, because cache fills are<br />
blocked in NEM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEL_CAR_CQOS</td><td>soc/intel/common/block/cpu</td><td>bool</td><td></td><td>
Cache Quality of Service allows more fine-grained control of cache<br />
usage. As result, it is possible to set up a portion of L2 cache for<br />
CAR and use the remainder for actual caching.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEL_CAR_NEM_ENHANCED</td><td>soc/intel/common/block/cpu</td><td>bool</td><td></td><td>
A current limitation of NEM (Non-Evict mode) is that code and data sizes<br />
are derived from the requirement to not write out any modified cache line.<br />
With NEM, if there is no physical memory behind the cached area,<br />
the modified data will be lost and NEM results will be inconsistent.<br />
ENHANCED NEM guarantees that modified data is always<br />
kept in cache while clean data is replaced.<br />
<br />
</td></tr>
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/intel/common</td><td>(comment)</td><td></td><td>Intel SoC Common PCH Code</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_PCH_BASE</td><td>soc/intel/common/pch</td><td>bool</td><td></td><td>
All common PCH code blocks between Gen-6 till latest-PCH should be<br />
part of this directory. A SoC Kconfig might select this option to include<br />
base PCH package while building new SOC block. Currently majority of<br />
common IP code blocks are part of soc/intel/common/block/ and<br />
SoC Kconfig just select those Kconfig option. Addition to that SoC<br />
code now having option to select required base PCH block to include<br />
common IP block.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/intel/common/pch</td><td>(comment)</td><td></td><td>Intel SoC Common PCH Code</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_INTEL_COMMON_PCH_LOCKDOWN</td><td>soc/intel/common/pch/lockdown</td><td>bool</td><td></td><td>
This option allows to have chipset lockdown for DMI, FAST_SPI and<br />
soc_lockdown_config() to implement any additional lockdown as PMC,<br />
LPC for supported PCH.<br />
<br />
</td></tr>
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ACPI_CONSOLE</td><td>soc/intel/common</td><td>bool</td><td></td><td>
Provide a mechanism for serial console based ACPI debug.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MMA</td><td>soc/intel/common</td><td>bool</td><td>Enable MMA (Memory Margin Analysis) support for Intel Core</td><td>
Set this option to y to enable MMA (Memory Margin Analysis) support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TPM_TIS_ACPI_INTERRUPT</td><td>soc/intel/common</td><td>int</td><td></td><td>
acpi_get_gpe() is used to provide interrupt status to TPM layer.<br />
This option specifies the GPE number.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE</td><td>soc/broadcom/cygnus</td><td>bool</td><td>Enable DDR auto self-refresh</td><td>
Warning: M0 expects that auto self-refresh is enabled. Modify<br />
with caution.<br />
<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_DRAM</td><td>soc/mediatek/mt8173</td><td>bool</td><td>Output verbose DRAM related debug messages</td><td>
This option enables additional DRAM related debug messages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_I2C</td><td>soc/mediatek/mt8173</td><td>bool</td><td>Output verbose I2C related debug messages</td><td>
This option enables I2C related debug messages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_PMIC</td><td>soc/mediatek/mt8173</td><td>bool</td><td>Output verbose PMIC related debug messages</td><td>
This option enables PMIC related debug messages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_PMIC_WRAP</td><td>soc/mediatek/mt8173</td><td>bool</td><td>Output verbose PMIC WRAP related debug messages</td><td>
This option enables PMIC WRAP related debug messages.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_DO_DSI_INIT</td><td>soc/nvidia/tegra210</td><td>bool</td><td>Use dsi graphics interface</td><td>
Initialize dsi display<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_DO_SOR_INIT</td><td>soc/nvidia/tegra210</td><td>bool</td><td>Use dp graphics interface</td><td>
Initialize dp display<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_TEGRA210_UARTA</td><td>soc/nvidia/tegra210</td><td>bool</td><td>UARTA</td><td>
Serial console on UART A.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_TEGRA210_UARTB</td><td>soc/nvidia/tegra210</td><td>bool</td><td>UARTB</td><td>
Serial console on UART B.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_TEGRA210_UARTC</td><td>soc/nvidia/tegra210</td><td>bool</td><td>UARTC</td><td>
Serial console on UART C.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_TEGRA210_UARTD</td><td>soc/nvidia/tegra210</td><td>bool</td><td>UARTD</td><td>
Serial console on UART D.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_TEGRA210_UARTE</td><td>soc/nvidia/tegra210</td><td>bool</td><td>UARTE</td><td>
Serial console on UART E.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_TEGRA210_UART_ADDRESS</td><td>soc/nvidia/tegra210</td><td>hex</td><td></td><td>
Map the UART names to the respective MMIO addres.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOTROM_SDRAM_INIT</td><td>soc/nvidia/tegra210</td><td>bool</td><td>SoC BootROM does SDRAM init with full BCT</td><td>
Use during Foster LPDDR4 bringup.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TRUSTZONE_CARVEOUT_SIZE_MB</td><td>soc/nvidia/tegra210</td><td>hex</td><td>Size of Trust Zone region</td><td>
Size of Trust Zone area in MiB to reserve in memory map.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TTB_SIZE_MB</td><td>soc/nvidia/tegra210</td><td>hex</td><td>Size of TTB</td><td>
Maximum size of Translation Table Buffer in MiB.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SEC_COMPONENT_SIZE_MB</td><td>soc/nvidia/tegra210</td><td>hex</td><td>Size of resident EL3 components</td><td>
Maximum size of resident EL3 components in MiB including BL31 and<br />
Secure OS.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_MTC</td><td>soc/nvidia/tegra210</td><td>bool</td><td>Add external Memory controller Training Code binary</td><td>
Select this option to add emc training firmware<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MTC_FILE</td><td>soc/nvidia/tegra210</td><td>string</td><td>tegra mtc firmware filename</td><td>
The filename of the mtc firmware<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MTC_DIRECTORY</td><td>soc/nvidia/tegra210</td><td>string</td><td>Directory where MTC firmware file is located</td><td>
Path to directory where MTC firmware file is located.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MTC_ADDRESS</td><td>soc/nvidia/tegra210</td><td>hex</td><td></td><td>
The DRAM location where MTC firmware to be loaded in. This location<br />
needs to be consistent with the location defined in tegra_mtc.ld<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_AMD_STONEYRIDGE_FP4</td><td>soc/amd/stoneyridge</td><td>bool</td><td></td><td>
AMD Stoney Ridge FP4 support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_AMD_STONEYRIDGE_FT4</td><td>soc/amd/stoneyridge</td><td>bool</td><td></td><td>
AMD Stoney Ridge FT4 support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_BSP_STACK_SIZE</td><td>soc/amd/stoneyridge</td><td>hex</td><td></td><td>
The amount of anticipated stack usage in CAR by bootblock and<br />
other stages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PRERAM_CBMEM_CONSOLE_SIZE</td><td>soc/amd/stoneyridge</td><td>hex</td><td></td><td>
Increase this value if preram cbmem console is getting truncated<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOTTOMIO_POSITION</td><td>soc/amd/stoneyridge</td><td>hex</td><td>Bottom of 32-bit IO space</td><td>
If PCI peripherals with big BARs are connected to the system<br />
the bottom of the IO must be decreased to allocate such<br />
devices.<br />
<br />
Declare the beginning of the 128MB-aligned MMIO region.  This<br />
option is useful when PCI peripherals requesting large address<br />
ranges are present.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_ID</td><td>soc/amd/stoneyridge</td><td>string</td><td></td><td>
The default VGA BIOS PCI vendor/device ID should be set to the<br />
result of the map_oprom_vendev() function in northbridge.c.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>STONEYRIDGE_XHCI_ENABLE</td><td>soc/amd/stoneyridge</td><td>bool</td><td>Enable Stoney Ridge XHCI Controller</td><td>
The XHCI controller must be enabled and the XHCI firmware<br />
must be added in order to have USB 3.0 support configured<br />
by coreboot. The OS will be responsible for enabling the XHCI<br />
controller if the the XHCI firmware is available but the<br />
XHCI controller is not enabled by coreboot.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>STONEYRIDGE_XHCI_FWM</td><td>soc/amd/stoneyridge</td><td>bool</td><td>Add xhci firmware</td><td>
Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>STONEYRIDGE_IMC_FWM</td><td>soc/amd/stoneyridge</td><td>bool</td><td>Add IMC firmware</td><td>
Add Stoney Ridge IMC Firmware to support the onboard fan control<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>STONEYRIDGE_GEC_FWM</td><td>soc/amd/stoneyridge</td><td>bool</td><td></td><td>
Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC.<br />
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>STONEYRIDGE_SATA_MODE</td><td>soc/amd/stoneyridge</td><td>int</td><td>SATA Mode</td><td>
Select the mode in which SATA should be driven.<br />
The default is NATIVE.<br />
0: NATIVE mode does not require a ROM.<br />
2: AHCI may work with or without AHCI ROM. It depends on the payload support.<br />
For example, seabios does not require the AHCI ROM.<br />
3: LEGACY IDE<br />
4: IDE to AHCI<br />
5: AHCI7804: ROM Required, and AMD driver required in the OS.<br />
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>NATIVE</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>AHCI</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>LEGACY IDE</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>IDE to AHCI</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>AHCI7804</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>IDE to AHCI7804</td></tr>
<tr bgcolor="#eeeeee">
<td>STONEYRIDGE_LEGACY_FREE</td><td>soc/amd/stoneyridge</td><td>bool</td><td>System is legacy free</td><td>
Select y if there is no keyboard controller in the system.<br />
This sets variables in AGESA and ACPI.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIRQ_CONTINUOUS_MODE</td><td>soc/amd/stoneyridge</td><td>bool</td><td></td><td>
Set this option to y for serial IRQ in continuous mode.<br />
Otherwise it is in quiet mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>STONEYRIDGE_ACPI_IO_BASE</td><td>soc/amd/stoneyridge</td><td>hex</td><td></td><td>
Base address for the ACPI registers.<br />
This value must match the hardcoded value of AGESA.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>STONEYRIDGE_UART</td><td>soc/amd/stoneyridge</td><td>bool</td><td>UART controller on Stoney Ridge</td><td>
There are two UART controllers in Stoney Ridge.<br />
The UART registers are memory-mapped. UART<br />
controller 0 registers range from FEDC_6000h<br />
to FEDC_6FFFh. UART controller 1 registers<br />
range from FEDC_8000h to FEDC_8FFFh.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_PSPSCUREOS</td><td>soc/amd/stoneyridge</td><td>bool</td><td>Include PSP SecureOS blobs in AMD firmware</td><td>
Include the PspSecureOs, PspTrustlet and TrustletKey binaries<br />
in the amdfw section.<br />
<br />
If unsure, answer 'y'<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AMDFW_OUTSIDE_CBFS</td><td>soc/amd/stoneyridge</td><td>bool</td><td>The AMD firmware is outside CBFS</td><td>
The AMDFW (PSP) is typically locatable in cbfs.  Select this<br />
option to manually attach the generated amdfw.rom outside of<br />
cbfs.  The location is selected by the FWM position.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AMD_FWM_POSITION_INDEX</td><td>soc/amd/stoneyridge</td><td>int</td><td>Firmware Directory Table location (0 to 5)</td><td>
Typically this is calculated by the ROM size, but there may<br />
be situations where you want to put the firmware directory<br />
table in a different location.<br />
0: 512 KB - 0xFFFA0000<br />
1: 1 MB   - 0xFFF20000<br />
2: 2 MB   - 0xFFE20000<br />
3: 4 MB   - 0xFFC20000<br />
4: 8 MB   - 0xFF820000<br />
5: 16 MB  - 0xFF020000<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>AMD Firmware Directory Table set to location for 512KB ROM</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>AMD Firmware Directory Table set to location for 1MB ROM</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>AMD Firmware Directory Table set to location for 2MB ROM</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>AMD Firmware Directory Table set to location for 4MB ROM</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>AMD Firmware Directory Table set to location for 8MB ROM</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/stoneyridge</td><td>(comment)</td><td></td><td>AMD Firmware Directory Table set to location for 16MB ROM</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_POWER_RESTORE</td><td>soc/amd/stoneyridge</td><td>int</td><td></td><td>
This option determines what state to go to once power is restored<br />
after having been lost in S0.  Select this option to automatically<br />
return to S0.  Otherwise the system will remain in S5 once power<br />
is restored.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VENDORCODE_FULL_SUPPORT</td><td>soc/amd/stoneyridge</td><td>int</td><td></td><td>
This option determines if all files under<br />
vendorcode/amd/pi/00670F00/ will be compiled or only<br />
selected procedures of source files (minimum required).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_AMD_COMMON</td><td>soc/amd/common</td><td>bool</td><td></td><td>
common code for AMD SOCs<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_AMD_COMMON_BLOCK</td><td>soc/amd/common/block</td><td>bool</td><td></td><td>
SoC driver for AMD common IP code<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>soc/amd/common/block</td><td>(comment)</td><td></td><td>AMD SoC Common IP Code</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_AMD_COMMON_BLOCK_S3</td><td>soc/amd/common/block/s3</td><td>bool</td><td></td><td>
Select this option to add S3 related functions to the build.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_AMD_COMMON_BLOCK_PSP</td><td>soc/amd/common/block/psp</td><td>bool</td><td></td><td>
This option builds in the Platform Security Processor initialization<br />
functions.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_AMD_PSP_SELECTABLE_SMU_FW</td><td>soc/amd/common/block/psp</td><td>bool</td><td></td><td>
Some PSP implementations allow storing SMU firmware into cbfs and<br />
calling the PSP to load the blobs at the proper time.<br />
<br />
The soc/&lt;codename&gt; should select this if its PSP supports the feature<br />
and each mainboard can choose to select an appropriate fanless or<br />
fanned set of blobs.  Ask your AMD representative whether your APU<br />
is considered fanless.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_AMD_COMMON_BLOCK_PI</td><td>soc/amd/common/block/pi</td><td>bool</td><td></td><td>
This option builds functions that interface AMD's AGESA.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PI_AGESA_CAR_HEAP_BASE</td><td>soc/amd/common/block/pi</td><td>hex</td><td></td><td>
The AGESA PI blob may be built to allow an optional callout for<br />
AgesaHeapRebase.  If AGESA calls AgesaHeapRebase, this option<br />
determines the location of the heap prior to DRAM availability.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PI_AGESA_TEMP_RAM_BASE</td><td>soc/amd/common/block/pi</td><td>hex</td><td></td><td>
During a boot from S5, AGESA copies its CAR-based heap to a temporary<br />
location in DRAM.  Once coreboot has established cbmem, the heap<br />
is moved again.  This symbol determines the temporary location for<br />
the heap.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PI_AGESA_HEAP_SIZE</td><td>soc/amd/common/block/pi</td><td>hex</td><td></td><td>
This option determines the amount of space allowed for AGESA heap<br />
prior to DRAM availability.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_AMD_COMMON_BLOCK_PCI</td><td>soc/amd/common/block/pci</td><td>bool</td><td></td><td>
This option builds functions used to program PCI interrupt<br />
routing, both PIC and APIC modes.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_AMD_COMMON_BLOCK_CAR</td><td>soc/amd/common/block/cpu</td><td>bool</td><td></td><td>
This option allows the SOC to use a standard AMD cache-as-ram (CAR)<br />
implementation.  CAR setup is built into bootblock and teardown is<br />
in postcar.  The teardown procedure does not preserve the stack so<br />
it may not be appropriate for a romstage implementation without<br />
additional consideration.  If this option is not used, the SOC must<br />
implement these functions separately.<br />
<br />
</td></tr>
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RK3399_SPREAD_SPECTRUM_DDR</td><td>soc/rockchip/rk3399</td><td>bool</td><td>Spread-spectrum DDR clock</td><td>
Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit<br />
used to modulate the frequency of the Silicon Creations' Fractional<br />
PLL in order to reduce EMI.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>toplevel</td><td>(comment)</td><td></td><td>CPU</td></tr>
<tr bgcolor="#eeeeee">
<td>RESET_ON_INVALID_RAMSTAGE_CACHE</td><td>cpu/intel/haswell</td><td>bool</td><td>Reset the system on S3 wake when ramstage cache invalid.</td><td>
The haswell romstage code caches the loaded ramstage program<br />
in SMM space. On S3 wake the romstage will copy over a fresh<br />
ramstage that was cached in the SMM space. This option determines<br />
the action to take when the ramstage cache is invalid. If selected<br />
the system will reset otherwise the ramstage will be reloaded from<br />
cbfs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_INTEL_FIRMWARE_INTERFACE_TABLE</td><td>cpu/intel/fit</td><td>None</td><td></td><td>
This option selects building a Firmware Interface Table (FIT).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_INTEL_NUM_FIT_ENTRIES</td><td>cpu/intel/fit</td><td>int</td><td></td><td>
This option selects the number of empty entries in the FIT table.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED</td><td>cpu/intel/turbo</td><td>None</td><td></td><td>
This option indicates that the turbo mode setting is not package<br />
scoped. i.e. enable_turbo() needs to be called on not just the bsp<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SET_VMX_LOCK_BIT</td><td>cpu/intel/common</td><td>bool</td><td>Set lock bit after configuring VMX</td><td>
Although the Intel manual says you must set the lock bit in addition<br />
to the VMX bit in order for VMX to work, this isn't strictly true, so<br />
we have the option to leave it unlocked and allow the OS (e.g. Linux)<br />
to manage things itself. This is beneficial for testing purposes as<br />
there is no need to reflash the firmware just to toggle the lock bit.<br />
However, leaving the lock bit unset will break Windows' detection of<br />
VMX support and built-in virtualization features like Hyper-V.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PARALLEL_MP</td><td>cpu/x86</td><td>bool</td><td></td><td>
This option uses common MP infrastructure for bringing up APs<br />
in parallel. It additionally provides a more flexible mechanism<br />
for sequencing the steps of bringing up the APs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PARALLEL_MP_AP_WORK</td><td>cpu/x86</td><td>bool</td><td></td><td>
Allow APs to do other work after initialization instead of going<br />
to sleep.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LAPIC_MONOTONIC_TIMER</td><td>cpu/x86</td><td>bool</td><td></td><td>
Expose monotonic time using the local APIC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TSC_CONSTANT_RATE</td><td>cpu/x86</td><td>bool</td><td></td><td>
This option asserts that the TSC ticks at a known constant rate.<br />
Therefore, no TSC calibration is required.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TSC_MONOTONIC_TIMER</td><td>cpu/x86</td><td>bool</td><td></td><td>
Expose monotonic time using the TSC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TSC_SYNC_LFENCE</td><td>cpu/x86</td><td>bool</td><td></td><td>
The CPU driver should select this if the CPU needs<br />
to execute an lfence instruction in order to synchronize<br />
rdtsc. This is true for all modern AMD CPUs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TSC_SYNC_MFENCE</td><td>cpu/x86</td><td>bool</td><td></td><td>
The CPU driver should select this if the CPU needs<br />
to execute an mfence instruction in order to synchronize<br />
rdtsc. This is true for all modern Intel CPUs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NO_FIXED_XIP_ROM_SIZE</td><td>cpu/x86</td><td>bool</td><td></td><td>
The XIP_ROM_SIZE Kconfig variable is used globally on x86<br />
with the assumption that all chipsets utilize this value.<br />
For the chipsets which do not use the variable it can lead<br />
to unnecessary alignment constraints in cbfs for romstage.<br />
Therefore, allow those chipsets a path to not be burdened.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SMM_MODULE_HEAP_SIZE</td><td>cpu/x86</td><td>hex</td><td></td><td>
This option determines the size of the heap within the SMM handler<br />
modules.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SMM_MODULE_STACK_SIZE</td><td>cpu/x86</td><td>hex</td><td></td><td>
This option determines the size of the stack within the SMM handler<br />
modules.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIALIZED_SMM_INITIALIZATION</td><td>cpu/x86</td><td>bool</td><td></td><td>
On some CPUs, there is a race condition in SMM.<br />
This can occur when both hyperthreads change SMM state<br />
variables in parallel without coordination.<br />
Setting this option serializes the SMM initialization<br />
to avoid an ugly hang in the boot process at the cost<br />
of a slightly longer boot time.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86_AMD_FIXED_MTRRS</td><td>cpu/x86</td><td>bool</td><td></td><td>
This option informs the MTRR code to use the RdMem and WrMem fields<br />
in the fixed MTRR MSRs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PLATFORM_USES_FSP1_0</td><td>cpu/x86</td><td>bool</td><td></td><td>
Selected for Intel processors/platform combinations that use the<br />
Intel Firmware Support Package (FSP) 1.0 for initialization.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING</td><td>cpu/x86</td><td>bool</td><td></td><td>
On certain platforms a boot speed gain can be realized if mirroring<br />
the payload data stored in non-volatile storage. On x86 systems the<br />
payload would typically live in a memory-mapped SPI part. Copying<br />
the SPI contents to RAM before performing the load can speed up<br />
the boot process.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOC_SETS_MSRS</td><td>cpu/x86</td><td>bool</td><td></td><td>
The SoC requires different access methods for reading and writing<br />
the MSRs.  Use SoC specific routines to handle the MSR access.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>GEODE_VSA_FILE</td><td>cpu/amd/geode_lx</td><td>bool</td><td>Add a VSA image</td><td>
Select this option if you have an AMD Geode LX vsa that you would<br />
like to add to your ROM.<br />
<br />
You will be able to specify the location and file name of the<br />
image later.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VSA_FILENAME</td><td>cpu/amd/geode_lx</td><td>string</td><td>AMD Geode LX VSA path and filename</td><td>
The path and filename of the file to use as VSA.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>XIP_ROM_SIZE</td><td>cpu/amd/agesa</td><td>hex</td><td></td><td>
Overwride the default write through caching size as 1M Bytes.<br />
On some AMD platforms, one socket supports 2 or more kinds of<br />
processor family, compiling several CPU families agesa code<br />
will increase the romstage size.<br />
In order to execute romstage in place on the flash ROM,<br />
more space is required to be set as write through caching.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_MRC_CACHE</td><td>cpu/amd/agesa</td><td>bool</td><td>Use cached memory configuration</td><td>
Try to restore memory training results<br />
from non-volatile memory.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FORCE_AM1_SOCKET_SUPPORT</td><td>cpu/amd/agesa/family16kb</td><td>bool</td><td></td><td>
Force AGESA to ignore package type mismatch between CPU and northbridge<br />
in memory code. This enables Socket AM1 support with current AGESA<br />
version for Kabini platform.<br />
Enable this option only if you have Socket AM1 board.<br />
Note that the AGESA release shipped with coreboot does not officially<br />
support the AM1 socket. Selecting this option might damage your hardware.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>XIP_ROM_SIZE</td><td>cpu/amd/pi</td><td>hex</td><td></td><td>
Overwride the default write through caching size as 1M Bytes.<br />
On some AMD platforms, one socket supports 2 or more kinds of<br />
processor family, compiling several CPU families agesa code<br />
will increase the romstage size.<br />
In order to execute romstage in place on the flash ROM,<br />
more space is required to be set as write through caching.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NO_CAR_GLOBAL_MIGRATION</td><td>cpu</td><td>bool</td><td></td><td>
This option is selected if there is no need to migrate CAR globals.<br />
All stages which use CAR globals can directly access the variables<br />
from their linked addresses.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SMP</td><td>cpu</td><td>bool</td><td></td><td>
This option is used to enable certain functions to make coreboot<br />
work correctly on symmetric multi processor (SMP) systems.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AP_SIPI_VECTOR</td><td>cpu</td><td>hex</td><td></td><td>
This must equal address of ap_sipi_vector from bootblock build.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MMX</td><td>cpu</td><td>bool</td><td></td><td>
Select MMX in your socket or model Kconfig if your CPU has MMX<br />
streaming SIMD instructions. ROMCC can build more efficient<br />
code if it can spill to MMX registers.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SSE</td><td>cpu</td><td>bool</td><td></td><td>
Select SSE in your socket or model Kconfig if your CPU has SSE<br />
streaming SIMD instructions. ROMCC can build more efficient<br />
code if it can spill to SSE (aka XMM) registers.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SSE2</td><td>cpu</td><td>bool</td><td></td><td>
Select SSE2 in your socket or model Kconfig if your CPU has SSE2<br />
streaming SIMD instructions. Some parts of coreboot can be built<br />
with more efficient code if SSE2 instructions are available.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USES_MICROCODE_HEADER_FILES</td><td>cpu</td><td>bool</td><td></td><td>
This is selected by a board or chipset to set the default for the<br />
microcode source choice to a list of external microcode headers<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_MICROCODE_CBFS_GENERATE</td><td>cpu</td><td>bool</td><td>Generate from tree</td><td>
Select this option if you want microcode updates to be assembled when<br />
building coreboot and included in the final image as a separate CBFS<br />
file. Microcode will not be hard-coded into ramstage.<br />
<br />
The microcode file may be removed from the ROM image at a later<br />
time with cbfstool, if desired.<br />
<br />
If unsure, select this option.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_MICROCODE_CBFS_EXTERNAL_HEADER</td><td>cpu</td><td>bool</td><td>Include external microcode header files</td><td>
Select this option if you want to include external c header files<br />
containing the CPU microcode. This will be included as a separate<br />
file in CBFS.<br />
<br />
A word of caution: only select this option if you are sure the<br />
microcode that you have is newer than the microcode shipping with<br />
coreboot.<br />
<br />
The microcode file may be removed from the ROM image at a later<br />
time with cbfstool, if desired.<br />
<br />
If unsure, select "Generate from tree"<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_MICROCODE_CBFS_NONE</td><td>cpu</td><td>bool</td><td>Do not include microcode updates</td><td>
Select this option if you do not want CPU microcode included in CBFS.<br />
Note that for some CPUs, the microcode is hard-coded into the source<br />
tree and is not loaded from CBFS. In this case, microcode will still<br />
be updated. There is a push to move all microcode to CBFS, but this<br />
change is not implemented for all CPUs.<br />
<br />
This option currently applies to:<br />
- Intel SandyBridge/IvyBridge<br />
- VIA Nano<br />
<br />
Microcode may be added to the ROM image at a later time with cbfstool,<br />
if desired.<br />
<br />
If unsure, select "Generate from tree"<br />
<br />
The GOOD:<br />
Microcode updates intend to solve issues that have been discovered<br />
after CPU production. The expected effect is that systems work as<br />
intended with the updated microcode, but we have also seen cases where<br />
issues were solved by not applying microcode updates.<br />
<br />
The BAD:<br />
Note that some operating system include these same microcode patches,<br />
so you may need to also disable microcode updates in your operating<br />
system for this option to have an effect.<br />
<br />
The UGLY:<br />
A word of CAUTION: some CPUs depend on microcode updates to function<br />
correctly. Not updating the microcode may leave the CPU operating at<br />
less than optimal performance, or may cause outright hangups.<br />
There are CPUs where coreboot cannot properly initialize the CPU<br />
without microcode updates<br />
For example, if running with the factory microcode, some Intel<br />
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs<br />
will hang when changing the frequency.<br />
<br />
Make sure you have a way of flashing the ROM externally before<br />
selecting this option.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_MICROCODE_MULTIPLE_FILES</td><td>cpu</td><td>bool</td><td></td><td>
Select this option to install separate microcode container files into<br />
CBFS instead of using the traditional monolithic microcode file format.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_MICROCODE_HEADER_FILES</td><td>cpu</td><td>string</td><td>List of space separated microcode header files with the path</td><td>
A list of one or more microcode header files with path from the<br />
coreboot directory.  These should be separated by spaces.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_UCODE_BINARIES</td><td>cpu</td><td>string</td><td>Microcode binary path and filename</td><td>
Some platforms have microcode in the blobs directory, and these can<br />
be hardcoded in the makefiles.  For platforms with microcode<br />
binaries that aren't in the makefile, set this option to pull<br />
in the microcode.<br />
<br />
This should contain the full path of the file for one or more<br />
microcode binary files to include, separated by spaces.<br />
<br />
If unsure, leave this blank.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>toplevel</td><td>(comment)</td><td></td><td>Northbridge</td></tr>
<tr bgcolor="#eeeeee">
<td>SET_TSEG_1MB</td><td>northbridge/intel/fsp_rangeley</td><td>bool</td><td>1 MB</td><td>
Set the TSEG area to 1 MB.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SET_TSEG_2MB</td><td>northbridge/intel/fsp_rangeley</td><td>bool</td><td>2 MB</td><td>
Set the TSEG area to 2 MB.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SET_TSEG_4MB</td><td>northbridge/intel/fsp_rangeley</td><td>bool</td><td>4 MB</td><td>
Set the TSEG area to 4 MB.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SET_TSEG_8MB</td><td>northbridge/intel/fsp_rangeley</td><td>bool</td><td>8 MB</td><td>
Set the TSEG area to 8 MB.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_FILE</td><td>northbridge/intel/fsp_rangeley/fsp</td><td>string</td><td></td><td>
The path and filename of the Intel FSP binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_LOC</td><td>northbridge/intel/fsp_rangeley/fsp</td><td>hex</td><td></td><td>
The location in CBFS that the FSP is located. This must match the<br />
value that is set in the FSP binary.  If the FSP needs to be moved,<br />
rebase the FSP with Intel's BCT (tool).<br />
<br />
The Rangeley FSP is built with a preferred base address of 0xFFF80000<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_NATIVE_RAMINIT</td><td>northbridge/intel/sandybridge</td><td>bool</td><td>Use native raminit</td><td>
Select if you want to use coreboot implementation of raminit rather than<br />
System Agent/MRC.bin. You should answer Y.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES</td><td>northbridge/intel/sandybridge</td><td>bool</td><td>Ignore vendor programmed fuses that limit max. DRAM frequency</td><td>
Ignore the mainboard's vendor programmed fuses that might limit the<br />
maximum DRAM frequency. By selecting this option the fuses will be<br />
ignored and the only limits on DRAM frequency are set by RAM's SPD and<br />
hard fuses in southbridge's clockgen.<br />
Disabled by default as it might causes system instability.<br />
Handle with care!<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS</td><td>northbridge/intel/sandybridge</td><td>bool</td><td>Ignore XMP profile max DIMMs per channel</td><td>
Ignore the max DIMMs per channel restriciton defined in XMP profiles.<br />
Disabled by default as it might cause system instability.<br />
Handle with care!<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MMCONF_BASE_ADDRESS</td><td>northbridge/intel/sandybridge</td><td>hex</td><td></td><td>
The MRC blob requires it to be at 0xf0000000.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MRC_FILE</td><td>northbridge/intel/sandybridge</td><td>string</td><td>Intel System Agent path and filename</td><td>
The path and filename of the file to use as System Agent<br />
binary.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_SIZE</td><td>northbridge/intel/haswell</td><td>hex</td><td></td><td>
The size of the cache-as-ram region required during bootblock<br />
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE<br />
must add up to a power of 2.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DCACHE_RAM_MRC_VAR_SIZE</td><td>northbridge/intel/haswell</td><td>hex</td><td></td><td>
The amount of cache-as-ram region required by the reference code.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_MRC</td><td>northbridge/intel/haswell</td><td>bool</td><td>Add a System Agent binary</td><td>
Select this option to add a System Agent binary to<br />
the resulting coreboot image.<br />
<br />
Note: Without this binary coreboot will not work<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MRC_FILE</td><td>northbridge/intel/haswell</td><td>string</td><td>Intel System Agent path and filename</td><td>
The path and filename of the file to use as System Agent<br />
binary.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PRE_GRAPHICS_DELAY</td><td>northbridge/intel/haswell</td><td>int</td><td>Graphics initialization delay in ms</td><td>
On some systems, coreboot boots so fast that connected monitors<br />
(mostly TVs) won't be able to wake up fast enough to talk to the<br />
VBIOS. On those systems we need to wait for a bit before executing<br />
the VBIOS.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>I945_LVDS</td><td>northbridge/intel/i945</td><td>string</td><td></td><td>
Selected by mainboards that use native graphics initialization<br />
for the LVDS port. A linear framebuffer is only supported for<br />
LVDS.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>OVERRIDE_CLOCK_DISABLE</td><td>northbridge/intel/i945</td><td>bool</td><td></td><td>
Usually system firmware turns off system memory clock<br />
signals to unused SO-DIMM slots to reduce EMI and power<br />
consumption.<br />
However, some boards do not like unused clock signals to<br />
be disabled.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAXIMUM_SUPPORTED_FREQUENCY</td><td>northbridge/intel/i945</td><td>int</td><td></td><td>
If non-zero, this designates the maximum DDR frequency<br />
the board supports, despite what the chipset should be<br />
capable of.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CHECK_SLFRCS_ON_RESUME</td><td>northbridge/intel/i945</td><td>int</td><td></td><td>
On some boards it may be neccessary to hard reset early<br />
during resume from S3 if the SLFRCS register indicates that<br />
a memory channel is not guaranteed to be in self-refresh.<br />
On other boards the check always creates a false positive,<br />
effectively making it impossible to resume.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SDRAMPWR_4DIMM</td><td>northbridge/intel/i440bx</td><td>bool</td><td></td><td>
This option affects how the SDRAMC register is programmed.<br />
Memory clock signals will not be routed properly if this option<br />
is set wrong.<br />
<br />
If your board has 4 DIMM slots, you must use select this option, in<br />
your Kconfig file of the board. On boards with 3 DIMM slots,<br />
do _not_ select this option.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_ID</td><td>northbridge/intel/fsp_sandybridge</td><td>string</td><td></td><td>
This is the default PCI ID for the sandybridge/ivybridge graphics<br />
devices.  This string names the vbios ROM in cbfs.  The following<br />
PCI IDs will be remapped to load this ROM:<br />
0x80860102, 0x8086010a, 0x80860112, 0x80860116<br />
0x80860122, 0x80860126, 0x80860166<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_FILE</td><td>northbridge/intel/fsp_sandybridge/fsp</td><td>string</td><td></td><td>
The path and filename of the Intel FSP binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_LOC</td><td>northbridge/intel/fsp_sandybridge/fsp</td><td>hex</td><td>Intel FSP Binary location in CBFS</td><td>
The location in CBFS that the FSP is located. This must match the<br />
value that is set in the FSP binary.  If the FSP needs to be moved,<br />
rebase the FSP with the Intel's BCT (tool).<br />
<br />
The Ivy Bridge Processor/Panther Point FSP is built with a preferred<br />
base address of 0xFFF80000<br />
<br />
</td></tr>
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOTTOMIO_POSITION</td><td>northbridge/amd/pi</td><td>hex</td><td>Bottom of 32-bit IO space</td><td>
If PCI peripherals with big BARs are connected to the system<br />
the bottom of the IO must be decreased to allocate such<br />
devices.<br />
<br />
Declare the beginning of the 128MB-aligned MMIO region.  This<br />
option is useful when PCI peripherals requesting large address<br />
ranges are present.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_ID</td><td>northbridge/amd/pi/00630F01</td><td>string</td><td></td><td>
The default VGA BIOS PCI vendor/device ID should be set to the<br />
result of the map_oprom_vendev() function in northbridge.c.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_ID</td><td>northbridge/amd/pi/00730F01</td><td>string</td><td></td><td>
The default VGA BIOS PCI vendor/device ID should be set to the<br />
result of the map_oprom_vendev() function in northbridge.c.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_ID</td><td>northbridge/amd/pi/00660F01</td><td>string</td><td></td><td>
The default VGA BIOS PCI vendor/device ID should be set to the<br />
result of the map_oprom_vendev() function in northbridge.c.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_ID</td><td>northbridge/amd/agesa/family16kb</td><td>string</td><td></td><td>
The default VGA BIOS PCI vendor/device ID should be set to the<br />
result of the map_oprom_vendev() function in northbridge.c.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SVI_HIGH_FREQ</td><td>northbridge/amd/amdfam10</td><td>bool</td><td></td><td>
Select this for boards with a Voltage Regulator able to operate<br />
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.<br />
<br />
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: HyperTransport setup</td></tr>
<tr bgcolor="#eeeeee">
<td>SVI_HIGH_FREQ</td><td>northbridge/amd/amdfam10</td><td>bool</td><td>HyperTransport downlink width</td><td>
This option sets the maximum permissible HyperTransport<br />
downlink width.<br />
<br />
Use of this option will only limit the autodetected HT width.<br />
It will not (and cannot) increase the width beyond the autodetected<br />
limits.<br />
<br />
This is primarily used to work around poorly designed or laid out HT<br />
traces on certain motherboards.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LIMIT_HT_DOWN_WIDTH_16</td><td>northbridge/amd/amdfam10</td><td>bool</td><td>HyperTransport uplink width</td><td>
This option sets the maximum permissible HyperTransport<br />
uplink width.<br />
<br />
Use of this option will only limit the autodetected HT width.<br />
It will not (and cannot) increase the width beyond the autodetected<br />
limits.<br />
<br />
This is primarily used to work around poorly designed or laid out HT<br />
traces on certain motherboards.<br />
<br />
</td></tr>

<tr bgcolor="#eeeeee">
<td></td><td>toplevel</td><td>(comment)</td><td></td><td>Southbridge</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEL_CHIPSET_LOCKDOWN</td><td>southbridge/intel/common</td><td>bool</td><td>Lock down chipset in coreboot</td><td>
Some registers within host bridge on particular chipsets should be<br />
locked down on each normal boot path (done by either coreboot or payload)<br />
and S3 resume (always done by coreboot). Select this to let coreboot<br />
to do this on normal boot path.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIRQ_CONTINUOUS_MODE</td><td>southbridge/intel/fsp_i89xx</td><td>bool</td><td></td><td>
If you set this option to y, the serial IRQ machine will be<br />
operated in continuous mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIRQ_CONTINUOUS_MODE</td><td>southbridge/intel/fsp_rangeley</td><td>bool</td><td></td><td>
If you set this option to y, the serial IRQ machine will be<br />
operated in continuous mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IFD_BIN_PATH</td><td>southbridge/intel/fsp_rangeley</td><td>string</td><td></td><td>
The path and filename to the descriptor.bin file.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEL_LYNXPOINT_LP</td><td>southbridge/intel/lynxpoint</td><td>bool</td><td></td><td>
Set this option to y for Lynxpont LP (Haswell ULT).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIRQ_CONTINUOUS_MODE</td><td>southbridge/intel/lynxpoint</td><td>bool</td><td></td><td>
If you set this option to y, the serial IRQ machine will be<br />
operated in continuous mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ME_MBP_CLEAR_LATE</td><td>southbridge/intel/lynxpoint</td><td>bool</td><td>Defer wait for ME MBP Cleared</td><td>
If you set this option to y, the Management Engine driver<br />
will defer waiting for the MBP Cleared indicator until the<br />
finalize step.  This can speed up boot time if the ME takes<br />
a long time to indicate this status.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FINALIZE_USB_ROUTE_XHCI</td><td>southbridge/intel/lynxpoint</td><td>bool</td><td>Route all ports to XHCI controller in finalize step</td><td>
If you set this option to y, the USB ports will be routed<br />
to the XHCI controller during the finalize SMM callback.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIRQ_CONTINUOUS_MODE</td><td>southbridge/intel/fsp_bd82x6x</td><td>bool</td><td></td><td>
If you set this option to y, the serial IRQ machine will be<br />
operated in continuous mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIRQ_CONTINUOUS_MODE</td><td>southbridge/intel/ibexpeak</td><td>bool</td><td></td><td>
If you set this option to y, the serial IRQ machine will be<br />
operated in continuous mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIRQ_CONTINUOUS_MODE</td><td>southbridge/intel/bd82x6x</td><td>bool</td><td></td><td>
If you set this option to y, the serial IRQ machine will be<br />
operated in continuous mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LOCK_SPI_FLASH_RO</td><td>southbridge/intel/bd82x6x</td><td>bool</td><td>Write-protect all flash sections</td><td>
Select this if you want to write-protect the whole firmware flash<br />
chip. The locking will take place during the chipset lockdown, which<br />
is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)<br />
or has to be triggered later (e.g. by the payload or the OS).<br />
<br />
NOTE: If you trigger the chipset lockdown unconditionally,<br />
you won't be able to write to the flash chip using the<br />
internal programmer any more.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LOCK_SPI_FLASH_NO_ACCESS</td><td>southbridge/intel/bd82x6x</td><td>bool</td><td>Write-protect all flash sections and read-protect non-BIOS sections</td><td>
Select this if you want to protect the firmware flash against all<br />
further accesses (with the exception of the memory mapped BIOS re-<br />
gion which is always readable). The locking will take place during<br />
the chipset lockdown, which is either triggered by coreboot (when<br />
INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.<br />
by the payload or the OS).<br />
<br />
NOTE: If you trigger the chipset lockdown unconditionally,<br />
you won't be able to write to the flash chip using the<br />
internal programmer any more.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NO_EARLY_SMBUS</td><td>southbridge/amd/cs5536</td><td>bool</td><td></td><td>
Skip the CS5536 early SMBUS initialization.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_XHCI_ENABLE</td><td>southbridge/amd/pi/hudson</td><td>bool</td><td>Enable Hudson XHCI Controller</td><td>
The XHCI controller must be enabled and the XHCI firmware<br />
must be added in order to have USB 3.0 support configured<br />
by coreboot. The OS will be responsible for enabling the XHCI<br />
controller if the the XHCI firmware is available but the<br />
XHCI controller is not enabled by coreboot.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_XHCI_FWM</td><td>southbridge/amd/pi/hudson</td><td>bool</td><td>Add xhci firmware</td><td>
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_IMC_FWM</td><td>southbridge/amd/pi/hudson</td><td>bool</td><td>Add IMC firmware</td><td>
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_GEC_FWM</td><td>southbridge/amd/pi/hudson</td><td>bool</td><td></td><td>
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.<br />
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_SATA_MODE</td><td>southbridge/amd/pi/hudson</td><td>int</td><td>SATA Mode</td><td>
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.<br />
The default is NATIVE.<br />
0: NATIVE mode does not require a ROM.<br />
1: RAID mode must have the two ROM files.<br />
2: AHCI may work with or without AHCI ROM. It depends on the payload support.<br />
For example, seabios does not require the AHCI ROM.<br />
3: LEGACY IDE<br />
4: IDE to AHCI<br />
5: AHCI7804: ROM Required, and AMD driver required in the OS.<br />
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/pi/hudson</td><td>(comment)</td><td></td><td>NATIVE</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/pi/hudson</td><td>(comment)</td><td></td><td>RAID</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/pi/hudson</td><td>(comment)</td><td></td><td>AHCI</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/pi/hudson</td><td>(comment)</td><td></td><td>LEGACY IDE</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/pi/hudson</td><td>(comment)</td><td></td><td>IDE to AHCI</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/pi/hudson</td><td>(comment)</td><td></td><td>AHCI7804</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/pi/hudson</td><td>(comment)</td><td></td><td>IDE to AHCI7804</td></tr>
<tr bgcolor="#eeeeee">
<td>RAID_ROM_ID</td><td>southbridge/amd/pi/hudson</td><td>string</td><td>RAID device PCI IDs</td><td>
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RAID_MISC_ROM_POSITION</td><td>southbridge/amd/pi/hudson</td><td>hex</td><td>RAID Misc ROM Position</td><td>
The RAID ROM requires that the MISC ROM is located between the range<br />
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.<br />
The CONFIG_ROM_SIZE must be larger than 0x100000.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_LEGACY_FREE</td><td>southbridge/amd/pi/hudson</td><td>bool</td><td>System is legacy free</td><td>
Select y if there is no keyboard controller in the system.<br />
This sets variables in AGESA and ACPI.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AZ_PIN</td><td>southbridge/amd/pi/hudson</td><td>hex</td><td></td><td>
bit 1,0 - pin 0<br />
bit 3,2 - pin 1<br />
bit 5,4 - pin 2<br />
bit 7,6 - pin 3<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AMDFW_OUTSIDE_CBFS</td><td>southbridge/amd/pi/hudson</td><td>hex</td><td></td><td>
The AMDFW (PSP) is typically locatable in cbfs.  Select this<br />
option to manually attach the generated amdfw.rom at an<br />
offset of 0x20000 from the bottom of the coreboot ROM image.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SERIRQ_CONTINUOUS_MODE</td><td>southbridge/amd/pi/hudson</td><td>bool</td><td></td><td>
Set this option to y for serial IRQ in continuous mode.<br />
Otherwise it is in quiet mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_ACPI_IO_BASE</td><td>southbridge/amd/pi/hudson</td><td>hex</td><td></td><td>
Base address for the ACPI registers.<br />
This value must match the hardcoded value of AGESA.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_UART</td><td>southbridge/amd/pi/hudson</td><td>bool</td><td>UART controller on Kern</td><td>
There are two UART controllers in Kern.<br />
The UART registers are memory-mapped. UART<br />
controller 0 registers range from FEDC_6000h<br />
to FEDC_6FFFh. UART controller 1 registers<br />
range from FEDC_8000h to FEDC_8FFFh.<br />
<br />
</td></tr>
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_XHCI_ENABLE</td><td>southbridge/amd/agesa/hudson</td><td>bool</td><td>Enable Hudson XHCI Controller</td><td>
The XHCI controller must be enabled and the XHCI firmware<br />
must be added in order to have USB 3.0 support configured<br />
by coreboot. The OS will be responsible for enabling the XHCI<br />
controller if the the XHCI firmware is available but the<br />
XHCI controller is not enabled by coreboot.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_XHCI_FWM</td><td>southbridge/amd/agesa/hudson</td><td>bool</td><td>Add xhci firmware</td><td>
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_IMC_FWM</td><td>southbridge/amd/agesa/hudson</td><td>bool</td><td>Add imc firmware</td><td>
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_GEC_FWM</td><td>southbridge/amd/agesa/hudson</td><td>bool</td><td></td><td>
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.<br />
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_SATA_MODE</td><td>southbridge/amd/agesa/hudson</td><td>int</td><td>SATA Mode</td><td>
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.<br />
The default is NATIVE.<br />
0: NATIVE mode does not require a ROM.<br />
1: RAID mode must have the two ROM files.<br />
2: AHCI may work with or without AHCI ROM. It depends on the payload support.<br />
For example, seabios does not require the AHCI ROM.<br />
3: LEGACY IDE<br />
4: IDE to AHCI<br />
5: AHCI7804: ROM Required, and AMD driver required in the OS.<br />
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/agesa/hudson</td><td>(comment)</td><td></td><td>NATIVE</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/agesa/hudson</td><td>(comment)</td><td></td><td>RAID</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/agesa/hudson</td><td>(comment)</td><td></td><td>AHCI</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/agesa/hudson</td><td>(comment)</td><td></td><td>LEGACY IDE</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/agesa/hudson</td><td>(comment)</td><td></td><td>IDE to AHCI</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/agesa/hudson</td><td>(comment)</td><td></td><td>AHCI7804</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/amd/agesa/hudson</td><td>(comment)</td><td></td><td>IDE to AHCI7804</td></tr>
<tr bgcolor="#eeeeee">
<td>RAID_ROM_ID</td><td>southbridge/amd/agesa/hudson</td><td>string</td><td>RAID device PCI IDs</td><td>
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RAID_MISC_ROM_POSITION</td><td>southbridge/amd/agesa/hudson</td><td>hex</td><td>RAID Misc ROM Position</td><td>
The RAID ROM requires that the MISC ROM is located between the range<br />
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.<br />
The CONFIG_ROM_SIZE must be larger than 0x100000.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HUDSON_LEGACY_FREE</td><td>southbridge/amd/agesa/hudson</td><td>bool</td><td>System is legacy free</td><td>
Select y if there is no keyboard controller in the system.<br />
This sets variables in AGESA and ACPI.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AZ_PIN</td><td>southbridge/amd/agesa/hudson</td><td>hex</td><td></td><td>
bit 1,0 - pin 0<br />
bit 3,2 - pin 1<br />
bit 5,4 - pin 2<br />
bit 7,6 - pin 3<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EXT_CONF_SUPPORT</td><td>southbridge/amd/sr5650</td><td>bool</td><td>Enable PCI-E MMCONFIG support</td><td>
Select to enable PCI-E MMCONFIG support on the SR5650.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_IDE_COMBINED_MODE</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>Enable SATA IDE combined mode</td><td>
If Combined Mode is enabled. IDE controller is exposed and<br />
SATA controller has control over Port0 through Port3,<br />
IDE controller has control over Port4 and Port5.<br />
<br />
If Combined Mode is disabled, IDE controller is hidden and<br />
SATA controller has full control of all 6 Ports when operating in non-IDE mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IDE_COMBINED_MODE</td><td>southbridge/amd/cimx/sb800</td><td>hex</td><td>SATA Mode</td><td>
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.<br />
The default is AHCI.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_SATA_IDE</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>NATIVE</td><td>
NATIVE does not require a ROM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_SATA_AHCI</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>AHCI</td><td>
AHCI is the default and may work with or without AHCI ROM. It depends on the payload support.<br />
For example, seabios does not require the AHCI ROM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_SATA_RAID</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>RAID</td><td>
sb800 RAID mode must have the two required ROM files.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RAID_ROM_ID</td><td>southbridge/amd/cimx/sb800</td><td>string</td><td>RAID device PCI IDs</td><td>
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RAID_MISC_ROM_POSITION</td><td>southbridge/amd/cimx/sb800</td><td>hex</td><td>RAID Misc ROM Position</td><td>
The RAID ROM requires that the MISC ROM is located between the range<br />
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.<br />
The CONFIG_ROM_SIZE must larger than 0x100000.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_IMC_FWM</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>Add IMC firmware</td><td>
Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_FWM_AT_FFFA0000</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>0xFFFA0000</td><td>
The IMC and GEC ROMs requires a 'signature' located at one of several<br />
fixed locations in memory.  The location used shouldn't matter, just<br />
select an area that doesn't conflict with anything else.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_FWM_AT_FFF20000</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>0xFFF20000</td><td>
The IMC and GEC ROMs requires a 'signature' located at one of several<br />
fixed locations in memory.  The location used shouldn't matter, just<br />
select an area that doesn't conflict with anything else.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_FWM_AT_FFE20000</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>0xFFE20000</td><td>
The IMC and GEC ROMs requires a 'signature' located at one of several<br />
fixed locations in memory.  The location used shouldn't matter, just<br />
select an area that doesn't conflict with anything else.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_FWM_AT_FFC20000</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>0xFFC20000</td><td>
The IMC and GEC ROMs requires a 'signature' located at one of several<br />
fixed locations in memory.  The location used shouldn't matter, just<br />
select an area that doesn't conflict with anything else.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_FWM_AT_FF820000</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>0xFF820000</td><td>
The IMC and GEC ROMs requires a 'signature' located at one of several<br />
fixed locations in memory.  The location used shouldn't matter, just<br />
select an area that doesn't conflict with anything else.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EHCI_BAR</td><td>southbridge/amd/cimx/sb800</td><td>hex</td><td>Fan Control</td><td>
Select the method of SB800 fan control to be used.  None would be<br />
for either fixed maximum speed fans connected to the SB800 or for<br />
an external chip controlling the fan speeds.  Manual control sets<br />
up the SB800 fan control registers.  IMC fan control uses the SB800<br />
IMC to actively control the fan speeds.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_NO_FAN_CONTROL</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>None</td><td>
No SB800 Fan control - Do not set up the SB800 fan control registers.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_MANUAL_FAN_CONTROL</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>Manual</td><td>
Configure the SB800 fan control registers in devicetree.cb.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SB800_IMC_FAN_CONTROL</td><td>southbridge/amd/cimx/sb800</td><td>bool</td><td>IMC Based</td><td>
Set up the SB800 to use the IMC based Fan controller.  This requires<br />
the IMC ROM from AMD.  Configure the registers in devicetree.cb.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SATA_CONTROLLER_MODE</td><td>southbridge/amd/cimx/sb900</td><td>hex</td><td></td><td>
0x0 = Native IDE mode.<br />
0x1 = RAID mode.<br />
0x2 = AHCI mode.<br />
0x3 = Legacy IDE mode.<br />
0x4 = IDE-&gt;AHCI mode.<br />
0x5 = AHCI mode as 7804 ID (AMD driver).<br />
0x6 = IDE-&gt;AHCI mode as 7804 ID (AMD driver).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCIB_ENABLE</td><td>southbridge/amd/cimx/sb900</td><td>bool</td><td></td><td>
n = Disable PCI Bridge Device 14 Function 4.<br />
y = Enable PCI Bridge Device 14 Function 4.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ACPI_SCI_IRQ</td><td>southbridge/amd/cimx/sb900</td><td>hex</td><td></td><td>
Set SCI IRQ to 9.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOUTHBRIDGE_AMD_SB700_33MHZ_SPI</td><td>southbridge/amd/sb700</td><td>bool</td><td>Enable high speed SPI clock</td><td>
When set, the SPI clock will run at 33MHz instead<br />
of the compatibility mode 16.5MHz.  Note that not<br />
all ROMs are capable of 33MHz operation, so you<br />
will need to verify this option is appropriate for<br />
the ROM you are using.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>toplevel</td><td>(comment)</td><td></td><td>Super I/O</td></tr>
<tr bgcolor="#eeeeee">
<td>SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG</td><td>superio/ite/common</td><td>bool</td><td></td><td>
Enable extended, 16-bit wide tacho counters.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SUPERIO_ITE_ENV_CTRL_8BIT_PWM</td><td>superio/ite/common</td><td>bool</td><td></td><td>
PWM duty cycles are set in 8-bit registers (instead of 7 bit).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SUPERIO_ITE_ENV_CTRL_PWM_FREQ2</td><td>superio/ite/common</td><td>bool</td><td></td><td>
The second FAN controller has a separate frequency setting.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>toplevel</td><td>(comment)</td><td></td><td>Embedded Controllers</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_ACPI</td><td>ec/acpi</td><td>bool</td><td></td><td>
ACPI Embedded Controller interface. Mostly found in laptops.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_KONTRON_IT8516E</td><td>ec/kontron/it8516e</td><td>bool</td><td></td><td>
Kontron uses an ITE IT8516E on the KTQM77. Its firmware might<br />
come from Fintek (mentioned as Finte*c* somewhere in their Linux<br />
driver).<br />
The KTQM77 is an embedded board and the IT8516E seems to be<br />
only used for fan control and GPIO.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_PURISM_LIBREM</td><td>ec/purism/librem</td><td>bool</td><td></td><td>
Purism Librem EC<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_QUANTA_IT8518</td><td>ec/quanta/it8518</td><td>bool</td><td></td><td>
Interface to QUANTA IT8518 Embedded Controller.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_QUANTA_ENE_KB3940Q</td><td>ec/quanta/ene_kb3940q</td><td>bool</td><td></td><td>
Interface to QUANTA ENE KB3940Q Embedded Controller.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC</td><td>ec/google/chromeec</td><td>bool</td><td></td><td>
Google's Chrome EC<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_ACPI_MEMMAP</td><td>ec/google/chromeec</td><td>bool</td><td></td><td>
When defined, ACPI accesses EC memmap data on ports 66h/62h. When<br />
not defined, the memmap data is instead accessed on 900h-9ffh via<br />
the LPC bus.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER</td><td>ec/google/chromeec</td><td>bool</td><td></td><td>
Expose methods for enabling and disabling port power on individual USB<br />
ports through the EC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_BOARDID</td><td>ec/google/chromeec</td><td>bool</td><td></td><td>
Provides common routine for reading boardid from Chrome EC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_I2C</td><td>ec/google/chromeec</td><td>bool</td><td></td><td>
Google's Chrome EC via I2C bus.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_I2C_PROTO3</td><td>ec/google/chromeec</td><td>bool</td><td></td><td>
Use only proto3 for i2c EC communication.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_LPC</td><td>ec/google/chromeec</td><td>bool</td><td></td><td>
Google Chrome EC via LPC bus.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_MEC</td><td>ec/google/chromeec</td><td>bool</td><td></td><td>
Microchip EC variant for LPC register access.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_PD</td><td>ec/google/chromeec</td><td>bool</td><td></td><td>
Indicates that Google's Chrome USB PD chip is present.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_SPI</td><td>ec/google/chromeec</td><td>bool</td><td></td><td>
Google's Chrome EC via SPI bus.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US</td><td>ec/google/chromeec</td><td>int</td><td></td><td>
Force delay after asserting /CS to allow EC to wakeup.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_BOARDNAME</td><td>ec/google/chromeec</td><td>string</td><td>Chrome EC board name for EC</td><td>
The board name used in the Chrome EC code base to build<br />
the EC firmware.  If set, the coreboot build with also<br />
build the EC firmware and add it to the image.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_PD_BOARDNAME</td><td>ec/google/chromeec</td><td>string</td><td>Chrome EC board name for PD</td><td>
The board name used in the Chrome EC code base to build<br />
the PD firmware.  If set, the coreboot build with also<br />
build the EC firmware and add it to the image.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_RTC</td><td>ec/google/chromeec</td><td>bool</td><td>Enable Chrome OS EC RTC</td><td>
Enable support for the real-time clock on the Chrome OS EC. This<br />
uses the EC_CMD_RTC_GET_VALUE command to read the current time.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_FIRMWARE_NONE</td><td>ec/google/chromeec</td><td>bool</td><td>No EC firmware is included</td><td>
Disable building and including any EC firmware in the image.<br />
<br />
config EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL<br />
bool "External EC firmware is included"<br />
help<br />
Include EC firmware binary in the image from an external source.<br />
It is expected to be built externally.<br />
<br />
config EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN<br />
bool "Builtin EC firmware is included"<br />
help<br />
Build and include EC firmware binary in the image.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_FIRMWARE_FILE</td><td>ec/google/chromeec</td><td>string</td><td>Chrome EC firmware path and filename</td><td>
The path and filename of the EC firmware file to use.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_PD_FIRMWARE_NONE</td><td>ec/google/chromeec</td><td>bool</td><td>No PD firmware is included</td><td>
Disable building and including any PD firmware in the image.<br />
<br />
config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_EXTERNAL<br />
bool "External PD firmware is included"<br />
help<br />
Include PD firmware binary in the image from an external source.<br />
It is expected to be built externally.<br />
<br />
config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_BUILTIN<br />
bool "Builtin PD firmware is included"<br />
help<br />
Build and include PD firmware binary in the image.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_PD_FIRMWARE_FILE</td><td>ec/google/chromeec</td><td>string</td><td>Chrome EC firmware path and filename for PD</td><td>
The path and filename of the PD firmware file to use.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_GOOGLE_CHROMEEC_SWITCHES</td><td>ec/google/chromeec</td><td>bool</td><td></td><td>
Enable support for Chrome OS mode switches provided by the Chrome OS<br />
EC.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>H8_BEEP_ON_DEATH</td><td>ec/lenovo/h8</td><td>bool</td><td>Beep on fatal error</td><td>
Beep when encountered a fatal error.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>H8_FLASH_LEDS_ON_DEATH</td><td>ec/lenovo/h8</td><td>bool</td><td>Flash LEDs on fatal error</td><td>
Flash all LEDs when encountered a fatal error.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>H8_SUPPORT_BT_ON_WIFI</td><td>ec/lenovo/h8</td><td>bool</td><td>Support bluetooth on wifi cards</td><td>
Disable BDC detection and assume bluetooth is installed. Required for<br />
bluetooth on wifi cards, as it's not possible to detect it in coreboot.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_RODA_IT8518</td><td>ec/roda/it8518</td><td>bool</td><td></td><td>
Interface to IT8518 embedded controller in Roda notebooks.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_SMSC_MEC1308</td><td>ec/smsc/mec1308</td><td>bool</td><td></td><td>
Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_COMPAL_ENE932</td><td>ec/compal/ene932</td><td>bool</td><td></td><td>
Interface to COMPAL ENE932 Embedded Controller.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>EC_HP_KBC1126</td><td>ec/hp/kbc1126</td><td>bool</td><td></td><td>
Interface to SMSC KBC1126 embedded controller in HP laptops.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>ec/hp/kbc1126</td><td>(comment)</td><td></td><td>Please select the following otherwise your laptop cannot be powered on.</td></tr>
<tr bgcolor="#eeeeee">
<td>KBC1126_FIRMWARE</td><td>ec/hp/kbc1126</td><td>bool</td><td>Add firmware images for KBC1126 EC</td><td>
Select this option to add the two firmware blobs for KBC1126.<br />
You need these two blobs to power on your machine.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>KBC1126_FW1</td><td>ec/hp/kbc1126</td><td>string</td><td>KBC1126 firmware #1 path and filename</td><td>
The path and filename of the file to use as KBC1126 firmware #1.<br />
You can use util/kbc1126/kbc1126_ec_dump to dump it from the<br />
vendor firmware.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>KBC1126_FW2</td><td>ec/hp/kbc1126</td><td>string</td><td>KBC1126 filename #2 path and filename</td><td>
The path and filename of the file to use as KBC1126 firmware #2.<br />
You can use util/kbc1126/kbc1126_ec_dump to dump it from the<br />
vendor firmware.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>drivers/intel/fsp1_0</td><td>(comment)</td><td></td><td>Intel FSP</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_FSP_BIN</td><td>drivers/intel/fsp1_0</td><td>bool</td><td>Use Intel Firmware Support Package</td><td>
Select this option to add an Intel FSP binary to<br />
the resulting coreboot image.<br />
<br />
Note: Without this binary, coreboot builds relying on the FSP<br />
will not boot<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_FILE</td><td>drivers/intel/fsp1_0</td><td>string</td><td>Intel FSP binary path and filename</td><td>
The path and filename of the Intel FSP binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_LOC</td><td>drivers/intel/fsp1_0</td><td>hex</td><td>Intel FSP Binary location in CBFS</td><td>
The location in CBFS that the FSP is located. This must match the<br />
value that is set in the FSP binary.  If the FSP needs to be moved,<br />
rebase the FSP with Intel's BCT (tool).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_FSP_FAST_BOOT</td><td>drivers/intel/fsp1_0</td><td>bool</td><td>Enable Fast Boot</td><td>
Enabling this feature will force the MRC data to be cached in NV<br />
storage to be used for speeding up boot time on future reboots<br />
and/or power cycles.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_MRC_CACHE</td><td>drivers/intel/fsp1_0</td><td>bool</td><td></td><td>
Enabling this feature will cause MRC data to be cached in NV storage.<br />
This can either be used for fast boot, or just because the FSP wants<br />
it to be saved.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MRC_CACHE_FMAP</td><td>drivers/intel/fsp1_0</td><td>bool</td><td>Use MRC Cache in FMAP</td><td>
Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.<br />
You must define a region in your FMAP named "RW_MRC_CACHE".<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MRC_CACHE_SIZE</td><td>drivers/intel/fsp1_0</td><td>hex</td><td>Fast Boot Data Cache Size</td><td>
This is the amount of space in NV storage that is reserved for the<br />
fast boot data cache storage.<br />
<br />
WARNING: Because this area will be erased and re-written, the size<br />
should be a full sector of the flash ROM chip and nothing else should<br />
be included in CBFS in any sector that the fast boot cache data is in.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VIRTUAL_ROM_SIZE</td><td>drivers/intel/fsp1_0</td><td>hex</td><td>Virtual ROM Size</td><td>
This is used to calculate the offset of the MRC data cache in NV<br />
Storage for fast boot.  If in doubt, leave this set to the default<br />
which sets the virtual size equal to the ROM size.<br />
<br />
Example: Cougar Canyon 2 has two 8 MB SPI ROMs.  When the SPI ROMs are<br />
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB.  When<br />
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM<br />
size is 16 MB.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_GENERIC_FSP_CAR_INC</td><td>drivers/intel/fsp1_0</td><td>bool</td><td></td><td>
The chipset can select this to use a generic cache_as_ram.inc file<br />
that should be good for all FSP based platforms.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_USES_UPD</td><td>drivers/intel/fsp1_0</td><td>bool</td><td></td><td>
If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_INTEL_FIRMWARE</td><td>southbridge/intel/common/firmware</td><td>bool</td><td></td><td>
Chipset uses the Intel Firmware Descriptor to describe the<br />
layout of the SPI ROM chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/intel/common/firmware</td><td>(comment)</td><td></td><td>Intel Firmware</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_IFD_BIN</td><td>southbridge/intel/common/firmware</td><td>bool</td><td>Add Intel descriptor.bin file</td><td>
The descriptor binary<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EM100</td><td>southbridge/intel/common/firmware</td><td>bool</td><td>Configure IFD for EM100 usage</td><td>
Set SPI frequency to 20MHz and disable Dual Output Fast Read Support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_ME_BIN</td><td>southbridge/intel/common/firmware</td><td>bool</td><td>Add Intel ME/TXE firmware</td><td>
The Intel processor in the selected system requires a special firmware<br />
for an integrated controller.  This might be called the Management<br />
Engine (ME), the Trusted Execution Engine (TXE) or something else<br />
depending on the chip. This firmware might or might not be available<br />
in coreboot's 3rdparty/blobs repository. If it is not and if you don't<br />
have access to the firmware from elsewhere, you can still build<br />
coreboot without it. In this case however, you'll have to make sure<br />
that you don't overwrite your ME/TXE firmware on your flash ROM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CHECK_ME</td><td>southbridge/intel/common/firmware</td><td>bool</td><td>Verify the integrity of the supplied ME/TXE firmware</td><td>
Verify the integrity of the supplied Intel ME/TXE firmware before<br />
proceeding with the build, in order to prevent an accidental loading<br />
of a corrupted ME/TXE image.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_ME_CLEANER</td><td>southbridge/intel/common/firmware</td><td>bool</td><td>Strip down the Intel ME/TXE firmware</td><td>
Use me_cleaner to remove all the non-fundamental code from the Intel<br />
ME/TXE firmware.<br />
The resulting Intel ME/TXE firmware will have only the code<br />
responsible for the very basic hardware initialization, leaving the<br />
ME/TXE subsystem essentially in a disabled state.<br />
<br />
Don't flash a modified ME/TXE firmware and a new coreboot image at the<br />
same time, test them in two different steps.<br />
<br />
WARNING: this tool isn't based on any official Intel documentation but<br />
only on reverse engineering and trial &amp; error.<br />
<br />
See the project's page<br />
https://github.com/corna/me_cleaner<br />
or the wiki<br />
https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner<br />
https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F<br />
https://github.com/corna/me_cleaner/wiki/me_cleaner-status<br />
for more info about this tool<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>southbridge/intel/common/firmware</td><td>(comment)</td><td></td><td>Please test the modified ME/TXE firmware and coreboot in two steps</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_GBE_BIN</td><td>southbridge/intel/common/firmware</td><td>bool</td><td>Add gigabit ethernet firmware</td><td>
The integrated gigabit ethernet controller needs a firmware file.<br />
Select this if you are going to use the PCH integrated controller<br />
and have the firmware.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_EC_BIN</td><td>southbridge/intel/common/firmware</td><td>bool</td><td>Add EC firmware</td><td>
The embedded controller needs a firmware file.<br />
<br />
Select this if you are going to use the PCH integrated controller<br />
and have the EC firmware. EC firmware will be added to final image<br />
through ifdtool.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BUILD_WITH_FAKE_IFD</td><td>southbridge/intel/common/firmware</td><td>bool</td><td>Build with a fake IFD</td><td>
If you don't have an Intel Firmware Descriptor (descriptor.bin) for your<br />
board, you can select this option and coreboot will build without it.<br />
The resulting coreboot.rom will not contain all parts required<br />
to get coreboot running on your board. You can however write only the<br />
BIOS section to your board's flash ROM and keep the other sections<br />
untouched. Unfortunately the current version of flashrom doesn't<br />
support this yet. But there is a patch pending [1].<br />
<br />
WARNING: Never write a complete coreboot.rom to your flash ROM if it<br />
was built with a fake IFD. It just won't work.<br />
<br />
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IFD_BIOS_SECTION</td><td>southbridge/intel/common/firmware</td><td>string</td><td>BIOS Region Starting:Ending addresses within the ROM</td><td>
The BIOS region is typically the size of the CBFS area, and is located<br />
at the end of the ROM space.<br />
<br />
For an 8MB ROM with a 3MB CBFS area, this would look like:<br />
0x00500000:0x007fffff<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IFD_ME_SECTION</td><td>southbridge/intel/common/firmware</td><td>string</td><td>ME/TXE Region Starting:Ending addresses within the ROM</td><td>
The ME/TXE region typically starts at around 0x1000 and often fills the<br />
ROM space not used by CBFS.<br />
<br />
For an 8MB ROM with a 3MB CBFS area, this might look like:<br />
0x00001000:0x004fffff<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IFD_GBE_SECTION</td><td>southbridge/intel/common/firmware</td><td>string</td><td>GBE Region Starting:Ending addresses within the ROM</td><td>
The Gigabit Ethernet ROM region is used when an Intel NIC is built into<br />
the Southbridge/SOC and the platform uses this device instead of an external<br />
PCIe NIC.  It will be located between the ME/TXE and the BIOS region.<br />
<br />
Leave this empty if you're unsure.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IFD_PLATFORM_SECTION</td><td>southbridge/intel/common/firmware</td><td>string</td><td>Platform Region Starting:Ending addresses within the Rom</td><td>
The Platform region is used for platform specific data.<br />
It will be located between the ME/TXE and the BIOS region.<br />
<br />
Leave this empty if you're unsure.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LOCK_MANAGEMENT_ENGINE</td><td>southbridge/intel/common/firmware</td><td>bool</td><td>Lock ME/TXE section</td><td>
The Intel Firmware Descriptor supports preventing write accesses<br />
from the host to the ME or TXE section in the firmware<br />
descriptor. If the section is locked, it can only be overwritten<br />
with an external SPI flash programmer. You will want this if you<br />
want to increase security of your ROM image once you are sure<br />
that the ME/TXE firmware is no longer going to change.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CBFS_SIZE</td><td>southbridge/intel/common/firmware</td><td>hex</td><td></td><td>
Reduce CBFS size to give room to the IFD blobs.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UDK_VERSION</td><td>vendorcode/intel</td><td>int</td><td></td><td>
UEFI Development Kit version for Platform<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: ChromeOS</td></tr>
<tr bgcolor="#eeeeee">
<td>CHROMEOS</td><td>vendorcode/google/chromeos</td><td>bool</td><td>Build for ChromeOS</td><td>
Enable ChromeOS specific features like the GPIO sub table in<br />
the coreboot table. NOTE: Enabling this option on an unsupported<br />
board will most likely break your build.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NO_TPM_RESUME</td><td>vendorcode/google/chromeos</td><td>bool</td><td></td><td>
On some boards the TPM stays powered up in S3. On those<br />
boards, booting Windows will break if the TPM resume command<br />
is sent during an S3 resume.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_REGULATORY_DOMAIN</td><td>vendorcode/google/chromeos</td><td>bool</td><td>Add regulatory domain methods</td><td>
This option is needed to add ACPI regulatory domain methods<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME</td><td>vendorcode/google/chromeos</td><td>bool</td><td></td><td>
Disable the platform heirarchy on resume path if the firmware<br />
is involved in resume. The hierarchy is disabled prior to jumping<br />
to the OS.  Note that this option is sepcific to TPM2 boards.<br />
This option is auto selected if CHROMEOS because it matches with<br />
vboot_reference model which disables the platform hierarchy in<br />
the boot loader. However, those operations need to be symmetric<br />
on normal boot as well as resume and coreboot is only involved<br />
in the resume piece w.r.t. the platform hierarchy.<br />
<br />
</td></tr>

<tr bgcolor="#eeeeee">
<td>GOOGLE_SMBIOS_MAINBOARD_VERSION</td><td>vendorcode/google</td><td>bool</td><td></td><td>
Provide a common implementation for mainboard version,<br />
which returns a formatted 'rev%d' board_id() string.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: AMD Platform Initialization</td></tr>
<tr bgcolor="#eeeeee">
<td>None</td><td>vendorcode/amd</td><td>None</td><td>AGESA source</td><td>
Select the method for including the AMD Platform Initialization<br />
code into coreboot.  Platform Initialization code is required for<br />
all AMD processors.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_AMD_AGESA_BINARY_PI</td><td>vendorcode/amd</td><td>bool</td><td>binary PI</td><td>
Use a binary PI package.  Generally, these will be stored in the<br />
"3rdparty/blobs" directory.  For some processors, these must be obtained<br />
directly from AMD Embedded Processors Group<br />
(http://www.amdcom/embedded).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_AMD_AGESA_OPENSOURCE</td><td>vendorcode/amd</td><td>bool</td><td>open-source AGESA</td><td>
Build the PI package ("AGESA") from source code in the "vendorcode"<br />
directory.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AGESA_BINARY_PI_VENDORCODE_PATH</td><td>vendorcode/amd/pi</td><td>string</td><td>AGESA PI directory path</td><td>
Specify where to find the AGESA header files<br />
for AMD platform initialization.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AGESA_BINARY_PI_FILE</td><td>vendorcode/amd/pi</td><td>string</td><td>AGESA PI binary file name</td><td>
Specify the binary file to use for AMD platform initialization.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AGESA_BINARY_PI_AS_STAGE</td><td>vendorcode/amd/pi</td><td>bool</td><td>AGESA Binary PI is added as stage to CBFS.</td><td>
AGESA will be added as a stage utilizing --xip cbfstool options<br />
as needed relocating the image to the proper location in memory-mapped<br />
cpu address space. It's required that the file be in ELF format<br />
containing the relocations necessary for relocating at runtime.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AGESA_SPLIT_MEMORY_FILES</td><td>vendorcode/amd/pi</td><td>bool</td><td>Split AGESA Binary PI into pre- and post-memory files.</td><td>
Specifies that AGESA is split into two binaries for pre- and<br />
post-memory.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AGESA_PRE_MEMORY_BINARY_PI_FILE</td><td>vendorcode/amd/pi</td><td>string</td><td></td><td>
Specify the binary file to use for pre-memory AMD platform<br />
initialization.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AGESA_POST_MEMORY_BINARY_PI_FILE</td><td>vendorcode/amd/pi</td><td>string</td><td></td><td>
Specify the binary file to use for post-memory AMD platform<br />
initialization.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>AGESA_BINARY_PI_LOCATION</td><td>vendorcode/amd/pi</td><td>hex</td><td>AGESA PI binary address in ROM</td><td>
Specify the ROM address at which to store the binary Platform<br />
Initialization code.<br />
<br />
</td></tr>

<tr bgcolor="#eeeeee">
<td>ARCH_RISCV_COMPRESSED</td><td>arch/riscv</td><td>bool</td><td></td><td>
Enable this option if your RISC-V processor supports compressed<br />
instructions (RVC). Currently, this enables RVC for all stages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ARCH_ARMV8_EXTENSION</td><td>arch/arm64/armv8</td><td>int</td><td></td><td>
Specify ARMv8 extension, for example '1' for ARMv8.1, to control the<br />
'-march' option passed into the compiler. Defaults to 0 for vanilla<br />
ARMv8 but may be overridden in the SoC's Kconfig.<br />
<br />
All ARMv8 implementations are downwards-compatible, so this does not<br />
need to be changed unless specific features (e.g. new instructions)<br />
are used by the SoC's coreboot code.<br />
<br />
</td></tr>
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ARM64_SECURE_OS_FILE</td><td>arch/arm64</td><td>string</td><td>Secure OS binary file</td><td>
Secure OS binary file.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ARM64_A53_ERRATUM_843419</td><td>arch/arm64</td><td>bool</td><td></td><td>
Some early Cortex-A53 revisions had a hardware bug that results in<br />
incorrect address calculations in rare cases. This option enables a<br />
linker workaround to avoid those cases if your toolchain supports it.<br />
Should be selected automatically by SoCs that are affected.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_MARCH_586</td><td>arch/x86</td><td>bool</td><td></td><td>
Allow a platform or processor to select to be compiled using<br />
the '-march=i586' option instead of the typical '-march=i686'<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CBMEM_TOP_BACKUP</td><td>arch/x86</td><td>int</td><td></td><td>
Platform implements non-volatile storage to cache cbmem_top()<br />
over stage transitions and optionally also over S3 suspend.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LATE_CBMEM_INIT</td><td>arch/x86</td><td>int</td><td></td><td>
Enable this in chipset's Kconfig if northbridge does not implement<br />
early cbmem_top() call for romstage. CBMEM tables will be allocated<br />
late in ramstage, after PCI devices resources are known.<br />
<br />
WARNING: Late CBMEM initialization is deprecated. Platforms that<br />
don't support early CBMEM initialization will be removed after<br />
the release of coreboot 4.7.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PRERAM_CBMEM_CONSOLE_SIZE</td><td>arch/x86</td><td>hex</td><td></td><td>
Increase this value if preram cbmem console is getting truncated<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EARLY_EBDA_INIT</td><td>arch/x86</td><td>bool</td><td></td><td>
Initialize BIOS EBDA area early in romstage to allow bootloader to<br />
use this region for storing data which can be available across<br />
various stages. If user is selecting this option then its users<br />
responsibility to perform EBDA initialization call during romstage.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOTBLOCK_DEBUG_SPINLOOP</td><td>arch/x86</td><td>bool</td><td></td><td>
Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait<br />
for a JTAG debugger to break into the execution sequence.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP</td><td>arch/x86</td><td>bool</td><td></td><td>
Select this value to provide a routine to save the BIST and timestamp<br />
values.  The default code places the BIST value in MM0 and the<br />
timestamp value in MM2:MM1.  Another file is necessary when the CPU<br />
does not support the MMx register set.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VERSTAGE_DEBUG_SPINLOOP</td><td>arch/x86</td><td>bool</td><td></td><td>
Add a spin (JMP .) in assembly_entry.S during early verstage to wait<br />
for a JTAG debugger to break into the execution sequence.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ROMSTAGE_DEBUG_SPINLOOP</td><td>arch/x86</td><td>bool</td><td></td><td>
Add a spin (JMP .) in assembly_entry.S during early romstage to wait<br />
for a JTAG debugger to break into the execution sequence.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SKIP_MAX_REBOOT_CNT_CLEAR</td><td>arch/x86</td><td>bool</td><td>Do not clear reboot count after successful boot</td><td>
Do not clear the reboot count immediately after successful boot.<br />
Set to allow the payload to control normal/fallback image recovery.<br />
Note that it is the responsibility of the payload to reset the<br />
normal boot bit to 1 after each successsful boot.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ACPI_CPU_STRING</td><td>arch/x86</td><td>string</td><td></td><td>
Sets the ACPI name string in the processor scope as written by<br />
the acpigen function. Default is \_PR.CPxx. Note that you need<br />
the \ escape character in the string.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COLLECT_TIMESTAMPS_NO_TSC</td><td>arch/x86</td><td>bool</td><td></td><td>
Use a non-TSC platform-dependent source for timestamps.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COLLECT_TIMESTAMPS_TSC</td><td>arch/x86</td><td>bool</td><td></td><td>
Use the TSC as the timestamp source.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAGING_IN_CACHE_AS_RAM</td><td>arch/x86</td><td>bool</td><td></td><td>
Chipsets scan select this option to preallocate area in cache-as-ram<br />
for storing paging data structures. PAE paging is currently the<br />
only thing being supported.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NUM_CAR_PAGE_TABLE_PAGES</td><td>arch/x86</td><td>int</td><td></td><td>
The number of 4KiB pages that should be pre-allocated for page tables.<br />
<br />
</td></tr>

<tr bgcolor="#6699dd">
<td colspan=5>Menu: Devices</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_VGA_TEXT_FRAMEBUFFER</td><td>device</td><td>bool</td><td></td><td>
Selected by graphics drivers that support legacy VGA text mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_VBE_LINEAR_FRAMEBUFFER</td><td>device</td><td>bool</td><td></td><td>
Selected by graphics drivers that can set up a VBE linear-framebuffer<br />
mode.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_LINEAR_FRAMEBUFFER</td><td>device</td><td>bool</td><td></td><td>
Selected by graphics drivers that can set up a generic linear<br />
framebuffer.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_FSP_GOP</td><td>device</td><td>bool</td><td></td><td>
Selected by drivers that support to run a blob that implements<br />
the Graphics Output Protocol (GOP).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_HAS_NATIVE_VGA_INIT</td><td>device</td><td>bool</td><td></td><td>
Selected by mainboards / drivers that provide native graphics<br />
init within coreboot.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_FORCE_NATIVE_VGA_INIT</td><td>device</td><td>bool</td><td></td><td>
Selected by mainboards / chipsets whose graphics driver can't or<br />
shouldn't be disabled.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_HAS_LIBGFXINIT</td><td>device</td><td>bool</td><td></td><td>
Selected by mainboards that implement support for `libgfxinit`.<br />
Usually this requires a list of ports to be probed for displays.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_DO_NATIVE_VGA_INIT</td><td>device</td><td>bool</td><td>Use native graphics init</td><td>
Some mainboards, such as the Google Link, allow initializing the<br />
display without the need of a binary only VGA OPROM. Enabling this<br />
option may be faster, but also lacks flexibility in setting modes.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_USE_LIBGFXINIT</td><td>device</td><td>bool</td><td>Use libgfxinit</td><td>
Use the SPARK library `libgfxinit` for the native graphics<br />
initialization. This requires an Ada toolchain.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_ROM_RUN</td><td>device</td><td>bool</td><td>Run VGA Option ROMs</td><td>
Execute VGA Option ROMs in coreboot if found. This can be used<br />
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS<br />
payload.<br />
<br />
When using a SeaBIOS payload it runs all option ROMs with much<br />
more complete BIOS interrupt services available than coreboot,<br />
which some option ROMs require in order to function correctly.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RUN_FSP_GOP</td><td>device</td><td>bool</td><td>Run a GOP driver</td><td>
Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support<br />
to run a GOP blob. This option enables graphics initialization with<br />
such a blob.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NO_GFX_INIT</td><td>device</td><td>bool</td><td>None</td><td>
Select this to not perform any graphics initialization in<br />
coreboot. This is useful if the payload (e.g. SeaBIOS) can<br />
initialize graphics or if pre-boot graphics are not required.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>S3_VGA_ROM_RUN</td><td>device</td><td>bool</td><td>Re-run VGA Option ROMs on S3 resume</td><td>
Execute VGA Option ROMs in coreboot when resuming from S3 suspend.<br />
<br />
When using a SeaBIOS payload it runs all option ROMs with much<br />
more complete BIOS interrupt services available than coreboot,<br />
which some option ROMs require in order to function correctly.<br />
<br />
If unsure, say N when using SeaBIOS as payload, Y otherwise.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ALWAYS_LOAD_OPROM</td><td>device</td><td>bool</td><td></td><td>
Always load option ROMs if any are found. The decision to run<br />
the ROM is still determined at runtime, but the distinction<br />
between loading and not running comes into play for CHROMEOS.<br />
<br />
An example where this is required is that VBT (Video BIOS Tables)<br />
are needed for the kernel's display driver to know how a piece of<br />
hardware is configured to be used.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ALWAYS_RUN_OPROM</td><td>device</td><td>bool</td><td></td><td>
Always uncondtionally run the option regardless of other<br />
policies.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ON_DEVICE_ROM_LOAD</td><td>device</td><td>bool</td><td>Load Option ROMs on PCI devices</td><td>
Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot.<br />
<br />
If disabled, only Option ROMs stored in CBFS will be executed by<br />
coreboot. If you are concerned about security, you might want to<br />
disable this option, but it might leave your system in a state of<br />
degraded functionality.<br />
<br />
When using a SeaBIOS payload it runs all option ROMs with much<br />
more complete BIOS interrupt services available than coreboot,<br />
which some option ROMs require in order to function correctly.<br />
<br />
If unsure, say N when using SeaBIOS as payload, Y otherwise.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCI_OPTION_ROM_RUN_REALMODE</td><td>device</td><td>bool</td><td>Native mode</td><td>
If you select this option, PCI Option ROMs will be executed<br />
natively on the CPU in real mode. No CPU emulation is involved,<br />
so this is the fastest, but also the least secure option.<br />
(only works on x86/x64 systems)<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCI_OPTION_ROM_RUN_YABEL</td><td>device</td><td>bool</td><td>Secure mode</td><td>
If you select this option, the x86emu CPU emulator will be used to<br />
execute PCI Option ROMs.<br />
<br />
This option prevents Option ROMs from doing dirty tricks with the<br />
system (such as installing SMM modules or hypervisors), but it is<br />
also significantly slower than the native Option ROM initialization<br />
method.<br />
<br />
This is the default choice for non-x86 systems.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>YABEL_PCI_ACCESS_OTHER_DEVICES</td><td>device</td><td>bool</td><td>Allow Option ROMs to access other devices</td><td>
Per default, YABEL only allows Option ROMs to access the PCI device<br />
that they are associated with. However, this causes trouble for some<br />
onboard graphics chips whose Option ROM needs to reconfigure the<br />
north bridge.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG</td><td>device</td><td>bool</td><td>Fake success on writing other device's config space</td><td>
By default, YABEL aborts when the Option ROM tries to write to other<br />
devices' config spaces. With this option enabled, the write doesn't<br />
follow through, but the Option ROM is allowed to go on.<br />
This can create issues such as hanging Option ROMs (if it depends on<br />
that other register changing to the written value), so test for<br />
impact before using this option.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>YABEL_VIRTMEM_LOCATION</td><td>device</td><td>hex</td><td>Location of YABEL's virtual memory</td><td>
YABEL requires 1MB memory for its CPU emulation. This memory is<br />
normally located at 16MB.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>YABEL_DIRECTHW</td><td>device</td><td>bool</td><td>Direct hardware access</td><td>
YABEL consists of two parts: It uses x86emu for the CPU emulation and<br />
additionally provides a PC system emulation that filters bad device<br />
and memory access (such as PCI config space access to other devices<br />
than the initialized one).<br />
<br />
When choosing this option, x86emu will pass through all hardware<br />
accesses to memory and I/O devices to the underlying memory and I/O<br />
addresses. While this option prevents Option ROMs from doing dirty<br />
tricks with the CPU (such as installing SMM modules or hypervisors),<br />
they can still access all devices in the system.<br />
Enable this option for a good compromise between security and speed.<br />
<br />
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: Display</td></tr>
<tr bgcolor="#eeeeee">
<td>FRAMEBUFFER_SET_VESA_MODE</td><td>device</td><td>bool</td><td>Set framebuffer graphics resolution</td><td>
Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FRAMEBUFFER_SET_VESA_MODE</td><td>device</td><td>bool</td><td>framebuffer graphics resolution</td><td>
This option sets the resolution used for the coreboot framebuffer (and<br />
bootsplash screen).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOTSPLASH</td><td>device</td><td>bool</td><td>Show graphical bootsplash</td><td>
This option shows a graphical bootsplash screen. The graphics are<br />
loaded from the CBFS file bootsplash.jpg.<br />
<br />
You can either specify the location and file name of the<br />
image in the 'General' section or add it manually to CBFS, using,<br />
for example, cbfstool.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_TEXT_FRAMEBUFFER</td><td>device</td><td>bool</td><td>Legacy VGA text mode</td><td>
If this option is enabled, coreboot will initialize graphics in<br />
legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set,<br />
switch to text mode before handing control to a payload.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBE_LINEAR_FRAMEBUFFER</td><td>device</td><td>bool</td><td>VESA framebuffer</td><td>
This option keeps the framebuffer mode set after coreboot finishes<br />
execution. If this option is enabled, coreboot will pass a<br />
framebuffer entry in its coreboot table and the payload will need a<br />
compatible driver.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GENERIC_LINEAR_FRAMEBUFFER</td><td>device</td><td>bool</td><td>Linear \"high-resolution\" framebuffer</td><td>
This option enables a high-resolution, linear framebuffer. If this<br />
option is enabled, coreboot will pass a framebuffer entry in its<br />
coreboot table and the payload will need a compatible driver.<br />
<br />
</td></tr>

<tr bgcolor="#eeeeee">
<td>PCIEXP_COMMON_CLOCK</td><td>device</td><td>bool</td><td>Enable PCIe Common Clock</td><td>
Detect and enable Common Clock on PCIe links.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCIEXP_ASPM</td><td>device</td><td>bool</td><td>Enable PCIe ASPM</td><td>
Detect and enable ASPM (Active State Power Management) on PCIe links.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCIEXP_CLK_PM</td><td>device</td><td>bool</td><td>Enable PCIe Clock Power Management</td><td>
Detect and enable Clock Power Management on PCIe.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PCIEXP_L1_SUB_STATE</td><td>device</td><td>bool</td><td>Enable PCIe ASPM L1 SubState</td><td>
Detect and enable ASPM on PCIe links.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EARLY_PCI_BRIDGE</td><td>device</td><td>bool</td><td>Early PCI bridge</td><td>
While coreboot is executing code from ROM, the coreboot resource<br />
allocator has not been running yet. Hence PCI devices living behind<br />
a bridge are not yet visible to the system.<br />
<br />
This option enables static configuration for a single pre-defined<br />
PCI bridge function on bus 0.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SUBSYSTEM_VENDOR_ID</td><td>device</td><td>hex</td><td>Override PCI Subsystem Vendor ID</td><td>
This config option will override the devicetree settings for<br />
PCI Subsystem Vendor ID.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SUBSYSTEM_DEVICE_ID</td><td>device</td><td>hex</td><td>Override PCI Subsystem Device ID</td><td>
This config option will override the devicetree settings for<br />
PCI Subsystem Device ID.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS</td><td>device</td><td>bool</td><td>Add a VGA BIOS image</td><td>
Select this option if you have a VGA BIOS image that you would<br />
like to add to your ROM.<br />
<br />
You will be able to specify the location and file name of the<br />
image later.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_FILE</td><td>device</td><td>string</td><td>VGA BIOS path and filename</td><td>
The path and filename of the file to use as VGA BIOS.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA_BIOS_ID</td><td>device</td><td>string</td><td>VGA device PCI IDs</td><td>
The comma-separated PCI vendor and device ID that would associate<br />
your VGA BIOS to your video card.<br />
<br />
Example: 1106,3230<br />
<br />
In the above example 1106 is the PCI vendor ID (in hex, but without<br />
the "0x" prefix) and 3230 specifies the PCI device ID of the<br />
video card (also in hex, without "0x" prefix).<br />
<br />
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEL_GMA_HAVE_VBT</td><td>device</td><td>bool</td><td></td><td>
Select this in the mainboard Kconfig to indicate the board has<br />
a data.vbt file.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEL_GMA_ADD_VBT</td><td>device</td><td>bool</td><td>Add a Video Bios Table (VBT) binary to CBFS</td><td>
Add a VBT data file to CBFS. The VBT describes the integrated<br />
GPU and connections, and is needed by the GOP driver integrated into<br />
FSP and the OS driver in order to initialize the display.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEL_GMA_VBT_FILE</td><td>device</td><td>string</td><td>VBT binary path and filename</td><td>
The path and filename of the VBT binary.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SOFTWARE_I2C</td><td>device</td><td>bool</td><td>Enable I2C controller emulation in software</td><td>
This config option will enable code to override the i2c_transfer<br />
routine with a (simple) software emulation of the protocol. This may<br />
be useful for debugging or on platforms where a driver for the real<br />
I2C controller is not (yet) available. The platform code needs to<br />
provide bindings to manually toggle I2C lines.<br />
<br />
</td></tr>

<tr bgcolor="#6699dd">
<td colspan=5>Menu: Generic Drivers</td></tr>
<tr bgcolor="#eeeeee">
<td>UART_OVERRIDE_INPUT_CLOCK_DIVIDER</td><td>drivers/uart</td><td>boolean</td><td></td><td>
Set to "y" when the platform overrides the uart_input_clock_divider<br />
routine.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UART_OVERRIDE_REFCLK</td><td>drivers/uart</td><td>boolean</td><td></td><td>
Set to "y" when the platform overrides the uart_platform_refclk<br />
routine.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_UART_OXPCIE</td><td>drivers/uart</td><td>bool</td><td>Oxford OXPCIe952</td><td>
Support for Oxford OXPCIe952 serial port PCIe cards.<br />
Currently only devices with the vendor ID 0x1415 and device ID<br />
0xc158 or 0xc11b will work.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UART_USE_REFCLK_AS_INPUT_CLOCK</td><td>drivers/uart</td><td>bool</td><td></td><td>
Use uart_platform_refclk to specify the input clock value.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UART_PCI_ADDR</td><td>drivers/uart</td><td>hex</td><td>UART's PCI bus, device, function address</td><td>
Specify zero if the UART is connected to another bus type.<br />
For PCI based UARTs, build the value as:<br />
* 1 &lt;&lt; 31 - Valid bit, PCI UART in use<br />
* Bus &lt;&lt; 20<br />
* Device &lt;&lt; 15<br />
* Function &lt;&lt; 12<br />
<br />
</td></tr>
# Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USBDEBUG</td><td>drivers/usb</td><td>bool</td><td>USB 2.0 EHCI debug dongle support</td><td>
This option allows you to use a so-called USB EHCI Debug device<br />
(such as the Ajays NET20DC, AMIDebug RX, or a system using the<br />
Linux "EHCI Debug Device gadget" driver found in recent kernel)<br />
to retrieve the coreboot debug messages (instead, or in addition<br />
to, a serial port).<br />
<br />
This feature is NOT supported on all chipsets in coreboot!<br />
<br />
It also requires a USB2 controller which supports the EHCI<br />
Debug Port capability.<br />
<br />
See https://www.coreboot.org/EHCI_Debug_Port for an up-to-date list<br />
of supported controllers.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USBDEBUG_IN_ROMSTAGE</td><td>drivers/usb</td><td>bool</td><td>Enable early (pre-RAM) usbdebug</td><td>
Configuring USB controllers in system-agent binary may cause<br />
problems to usbdebug. Disabling this option delays usbdebug to<br />
be setup on entry to ramstage.<br />
<br />
If unsure, say Y.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USBDEBUG_HCD_INDEX</td><td>drivers/usb</td><td>int</td><td>Index for EHCI controller to use with usbdebug</td><td>
Some boards have multiple EHCI controllers with possibly only<br />
one having the Debug Port capability on an external USB port.<br />
<br />
Mapping of this index to PCI device functions is southbridge<br />
specific and mainboard level Kconfig should already provide<br />
a working default value here.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USBDEBUG_DEFAULT_PORT</td><td>drivers/usb</td><td>int</td><td>Default USB port to use as Debug Port</td><td>
Selects which physical USB port usbdebug dongle is connected to.<br />
Setting of 0 means to scan possible ports starting from 1.<br />
<br />
Intel platforms have hardwired the debug port location and this<br />
setting makes no difference there.<br />
<br />
Hence, if you select the correct port here, you can speed up<br />
your boot time. Which USB port number refers to which actual<br />
port on your mainboard (potentially also USB pin headers on<br />
your mainboard) is highly board-specific, and you'll likely<br />
have to find out by trial-and-error.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USBDEBUG_DONGLE_STD</td><td>drivers/usb</td><td>bool</td><td>USB gadget driver or Net20DC</td><td>
Net20DC, BeagleBone Black, Raspberry Pi Zero W<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USBDEBUG_DONGLE_BEAGLEBONE</td><td>drivers/usb</td><td>bool</td><td>BeagleBone</td><td>
Use this to configure the USB hub on BeagleBone board.<br />
Do NOT select this for the BeagleBone Black.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USBDEBUG_DONGLE_FTDI_FT232H</td><td>drivers/usb</td><td>bool</td><td>FTDI FT232H UART</td><td>
Use this with FT232H usb-to-uart. Configuration is hard-coded<br />
to use 8n1, no flow control.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USBDEBUG_DONGLE_FTDI_FT232H_BAUD</td><td>drivers/usb</td><td>int</td><td>FTDI FT232H baud rate</td><td>
Select baud rate for FT232H in the range 733..12,000,000. Make<br />
sure that your receiving side supports the same setting and your<br />
connection works with it. Multiples of 115,200 seem to be a good<br />
choice, and EHCI debug usually can't saturate more than 576,000.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COMMON_CBFS_SPI_WRAPPER</td><td>drivers/spi</td><td>bool</td><td></td><td>
Use common wrapper to interface CBFS to SPI bootrom.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your chipset driver needs to store certain<br />
data in the SPI flash.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOT_DEVICE_SPI_FLASH_BUS</td><td>drivers/spi</td><td>int</td><td></td><td>
Which SPI bus the boot device is connected to.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOT_DEVICE_SPI_FLASH_RW_NOMMAP</td><td>drivers/spi</td><td>bool</td><td></td><td>
Provide common implementation of the RW boot device that<br />
doesn't provide mmap() operations.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY</td><td>drivers/spi</td><td>bool</td><td></td><td>
Include the common implementation in all stages, including the<br />
early ones.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_SMM</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if you want SPI flash support in SMM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_NO_FAST_READ</td><td>drivers/spi</td><td>bool</td><td>Disable Fast Read command</td><td>
Select this option if your setup requires to avoid "fast read"s<br />
from the SPI flash parts.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_ADESTO</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your chipset driver needs to store certain<br />
data in the SPI flash and your SPI flash is made by Adesto Technologies.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_AMIC</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your chipset driver needs to store certain<br />
data in the SPI flash and your SPI flash is made by AMIC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_ATMEL</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your chipset driver needs to store certain<br />
data in the SPI flash and your SPI flash is made by Atmel.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_EON</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your chipset driver needs to store certain<br />
data in the SPI flash and your SPI flash is made by EON.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_GIGADEVICE</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your chipset driver needs to store certain<br />
data in the SPI flash and your SPI flash is made by Gigadevice.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_MACRONIX</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your chipset driver needs to store certain<br />
data in the SPI flash and your SPI flash is made by Macronix.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_SPANSION</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your chipset driver needs to store certain<br />
data in the SPI flash and your SPI flash is made by Spansion.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_SST</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your chipset driver needs to store certain<br />
data in the SPI flash and your SPI flash is made by SST.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_STMICRO</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your chipset driver needs to store certain<br />
data in the SPI flash and your SPI flash is made by ST MICRO.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_WINBOND</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your chipset driver needs to store certain<br />
data in the SPI flash and your SPI flash is made by Winbond.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B</td><td>drivers/spi</td><td>bool</td><td></td><td>
Select this option if your SPI flash supports the fast read dual-<br />
output command (opcode 0x3b) where the opcode and address are sent<br />
to the chip on MOSI and data is received on both MOSI and MISO.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_FLASH_HAS_VOLATILE_GROUP</td><td>drivers/spi</td><td>bool</td><td></td><td>
Allows chipset to group write/erase operations under a single volatile<br />
group.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ELOG</td><td>drivers/elog</td><td>bool</td><td>Support for flash based event log</td><td>
Enable support for flash based event logging.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ELOG_CBMEM</td><td>drivers/elog</td><td>bool</td><td>Store a copy of ELOG in CBMEM</td><td>
This option will have ELOG store a copy of the flash event log<br />
in a CBMEM region and export that address in SMBIOS to the OS.<br />
This is useful if the ELOG location is not in memory mapped flash,<br />
but it means that events added at runtime via the SMI handler<br />
will not be reflected in the CBMEM copy of the log.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ELOG_GSMI</td><td>drivers/elog</td><td>bool</td><td>SMI interface to write and clear event log</td><td>
This interface is compatible with the linux kernel driver<br />
available with CONFIG_GOOGLE_GSMI and can be used to write<br />
kernel reset/shutdown messages to the event log.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ELOG_BOOT_COUNT</td><td>drivers/elog</td><td>bool</td><td>Maintain a monotonic boot number in CMOS</td><td>
Store a monotonic boot number in CMOS and provide an interface<br />
to read the current value and increment the counter.  This boot<br />
counter will be logged as part of the System Boot event.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ELOG_BOOT_COUNT_CMOS_OFFSET</td><td>drivers/elog</td><td>int</td><td>Offset in CMOS to store the boot count</td><td>
This value must be greater than 16 bytes so as not to interfere<br />
with the standard RTC region.  Requires 8 bytes.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>REALTEK_8168_RESET</td><td>drivers/net</td><td>bool</td><td></td><td>
This forces a realtek 10ec:8168 card to reset to ensure power state<br />
is correct at boot.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>REALTEK_8168_MACADDRESS</td><td>drivers/net</td><td>string</td><td>Realtek rt8168 mac address</td><td>
This is a string to set the mac address on a Realtek rt8168 card.<br />
It must be in the form  of "xx:xx:xx:xx:xx:xx", where x is a<br />
hexadecimal number for it to be valid. Failing to do so will<br />
result in the default macaddress being used.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RT8168_SET_LED_MODE</td><td>drivers/net</td><td>bool</td><td></td><td>
This is to set a customized LED mode to distinguish 10/100/1000<br />
link and speed status with limited LEDs avaiable on a board.<br />
Please refer to RTL811x datasheet section 7.2 Customizable LED<br />
Configuration for details. With this flag enabled, the<br />
customized_leds variable will be read from devicetree setting.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>DIGITIZER_AUTODETECT</td><td>drivers/lenovo</td><td>bool</td><td>Autodetect</td><td>
The presence of digitizer is inferred from model number stored in<br />
AT24RF chip.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DIGITIZER_PRESENT</td><td>drivers/lenovo</td><td>bool</td><td>Present</td><td>
The digitizer is assumed to be present.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DIGITIZER_ABSENT</td><td>drivers/lenovo</td><td>bool</td><td>Absent</td><td>
The digitizer is assumed to be absent.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CACHE_MRC_SETTINGS</td><td>drivers/mrc_cache</td><td>bool</td><td></td><td>
Save cached MRC settings<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MRC_WRITE_NV_LATE</td><td>drivers/mrc_cache</td><td>bool</td><td></td><td>
MRC settings are normally written to NVRAM at BS_DEV_ENUMERATE-EXIT.<br />
If a platform requires MRC settings written to NVRAM later than<br />
normal, select this item.  This will cause the write to occur at<br />
BS_OS_RESUME_CHECK-ENTRY.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GIC</td><td>drivers/gic</td><td>None</td><td></td><td>
This option enables GIC support, the ARM generic interrupt controller.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVER_MAXIM_MAX77686</td><td>drivers/maxim/max77686</td><td>bool</td><td></td><td>
Maxim MAX77686 power regulator<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_SIL_3114</td><td>drivers/sil/3114</td><td>bool</td><td>Silicon Image SIL3114</td><td>
It sets PCI class to IDE compatible native mode, allowing<br />
SeaBIOS, FILO etc... to boot from it.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>PLATFORM_USES_FSP1_1</td><td>drivers/intel/fsp1_1</td><td>bool</td><td></td><td>
Does the code require the Intel Firmware Support Package?<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>drivers/intel/fsp1_1</td><td>(comment)</td><td></td><td>Intel FSP 1.1</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_FSP_BIN</td><td>drivers/intel/fsp1_1</td><td>bool</td><td>Should the Intel FSP binary be added to the flash image</td><td>
Select this option to add an Intel FSP binary to<br />
the resulting coreboot image.<br />
<br />
Note: Without this binary, coreboot builds relying on the FSP<br />
will not boot<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_MICROCODE_CBFS_LEN</td><td>drivers/intel/fsp1_1</td><td>hex</td><td>Microcode update region length in bytes</td><td>
The length in bytes of the microcode update region.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CPU_MICROCODE_CBFS_LOC</td><td>drivers/intel/fsp1_1</td><td>hex</td><td>Microcode update base address in CBFS</td><td>
The location (base address) in CBFS that contains the microcode update<br />
binary.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_FILE</td><td>drivers/intel/fsp1_1</td><td>string</td><td>Intel FSP binary path and filename</td><td>
The path and filename of the Intel FSP binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_LOC</td><td>drivers/intel/fsp1_1</td><td>hex</td><td>Intel FSP Binary location in CBFS</td><td>
The location in CBFS that the FSP is located. This must match the<br />
value that is set in the FSP binary.  If the FSP needs to be moved,<br />
rebase the FSP with Intel's BCT (tool).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DISPLAY_UPD_DATA</td><td>drivers/intel/fsp1_1</td><td>bool</td><td>Display UPD data</td><td>
Display the user specified product data prior to memory<br />
initialization.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_USES_UPD</td><td>drivers/intel/fsp1_1</td><td>bool</td><td></td><td>
If this FSP uses UPD/VPD data regions, select this in the chipset<br />
Kconfig.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_GENERIC_FSP_CAR_INC</td><td>drivers/intel/fsp1_1</td><td>bool</td><td></td><td>
The chipset can select this to use a generic cache_as_ram.inc file<br />
that should be good for all FSP based platforms.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEL_DDI</td><td>drivers/intel/gma</td><td>bool</td><td></td><td>
helper functions for intel DDI operations<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEL_GMA_SSC_ALTERNATE_REF</td><td>drivers/intel/gma</td><td>bool</td><td></td><td>
Set when the SSC reference clock for LVDS runs at a different fre-<br />
quency than the general display reference clock.<br />
<br />
To be set by northbridge or mainboard Kconfig.  For most platforms,<br />
there is no choice, i.e. for i945 and gm45 the SSC reference always<br />
differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz<br />
DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's<br />
the same frequency for SSC/non-SSC (120MHz).  The only, currently<br />
supported platform with a choice seems to be Pineview, where the<br />
alternative is 100MHz vs. the default 96MHz.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>INTEL_GMA_SWSMISCI</td><td>drivers/intel/gma</td><td>bool</td><td></td><td>
Select this option for Atom-based platforms which use the SWSMISCI<br />
register (0xe0) rather than the SWSCI register (0xe8).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GFX_GMA_ANALOG_I2C_PORT</td><td>drivers/intel/gma</td><td>string</td><td></td><td>
Boards with a DVI-I connector share the I2C pins for both analog and<br />
digital displays. In that case, the EDID for a VGA display has to be<br />
read over the I2C interface of the coupled digital port.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PLATFORM_USES_FSP2_0</td><td>drivers/intel/fsp2_0</td><td>bool</td><td></td><td>
Include FSP 2.0 wrappers and functionality<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ADD_FSP_BINARIES</td><td>drivers/intel/fsp2_0</td><td>bool</td><td>Add Intel FSP 2.0 binaries to CBFS</td><td>
Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not<br />
use the FSP-T binary and it is not added.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DISPLAY_FSP_CALLS_AND_STATUS</td><td>drivers/intel/fsp2_0</td><td>bool</td><td>Display the FSP calls and status</td><td>
Display the FSP call entry point and parameters prior to calling FSP<br />
and display the status upon return from FSP.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DISPLAY_FSP_HEADER</td><td>drivers/intel/fsp2_0</td><td>bool</td><td>Display the FSP header</td><td>
Display the FSP header information when the FSP file is found.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DISPLAY_HOBS</td><td>drivers/intel/fsp2_0</td><td>bool</td><td>Display the hand-off-blocks</td><td>
Display the FSP HOBs which are provided for coreboot.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DISPLAY_UPD_DATA</td><td>drivers/intel/fsp2_0</td><td>bool</td><td>Display UPD data</td><td>
Display the user specified product data prior to memory<br />
initialization.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_T_FILE</td><td>drivers/intel/fsp2_0</td><td>string</td><td>Intel FSP-T (temp ram init) binary path and filename</td><td>
The path and filename of the Intel FSP-M binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_M_FILE</td><td>drivers/intel/fsp2_0</td><td>string</td><td>Intel FSP-M (memory init) binary path and filename</td><td>
The path and filename of the Intel FSP-M binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_S_FILE</td><td>drivers/intel/fsp2_0</td><td>string</td><td>Intel FSP-S (silicon init) binary path and filename</td><td>
The path and filename of the Intel FSP-S binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_CAR</td><td>drivers/intel/fsp2_0</td><td>bool</td><td>Use FSP TempRamInit &amp; TempRamExit APIs</td><td>
Use FSP APIs to initialize &amp; Tear Down the Cache-As-Ram<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_M_XIP</td><td>drivers/intel/fsp2_0</td><td>bool</td><td>Is FSP-M XIP</td><td>
Select this value when FSP-M is execute-in-place.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VERIFY_HOBS</td><td>drivers/intel/fsp2_0</td><td>bool</td><td>Verify the FSP hand-off-blocks</td><td>
Verify that the HOBs required by coreboot are returned by FSP and<br />
that the resource HOBs are in the correct order and position.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DISPLAY_FSP_VERSION_INFO</td><td>drivers/intel/fsp2_0</td><td>bool</td><td>Display Firmware Ingredient Version Information</td><td>
Select this option to display Firmware version information.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS</td><td>drivers/intel/fsp2_0</td><td>bool</td><td></td><td>
This is selected by SoC or mainboard to supply their own<br />
concept of a version for the memory settings respectively.<br />
This allows deployed systems to bump their version number<br />
with the same FSP which will trigger a retrain of the memory.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_INTEL_WIFI</td><td>drivers/intel/wifi</td><td>bool</td><td>Support Intel PCI-e WiFi adapters</td><td>
When enabled, add identifiers in ACPI and SMBIOS tables to<br />
make OS drivers work with certain Intel PCI-e WiFi chipsets.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_SAR</td><td>drivers/intel/wifi</td><td>bool</td><td></td><td>
Enable it when wifi driver uses SAR configuration feature.<br />
VPD entry "wifi_sar" is required to support it.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DSAR_SET_NUM</td><td>drivers/intel/wifi</td><td>hex</td><td>Number of SAR sets when D-SAR is enabled</td><td>
There can be up to 3 optional SAR table sets.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>drivers/intel/fsp1_0</td><td>(comment)</td><td></td><td>Intel FSP</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_FSP_BIN</td><td>drivers/intel/fsp1_0</td><td>bool</td><td>Use Intel Firmware Support Package</td><td>
Select this option to add an Intel FSP binary to<br />
the resulting coreboot image.<br />
<br />
Note: Without this binary, coreboot builds relying on the FSP<br />
will not boot<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_FILE</td><td>drivers/intel/fsp1_0</td><td>string</td><td>Intel FSP binary path and filename</td><td>
The path and filename of the Intel FSP binary for this platform.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_LOC</td><td>drivers/intel/fsp1_0</td><td>hex</td><td>Intel FSP Binary location in CBFS</td><td>
The location in CBFS that the FSP is located. This must match the<br />
value that is set in the FSP binary.  If the FSP needs to be moved,<br />
rebase the FSP with Intel's BCT (tool).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_FSP_FAST_BOOT</td><td>drivers/intel/fsp1_0</td><td>bool</td><td>Enable Fast Boot</td><td>
Enabling this feature will force the MRC data to be cached in NV<br />
storage to be used for speeding up boot time on future reboots<br />
and/or power cycles.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ENABLE_MRC_CACHE</td><td>drivers/intel/fsp1_0</td><td>bool</td><td></td><td>
Enabling this feature will cause MRC data to be cached in NV storage.<br />
This can either be used for fast boot, or just because the FSP wants<br />
it to be saved.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MRC_CACHE_FMAP</td><td>drivers/intel/fsp1_0</td><td>bool</td><td>Use MRC Cache in FMAP</td><td>
Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.<br />
You must define a region in your FMAP named "RW_MRC_CACHE".<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MRC_CACHE_SIZE</td><td>drivers/intel/fsp1_0</td><td>hex</td><td>Fast Boot Data Cache Size</td><td>
This is the amount of space in NV storage that is reserved for the<br />
fast boot data cache storage.<br />
<br />
WARNING: Because this area will be erased and re-written, the size<br />
should be a full sector of the flash ROM chip and nothing else should<br />
be included in CBFS in any sector that the fast boot cache data is in.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VIRTUAL_ROM_SIZE</td><td>drivers/intel/fsp1_0</td><td>hex</td><td>Virtual ROM Size</td><td>
This is used to calculate the offset of the MRC data cache in NV<br />
Storage for fast boot.  If in doubt, leave this set to the default<br />
which sets the virtual size equal to the ROM size.<br />
<br />
Example: Cougar Canyon 2 has two 8 MB SPI ROMs.  When the SPI ROMs are<br />
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB.  When<br />
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM<br />
size is 16 MB.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USE_GENERIC_FSP_CAR_INC</td><td>drivers/intel/fsp1_0</td><td>bool</td><td></td><td>
The chipset can select this to use a generic cache_as_ram.inc file<br />
that should be good for all FSP based platforms.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FSP_USES_UPD</td><td>drivers/intel/fsp1_0</td><td>bool</td><td></td><td>
If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_INTEL_MIPI_CAMERA</td><td>drivers/intel/mipi_camera</td><td>bool</td><td></td><td>
MIPI CSI I2C camera SSDT generator. Generates SSDB and PWDB<br />
structures which are used by the Intel kernel drivers.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_EMULATION_QEMU_BOCHS</td><td>drivers/emulation/qemu</td><td>bool</td><td>bochs dispi interface vga driver</td><td>
VGA driver for qemu emulated vga cards supporting<br />
the bochs dispi interface.  This includes<br />
standard vga, vmware svga and qxl.  The default<br />
vga (cirrus) is *not* supported, so you have to<br />
pick another one explicitly via 'qemu -vga $card'.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>I2C_TPM</td><td>drivers/i2c/tpm</td><td>bool</td><td></td><td>
I2C TPM driver is enabled!<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_HAS_I2C_TPM_ATMEL</td><td>drivers/i2c/tpm</td><td>bool</td><td></td><td>
Board has an Atmel I2C TPM support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_HAS_I2C_TPM_CR50</td><td>drivers/i2c/tpm</td><td>bool</td><td></td><td>
Board has a Cr50 I2C TPM support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_HAS_I2C_TPM_GENERIC</td><td>drivers/i2c/tpm</td><td>bool</td><td></td><td>
Board has a generic I2C TPM support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_I2C_RTD2132</td><td>drivers/i2c/rtd2132</td><td>bool</td><td></td><td>
Enable support for Realtek RTD2132 DisplayPort to LVDS bridge chip.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_I2C_RX6110SA</td><td>drivers/i2c/rx6110sa</td><td>bool</td><td></td><td>
Enable support for external RTC chip RX6110 SA.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_I2C_PCA9538</td><td>drivers/i2c/pca9538</td><td>bool</td><td></td><td>
Enable support for I2C I/O expander PCA9538.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_I2C_DESIGNWARE</td><td>drivers/i2c/designware</td><td>bool</td><td></td><td>
Designware I2C support<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ</td><td>drivers/i2c/designware</td><td>int</td><td></td><td>
The i2c ip block's clock.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_TPM</td><td>drivers/spi/tpm</td><td>bool</td><td></td><td>
SPI TPM driver is enabled!<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_HAS_SPI_TPM_CR50</td><td>drivers/spi/tpm</td><td>bool</td><td></td><td>
Board has SPI TPM support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVER_XPOWERS_AXP209</td><td>drivers/xpowers/axp209</td><td>bool</td><td></td><td>
X-Powers AXP902 Power Management Unit<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVER_XPOWERS_AXP209_BOOTBLOCK</td><td>drivers/xpowers/axp209</td><td>bool</td><td></td><td>
Make AXP209 functionality available in he bootblock.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVER_TI_TPS65090</td><td>drivers/ti/tps65090</td><td>bool</td><td></td><td>
TI TPS65090<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVER_PARADE_PS8625</td><td>drivers/parade/ps8625</td><td>bool</td><td></td><td>
Parade ps8625 display port to lvds bridge<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVER_PARADE_PS8640</td><td>drivers/parade/ps8640</td><td>bool</td><td></td><td>
Parade PS8640 MIPI DSI to eDP Converter<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>LPC_TPM</td><td>drivers/pc80/tpm</td><td>bool</td><td></td><td>
LPC TPM driver is enabled!<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TPM_TIS_BASE_ADDRESS</td><td>drivers/pc80/tpm</td><td>hex</td><td></td><td>
This can be used to adjust the TPM memory base address.<br />
The default is specified by the TCG PC Client Specific TPM<br />
Interface Specification 1.2 and should not be changed unless<br />
the TPM being used does not conform to TPM TIS 1.2.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TPM_PIRQ</td><td>drivers/pc80/tpm</td><td>hex</td><td></td><td>
This can be used to specify a PIRQ to use instead of SERIRQ,<br />
which is needed for SPI TPM interrupt support on x86.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_HAS_LPC_TPM</td><td>drivers/pc80/tpm</td><td>bool</td><td></td><td>
Board has LPC TPM support<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>VGA</td><td>drivers/pc80/vga</td><td>bool</td><td></td><td>
Include legacy VGA support code.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>DRIVERS_PS2_KEYBOARD</td><td>drivers/pc80/pc</td><td>bool</td><td>PS/2 keyboard init</td><td>
Enable this option to initialize PS/2 keyboards found connected<br />
to the PS/2 port.<br />
<br />
Some payloads (eg, filo) require this option.  Other payloads<br />
(eg, GRUB 2, SeaBIOS, Linux) do not require it.<br />
Initializing a PS/2 keyboard can take several hundred milliseconds.<br />
<br />
If you know you will only use a payload which does not require<br />
this option, then you can say N here to speed up boot time.<br />
Otherwise say Y.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>STORAGE_ERASE</td><td>commonlib/storage</td><td>bool</td><td>Support SD/MMC erase operations</td><td>
Select to enable SD/MMC erase oprations<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>STORAGE_WRITE</td><td>commonlib/storage</td><td>bool</td><td>Support SD/MMC write operations</td><td>
Select to enable SD/MMC write oprations<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SD_MMC_DEBUG</td><td>commonlib/storage</td><td>bool</td><td>Debug SD/MMC card/devices operations</td><td>
Display overview of SD/MMC card/device operations<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SD_MMC_TRACE</td><td>commonlib/storage</td><td>bool</td><td>Trace SD/MMC card/device operations</td><td>
Display details of SD/MMC card/device operations<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SDHC_DEBUG</td><td>commonlib/storage</td><td>bool</td><td>Debug SD/MMC controller settings</td><td>
Display clock speed and bus width settings<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SDHC_TRACE</td><td>commonlib/storage</td><td>bool</td><td>Trace SD/MMC controller operations</td><td>
Display the operations performed by the SD/MMC controller<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SDHCI_ADMA_IN_BOOTBLOCK</td><td>commonlib/storage</td><td>bool</td><td></td><td>
Determine if bootblock is able to use ADMA2 or ADMA64<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SDHCI_ADMA_IN_ROMSTAGE</td><td>commonlib/storage</td><td>bool</td><td></td><td>
Determine if romstage is able to use ADMA2 or ADMA64<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SDHCI_ADMA_IN_VERSTAGE</td><td>commonlib/storage</td><td>bool</td><td></td><td>
Determine if verstage is able to use ADMA2 or ADMA64<br />
<br />
</td></tr>

<tr bgcolor="#6699dd">
<td colspan=5>Menu: Security</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: Verified Boot (vboot)</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT</td><td>security/vboot</td><td>bool</td><td>Verify firmware with vboot.</td><td>
Enabling VBOOT will use vboot to verify the components of the firmware<br />
(stages, payload, etc).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_VBNV_CMOS</td><td>security/vboot</td><td>bool</td><td></td><td>
VBNV is stored in CMOS<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_VBNV_OFFSET</td><td>security/vboot</td><td>hex</td><td></td><td>
CMOS offset for VbNv data. This value must match cmos.layout<br />
in the mainboard directory, minus 14 bytes for the RTC.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_VBNV_CMOS_BACKUP_TO_FLASH</td><td>security/vboot</td><td>bool</td><td></td><td>
Vboot non-volatile storage data will be backed up from CMOS to flash<br />
and restored from flash if the CMOS is invalid due to power loss.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_VBNV_EC</td><td>security/vboot</td><td>bool</td><td></td><td>
VBNV is stored in EC<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_VBNV_FLASH</td><td>security/vboot</td><td>bool</td><td></td><td>
VBNV is stored in flash storage<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_STARTS_IN_BOOTBLOCK</td><td>security/vboot</td><td>bool</td><td></td><td>
Firmware verification happens during the end of or right after the<br />
bootblock. This implies that a static VBOOT2_WORK() buffer must be<br />
allocated in memlayout.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_STARTS_IN_ROMSTAGE</td><td>security/vboot</td><td>bool</td><td></td><td>
Firmware verification happens during the end of romstage (after<br />
memory initialization). This implies that vboot working data is<br />
allocated in CBMEM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_MOCK_SECDATA</td><td>security/vboot</td><td>bool</td><td>Mock secdata for firmware verification</td><td>
Enabling VBOOT_MOCK_SECDATA will mock secdata for the firmware<br />
verification to avoid access to a secdata storage (typically TPM).<br />
All operations for a secdata storage will be successful. This option<br />
can be used during development when a TPM is not present or broken.<br />
THIS SHOULD NOT BE LEFT ON FOR PRODUCTION DEVICES.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_DISABLE_DEV_ON_RECOVERY</td><td>security/vboot</td><td>bool</td><td></td><td>
When this option is enabled, the Chrome OS device leaves the<br />
developer mode as soon as recovery request is detected. This is<br />
handy on embedded devices with limited input capabilities.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_SEPARATE_VERSTAGE</td><td>security/vboot</td><td>bool</td><td></td><td>
If this option is set, vboot verification runs in a standalone stage<br />
that is loaded from the bootblock and exits into romstage. If it is<br />
not set, the verification code is linked directly into the bootblock<br />
or the romstage and runs as part of that stage (cf. related options<br />
VBOOT_STARTS_IN_BOOTBLOCK/_ROMSTAGE and VBOOT_RETURN_FROM_VERSTAGE).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_RETURN_FROM_VERSTAGE</td><td>security/vboot</td><td>bool</td><td></td><td>
If this is set, the verstage returns back to the calling stage instead<br />
of exiting to the succeeding stage so that the verstage space can be<br />
reused by the succeeding stage. This is useful if a RAM space is too<br />
small to fit both the verstage and the succeeding stage.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT</td><td>security/vboot</td><td>bool</td><td></td><td>
This option ensures that the recovery request is not lost because of<br />
reboots caused after vboot verification is run. e.g. reboots caused by<br />
FSP components on Intel platforms.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_OPROM_MATTERS</td><td>security/vboot</td><td>bool</td><td></td><td>
Set this option to indicate to vboot that this platform will skip its<br />
display initialization on a normal (non-recovery, non-developer) boot.<br />
Vboot calls this "oprom matters" because on x86 devices this<br />
traditionally meant that the video option ROM will not be loaded, but<br />
it works functionally the same for other platforms that can skip their<br />
native display initialization code instead.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_HAS_REC_HASH_SPACE</td><td>security/vboot</td><td>bool</td><td></td><td>
Set this option to indicate to vboot that recovery data hash space<br />
is present in TPM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_EC_SOFTWARE_SYNC</td><td>security/vboot</td><td>bool</td><td>Enable EC software sync</td><td>
EC software sync is a mechanism where the AP helps the EC verify its<br />
firmware similar to how vboot verifies the main system firmware. This<br />
option selects whether vboot should support EC software sync.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_EC_SLOW_UPDATE</td><td>security/vboot</td><td>bool</td><td></td><td>
Whether the EC (or PD) is slow to update and needs to display a<br />
screen that informs the user the update is happening.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_EC_EFS</td><td>security/vboot</td><td>bool</td><td></td><td>
CrosEC can support EFS: Early Firmware Selection. If it's enabled,<br />
software sync need to also support it. This setting tells vboot to<br />
perform EFS software sync.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_PHYSICAL_DEV_SWITCH</td><td>security/vboot</td><td>bool</td><td></td><td>
Whether this platform has a physical developer switch. Note that this<br />
disables virtual dev switch functionality (through secdata). Operation<br />
where both a physical pin and the virtual switch get sampled is not<br />
supported by coreboot.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_PHYSICAL_REC_SWITCH</td><td>security/vboot</td><td>bool</td><td></td><td>
Whether this platform has a physical recovery switch.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_LID_SWITCH</td><td>security/vboot</td><td>bool</td><td></td><td>
Whether this platform has a lid switch. If it does, vboot will not<br />
decrement try counters for boot failures if the lid is closed.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_WIPEOUT_SUPPORTED</td><td>security/vboot</td><td>bool</td><td></td><td>
When this option is enabled, the firmware provides the ability to<br />
signal the application the need for factory reset (a.k.a. wipe<br />
out) of the device<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_FWID_MODEL</td><td>security/vboot</td><td>string</td><td>Firmware ID model</td><td>
This is the first part of the FWID written to various regions of a<br />
vboot firmware image to identify its version.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_FWID_VERSION</td><td>security/vboot</td><td>string</td><td>Firmware ID version</td><td>
This is the second part of the FWID written to various regions of a<br />
vboot firmware image to identify its version.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>VBOOT_NO_BOARD_SUPPORT</td><td>security/vboot</td><td>bool</td><td>Allow the use of vboot without board support</td><td>
Enable weak functions for get_write_protect_state and<br />
get_recovery_mode_switch in order to proceed with refactoring<br />
of the vboot2 code base. Later on this code is removed and replaced<br />
by interfaces.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RO_REGION_ONLY</td><td>security/vboot</td><td>string</td><td>Additional files that should not be copied to RW</td><td>
Add a space delimited list of filenames that should only be in the<br />
RO section.<br />
<br />
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: GBB configuration</td></tr>

<tr bgcolor="#6699dd">
<td colspan=5>Menu: Vboot Keys</td></tr>


<tr bgcolor="#eeeeee">
<td>POWER_OFF_ON_CR50_UPDATE</td><td>security/tpm/tss/vendor/cr50</td><td>bool</td><td></td><td>
Power off machine while waiting for CR50 update to take effect.<br />
<br />
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: Trusted Platform Module</td></tr>
<tr bgcolor="#eeeeee">
<td>USER_TPM1</td><td>security/tpm</td><td>bool</td><td>1.2</td><td>
Enable this option to enable TPM 1.0 - 1.2 support in coreboot.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>USER_TPM2</td><td>security/tpm</td><td>bool</td><td>2.0</td><td>
Enable this option to enable TPM 2.0 support in coreboot.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TPM_DEACTIVATE</td><td>security/tpm</td><td>bool</td><td>Deactivate TPM</td><td>
Deactivate TPM by issuing deactivate command.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_TPM</td><td>security/tpm</td><td>bool</td><td>Output verbose TPM debug messages</td><td>
This option enables additional TPM related debug messages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TPM_RDRESP_NEED_DELAY</td><td>security/tpm</td><td>bool</td><td>Enable Delay Workaround for TPM</td><td>
Certain TPMs seem to need some delay when reading response<br />
to work around a race-condition-related issue, possibly<br />
caused by ill-programmed TPM firmware.<br />
<br />
</td></tr>


<tr bgcolor="#eeeeee">
<td>ACPI_SATA_GENERATOR</td><td>acpi</td><td>bool</td><td></td><td>
Use ACPI SATA port generator.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ACPI_INTEL_HARDWARE_SLEEP_VALUES</td><td>acpi</td><td>bool</td><td></td><td>
Provide common definitions for Intel hardware PM1_CNT register sleep<br />
values.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ACPI_AMD_HARDWARE_SLEEP_VALUES</td><td>acpi</td><td>bool</td><td></td><td>
Provide common definitions for AMD hardware PM1_CNT register sleep<br />
values.<br />
<br />
</td></tr>
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOT_DEVICE_MEMORY_MAPPED</td><td>toplevel</td><td>bool</td><td></td><td>
Inform system if SPI is memory-mapped or not.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOT_DEVICE_SUPPORTS_WRITES</td><td>toplevel</td><td>bool</td><td></td><td>
Indicate that the platform has writable boot device<br />
support.<br />
<br />
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: Console</td></tr>
<tr bgcolor="#eeeeee">
<td>BOOTBLOCK_CONSOLE</td><td>console</td><td>bool</td><td>Enable early (bootblock) console output.</td><td>
Use console during the bootblock if supported<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>POSTCAR_CONSOLE</td><td>console</td><td>bool</td><td>Enable console output during postcar.</td><td>
Use console during the postcar if supported<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SQUELCH_EARLY_SMP</td><td>console</td><td>bool</td><td>Squelch AP CPUs from early console.</td><td>
When selected only the BSP CPU will output to early console.<br />
<br />
Console drivers have unpredictable behaviour if multiple threads<br />
attempt to share the same resources without a spinlock.<br />
<br />
If unsure, say Y.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL</td><td>console</td><td>bool</td><td>Serial port console output</td><td>
Send coreboot debug output to a serial port.<br />
<br />
The type of serial port driver selected based on your configuration is<br />
shown on the following menu line. Supporting multiple different types<br />
of UARTs in one build is not supported.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>console</td><td>(comment)</td><td></td><td>I/O mapped, 8250-compatible</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>console</td><td>(comment)</td><td></td><td>memory mapped, 8250-compatible</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>console</td><td>(comment)</td><td></td><td>device-specific UART</td></tr>
<tr bgcolor="#eeeeee">
<td>UART_FOR_CONSOLE</td><td>console</td><td>int</td><td>Index for UART port to use for console</td><td>
Select an I/O port to use for serial console:<br />
0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TTYS0_BASE</td><td>console</td><td>hex</td><td></td><td>
Map the COM port number to the respective I/O port.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>console</td><td>(comment)</td><td></td><td>Serial port base address = 0x3f8</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>console</td><td>(comment)</td><td></td><td>Serial port base address = 0x2f8</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>console</td><td>(comment)</td><td></td><td>Serial port base address = 0x3e8</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>console</td><td>(comment)</td><td></td><td>Serial port base address = 0x2e8</td></tr>
<tr bgcolor="#eeeeee">
<td>UART_OVERRIDE_BAUDRATE</td><td>console</td><td>boolean</td><td></td><td>
Set to "y" when the platform overrides the baudrate by providing<br />
a get_uart_baudrate routine.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_921600</td><td>console</td><td>bool</td><td>921600</td><td>
Set serial port Baud rate to 921600.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_460800</td><td>console</td><td>bool</td><td>460800</td><td>
Set serial port Baud rate to 460800.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_230400</td><td>console</td><td>bool</td><td>230400</td><td>
Set serial port Baud rate to 230400.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_115200</td><td>console</td><td>bool</td><td>115200</td><td>
Set serial port Baud rate to 115200.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_57600</td><td>console</td><td>bool</td><td>57600</td><td>
Set serial port Baud rate to 57600.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_38400</td><td>console</td><td>bool</td><td>38400</td><td>
Set serial port Baud rate to 38400.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_19200</td><td>console</td><td>bool</td><td>19200</td><td>
Set serial port Baud rate to 19200.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SERIAL_9600</td><td>console</td><td>bool</td><td>9600</td><td>
Set serial port Baud rate to 9600.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TTYS0_BAUD</td><td>console</td><td>int</td><td></td><td>
Map the Baud rates to an integer.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPKMODEM</td><td>console</td><td>bool</td><td>spkmodem (console on speaker) console output</td><td>
Send coreboot debug output through speaker<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_USB</td><td>console</td><td>bool</td><td>USB dongle console output</td><td>
Send coreboot debug output to USB.<br />
<br />
Configuration for USB hardware is under menu Generic Drivers.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ONBOARD_VGA_IS_PRIMARY</td><td>console</td><td>bool</td><td>Use onboard VGA as primary video device</td><td>
If not selected, the last adapter found will be used.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_NE2K</td><td>console</td><td>bool</td><td>Network console over NE2000 compatible Ethernet adapter</td><td>
Send coreboot debug output to a Ethernet console, it works<br />
same way as Linux netconsole, packets are received to UDP<br />
port 6666 on IP/MAC specified with options bellow.<br />
Use following netcat command: nc -u -l -p 6666<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_NE2K_DST_MAC</td><td>console</td><td>string</td><td>Destination MAC address of remote system</td><td>
Type in either MAC address of logging system or MAC address<br />
of the router.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_NE2K_DST_IP</td><td>console</td><td>string</td><td>Destination IP of logging system</td><td>
This is IP address of the system running for example<br />
netcat command to dump the packets.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_NE2K_SRC_IP</td><td>console</td><td>string</td><td>IP address of coreboot system</td><td>
This is the IP of the coreboot system<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_NE2K_IO_PORT</td><td>console</td><td>hex</td><td>NE2000 adapter fixed IO port address</td><td>
This is the IO port address for the IO port<br />
on the card, please select some non-conflicting region,<br />
32 bytes of IO spaces will be used (and align on 32 bytes<br />
boundary, qemu needs broader align)<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_CBMEM</td><td>console</td><td>bool</td><td>Send console output to a CBMEM buffer</td><td>
Enable this to save the console output in a CBMEM buffer. This would<br />
allow to see coreboot console output from Linux space.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_CBMEM_BUFFER_SIZE</td><td>console</td><td>hex</td><td>Room allocated for console output in CBMEM</td><td>
Space allocated for console output storage in CBMEM. The default<br />
value (128K or 0x20000 bytes) is large enough to accommodate<br />
even the BIOS_SPEW level.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_CBMEM_DUMP_TO_UART</td><td>console</td><td>bool</td><td>Dump CBMEM console on resets</td><td>
Enable this to have CBMEM console buffer contents dumped on the<br />
serial output in case serial console is disabled and the device<br />
resets itself while trying to boot the payload.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SPI_FLASH</td><td>console</td><td>bool</td><td>SPI Flash console output</td><td>
Send coreboot debug output to the SPI Flash in the FMAP CONSOLE area<br />
<br />
This option can cause premature wear on the SPI flash and should not<br />
be used as a normal means of debugging. It is only to be enabled and<br />
used when porting a new motherboard which has no other console<br />
available (no UART, no POST, no cbmem access(non bootable)). Since<br />
a non bootable machine will require the use of an external SPI Flash<br />
programmer, the developer can grab the console log at the same time.<br />
<br />
The flash console will not be erased on reboot, so once it is full,<br />
the flashconsole driver will stop writing to it. This is to avoid<br />
wear on the flash, and to avoid erasing sectors (which may freeze<br />
the SPI controller on skylake).<br />
<br />
The 'CONSOLE' area can be extracted from the FMAP with :<br />
cbfstool rom.bin read -r CONSOLE -f console.log<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_SPI_FLASH_BUFFER_SIZE</td><td>console</td><td>hex</td><td>Room allocated for console output in FMAP</td><td>
Space allocated for console output storage in FMAP. The default<br />
value (128K or 0x20000 bytes) is large enough to accommodate<br />
even the BIOS_SPEW level.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_QEMU_DEBUGCON</td><td>console</td><td>bool</td><td>QEMU debug console output</td><td>
Send coreboot debug output to QEMU's isa-debugcon device:<br />
<br />
qemu-system-x86_64 \<br />
-chardev file,id=debugcon,path=/dir/file.log \<br />
-device isa-debugcon,iobase=0x402,chardev=debugcon<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SPI_CONSOLE</td><td>console</td><td>bool</td><td>SPI debug console output</td><td>
Enable support for the debug console on the Dediprog EM100Pro.<br />
This is currently working only in ramstage due to how the spi<br />
drivers are written.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_OVERRIDE_LOGLEVEL</td><td>console</td><td>boolean</td><td></td><td>
Set to "y" when the platform overrides the loglevel by providing<br />
a get_console_loglevel routine.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEFAULT_CONSOLE_LOGLEVEL_8</td><td>console</td><td>bool</td><td>8: SPEW</td><td>
Way too many details.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEFAULT_CONSOLE_LOGLEVEL_7</td><td>console</td><td>bool</td><td>7: DEBUG</td><td>
Debug-level messages.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEFAULT_CONSOLE_LOGLEVEL_6</td><td>console</td><td>bool</td><td>6: INFO</td><td>
Informational messages.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEFAULT_CONSOLE_LOGLEVEL_5</td><td>console</td><td>bool</td><td>5: NOTICE</td><td>
Normal but significant conditions.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEFAULT_CONSOLE_LOGLEVEL_4</td><td>console</td><td>bool</td><td>4: WARNING</td><td>
Warning conditions.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEFAULT_CONSOLE_LOGLEVEL_3</td><td>console</td><td>bool</td><td>3: ERR</td><td>
Error conditions.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEFAULT_CONSOLE_LOGLEVEL_2</td><td>console</td><td>bool</td><td>2: CRIT</td><td>
Critical conditions.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEFAULT_CONSOLE_LOGLEVEL_1</td><td>console</td><td>bool</td><td>1: ALERT</td><td>
Action must be taken immediately.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEFAULT_CONSOLE_LOGLEVEL_0</td><td>console</td><td>bool</td><td>0: EMERG</td><td>
System is unusable.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEFAULT_CONSOLE_LOGLEVEL</td><td>console</td><td>int</td><td></td><td>
Map the log level config names to an integer.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CMOS_POST</td><td>console</td><td>bool</td><td>Store post codes in CMOS for debugging</td><td>
If enabled, coreboot will store post codes in CMOS and switch between<br />
two offsets on each boot so the last post code in the previous boot<br />
can be retrieved.  This uses 3 bytes of CMOS.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CMOS_POST_OFFSET</td><td>console</td><td>hex</td><td>Offset into CMOS to store POST codes</td><td>
If CMOS_POST is enabled then an offset into CMOS must be provided.<br />
If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value<br />
defined in the mainboard option table.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CMOS_POST_EXTRA</td><td>console</td><td>bool</td><td>Store extra logging info into CMOS</td><td>
This will enable extra logging of work that happens between post<br />
codes into CMOS for debug.  This uses an additional 8 bytes of CMOS.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CONSOLE_POST</td><td>console</td><td>bool</td><td>Show POST codes on the debug console</td><td>
If enabled, coreboot will additionally print POST codes (which are<br />
usually displayed using a so-called "POST card" ISA/PCI/PCI-E<br />
device) on the debug console.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>POST_IO</td><td>console</td><td>bool</td><td>Send POST codes to an IO port</td><td>
If enabled, POST codes will be written to an IO port.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>POST_IO_PORT</td><td>console</td><td>hex</td><td>IO port for POST codes</td><td>
POST codes on x86 are typically written to the LPC bus on port<br />
0x80. However, it may be desirable to change the port number<br />
depending on the presence of coprocessors/microcontrollers or if the<br />
platform does not support IO in the conventional x86 manner.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NO_EARLY_BOOTBLOCK_POSTCODES</td><td>console</td><td>hex</td><td></td><td>
Some chipsets require that the routing for the port 80h POST<br />
code be configured before any POST codes are sent out.<br />
This can be done in the boot block, but there are a couple of<br />
POST codes that go out before the chipset's bootblock initialization<br />
can happen.  This option suppresses those POST codes.<br />
<br />
</td></tr>

<tr bgcolor="#eeeeee">
<td>ACPI_HUGE_LOWMEM_BACKUP</td><td>toplevel</td><td>bool</td><td></td><td>
On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RESUME_PATH_SAME_AS_BOOT</td><td>toplevel</td><td>bool</td><td></td><td>
This option indicates that when a system resumes it takes the<br />
same path as a regular boot. e.g. an x86 system runs from the<br />
reset vector at 0xfffffff0 on both resume and warm/cold boot.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_HARD_RESET</td><td>toplevel</td><td>bool</td><td></td><td>
This variable specifies whether a given board has a hard_reset<br />
function, no matter if it's provided by board code or chipset code.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK</td><td>toplevel</td><td>bool</td><td></td><td>
This should be enabled on certain plaforms, such as the AMD<br />
SR565x, that cannot handle concurrent CBFS accesses from<br />
multiple APs during early startup.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_MONOTONIC_TIMER</td><td>toplevel</td><td>bool</td><td></td><td>
The board/chipset provides a monotonic timer.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GENERIC_UDELAY</td><td>toplevel</td><td>bool</td><td></td><td>
The board/chipset uses a generic udelay function utilizing the<br />
monotonic timer.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIMER_QUEUE</td><td>toplevel</td><td>bool</td><td></td><td>
Provide a timer queue for performing time-based callbacks.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COOP_MULTITASKING</td><td>toplevel</td><td>bool</td><td></td><td>
Cooperative multitasking allows callbacks to be multiplexed on the<br />
main thread of ramstage. With this enabled it allows for multiple<br />
execution paths to take place when they have udelay() calls within<br />
their code.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NUM_THREADS</td><td>toplevel</td><td>int</td><td></td><td>
How many execution threads to cooperatively multitask with.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_OPTION_TABLE</td><td>toplevel</td><td>bool</td><td></td><td>
This variable specifies whether a given board has a cmos.layout<br />
file containing NVRAM/CMOS bit definitions.<br />
It defaults to 'n' but can be selected in mainboard/*/Kconfig.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GFXUMA</td><td>toplevel</td><td>bool</td><td></td><td>
Enable Unified Memory Architecture for graphics.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_ACPI_TABLES</td><td>toplevel</td><td>bool</td><td></td><td>
This variable specifies whether a given board has ACPI table support.<br />
It is usually set in mainboard/*/Kconfig.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_MP_TABLE</td><td>toplevel</td><td>bool</td><td></td><td>
This variable specifies whether a given board has MP table support.<br />
It is usually set in mainboard/*/Kconfig.<br />
Whether or not the MP table is actually generated by coreboot<br />
is configurable by the user via GENERATE_MP_TABLE.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>HAVE_PIRQ_TABLE</td><td>toplevel</td><td>bool</td><td></td><td>
This variable specifies whether a given board has PIRQ table support.<br />
It is usually set in mainboard/*/Kconfig.<br />
Whether or not the PIRQ table is actually generated by coreboot<br />
is configurable by the user via GENERATE_PIRQ_TABLE.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAX_PIRQ_LINKS</td><td>toplevel</td><td>int</td><td></td><td>
This variable specifies the number of PIRQ interrupt links which are<br />
routable. On most chipsets, this is 4, INTA through INTD. Some<br />
chipsets offer more than four links, commonly up to INTH. They may<br />
also have a separate link for ATA or IOAPIC interrupts. When the PIRQ<br />
table specifies links greater than 4, pirq_route_irqs will not<br />
function properly, unless this variable is correctly set.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>ACPI_NHLT</td><td>toplevel</td><td>bool</td><td></td><td>
Build support for NHLT (non HD Audio) ACPI table generation.<br />
<br />
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: System tables</td></tr>
<tr bgcolor="#eeeeee">
<td>GENERATE_MP_TABLE</td><td>toplevel</td><td>bool</td><td>Generate an MP table</td><td>
Generate an MP table (conforming to the Intel MultiProcessor<br />
specification 1.4) for this board.<br />
<br />
If unsure, say Y.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GENERATE_PIRQ_TABLE</td><td>toplevel</td><td>bool</td><td>Generate a PIRQ table</td><td>
Generate a PIRQ table for this board.<br />
<br />
If unsure, say Y.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GENERATE_SMBIOS_TABLES</td><td>toplevel</td><td>bool</td><td>Generate SMBIOS tables</td><td>
Generate SMBIOS tables for this board.<br />
<br />
If unsure, say Y.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_SERIAL_NUMBER</td><td>toplevel</td><td>string</td><td>SMBIOS Serial Number</td><td>
The Serial Number to store in SMBIOS structures.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_VERSION</td><td>toplevel</td><td>string</td><td>SMBIOS Version Number</td><td>
The Version Number to store in SMBIOS structures.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_SMBIOS_MANUFACTURER</td><td>toplevel</td><td>string</td><td>SMBIOS Manufacturer</td><td>
Override the default Manufacturer stored in SMBIOS structures.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAINBOARD_SMBIOS_PRODUCT_NAME</td><td>toplevel</td><td>string</td><td>SMBIOS Product name</td><td>
Override the default Product name stored in SMBIOS structures.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SMBIOS_ENCLOSURE_TYPE</td><td>toplevel</td><td>hex</td><td></td><td>
System Enclosure or Chassis Types as defined in SMBIOS specification.<br />
The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) or<br />
SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set.<br />
<br />
</td></tr>

<tr bgcolor="#6699dd">
<td colspan=5>Menu: Payload</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_NONE</td><td>payloads</td><td>bool</td><td>None</td><td>
Select this option if you want to create an "empty" coreboot<br />
ROM image for a certain mainboard, i.e. a coreboot ROM image<br />
which does not yet contain a payload.<br />
<br />
For such an image to be useful, you have to use 'cbfstool'<br />
to add a payload to the ROM image later.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_ELF</td><td>payloads</td><td>bool</td><td>An ELF executable payload</td><td>
Select this option if you have a payload image (an ELF file)<br />
which coreboot should run as soon as the basic hardware<br />
initialization is completed.<br />
<br />
You will be able to specify the location and file name of the<br />
payload image later.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_BAYOU</td><td>payloads</td><td>bool</td><td>Bayou</td><td>
Select this option if you want to set bayou as your primary<br />
payload.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_FILO</td><td>payloads/external/FILO.name</td><td>bool</td><td>FILO</td><td>
Select this option if you want to build a coreboot image<br />
with a FILO payload. If you don't know what this is<br />
about, just leave it enabled.<br />
<br />
See https://coreboot.org/Payloads for more information.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_SEABIOS</td><td>payloads/external/SeaBIOS.name</td><td>bool</td><td>SeaBIOS</td><td>
Select this option if you want to build a coreboot image<br />
with a SeaBIOS payload. If you don't know what this is<br />
about, just leave it enabled.<br />
<br />
See https://coreboot.org/Payloads for more information.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_TIANOCORE</td><td>payloads/external/tianocore.name</td><td>bool</td><td>Tianocore coreboot payload package</td><td>
Select this option if you want to build a coreboot image<br />
with a Tianocore payload. If you don't know what this is<br />
about, just leave it enabled.<br />
<br />
See https://coreboot.org/Payloads for more information.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_UBOOT</td><td>payloads/external/U-Boot.name</td><td>bool</td><td>U-Boot (Experimental)</td><td>
Select this option if you want to build a coreboot image<br />
with a U-Boot payload.<br />
<br />
See https://coreboot.org/Payloads and U-Boot's documentation<br />
at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86<br />
for more information.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_DEPTHCHARGE</td><td>payloads/external/depthcharge.name</td><td>bool</td><td>Depthcharge</td><td>
Select this option if you want to build a coreboot image<br />
with a depthcharge payload.<br />
<br />
See https://coreboot.org/Payloads for more information.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_LINUX</td><td>payloads/external/linux.name</td><td>bool</td><td>A Linux payload</td><td>
Select this option if you have a Linux bzImage which coreboot<br />
should run as soon as the basic hardware initialization<br />
is completed.<br />
<br />
You will be able to specify the location and file name of the<br />
payload image later.<br />
<br />
</td></tr>
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_GRUB2</td><td>payloads/external/GRUB2.name</td><td>bool</td><td>GRUB2</td><td>
Select this option if you want to build a coreboot image<br />
with a GRUB2 payload. If you don't know what this is<br />
about, just leave it enabled.<br />
<br />
See https://coreboot.org/Payloads for more information.<br />
<br />
</td></tr>
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FILO_STABLE</td><td>payloads/external/FILO</td><td>bool</td><td>0.6.0</td><td>
Stable FILO version<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FILO_MASTER</td><td>payloads/external/FILO</td><td>bool</td><td>HEAD</td><td>
Newest FILO version<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SEABIOS_STABLE</td><td>payloads/external/SeaBIOS</td><td>bool</td><td>1.11.1</td><td>
Stable SeaBIOS version<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SEABIOS_MASTER</td><td>payloads/external/SeaBIOS</td><td>bool</td><td>master</td><td>
Newest SeaBIOS version<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SEABIOS_REVISION</td><td>payloads/external/SeaBIOS</td><td>bool</td><td>git revision</td><td>
Select this option if you have a specific commit or branch<br />
that you want to use as the revision from which to<br />
build SeaBIOS.<br />
<br />
You will be able to specify the name of a branch or a commit id<br />
later.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SEABIOS_REVISION_ID</td><td>payloads/external/SeaBIOS</td><td>string</td><td>Insert a commit's SHA-1 or a branch name</td><td>
The commit's SHA-1 or branch name of the revision to use.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SEABIOS_PS2_TIMEOUT</td><td>payloads/external/SeaBIOS</td><td>int</td><td>PS/2 keyboard controller initialization timeout (milliseconds)</td><td>
Some PS/2 keyboard controllers don't respond to commands immediately<br />
after powering on. This specifies how long SeaBIOS will wait for the<br />
keyboard controller to become ready before giving up.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SEABIOS_THREAD_OPTIONROMS</td><td>payloads/external/SeaBIOS</td><td>bool</td><td>Hardware init during option ROM execution</td><td>
Allow hardware init to run in parallel with optionrom execution.<br />
<br />
This can reduce boot time, but can cause some timing<br />
variations during option ROM code execution. It is not<br />
known if all option ROMs will behave properly with this option.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SEABIOS_VGA_COREBOOT</td><td>payloads/external/SeaBIOS</td><td>bool</td><td>Include generated option rom that implements legacy VGA BIOS compatibility</td><td>
coreboot can initialize the GPU of some mainboards.<br />
<br />
After initializing the GPU, the information about it can be passed to the payload.<br />
Provide an option rom that implements this legacy VGA BIOS compatibility requirement.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_CONFIGFILE</td><td>payloads/external/SeaBIOS</td><td>string</td><td>SeaBIOS config file</td><td>
This option allows a platform to set Kconfig options for a basic<br />
SeaBIOS payload.  In general, if the option is used, the default<br />
would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SEABIOS_BOOTORDER_FILE</td><td>payloads/external/SeaBIOS</td><td>string</td><td>SeaBIOS bootorder file</td><td>
Add a SeaBIOS bootorder file.  From the wiki:<br />
"The bootorder file may be used to configure the boot up order. The file<br />
should be ASCII text and contain one line per boot method. The description<br />
of each boot method follows an Open Firmware device path format. SeaBIOS<br />
will attempt to boot from each item in the file - first line of the file<br />
first."<br />
<br />
See: https://www.coreboot.org/SeaBIOS#Configuring_boot_order<br />
<br />
If used, a typical value would be:<br />
$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>SEABIOS_DEBUG_LEVEL</td><td>payloads/external/SeaBIOS</td><td>int</td><td>SeaBIOS debug level (verbosity)</td><td>
The higher the number, the more verbose SeaBIOS will be. See the table<br />
below for the current values corresponding to various items as of SeaBIOS<br />
version 1.10.1. Set this value to -1 to use SeaBIOS' default.<br />
<br />
Output at various SeaBIOS log levels:<br />
level 0  - Logging disabled<br />
level 1  - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM<br />
level 2  - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h<br />
level 3  - bootsplash, initializations, SeaBIOS VGA BIOS interrupts<br />
level 4  - bios tables, more optionrom<br />
level 5  - Extra bootsplash, more XHCI<br />
level 6  - ATA commands, extra optionrom<br />
level 7  - extra ps2 commands, more OHCI &amp; EHCI<br />
level 8  - extra malloc info, more AHCI<br />
level 9  - interrupts 15h, 16h, 1ah, APM, PCI, SMIs, PCIBIOS,<br />
USB-HID commands, SDcard commands, Floppy commands<br />
level 10 - interrupt 13h (Drives other than floppy)<br />
level 20 - interrupt 10h (Display)<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>payloads/external/SeaBIOS</td><td>(comment)</td><td></td><td>Using default SeaBIOS log level</td></tr>
<tr bgcolor="#eeeeee">
<td></td><td>payloads/external/SeaBIOS</td><td>(comment)</td><td></td><td>SeaBIOS logging disabled</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_FILE</td><td>payloads/external/tianocore</td><td>string</td><td>Tianocore binary</td><td>
The result of a corebootPkg build<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_FILE</td><td>payloads/external/tianocore</td><td>string</td><td>Tianocore version</td><td>
Select which version of Tianocore to build (default is to build stable)<br />
stable: a version of Tianocore that builds without any errors<br />
master: most recent version from upstream Tianocore repository<br />
revision: use specific commit or branch to build Tianocore (specified by user)<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIANOCORE_STABLE</td><td>payloads/external/tianocore</td><td>bool</td><td>stable</td><td>
Select this option to build the stable tianocore version<br />
i.e. a version of Tianocore that builds without any errors<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIANOCORE_MASTER</td><td>payloads/external/tianocore</td><td>bool</td><td>master</td><td>
Select this option to build the master tianocore version<br />
i.e. most recent version from upstream Tianocore repository<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIANOCORE_REVISION</td><td>payloads/external/tianocore</td><td>bool</td><td>git revision</td><td>
Select this option if you have a specific commit or branch<br />
that you want to use as the revision from which to<br />
build Tianocore.<br />
<br />
You will be able to specify the name of a branch or a commit id<br />
later.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIANOCORE_REVISION_ID</td><td>payloads/external/tianocore</td><td>string</td><td>Insert a commit's SHA-1 or a branch name</td><td>
The commit's SHA-1 or branch name of the revision to use.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIANOCORE_REVISION_ID</td><td>payloads/external/tianocore</td><td>string</td><td>Target architecture</td><td>
The Tianocore coreboot Payload Package binary can be<br />
built for either only IA32 or both X64 and IA32 architectures.<br />
Select which architecture(s) to build for; default is to build<br />
for both X64 and IA32.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIANOCORE_TARGET_IA32</td><td>payloads/external/tianocore</td><td>bool</td><td>IA32</td><td>
By selecting this option, the target architecture will be built<br />
for only IA32.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIANOCORE_TARGET_X64</td><td>payloads/external/tianocore</td><td>bool</td><td>X64</td><td>
By selecting this option, the target architecture will be built<br />
for X64 and IA32.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIANOCORE_TARGET_X64</td><td>payloads/external/tianocore</td><td>bool</td><td>Tianocore build</td><td>
Select whether to generate a debug or release build for<br />
Tianocore; default is to generate a release build.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIANOCORE_DEBUG</td><td>payloads/external/tianocore</td><td>bool</td><td>Generate Tianocore debug build</td><td>
Generate a debug build.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TIANOCORE_RELEASE</td><td>payloads/external/tianocore</td><td>bool</td><td>Generate Tianocore release build</td><td>
Generate a release build.<br />
<br />
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: PXE Options</td></tr>
<tr bgcolor="#eeeeee">
<td>PXE_ROM</td><td>payloads/external/iPXE</td><td>bool</td><td>Add an existing PXE ROM image</td><td>
Select this option if you have a PXE ROM image that you would<br />
like to add to your ROM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>BUILD_IPXE</td><td>payloads/external/iPXE</td><td>bool</td><td>Build and add an iPXE ROM</td><td>
Select this option to fetch and build a ROM from the iPXE project.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IPXE_STABLE</td><td>payloads/external/iPXE</td><td>bool</td><td>2017.3</td><td>
iPXE uses a rolling release with no stable version, for<br />
reproducibility, use the last commit of a given month as the<br />
'stable' version.<br />
This is iPXE from the end of March, 2017.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>IPXE_MASTER</td><td>payloads/external/iPXE</td><td>bool</td><td>master</td><td>
Newest iPXE version.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PXE_ROM_FILE</td><td>payloads/external/iPXE</td><td>string</td><td>PXE ROM filename</td><td>
The path and filename of the file to use as PXE ROM.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PXE_ROM_ID</td><td>payloads/external/iPXE</td><td>string</td><td>network card PCI IDs</td><td>
The comma-separated PCI vendor and device ID that would associate<br />
your PXE ROM to your network card.<br />
<br />
Example: 10ec,8168<br />
<br />
In the above example 10ec is the PCI vendor ID (in hex, but without<br />
the "0x" prefix) and 8168 specifies the PCI device ID of the<br />
network card (also in hex, without "0x" prefix).<br />
<br />
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.<br />
<br />
</td></tr>

<tr bgcolor="#eeeeee">
<td>UBOOT_STABLE</td><td>payloads/external/U-Boot</td><td>bool</td><td>v2016.1</td><td>
Stable U-Boot version<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>UBOOT_MASTER</td><td>payloads/external/U-Boot</td><td>bool</td><td>master</td><td>
Newest U-Boot version<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_CONFIGFILE</td><td>payloads/external/U-Boot</td><td>string</td><td>U-Boot config file</td><td>
This option allows a platform to set Kconfig options for a basic<br />
U-Boot payload.  In general, if the option is used, the default<br />
would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_uboot"<br />
for a config stored in the coreboot mainboard directory, or<br />
"$(project_dir)/configs/coreboot-x86_defconfig" to use a config<br />
from the U-Boot config directory<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEPTHCHARGE_STABLE</td><td>payloads/external/depthcharge</td><td>bool</td><td>stable</td><td>
Latest stable version.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEPTHCHARGE_MASTER</td><td>payloads/external/depthcharge</td><td>bool</td><td>master</td><td>
Newest Depthcharge version.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEPTHCHARGE_REVISION</td><td>payloads/external/depthcharge</td><td>bool</td><td>git revision</td><td>
Select this option if you have a specific commit or branch that<br />
you want to use as the revision from which to build Depthcharge.<br />
<br />
You will be able to specify the name of a branch or a commit SHA<br />
later.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEPTHCHARGE_REVISION_ID</td><td>payloads/external/depthcharge</td><td>string</td><td>Insert a commit's SHA-1 or a branch name</td><td>
The commit's SHA-1 or branch name of the revision to use.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LP_DEFCONFIG_OVERRIDE</td><td>payloads/external/depthcharge</td><td>bool</td><td>Use default libpayload config</td><td>
The Depthcharge makefile looks for a file config.&lt;boardname&gt; in the<br />
libpayload/configs directory.  Say Y here to use the file defconfig<br />
instead.  This is can be a convenience for development purposes, or<br />
if the defaults in defconfig are sufficient for your system.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_FILE</td><td>payloads/external/linux</td><td>string</td><td>Linux path and filename</td><td>
The path and filename of the bzImage kernel to use as payload.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LINUX_COMMAND_LINE</td><td>payloads/external/linux</td><td>string</td><td>Linux command line</td><td>
A command line to add to the Linux kernel.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>LINUX_INITRD</td><td>payloads/external/linux</td><td>string</td><td>Linux initrd</td><td>
An initrd image to add to the Linux kernel.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GRUB2_STABLE</td><td>payloads/external/GRUB2</td><td>bool</td><td>2.02</td><td>
Stable GRUB2 version<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GRUB2_MASTER</td><td>payloads/external/GRUB2</td><td>bool</td><td>HEAD</td><td>
Newest GRUB2 version<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GRUB2_REVISION</td><td>payloads/external/GRUB2</td><td>bool</td><td>git revision</td><td>
Select this option if you have a specific commit or branch<br />
that you want to use as the revision from which to<br />
build GRUB2.<br />
<br />
You will be able to specify the name of a branch or a commit id<br />
later.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GRUB2_REVISION_ID</td><td>payloads/external/GRUB2</td><td>string</td><td>Insert a commit's SHA-1 or a branch name</td><td>
The commit's SHA-1 or branch name of the revision to use.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GRUB2_EXTRA_MODULES</td><td>payloads/external/GRUB2</td><td>string</td><td>Extra modules to include in GRUB image</td><td>
Space-separated list of additional modules to include. Few common<br />
ones:<br />
* bsd for *BSD<br />
* png/jpg for PNG/JPG images<br />
* gfxmenu for graphical menus (you'll need a theme as well)<br />
* gfxterm_background for setting background<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GRUB2_INCLUDE_RUNTIME_CONFIG_FILE</td><td>payloads/external/GRUB2</td><td>bool</td><td>Include GRUB2 runtime config file into ROM image</td><td>
The GRUB2 payload reads its runtime configuration file from etc/grub.cfg<br />
stored in the CBFS on the flash ROM chip. Without that, it’ll just drop<br />
into a rescue shell.<br />
<br />
This configuration may need to be coreboot specific.<br />
<br />
Select this option, if you want to include the GRUB2 runtime<br />
configuration file into CBFS as `etc/grub.cfg` automatically.<br />
<br />
You will be able to specify the path of the configuration file later.<br />
<br />
Without this option you would need to add this file manually with<br />
build/cbfstool build/coreboot.rom add -f grub.cfg -n etc/grub.cfg -t raw<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GRUB2_RUNTIME_CONFIG_FILE</td><td>payloads/external/GRUB2</td><td>string</td><td>Path of grub.cfg</td><td>
The path of the GRUB2 runtime configuration file to be added to CBFS.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_FILE</td><td>payloads</td><td>string</td><td>Payload path and filename</td><td>
The path and filename of the ELF executable file to use as payload.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_FILE</td><td>payloads</td><td>string</td><td>Payload compression algorithm</td><td>
Choose the compression algorithm for the chosen payloads.<br />
You can choose between LZMA and LZ4.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COMPRESSED_PAYLOAD_LZMA</td><td>payloads</td><td>bool</td><td>Use LZMA compression for payloads</td><td>
In order to reduce the size payloads take up in the ROM chip<br />
coreboot can compress them using the LZMA algorithm.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COMPRESSED_PAYLOAD_LZ4</td><td>payloads</td><td>bool</td><td>Use LZ4 compression for payloads</td><td>
In order to reduce the size payloads take up in the ROM chip<br />
coreboot can compress them using the LZ4 algorithm.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_OPTIONS</td><td>payloads</td><td>string</td><td></td><td>
Additional cbfstool options for the payload<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>PAYLOAD_IS_FLAT_BINARY</td><td>payloads</td><td>string</td><td></td><td>
Add the payload to cbfs as a flat binary type instead of as an<br />
elf payload<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>COMPRESS_SECONDARY_PAYLOAD</td><td>payloads</td><td>bool</td><td>Use LZMA compression for secondary payloads</td><td>
In order to reduce the size secondary payloads take up in the<br />
ROM chip they can be compressed using the LZMA algorithm.<br />
<br />
</td></tr>
<tr bgcolor="#6699dd">
<td colspan=5>Menu: Secondary Payloads</td></tr>
<tr bgcolor="#eeeeee">
<td>COREINFO_SECONDARY_PAYLOAD</td><td>payloads</td><td>bool</td><td>Load coreinfo as a secondary payload</td><td>
coreinfo can be loaded as a secondary payload under SeaBIOS, GRUB,<br />
or any other payload that can load additional payloads.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MEMTEST_SECONDARY_PAYLOAD</td><td>payloads</td><td>bool</td><td>Load Memtest86+ as a secondary payload</td><td>
Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB,<br />
or any other payload that can load additional payloads.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MEMTEST_STABLE</td><td>payloads</td><td>bool</td><td>Stable</td><td>
Stable Memtest86+ version.<br />
<br />
For reproducible builds, this option must be selected.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MEMTEST_MASTER</td><td>payloads</td><td>bool</td><td>Master</td><td>
Newest Memtest86+ version.<br />
<br />
This option will fetch the newest version of the Memtest86+ code,<br />
updating as new changes are committed.  This makes the build<br />
non-reproducible, as it can fetch different code each time.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NVRAMCUI_SECONDARY_PAYLOAD</td><td>payloads</td><td>bool</td><td>Load nvramcui as a secondary payload</td><td>
nvramcui can be loaded as a secondary payload under SeaBIOS, GRUB,<br />
or any other payload that can load additional payloads.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TINT_SECONDARY_PAYLOAD</td><td>payloads</td><td>bool</td><td>Load tint as a secondary payload</td><td>
tint can be loaded as a secondary payload under SeaBIOS, GRUB,<br />
or any other payload that can load additional payloads.<br />
<br />
</td></tr>


<tr bgcolor="#6699dd">
<td colspan=5>Menu: Debugging</td></tr>
<tr bgcolor="#eeeeee">
<td>GDB_STUB</td><td>toplevel</td><td>bool</td><td>GDB debugging support</td><td>
If enabled, you will be able to set breakpoints for gdb debugging.<br />
See src/arch/x86/lib/c_start.S for details.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GDB_WAIT</td><td>toplevel</td><td>bool</td><td>Wait for a GDB connection in the ramstage</td><td>
If enabled, coreboot will wait for a GDB connection in the ramstage.<br />
<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FATAL_ASSERTS</td><td>toplevel</td><td>bool</td><td>Halt when hitting a BUG() or assertion error</td><td>
If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_CBFS</td><td>toplevel</td><td>bool</td><td>Output verbose CBFS debug messages</td><td>
This option enables additional CBFS related debug messages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_RAM_SETUP</td><td>toplevel</td><td>bool</td><td>Output verbose RAM init debug messages</td><td>
This option enables additional RAM init related debug messages.<br />
It is recommended to enable this when debugging issues on your<br />
board which might be RAM init related.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_CAR</td><td>toplevel</td><td>bool</td><td>Output verbose Cache-as-RAM debug messages</td><td>
This option enables additional CAR related debug messages.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_PIRQ</td><td>toplevel</td><td>bool</td><td>Check PIRQ table consistency</td><td>
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_SMBUS</td><td>toplevel</td><td>bool</td><td>Output verbose SMBus debug messages</td><td>
This option enables additional SMBus (and SPD) debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_SMI</td><td>toplevel</td><td>bool</td><td>Output verbose SMI debug messages</td><td>
This option enables additional SMI related debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_SMM_RELOCATION</td><td>toplevel</td><td>bool</td><td>Debug SMM relocation code</td><td>
This option enables additional SMM handler relocation related<br />
debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_MALLOC</td><td>toplevel</td><td>bool</td><td>Output verbose malloc debug messages</td><td>
This option enables additional malloc related debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_ACPI</td><td>toplevel</td><td>bool</td><td>Output verbose ACPI debug messages</td><td>
This option enables additional ACPI related debug messages.<br />
<br />
Note: This option will slightly increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>REALMODE_DEBUG</td><td>toplevel</td><td>bool</td><td>Enable debug messages for option ROM execution</td><td>
This option enables additional x86emu related debug messages.<br />
<br />
Note: This option will increase the time to emulate a ROM.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG</td><td>toplevel</td><td>bool</td><td>Output verbose x86emu debug messages</td><td>
This option enables additional x86emu related debug messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_JMP</td><td>toplevel</td><td>bool</td><td>Trace JMP/RETF</td><td>
Print information about JMP and RETF opcodes from x86emu.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_TRACE</td><td>toplevel</td><td>bool</td><td>Trace all opcodes</td><td>
Print _all_ opcodes that are executed by x86emu.<br />
<br />
WARNING: This will produce a LOT of output and take a long time.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_PNP</td><td>toplevel</td><td>bool</td><td>Log Plug&amp;Play accesses</td><td>
Print Plug And Play accesses made by option ROMs.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_DISK</td><td>toplevel</td><td>bool</td><td>Log Disk I/O</td><td>
Print Disk I/O related messages.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_PMM</td><td>toplevel</td><td>bool</td><td>Log PMM</td><td>
Print messages related to POST Memory Manager (PMM).<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_VBE</td><td>toplevel</td><td>bool</td><td>Debug VESA BIOS Extensions</td><td>
Print messages related to VESA BIOS Extension (VBE) functions.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_INT10</td><td>toplevel</td><td>bool</td><td>Redirect INT10 output to console</td><td>
Let INT10 (i.e. character output) calls print messages to debug output.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_INTERRUPTS</td><td>toplevel</td><td>bool</td><td>Log intXX calls</td><td>
Print messages related to interrupt handling.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_CHECK_VMEM_ACCESS</td><td>toplevel</td><td>bool</td><td>Log special memory accesses</td><td>
Print messages related to accesses to certain areas of the virtual<br />
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_MEM</td><td>toplevel</td><td>bool</td><td>Log all memory accesses</td><td>
Print memory accesses made by option ROM.<br />
Note: This also includes accesses to fetch instructions.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_IO</td><td>toplevel</td><td>bool</td><td>Log IO accesses</td><td>
Print I/O accesses made by option ROM.<br />
<br />
Note: This option will increase the size of the coreboot image.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>X86EMU_DEBUG_TIMINGS</td><td>toplevel</td><td>bool</td><td>Output timing information</td><td>
Print timing information needed by i915tool.<br />
<br />
If unsure, say N.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_SPI_FLASH</td><td>toplevel</td><td>bool</td><td>Output verbose SPI flash debug messages</td><td>
This option enables additional SPI flash related debug messages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_USBDEBUG</td><td>toplevel</td><td>bool</td><td>Output verbose USB 2.0 EHCI debug dongle messages</td><td>
This option enables additional USB 2.0 debug dongle related messages.<br />
<br />
Select this to debug the connection of usbdebug dongle. Note that<br />
you need some other working console to receive the messages.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_INTEL_ME</td><td>toplevel</td><td>bool</td><td>Verbose logging for Intel Management Engine</td><td>
Enable verbose logging for Intel Management Engine driver that<br />
is present on Intel 6-series chipsets.<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>TRACE</td><td>toplevel</td><td>bool</td><td>Trace function calls</td><td>
If enabled, every function will print information to console once<br />
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)<br />
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP<br />
of calling function. Please note some printk related functions<br />
are omitted from trace to have good looking console dumps.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_COVERAGE</td><td>toplevel</td><td>bool</td><td>Debug code coverage</td><td>
If enabled, the code coverage hooks in coreboot will output some<br />
information about the coverage data that is dumped.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_BOOT_STATE</td><td>toplevel</td><td>bool</td><td>Debug boot state machine</td><td>
Control debugging of the boot state machine.  When selected displays<br />
the state boundaries in ramstage.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DEBUG_ADA_CODE</td><td>toplevel</td><td>bool</td><td>Compile debug code in Ada sources</td><td>
Add the compiler switch `-gnata` to compile code guarded by<br />
`pragma Debug`.<br />
<br />
</td></tr>

<tr bgcolor="#eeeeee">
<td>NO_EDID_FILL_FB</td><td>lib</td><td>bool</td><td></td><td>
Don't include default fill_lb_framebuffer() implementation. Select<br />
this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides<br />
its own fill_lb_framebuffer() implementation.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RAMSTAGE_ADA</td><td>lib</td><td>bool</td><td></td><td>
Selected by features that use Ada code in ramstage.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RAMSTAGE_LIBHWBASE</td><td>lib</td><td>bool</td><td></td><td>
Selected by features that require `libhwbase` in ramstage.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>FLATTENED_DEVICE_TREE</td><td>lib</td><td>bool</td><td></td><td>
Selected by features that require to parse and manipulate a flattened<br />
devicetree in ramstage.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>POWER_BUTTON_DEFAULT_ENABLE</td><td>toplevel</td><td>bool</td><td></td><td>
Select when the board has a power button which can optionally be<br />
disabled by the user.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>POWER_BUTTON_DEFAULT_DISABLE</td><td>toplevel</td><td>bool</td><td></td><td>
Select when the board has a power button which can optionally be<br />
enabled by the user, e.g. when the board ships with a jumper over<br />
the power switch contacts.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>POWER_BUTTON_FORCE_ENABLE</td><td>toplevel</td><td>bool</td><td></td><td>
Select when the board requires that the power button is always<br />
enabled.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>POWER_BUTTON_FORCE_DISABLE</td><td>toplevel</td><td>bool</td><td></td><td>
Select when the board requires that the power button is always<br />
disabled, e.g. when it has been hardwired to ground.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>POWER_BUTTON_IS_OPTIONAL</td><td>toplevel</td><td>bool</td><td></td><td>
Internal option that controls ENABLE_POWER_BUTTON visibility.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>REG_SCRIPT</td><td>toplevel</td><td>bool</td><td></td><td>
Internal option that controls whether we compile in register scripts.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAX_REBOOT_CNT</td><td>toplevel</td><td>int</td><td></td><td>
Internal option that sets the maximum number of bootblock executions allowed<br />
with the normal image enabled before assuming the normal image is defective<br />
and switching to the fallback image.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CREATE_BOARD_CHECKLIST</td><td>toplevel</td><td>bool</td><td></td><td>
When selected, creates a webpage showing the implementation status for<br />
the board.  Routines highlighted in green are complete, yellow are<br />
optional and red are required and must be implemented.  A table is<br />
produced for each stage of the boot process except the bootblock.  The<br />
red items may be used as an implementation checklist for the board.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>MAKE_CHECKLIST_PUBLIC</td><td>toplevel</td><td>bool</td><td></td><td>
When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html<br />
is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board<br />
directory.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>CHECKLIST_DATA_FILE_LOCATION</td><td>toplevel</td><td>string</td><td></td><td>
Location of the &lt;stage&gt;_complete.dat and &lt;stage&gt;_optional.dat files<br />
that are consumed during checklist processing.  &lt;stage&gt;_complete.dat<br />
contains the symbols that are expected to be in the resulting image.<br />
&lt;stage&gt;_optional.dat is a subset of &lt;stage&gt;_complete.dat and contains<br />
a list of weak symbols which the resulting image may consume.  Other<br />
symbols contained only in &lt;stage&gt;_complete.dat will be flagged as<br />
required and not implemented if a weak implementation is found in the<br />
resulting image.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NO_XIP_EARLY_STAGES</td><td>toplevel</td><td>bool</td><td></td><td>
Identify if early stages are eXecute-In-Place(XIP).<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>EARLY_CBMEM_LIST</td><td>toplevel</td><td>bool</td><td></td><td>
Enable display of CBMEM during romstage and postcar.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>RELOCATABLE_MODULES</td><td>toplevel</td><td>bool</td><td></td><td>
If RELOCATABLE_MODULES is selected then support is enabled for<br />
building relocatable modules in the RAM stage. Those modules can be<br />
loaded anywhere and all the relocations are handled automatically.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>NO_STAGE_CACHE</td><td>toplevel</td><td>bool</td><td></td><td>
Do not save any component in stage cache for resume path. On resume,<br />
all components would be read back from CBFS again.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GENERIC_GPIO_LIB</td><td>toplevel</td><td>bool</td><td></td><td>
If enabled, compile the generic GPIO library. A "generic" GPIO<br />
implies configurability usually found on SoCs, particularly the<br />
ability to control internal pull resistors.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>GENERIC_SPD_BIN</td><td>toplevel</td><td>bool</td><td></td><td>
If enabled, add support for adding spd.hex files in cbfs as spd.bin<br />
and locating it runtime to load SPD. Additionally provide provision to<br />
fetch SPD over SMBus.<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DIMM_MAX</td><td>toplevel</td><td>int</td><td></td><td>
Total number of memory DIMM slots available on motherboard.<br />
It is multiplication of number of channel to number of DIMMs per<br />
channel<br />
<br />
</td></tr>
<tr bgcolor="#eeeeee">
<td>DIMM_SPD_SIZE</td><td>toplevel</td><td>int</td><td></td><td>
Total SPD size that will be used for DIMM.<br />
Ex: DDR3 256, DDR4 512.<br />
<br />
</td></tr>
</table>