This is an automatically generated list of '''coreboot compile-time options'''. Last update: 4.13-1263-gd4b58259c4

Option	Source	Format	Short Description	Description
Menu: General setup
LOCALVERSION	toplevel	string	Local version string	Append an extra string to the end of the coreboot version. This can be useful if, for instance, you want to append the respective board's hostname or some other identifying string to the coreboot version number, so that you can easily distinguish boot logs of different boards from each other.
CONFIGURABLE_CBFS_PREFIX	toplevel	bool		Select this to prompt to use to configure the prefix for cbfs files.
CBFS_PREFIX	toplevel	string	CBFS prefix to use	Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative.
CBFS_PREFIX	toplevel	string	Compiler to use	This option allows you to select the compiler used for building coreboot. You must build the coreboot crosscompiler for the board that you have selected. To build all the GCC crosscompilers (takes a LONG time), run: make crossgcc For help on individual architectures, run the command: make help_toolchain
COMPILER_GCC	toplevel	bool	GCC	Use the GNU Compiler Collection (GCC) to build coreboot. For details see http://gcc.gnu.org.
COMPILER_LLVM_CLANG	toplevel	bool	LLVM/clang (TESTING ONLY - Not currently working)	Use LLVM/clang to build coreboot. To use this, you must build the coreboot version of the clang compiler. Run the command make clang Note that this option is not currently working correctly and should really only be selected if you're trying to work on getting clang operational. For details see http://clang.llvm.org.
ANY_TOOLCHAIN	toplevel	bool	Allow building with any toolchain	Many toolchains break when building coreboot since it uses quite unusual linker features. Unless developers explicitely request it, we'll have to assume that they use their distro compiler by mistake. Make sure that using patched compilers is a conscious decision.
CCACHE	toplevel	bool	Use ccache to speed up (re)compilation	Enables the use of ccache for faster builds. Requires the ccache utility in your system $PATH. For details see https://ccache.samba.org.
FMD_GENPARSER	toplevel	bool	Generate flashmap descriptor parser using flex and bison	Enable this option if you are working on the flashmap descriptor parser and made changes to fmd_scanner.l or fmd_parser.y. Otherwise, say N to use the provided pregenerated scanner/parser.
UTIL_GENPARSER	toplevel	bool	Generate SCONFIG & BINCFG parser using flex and bison	Enable this option if you are working on the sconfig device tree parser or bincfg and made changes to the .l or .y files. Otherwise, say N to use the provided pregenerated scanner/parser.
USE_OPTION_TABLE	toplevel	bool	Use CMOS for configuration values	Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard-coded values.
STATIC_OPTION_TABLE	toplevel	bool	Load default configuration values into CMOS on each boot	Enable this option to reset "CMOS" NVRAM values to default on every boot. Use this if you want the NVRAM configuration to never be modified from its default values.
COMPRESS_RAMSTAGE	toplevel	bool	Compress ramstage with LZMA	Compress ramstage to save memory in the flash image.
COMPRESS_PRERAM_STAGES	toplevel	bool	Compress romstage and verstage with LZ4	Compress romstage and (if it exists) verstage with LZ4 to save flash space and speed up boot, since the time for reading the image from SPI (and in the vboot case verifying it) is usually much greater than the time spent decompressing. Doesn't work for XIP stages (assume all ARCH_X86 for now) for obvious reasons.
COMPRESS_BOOTBLOCK	toplevel	bool		This option can be used to compress the bootblock with LZ4 and attach a small self-decompression stub to its front. This can drastically reduce boot time on platforms where the bootblock is loaded over a very slow connection and bootblock size trumps all other factors for speed. Since using this option usually requires changes to the SoC memlayout and possibly extra support code, it should not be user-selectable. (There's no real point in offering this to the user anyway... if it works and saves boot time, you would always want it.)
INCLUDE_CONFIG_FILE	toplevel	bool	Include the coreboot .config file into the ROM image	Include the .config file that was used to compile coreboot in the (CBFS) ROM image. This is useful if you want to know which options were used to build a specific coreboot.rom image. Saying Y here will increase the image size by 2-3KB. You can use the following command to easily list the options: grep -a CONFIG_ coreboot.rom Alternatively, you can also use cbfstool to print the image contents (including the raw 'config' item we're looking for). Example: $ cbfstool coreboot.rom print coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, offset 0x0 Alignment: 64 bytes Name Offset Type Size cmos_layout.bin 0x0 CMOS layout 1159 fallback/romstage 0x4c0 stage 339756 fallback/ramstage 0x53440 stage 186664 fallback/payload 0x80dc0 payload 51526 config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440
COLLECT_TIMESTAMPS	toplevel	bool	Create a table of timestamps collected during boot	Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process.
TIMESTAMPS_ON_CONSOLE	toplevel	bool	Print the timestamp values on the console	Print the timestamps to the debug console if enabled at level info.
USE_BLOBS	toplevel	bool	Allow use of binary-only repository	This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. This flag ensures that a "Free" option remains available for users.
USE_AMD_BLOBS	toplevel	bool	Allow AMD blobs repository (with license agreement)	This draws in the amd_blobs repository, which contains binary files distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares, etc. Selecting this item to download or clone the repo implies your agreement to the AMD license agreement. A copy of the license text may be reviewed by reading Documentation/soc/amd/amdblobs_license.md, and your copy of the license is present in the repo once downloaded. Note that for some products, omitting PSP, SMU images, or other items may result in a nonbooting coreboot.rom.
USE_QC_BLOBS	toplevel	bool	Allow QC blobs repository (selecting this agrees to the license!)	This draws in the qc_blobs repository, which contains binary files distributed by Qualcomm that are required to build firmware for certain Qualcomm SoCs (including QcLib, QC-SEC, qtiseclib and QUP firmware). If you say Y here you are implicitly agreeing to the Qualcomm license agreement which can be found at: https://review.coreboot.org/cgit/qc_blobs.git/tree/LICENSE *************************************************** PLEASE MAKE SURE YOU READ AND AGREE TO ALL TERMS IN ABOVE LICENSE AGREEMENT BEFORE SELECTING THIS OPTION! *************************************************** Not selecting this option means certain Qualcomm SoCs and related mainboards cannot be built and will be hidden from the "Mainboards" section.
COVERAGE	toplevel	bool	Code coverage support	Add code coverage support for coreboot. This will store code coverage information in CBMEM for extraction from user space. If unsure, say N.
UBSAN	toplevel	bool	Undefined behavior sanitizer support	Instrument the code with checks for undefined behavior. If unsure, say N because it adds a small performance penalty and may abort on code that happens to work in spite of the UB.
ASAN_IN_ROMSTAGE	toplevel	bool		Enable address sanitizer in romstage for platform.
ASAN_IN_RAMSTAGE	toplevel	bool		Enable address sanitizer in ramstage for platform.
ASAN	toplevel	bool	Address sanitizer support	Enable address sanitizer - runtime memory debugger, designed to find out-of-bounds accesses and use-after-scope bugs. This feature consumes up to 1/8 of available memory and brings about ~1.5x performance slowdown. If unsure, say N.
	toplevel	(comment)		Before using this feature, make sure that
	toplevel	(comment)		asan_shadow_offset_callback patch is applied to GCC.
NO_STAGE_CACHE	toplevel	bool	Disabled	Do not save any component in stage cache for resume path. On resume, all components would be read back from CBFS again.
TSEG_STAGE_CACHE	toplevel	bool	TSEG	The option enables stage cache support for platform. Platform can stash copies of postcar, ramstage and raw runtime data inside SMM TSEG, to be restored on S3 resume path.
CBMEM_STAGE_CACHE	toplevel	bool	CBMEM	The option enables stage cache support for platform. Platform can stash copies of postcar, ramstage and raw runtime data inside CBMEM. While the approach is faster than reloading stages from boot media it is also a possible attack scenario via which OS can possibly circumvent SMM locks and SPI write protections. If unsure, select 'N'
UPDATE_IMAGE	toplevel	bool	Update existing coreboot.rom image	If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already is a suitable file for further processing. The bootblock will not be modified. If unsure, select 'N'
BOOTSPLASH_IMAGE	toplevel	bool	Add a bootsplash image	Select this option if you have a bootsplash image that you would like to add to your ROM. This will only add the image to the ROM. To actually run it check options under 'Display' section.
BOOTSPLASH_FILE	toplevel	string	Bootsplash path and filename	The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg.
FW_CONFIG	toplevel	bool	Firmware Configuration Probing	Enable support for probing devices with fw_config. This is a simple bitmask broken into fields and options for probing.
FW_CONFIG_SOURCE_CBFS	toplevel	bool	Obtain Firmware Configuration value from CBFS	With this option enabled coreboot will look for the 32bit firmware configuration value in CBFS at the selected prefix with the file name "fw_config". This option will override other sources and allow the local image to preempt the mainboard selected source.
FW_CONFIG_SOURCE_CHROMEEC_CBI	toplevel	bool	Obtain Firmware Configuration value from Google Chrome EC CBI	This option tells coreboot to read the firmware configuration value from the Google Chrome Embedded Controller CBI interface. This source is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was found in CBFS.
RAMPAYLOAD	toplevel	bool	Enable coreboot flow without executing ramstage	If this option is enabled, coreboot flow will skip ramstage loading and execution of ramstage to load payload. Instead it is expected to load payload from postcar stage itself. In this flow coreboot will perform basic x86 initialization (DRAM resource allocation), MTRR programming, Skip PCI enumeration logic and only allocate BAR for fixed devices (bootable devices, TPM over GSPI).
CONFIGURABLE_RAMSTAGE	toplevel	bool	Enable a configurable ramstage.	A configurable ramstage allows you to select which parts of the ramstage to run. Currently, we can only select a minimal PCI scanning step. The minimal PCI scanning will only check those parts that are enabled in the devicetree.cb. By convention none of those devices should be bridges.
MINIMAL_PCI_SCANNING	toplevel	bool	Enable minimal PCI scanning	If this option is enabled, coreboot will scan only PCI devices marked as mandatory in devicetree.cb
Menu: Mainboard
	mainboard	(comment)		Important: Run 'make distclean' before switching boards
ONBOARD_MEM_SAMSUNG	mainboard/portwell/m107	bool	Samsung	Samsung K4B8G1646D memory
ONBOARD_MEM_MICRON	mainboard/portwell/m107	bool	Micron	Micron MT41K512M16HA memory
ONBOARD_MEM_KINGSTON	mainboard/portwell/m107	bool	Kingston	Kingston B5116ECMDXGGB memory
BMC_INFO_LOC	mainboard/scaleway/tagada	hex	BMC information location in flash	Location of BMC SERIAL information.
HUDSON_LEGACY_FREE	mainboard/bap/ode_e20XX	bool	Select DDR3 clock	Select your preferred DDR3 clock setting. Note: This option changes the total power consumption. If unsure, use DDR3-1066.
BOARD_EMULATION_QEMU_AARCH64	mainboard/emulation/qemu-aarch64.name	bool	QEMU AArch64 (virt)	To execute, do: qemu-system-aarch64 -bios ./build/coreboot.rom -M virt,secure=on,virtualization=on -cpu cortex-a53 -nographic -m 8192M
MAINBOARD_DIR	mainboard/kontron/mal10	string	Carrier board	This option sets the type of carrier board to be used with the Kontron mAL10 COMe module.
BOARD_KONTRON_T10_TNI	mainboard/kontron/mal10	bool	Kontron i-T10-TNIx	By selecting this option, the target ROM image will be built for the Kontron Ref.Carrier-i T10-TNI carrier board.
	mainboard/adlink	(comment)		see under vendor LiPPERT
	mainboard/google/kahlee.name	(comment)		Kahlee
	mainboard/google/deltaur.name	(comment)		Deltaur
	mainboard/google/beltino.name	(comment)		Beltino
	mainboard/google/jecht.name	(comment)		Jecht
	mainboard/google/zork.name	(comment)		Zork
	mainboard/google/oak.name	(comment)		Oak
	mainboard/google/auron.name	(comment)		Auron
	mainboard/google/trogdor.name	(comment)		Trogdor
	mainboard/google/trogdor.name	(comment)		(Trogdor requires 'Allow QC blobs repository')
	mainboard/google/slippy.name	(comment)		Slippy
	mainboard/google/sarien.name	(comment)		Sarien
	mainboard/google/reef.name	(comment)		Reef
	mainboard/google/hatch.name	(comment)		Hatch
	mainboard/google/glados.name	(comment)		Glados
	mainboard/google/guybrush.name	(comment)		Guybrush
	mainboard/google/drallion.name	(comment)		Drallion
	mainboard/google/volteer.name	(comment)		Volteer
	mainboard/google/gru.name	(comment)		Gru
	mainboard/google/veyron.name	(comment)		Veyron
	mainboard/google/octopus.name	(comment)		Octopus
	mainboard/google/poppy.name	(comment)		Poppy
	mainboard/google/rambi.name	(comment)		Rambi
	mainboard/google/cyan.name	(comment)		Cyan
	mainboard/google/asurada.name	(comment)		Asurada
	mainboard/google/fizz.name	(comment)		Fizz
	mainboard/google/kukui.name	(comment)		Kukui
	mainboard/google/kukui.name	(comment)		Jacuzzi
FMDFILE	mainboard/google/kahlee	string		The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, but in some cases more complex setups are required. When an fmd is specified, it overrides the default format.
USE_OEM_BIN	mainboard/google/kahlee	bool	Add an oem.bin file	Add an oem.bin file to identify the manufacturer in SMBIOS, overriding the CONFIG_MAINBOARD_SMBIOS_MANUFACTURER value.
MAINBOARD_PART_NUMBER	mainboard/google/nyan	string	BCT boot media	Which boot media to configure the BCT for.
NYAN_BCT_CFG_SPI	mainboard/google/nyan	bool	SPI	Configure the BCT for booting from SPI.
NYAN_BCT_CFG_EMMC	mainboard/google/nyan	bool	eMMC	Configure the BCT for booting from eMMC.
BOOT_DEVICE_SPI_FLASH_BUS	mainboard/google/nyan	int	SPI bus with boot media ROM	Which SPI bus the boot media is connected to.
PICASSO_FW_A_POSITION	mainboard/google/zork	hex		Location of the AMD firmware in the RW_A region. This is the start of the RW-A region + 64 bytes for the cbfs header.
PICASSO_FW_B_POSITION	mainboard/google/zork	hex		Location of the AMD firmware in the RW_B region. This is the start of the RW-A region + 64 bytes for the cbfs header.
VARIANT_SUPPORTS_PRE_V3_SCHEMATICS	mainboard/google/zork	bool		Whether this variant supports pre-v3 version of schematics. Eventually, when a variant moves to a point where it no longer has to support pre-v3 schematics, `default y` entry for it can be dropped.
VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS	mainboard/google/zork	int		Minimum board version where the variant starts supporting v3.6+ version of reference schematics.
VARIANT_MIN_BOARD_ID_V3_SCHEMATICS	mainboard/google/zork	int		Minimum board version where the variant starts supporting v3 version of reference schematics.
VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH	mainboard/google/zork	bool		Whether this variant supports active high power enable for WiFi. For pre-v3 schematics, this is always true. There are some variants which used v3 schematics, but did not pick up the change for active low WiFi power enable. Those variants will have to set this config to true. Eventually, when a variant needs to only support v3 schematics with active low power enable for WiFi, `default y` entry for it can be dropped.
VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW	mainboard/google/zork	int		Minimum board version where the variant starts supporting active low power enable for WiFi.
VARIANT_HAS_FPMCU	mainboard/google/zork	bool		Select y if any SKU of the board has a fingerprint sensor
VARIANT_MAX_BOARD_ID_BROKEN_FMPCU_POWER	mainboard/google/zork	int		Last board version that needs the extra delay for FPMCU init.
MAINBOARD_PART_NUMBER	mainboard/google/nyan_big	string	BCT boot media	Which boot media to configure the BCT for.
NYAN_BIG_BCT_CFG_SPI	mainboard/google/nyan_big	bool	SPI	Configure the BCT for booting from SPI.
NYAN_BIG_BCT_CFG_EMMC	mainboard/google/nyan_big	bool	eMMC	Configure the BCT for booting from eMMC.
BOOT_DEVICE_SPI_FLASH_BUS	mainboard/google/nyan_big	int	SPI bus with boot media ROM	Which SPI bus the boot media is connected to.
AMD_FWM_POSITION_INDEX	mainboard/google/guybrush	int		TODO: might need to be adapted for better placement of files in cbfs
DRAM_SIZE_MB	mainboard/google/foster	int	BCT boot media	Which boot media to configure the BCT for.
FOSTER_BCT_CFG_SPI	mainboard/google/foster	bool	SPI	Configure the BCT for booting from SPI.
FOSTER_BCT_CFG_EMMC	mainboard/google/foster	bool	eMMC	Configure the BCT for booting from eMMC.
BOOT_DEVICE_SPI_FLASH_BUS	mainboard/google/foster	int	SPI bus with boot media ROM	Which SPI bus the boot media is connected to.
MAINBOARD_PART_NUMBER	mainboard/google/nyan_blaze	string	BCT boot media	Which boot media to configure the BCT for.
NYAN_BLAZE_BCT_CFG_SPI	mainboard/google/nyan_blaze	bool	SPI	Configure the BCT for booting from SPI.
NYAN_BLAZE_BCT_CFG_EMMC	mainboard/google/nyan_blaze	bool	eMMC	Configure the BCT for booting from eMMC.
BOOT_DEVICE_SPI_FLASH_BUS	mainboard/google/nyan_blaze	int	SPI bus with boot media ROM	Which SPI bus the boot media is connected to.
DISPLAY_SPD_DATA	mainboard/google/cyan	bool	Display Memory Serial Presence Detect Data	When enabled displays the memory configuration data.
DRAM_SIZE_MB	mainboard/google/smaug	int	BCT boot media	Which boot media to configure the BCT for.
SMAUG_BCT_CFG_SPI	mainboard/google/smaug	bool	SPI	Configure the BCT for booting from SPI.
SMAUG_BCT_CFG_EMMC	mainboard/google/smaug	bool	eMMC	Configure the BCT for booting from eMMC.
BOOT_DEVICE_SPI_FLASH_BUS	mainboard/google/smaug	int	SPI bus with boot media ROM	Which SPI bus the boot media is connected to.
	mainboard/clevo/cml-u.name	(comment)		Comet Lake U
	mainboard/clevo/kbl-u.name	(comment)		Kaby Lake U
AGESA_USE_1_0_0_4_HEADER	mainboard/pcengines/apu2	bool		Due to a bug in AGESA 1.0.0.A affecting boards without UMA, it is impossible to use the newest blob. Using an older 1.0.0.4 blob workarounds the problem, however some headers changes between blob revisions. This option removes the changes in headers introduced with AGESA 1.0.0.A to fit the 1.0.0.4 revision.
HWM_PORT	mainboard/amd/padmelon	hex		HWM base address must be an odd address. Hardware monitor used addresses are HWM_PORT for index an HWM_PORT + 1 for data. If changed, make sure fan_init.c IO window setting. The HWM (Hardware Monitor) is used for fan control within padmelon.
AMD_LPC_DEBUG_CARD	mainboard/amd/mandolin	bool	Enable LPC-Serial debug card on the debug header	AMD's debug card contains an SMSC SIO1036 device which provides an I/O-mapped UART in the system. This is mutually exclusive with AMD_SOC_CONSOLE_UART which selects the SoC's integrated memory-mapped UART for coreboot console output.
AMD_FWM_POSITION_INDEX	mainboard/amd/mandolin	int		TODO: might need to be adapted for better placement of files in cbfs
MANDOLIN_MCHP_FW_FILE	mainboard/amd/mandolin	string		The EC firmware blob is usually the first 128kByte of the stock firmware image.
MANDOLIN_MCHP_FW_FILE	mainboard/amd/mandolin	string	State of IOMux for LPC/eMMC signals	Mandolin is designed to use either LPC or eMMC signals. Use this selection to determine which are configured for this image.
MANDOLIN_LPC	mainboard/amd/mandolin	bool		Picasso's LPC bus signals are MUXed with some of the EMMC signals. Select this option if LPC signals are required.
VGA_BIOS_DGPU_ID	mainboard/amd/mandolin	string		The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.
AMD_FWM_POSITION_INDEX	mainboard/amd/majolica	int		TODO: might need to be adapted for better placement of files in cbfs
MAJOLICA_MCHP_FW_FILE	mainboard/amd/majolica	string		The EC firmware blob is usually the first 128kByte of the stock firmware image.
	mainboard/intel/coffeelake_rvp.name	(comment)		Coffeelake RVP
DIMM_SPD_SIZE	mainboard/intel/tglrvp	int	ON BOARD EC	This option allows you to select the on board EC to use. Select whether the board has Intel EC or Chrome EC
Menu: Debugging
DISABLE_UART_ON_TESTPADS	mainboard/intel/dcp847ske	bool	Disable UART on testpads	Serial output requires soldering to the testpad next to NCT5577D pin 18 (txd) and gnd.
VGA_BIOS_FILE	mainboard/intel/strago	string		The C0 version of the video BIOS gets computed from this name so that they can both be added. Only the correct one for the system will be run.
VGA_BIOS_ID	mainboard/intel/strago	string		The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1
BASEBOARD_GLKRVP_LAPTOP	mainboard/intel/glkrvp	None	ON BOARD EC	This option allows you to select the on board EC to use. Select whether the board has Intel EC or Chrome EC
GALILEO_GEN2	mainboard/intel/galileo	bool	Board generation: GEN1 (n) or GEN2 (y)	The coreboot binary will configure only one generation of the Galileo board since coreboot can not determine the board generation at runtime. Select which generation of the Galileo that coreboot should initialize.
FSP_BUILD_TYPE_DEBUG	mainboard/intel/galileo	bool	Debug	Use the debug version of FSP
FSP_BUILD_TYPE_RELEASE	mainboard/intel/galileo	bool	Release	Use the release version of FSP
FSP_TYPE_2_0	mainboard/intel/galileo	bool	MemInit subroutine	FSP 2.0 implemented as subroutines, no EDK-II cores
FSP_TYPE_2_0_PEI	mainboard/intel/galileo	bool	SEC + PEI Core + MemInit PEIM	FSP 2.0 implemented using SEC and PEI core
FSP_DEBUG_ALL	mainboard/intel/galileo	bool	Enable all FSP debug support	Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA also turn on FSP 2.0 debug support for ESRAM_LAYOUT, FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS
VBOOT_WITH_CRYPTO_SHIELD	mainboard/intel/galileo	bool	Verified boot using the Crypto Shield board	Perform a verified boot using the TPM on the Crypto Shield board.
DRIVER_TPM_I2C_ADDR	mainboard/intel/galileo	hex	Address of the I2C TPM chip	I2C address of the TPM chip on the Crypto Shield board.
FMDFILE	mainboard/intel/galileo	string	FMAP description file in fmd format	The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, but in some cases more complex setups are required. When an FMD descriptionn file is specified, the build system uses it instead of creating a default FMAP file.
DIMM_SPD_SIZE	mainboard/intel/adlrvp	int	ON BOARD EC	This option allows you to select the on board EC to use. Select whether the board has Intel EC or Chrome EC
ENABLE_FSP_MEMORY_DOWN	mainboard/intel/harcuvar	bool	Enable Memory Down	Select this option to enable Memory Down function.
SPD_LOC	mainboard/intel/harcuvar	hex	SPD binary location in cbfs	Location of SPD binary for memory down function.
ONBOARD_SAMSUNG_MEM	mainboard/facebook/fbg1701	bool	Onboard memory manufacturer Samsung	Samsung K4B8G1646D memory
BOARD_EXAMPLE_MIN86	mainboard/example/min86.name	bool	Minimal x86 fake board	This example mainboard code along with the example/min86 SoC should serve as a minimal example how a buildable x86 SoC code base can look like. This can serve, for instance, as a basis to add new SoCs to coreboot. Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes.
VGA_BIOS_FILE	mainboard/protectli/vault_bsw	string		The C0 version of the video bios gets computed from this name so that they can both be added. Only the correct one for the system will be run.
VGA_BIOS_ID	mainboard/protectli/vault_bsw	string		The VGA_BIOS_ID for the C0 version of the video bios is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1
BOARD_ASUS_F2A85_M_DDR3_VOLT_135	mainboard/asus/f2a85-m	bool	1.35V	Set DRR3 memory voltage to 1.35V
BOARD_ASUS_F2A85_M_DDR3_VOLT_150	mainboard/asus/f2a85-m	bool	1.50V	Set DRR3 memory voltage to 1.50V
BOARD_ASUS_F2A85_M_DDR3_VOLT_165	mainboard/asus/f2a85-m	bool	1.65V	Set DRR3 memory voltage to 1.65V
	mainboard/siemens/chili.name	(comment)		CHILI
	mainboard/siemens/mc_apl1.name	(comment)		MC APLx
INCLUDE_SMSC_SCH5545_EC_FW	mainboard/dell/optiplex_9010	bool	Include SMSC SCH5545 EC firmware binary	This option allows to add the SMSC SCH5545 Environmental Controller firmware binary. The firmware must be loaded after each power failure in order to properly initialize the fan control, because EC loses its configuration when power is cut off. Otherwise the fans will keep running at full speed after power failure.
	mainboard/lippert	(comment)		was acquired by ADLINK
DRIVERS_UART_8250IO	mainboard/purism/librem_bdw	string		This platform does not have any way to get standard serial output so disable it by default.
BOARD_ROMSIZE_KB_65536	mainboard	bool	ROM chip size	Select the size of the ROM chip you intend to flash coreboot on. The build system will take care of creating a coreboot.rom file of the matching size.
COREBOOT_ROMSIZE_KB_256	mainboard	bool	256 KB	Choose this option if you have a 256 KB ROM chip.
COREBOOT_ROMSIZE_KB_512	mainboard	bool	512 KB	Choose this option if you have a 512 KB ROM chip.
COREBOOT_ROMSIZE_KB_1024	mainboard	bool	1024 KB (1 MB)	Choose this option if you have a 1024 KB (1 MB) ROM chip.
COREBOOT_ROMSIZE_KB_2048	mainboard	bool	2048 KB (2 MB)	Choose this option if you have a 2048 KB (2 MB) ROM chip.
COREBOOT_ROMSIZE_KB_4096	mainboard	bool	4096 KB (4 MB)	Choose this option if you have a 4096 KB (4 MB) ROM chip.
COREBOOT_ROMSIZE_KB_5120	mainboard	bool	5120 KB (5 MB)	Choose this option if you have a 5120 KB (5 MB) ROM chip.
COREBOOT_ROMSIZE_KB_6144	mainboard	bool	6144 KB (6 MB)	Choose this option if you have a 6144 KB (6 MB) ROM chip.
COREBOOT_ROMSIZE_KB_8192	mainboard	bool	8192 KB (8 MB)	Choose this option if you have a 8192 KB (8 MB) ROM chip.
COREBOOT_ROMSIZE_KB_10240	mainboard	bool	10240 KB (10 MB)	Choose this option if you have a 10240 KB (10 MB) ROM chip.
COREBOOT_ROMSIZE_KB_12288	mainboard	bool	12288 KB (12 MB)	Choose this option if you have a 12288 KB (12 MB) ROM chip.
COREBOOT_ROMSIZE_KB_16384	mainboard	bool	16384 KB (16 MB)	Choose this option if you have a 16384 KB (16 MB) ROM chip.
COREBOOT_ROMSIZE_KB_32768	mainboard	bool	32768 KB (32 MB)	Choose this option if you have a 32768 KB (32 MB) ROM chip.
COREBOOT_ROMSIZE_KB_65536	mainboard	bool	65536 KB (64 MB)	Choose this option if you have a 65536 KB (64 MB) ROM chip.
ENABLE_POWER_BUTTON	mainboard	bool	Enable the power button	The selected mainboard can optionally have the power button tied to ground with a jumper so that the button appears to be constantly depressed. If this option is enabled and the jumper is installed then the board will turn on, but turn off again after a short timeout, usually 4 seconds. Select Y here if you have removed the jumper and want to use an actual power button. Select N if you have the jumper installed.
POWER_STATE_DEFAULT_ON_AFTER_FAILURE	mainboard	bool		Selected by platforms or mainboards that want a "default on" behaviour.
POWER_STATE_DEFAULT_ON_AFTER_FAILURE	mainboard	bool	System Power State after Failure	Provides a default for the power state the system should go into after G3 (power loss). On many boards this can be overridden by an NVRAM option.
POWER_STATE_OFF_AFTER_FAILURE	mainboard	bool	S5 Soft Off	Choose this option if you want to put system into S5 after reapplying power after failure.
POWER_STATE_ON_AFTER_FAILURE	mainboard	bool	S0 Full On	Choose this option if you want to keep system in S0 after reapplying power after failure.
POWER_STATE_PREVIOUS_AFTER_FAILURE	mainboard	bool	Keep Previous State	Choose this option if you want to keep system in the same power state as before failure after reapplying power.
DEVICETREE	toplevel	string		This symbol allows mainboards to select a different file under their mainboard directory for the devicetree.cb file. This allows the board variants that need different devicetrees to be in the same directory. Examples: "devicetree.variant.cb" "variant/devicetree.cb"
OVERRIDE_DEVICETREE	toplevel	string		This symbol allows variants to provide an override devicetree file to override the registers and/or add new devices on top of the ones provided by baseboard devicetree using CONFIG_DEVICETREE. Examples: "devicetree.variant-override.cb" "variant/devicetree-override.cb"
FMDFILE	toplevel	string	fmap description file in fmd format	The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, but in some cases more complex setups are required. When an fmd is specified, it overrides the default format.
CBFS_SIZE	toplevel	hex	Size of CBFS filesystem in ROM	This is the part of the ROM actually managed by CBFS, located at the end of the ROM (passed through cbfstool -o) on x86 and at at the start of the ROM (passed through cbfstool -s) everywhere else. It defaults to span the whole ROM on all but Intel systems that use an Intel Firmware Descriptor. It can be overridden to make coreboot live alongside other components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE binaries. This symbol should only be used to generate a default FMAP and is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
CBFS_AUTOGEN_ATTRIBUTES	toplevel	bool		If this option is selected, every file in cbfs which has a constraint regarding position or alignment will get an additional file attribute which describes this constraint.
Menu: Chipset
	toplevel	(comment)		SoC
DEBUG_DRAM	soc/mediatek/mt8183	bool	Output verbose DRAM related debug messages	This option enables additional DRAM related debug messages.
MT8183_DRAM_EMCP	soc/mediatek/mt8183	bool		The eMCP platform should select this option to run at different DRAM frequencies.
MT8183_DRAM_DVFS	soc/mediatek/mt8183	bool		This options enables DRAM calibration with multiple frequencies (low, medium and high) for DVFS feature.
SSPM_FIRMWARE	soc/mediatek/mt8183	string		The file name of the MediaTek SSPM firmware.
DEBUG_DRAM	soc/mediatek/mt8192	bool	Output verbose DRAM related debug messages	This option enables additional DRAM related debug messages.
MT8192_DRAM_EMCP	soc/mediatek/mt8192	bool		The eMCP platform should select this option to run at different DRAM frequencies.
MT8192_DRAM_DVFS	soc/mediatek/mt8192	bool		This option enables DRAM calibration with multiple frequencies (low, medium and high frequency groups, with total 7 frequencies) for DVFS feature. All supported data rates are: 800, 1200, 1600, 1866, 2400, 3200, 4266.
MEMORY_TEST	soc/mediatek/mt8192	bool		This option enables memory basic compare test to verify the DRAM read or write is as expected.
DPM_DM_FIRMWARE	soc/mediatek/mt8192	string		The file name of the MediaTek DPM DM firmware
DPM_PM_FIRMWARE	soc/mediatek/mt8192	string		The file name of the MediaTek DPM PM firmware
MCUPM_FIRMWARE	soc/mediatek/mt8192	string		The file name of the MediaTek MCUPM firmware.
SPM_FIRMWARE	soc/mediatek/mt8192	string		The file name of the MediaTek SPM firmware.
SSPM_FIRMWARE	soc/mediatek/mt8192	string		The file name of the MediaTek SSPM firmware.
FLASH_DUAL_READ	soc/mediatek/mt8192	bool		When this option is enabled, the flash controller provides the ability to dual read mode.
SRCLKEN_RC_SUPPORT	soc/mediatek/mt8192	bool		This option enables clock buffer remote controller module to control PMIC 26MHz clock output.
DEBUG_DRAM	soc/mediatek/mt8173	bool	Output verbose DRAM related debug messages	This option enables additional DRAM related debug messages.
DEBUG_I2C	soc/mediatek/mt8173	bool	Output verbose I2C related debug messages	This option enables I2C related debug messages.
DEBUG_PMIC	soc/mediatek/mt8173	bool	Output verbose PMIC related debug messages	This option enables PMIC related debug messages.
DEBUG_PMIC_WRAP	soc/mediatek/mt8173	bool	Output verbose PMIC WRAP related debug messages	This option enables PMIC WRAP related debug messages.
SBL_BLOB	soc/qualcomm/ipq806x	string	file name of the Qualcomm SBL blob	The path and filename of the binary blob containing ipq806x early initialization code, as supplied by the vendor.
SOC_QUALCOMM_COMMON	soc/qualcomm/common	bool		Selected by platforms that use the common code.
IPQ_QFN_PART	soc/qualcomm/ipq40xx	bool		Is the SoC a QFN part (as opposed to a BGA part)
SBL_ELF	soc/qualcomm/ipq40xx	string	file name of the QCA SBL ELF	The path and filename of the binary blob containing ipq40xx early initialization code, as supplied by the vendor.
SBL_UTIL_PATH	soc/qualcomm/ipq40xx	string	Path for utils to combine SBL_ELF and bootblock	Path for utils to combine SBL_ELF and bootblock
UART_FOR_CONSOLE	soc/qualcomm/sc7180	int		Select the QUP instance to be used for UART console output.
SOC_AMD_CEZANNE	soc/amd/cezanne	bool		AMD Cezanne support
EARLY_RESERVED_DRAM_BASE	soc/amd/cezanne	hex		This variable defines the base address of the DRAM which is reserved for usage by coreboot in early stages (i.e. before ramstage is up). This memory gets reserved in BIOS tables to ensure that the OS does not use it, thus preventing corruption of OS memory in case of S3 resume.
PSP_APOB_DRAM_ADDRESS	soc/amd/cezanne	hex		Location in DRAM where the PSP will copy the AGESA PSP Output Block.
PRERAM_CBMEM_CONSOLE_SIZE	soc/amd/cezanne	hex		Increase this value if preram cbmem console is getting truncated
C_ENV_BOOTBLOCK_SIZE	soc/amd/cezanne	hex		Sets the size of the bootblock stage that should be loaded in DRAM. This variable controls the DRAM allocation size in linker script for bootblock stage.
ROMSTAGE_ADDR	soc/amd/cezanne	hex		Sets the address in DRAM where romstage should be loaded.
ROMSTAGE_SIZE	soc/amd/cezanne	hex		Sets the size of DRAM allocation for romstage in linker script.
FSP_M_ADDR	soc/amd/cezanne	hex		Sets the address in DRAM where FSP-M should be loaded. cbfstool performs relocation of FSP-M to this address.
FSP_M_SIZE	soc/amd/cezanne	hex		Sets the size of DRAM allocation for FSP-M in linker script.
SOC_AMD_STONEYRIDGE	soc/amd/stoneyridge	bool		AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh.
AMD_APU_STONEYRIDGE	soc/amd/stoneyridge	bool		AMD Stoney Ridge APU
AMD_APU_PRAIRIEFALCON	soc/amd/stoneyridge	bool		AMD Embedded Prairie Falcon APU
AMD_APU_MERLINFALCON	soc/amd/stoneyridge	bool		AMD Embedded Merlin Falcon APU
AMD_APU_PKG_FP4	soc/amd/stoneyridge	bool		AMD FP4 package
AMD_APU_PKG_FT4	soc/amd/stoneyridge	bool		AMD FT4 package
DCACHE_BSP_STACK_SIZE	soc/amd/stoneyridge	hex		The amount of anticipated stack usage in CAR by bootblock and other stages.
PRERAM_CBMEM_CONSOLE_SIZE	soc/amd/stoneyridge	hex		Increase this value if preram cbmem console is getting truncated
BOTTOMIO_POSITION	soc/amd/stoneyridge	hex	Bottom of 32-bit IO space	If PCI peripherals with big BARs are connected to the system the bottom of the IO must be decreased to allocate such devices. Declare the beginning of the 128MB-aligned MMIO region. This option is useful when PCI peripherals requesting large address ranges are present.
VGA_BIOS_ID	soc/amd/stoneyridge	string		The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.
STONEYRIDGE_XHCI_ENABLE	soc/amd/stoneyridge	bool	Enable Stoney Ridge XHCI Controller	The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI controller if the XHCI firmware is available but the XHCI controller is not enabled by coreboot.
STONEYRIDGE_XHCI_FWM	soc/amd/stoneyridge	bool	Add xhci firmware	Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0
STONEYRIDGE_GEC_FWM	soc/amd/stoneyridge	bool		Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC. Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
STONEYRIDGE_SATA_MODE	soc/amd/stoneyridge	int	SATA Mode	Select the mode in which SATA should be driven. The default is NATIVE. 0: NATIVE mode does not require a ROM. 2: AHCI may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM. 3: LEGACY IDE 4: IDE to AHCI 5: AHCI7804: ROM Required, and AMD driver required in the OS. 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
	soc/amd/stoneyridge	(comment)		NATIVE
	soc/amd/stoneyridge	(comment)		AHCI
	soc/amd/stoneyridge	(comment)		LEGACY IDE
	soc/amd/stoneyridge	(comment)		IDE to AHCI
	soc/amd/stoneyridge	(comment)		AHCI7804
	soc/amd/stoneyridge	(comment)		IDE to AHCI7804
STONEYRIDGE_LEGACY_FREE	soc/amd/stoneyridge	bool	System is legacy free	Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI.
SERIRQ_CONTINUOUS_MODE	soc/amd/stoneyridge	bool		Set this option to y for serial IRQ in continuous mode. Otherwise it is in quiet mode.
STONEYRIDGE_ACPI_IO_BASE	soc/amd/stoneyridge	hex		Base address for the ACPI registers. This value must match the hardcoded value of AGESA.
ACPI_BERT	soc/amd/stoneyridge	bool	Build ACPI BERT Table	Report Machine Check errors identified in POST to the OS in an ACPI Boot Error Record Table. This option reserves an 8MB region for building the error structures.
USE_PSPSECUREOS	soc/amd/stoneyridge	bool	Include PSP SecureOS blobs in AMD firmware	Include the PspSecureOs, PspTrustlet and TrustletKey binaries in the amdfw section. If unsure, answer 'y'
SOC_AMD_PSP_SELECTABLE_SMU_FW	soc/amd/stoneyridge	bool		Some ST implementations allow storing SMU firmware into cbfs and calling the PSP to load the blobs at the proper time. Merlin Falcon does not support it. If you are using 00670F00 SOC, ask your AMD representative if it supports it or not.
AMDFW_OUTSIDE_CBFS	soc/amd/stoneyridge	bool	The AMD firmware is outside CBFS	The AMDFW (PSP) is typically locatable in cbfs. Select this option to manually attach the generated amdfw.rom outside of cbfs. The location is selected by the FWM position.
AMD_FWM_POSITION_INDEX	soc/amd/stoneyridge	int	Firmware Directory Table location (0 to 5)	Typically this is calculated by the ROM size, but there may be situations where you want to put the firmware directory table in a different location. 0: 512 KB - 0xFFFA0000 1: 1 MB - 0xFFF20000 2: 2 MB - 0xFFE20000 3: 4 MB - 0xFFC20000 4: 8 MB - 0xFF820000 5: 16 MB - 0xFF020000
	soc/amd/stoneyridge	(comment)		AMD Firmware Directory Table set to location for 512KB ROM
	soc/amd/stoneyridge	(comment)		AMD Firmware Directory Table set to location for 1MB ROM
	soc/amd/stoneyridge	(comment)		AMD Firmware Directory Table set to location for 2MB ROM
	soc/amd/stoneyridge	(comment)		AMD Firmware Directory Table set to location for 4MB ROM
	soc/amd/stoneyridge	(comment)		AMD Firmware Directory Table set to location for 8MB ROM
	soc/amd/stoneyridge	(comment)		AMD Firmware Directory Table set to location for 16MB ROM
MAINBOARD_POWER_RESTORE	soc/amd/stoneyridge	int		This option determines what state to go to once power is restored after having been lost in S0. Select this option to automatically return to S0. Otherwise the system will remain in S5 once power is restored.
SOC_AMD_PICASSO	soc/amd/picasso	bool		AMD Picasso support
FSP_M_FILE	soc/amd/picasso	string	FSP-M (memory init) binary path and filename	The path and filename of the FSP-M binary for this platform.
FSP_S_FILE	soc/amd/picasso	string	FSP-S (silicon init) binary path and filename	The path and filename of the FSP-S binary for this platform.
EARLY_RESERVED_DRAM_BASE	soc/amd/picasso	hex		This variable defines the base address of the DRAM which is reserved for usage by coreboot in early stages (i.e. before ramstage is up). This memory gets reserved in BIOS tables to ensure that the OS does not use it, thus preventing corruption of OS memory in case of S3 resume.
PSP_APOB_DRAM_ADDRESS	soc/amd/picasso	hex		Location in DRAM where the PSP will copy the AGESA PSP Output Block.
PSP_SHAREDMEM_BASE	soc/amd/picasso	hex		This variable defines the base address in DRAM memory where PSP copies vboot workbuf to. This is used in linker script to have a static allocation for the buffer as well as for adding relevant entries in BIOS directory table for the PSP.
PSP_SHAREDMEM_SIZE	soc/amd/picasso	hex		Sets the maximum size for the PSP to pass the vboot workbuf and any logs or timestamps back to coreboot. This will be copied into main memory by the PSP and will be available when the x86 is started. The workbuf's base depends on the address of the reset vector.
PRERAM_CBMEM_CONSOLE_SIZE	soc/amd/picasso	hex		Increase this value if preram cbmem console is getting truncated
C_ENV_BOOTBLOCK_SIZE	soc/amd/picasso	hex		Sets the size of the bootblock stage that should be loaded in DRAM. This variable controls the DRAM allocation size in linker script for bootblock stage.
ROMSTAGE_ADDR	soc/amd/picasso	hex		Sets the address in DRAM where romstage should be loaded.
ROMSTAGE_SIZE	soc/amd/picasso	hex		Sets the size of DRAM allocation for romstage in linker script.
FSP_M_ADDR	soc/amd/picasso	hex		Sets the address in DRAM where FSP-M should be loaded. cbfstool performs relocation of FSP-M to this address.
FSP_M_SIZE	soc/amd/picasso	hex		Sets the size of DRAM allocation for FSP-M in linker script.
VERSTAGE_ADDR	soc/amd/picasso	hex		Sets the address in DRAM where verstage should be loaded if running as a separate stage on x86.
VERSTAGE_SIZE	soc/amd/picasso	hex		Sets the size of DRAM allocation for verstage in linker script if running as a separate stage on x86.
VGA_BIOS_ID	soc/amd/picasso	string		The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev_rev() function in northbridge.c.
VGA_BIOS_SECOND_ID	soc/amd/picasso	string		Because Dali and Picasso need different video BIOSes, but have the same vendor/device IDs, we need an alternate method to determine the correct video BIOS. In map_oprom_vendev_rev(), we look at the cpuid and decide which rom to load. Even though the hardware has the same vendor/device IDs, the vBIOS contains a different device ID, confusing the situation even more.
CHECK_REV_IN_OPROM_NAME	soc/amd/picasso	bool		Select this in the platform BIOS or chipset if the option rom has a revision that needs to be checked when searching CBFS.
PICASSO_FCH_IOAPIC_ID	soc/amd/picasso	hex		The Picasso APU has two IOAPICs, one in the FCH and one in the northbridge. Set this value for the intended ID to assign to the FCH IOAPIC. The value should be >= MAX_CPUS and different from the GNB's IOAPIC_ID.
PICASSO_GNB_IOAPIC_ID	soc/amd/picasso	hex		The Picasso APU has two IOAPICs, one in the FCH and one in the northbridge. Set this value for the intended ID to assign to the GNB IOAPIC. The value should be >= MAX_CPUS and different from the FCH's IOAPIC_ID.
SERIRQ_CONTINUOUS_MODE	soc/amd/picasso	bool		Set this option to y for serial IRQ in continuous mode. Otherwise it is in quiet mode.
PICASSO_ACPI_IO_BASE	soc/amd/picasso	hex		Base address for the ACPI registers.
ACPI_BERT	soc/amd/picasso	bool	Build ACPI BERT Table	Report Machine Check errors identified in POST to the OS in an ACPI Boot Error Record Table.
ACPI_BERT_SIZE	soc/amd/picasso	hex		Specify the amount of DRAM reserved for gathering the data used to generate the ACPI table.
ACPI_SSDT_PSD_INDEPENDENT	soc/amd/picasso	bool	Allow core p-state independent transitions	AMD recommends the ACPI _PSD object to be configured to cause cores to transition between p-states independently. A vendor may choose to generate _PSD object to allow cores to transition together.
DISABLE_SPI_FLASH_ROM_SHARING	soc/amd/picasso	int		Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin which indicates a board level ROM transaction request. This removes arbitration with board and assumes the chipset controls the SPI flash bus entirely.
MAINBOARD_POWER_RESTORE	soc/amd/picasso	int		This option determines what state to go to once power is restored after having been lost in S0. Select this option to automatically return to S0. Otherwise the system will remain in S5 once power is restored.
FSP_TEMP_RAM_SIZE	soc/amd/picasso	hex		The amount of coreboot-allocated heap and stack usage by the FSP.
Menu: PSP Configuration Options
AMD_FWM_POSITION_INDEX	soc/amd/picasso	int	Firmware Directory Table location (0 to 5)	Typically this is calculated by the ROM size, but there may be situations where you want to put the firmware directory table in a different location. 0: 512 KB - 0xFFFA0000 1: 1 MB - 0xFFF20000 2: 2 MB - 0xFFE20000 3: 4 MB - 0xFFC20000 4: 8 MB - 0xFF820000 5: 16 MB - 0xFF020000
	soc/amd/picasso	(comment)		AMD Firmware Directory Table set to location for 512KB ROM
	soc/amd/picasso	(comment)		AMD Firmware Directory Table set to location for 1MB ROM
	soc/amd/picasso	(comment)		AMD Firmware Directory Table set to location for 2MB ROM
	soc/amd/picasso	(comment)		AMD Firmware Directory Table set to location for 4MB ROM
	soc/amd/picasso	(comment)		AMD Firmware Directory Table set to location for 8MB ROM
	soc/amd/picasso	(comment)		AMD Firmware Directory Table set to location for 16MB ROM
USE_PSPSECUREOS	soc/amd/picasso	bool		Include the PspSecureOs and PspTrustlet binaries in the PSP build. If unsure, answer 'y'
PSP_LOAD_MP2_FW	soc/amd/picasso	bool		Include the MP2 firmwares and configuration into the PSP build. If unsure, answer 'n'
PSP_LOAD_S0I3_FW	soc/amd/picasso	bool		Select this item to include the S0i3 file into the PSP build.
HAVE_PSP_WHITELIST_FILE	soc/amd/picasso	bool	Include a debug whitelist file in PSP build	Support secured unlock prior to reset using a whitelisted number? This feature requires a signed whitelist image and bootloader from AMD. If unsure, answer 'n'
PSP_SHAREDMEM_SIZE	soc/amd/picasso	hex	Maximum size of shared memory area	Sets the maximum size for the PSP to pass the vboot workbuf and any logs or timestamps back to coreboot. This will be copied into main memory by the PSP and will be available when the x86 is started.
PSP_UNLOCK_SECURE_DEBUG	soc/amd/picasso	bool	Unlock secure debug	Select this item to enable secure debug options in PSP.
PSP_VERSTAGE_FILE	soc/amd/picasso	string	Specify the PSP_verstage file path	Add psp_verstage file to the build & PSP Directory Table
PSP_VERSTAGE_SIGNING_TOKEN	soc/amd/picasso	string	Specify the PSP_verstage Signature Token file path	Add psp_verstage signature token to the build & PSP Directory Table
VBOOT_STARTS_BEFORE_BOOTBLOCK	soc/amd/picasso	string		Runs verstage on the PSP. Only available on certain Chrome OS branded parts from AMD.
VBOOT_HASH_BLOCK_SIZE	soc/amd/picasso	hex		Because the bulk of the time in psp_verstage to hash the RO cbfs is spent in the overhead of doing svc calls, increasing the hash block size significantly cuts the verstage hashing time as seen below. 4k takes 180ms 16k takes 44ms 32k takes 33.7ms 36k takes 32.5ms There's actually still room for an even bigger stack, but we've reached a point of diminishing returns.
CMOS_RECOVERY_BYTE	soc/amd/picasso	hex		If the workbuf is not passed from the PSP to coreboot, set the recovery flag and reboot. The PSP will read this byte, mark the recovery request in VBNV, and reset the system into recovery mode. This is the byte before the default first byte used by VBNV (0x26 + 0x0E - 1)
RWA_REGION_ONLY	soc/amd/picasso	string		Add a space-delimited list of filenames that should only be in the RW-A section.
RWB_REGION_ONLY	soc/amd/picasso	string		Add a space-delimited list of filenames that should only be in the RW-B section.
PICASSO_FW_A_POSITION	soc/amd/picasso	hex		Location of the AMD firmware in the RW_A region
PICASSO_FW_B_POSITION	soc/amd/picasso	hex		Location of the AMD firmware in the RW_B region
SOC_AMD_COMMON	soc/amd/common.common	bool		common code blocks for AMD SOCs
SOC_AMD_COMMON_BLOCK_ACPIMMIO	soc/amd/common/block/acpimmio	bool		Select this option to enable hardware blocks in the AcpiMmio address space (0xfed8xxxx).
SOC_AMD_COMMON_BLOCK_SPI	soc/amd/common/block/spi	bool		Select this option to add FCH SPI controller functions to the build. This overwrites the structure spi_flash_ops to use FCH SPI code instead of individual SPI specific code.
EFS_SPI_READ_MODE	soc/amd/common/block/spi	int		SPI read mode to be programmed by the PSP. The numbers in the options below indicate how many wires are utilized for command, address and data. For instance 1-1-2 means 1 command, 1 address and 2 data wires. 0: Normal Read (up to 33M) 1: Reserved 2: Dual IO (1-1-2) 3: Quad IO (1-1-4) 4: Dual IO (1-2-2) 5: Quad IO (1-4-4) 6: Normal Read (up to 66M) 7: Fast Read
EFS_SPI_SPEED	soc/amd/common/block/spi	int		SPI Fast Speed to be programmed by the PSP. 0: 66.66Mhz 1: 33.33MHz 2: 22.22MHz 3: 16.66MHz 4: 100MHz 5: 800KHz
EFS_SPI_MICRON_FLAG	soc/amd/common/block/spi	int		For Family 17h Model 00h and later SoC the PSP must be aware if a Micron part is present in EFS. Automatic detection (option 2) is available for Family 17h Model 30h-3Fh but is unsupported otherwise. 0: Board does not use Micron parts 1: Board always uses Micron parts 2: Micron parts are optional
SOC_AMD_COMMON_BLOCK_S3	soc/amd/common/block/s3	bool		Select this option to add S3 related functions to the build.
SOC_AMD_COMMON_BLOCK_GRAPHICS	soc/amd/common/block/graphics	bool		Select this option to use AMD common graphics driver support.
SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF	soc/amd/common/block/graphics	bool		Select this option to provide ATIF method with display brightness querying. Currently, the exported values only open up 0-255 as the brightness range for the display.
SOC_AMD_COMMON_BLOCK_SMI	soc/amd/common/block/smi	bool		Select this option to add the common functions for setting up the SMI configuration to the build.
SOC_AMD_COMMON_BLOCK_PSP	soc/amd/common/block/psp	bool		This option builds in the Platform Security Processor initialization functions. Do not select this directly in SoC code, select SOC_AMD_COMMON_BLOCK_PSP_GENx instead.
SOC_AMD_COMMON_BLOCK_PSP_GEN1	soc/amd/common/block/psp	bool		Used by the PSP in AMD systems before family 17h, e.g. stoneyridge.
SOC_AMD_COMMON_BLOCK_PSP_GEN2	soc/amd/common/block/psp	bool		Used by the PSP in AMD family 17h, 19h and possibly newer CPUs.
SOC_AMD_PSP_SELECTABLE_SMU_FW	soc/amd/common/block/psp	bool		Some PSP implementations allow storing SMU firmware into cbfs and calling the PSP to load the blobs at the proper time. The soc/<codename> should select this if its PSP supports the feature and each mainboard can choose to select an appropriate fanless or fanned set of blobs. Ask your AMD representative whether your APU is considered fanless.
SOC_AMD_COMMON_BLOCK_BANKED_GPIOS	soc/amd/common/block/gpio_banks	bool		Select this option to use the newer style banks of GPIO signals. These are at offsets +0x1500, +0x1600, and +0x1700 from the AcpiMmio base.
SOC_AMD_COMMON_BLOCK_ALINK	soc/amd/common/block/alink	bool		Select this option to access the FCH A-link configuration registers.
SOC_AMD_COMMON_BLOCK_SATA	soc/amd/common/block/sata	bool		Select this option to use AMD common SATA driver support.
SOC_AMD_COMMON_BLOCK_ACPI	soc/amd/common/block/acpi	bool		Select this option to use the AcpiMmio ACPI registers.
SOC_AMD_COMMON_BLOCK_PI	soc/amd/common/block/pi	bool		This option builds functions that interface AMD's AGESA reference code packaged in the binaryPI form.
PI_AGESA_CAR_HEAP_BASE	soc/amd/common/block/pi	hex		The AGESA PI blob may be built to allow an optional callout for AgesaHeapRebase. If AGESA calls AgesaHeapRebase, this option determines the location of the heap prior to DRAM availability.
PI_AGESA_TEMP_RAM_BASE	soc/amd/common/block/pi	hex		During a boot from S5, AGESA copies its CAR-based heap to a temporary location in DRAM. Once coreboot has established cbmem, the heap is moved again. This symbol determines the temporary location for the heap.
PI_AGESA_HEAP_SIZE	soc/amd/common/block/pi	hex		This option determines the amount of space allowed for AGESA heap prior to DRAM availability.
SOC_AMD_COMMON_BLOCK_PCI	soc/amd/common/block/pci	bool		This option builds functions used to program PCI interrupt routing, both PIC and APIC modes.
SOC_AMD_COMMON_BLOCK_PCI_MMCONF	soc/amd/common/block/pci	bool		Selecting this option adds the AMD-common enable_pci_mmconf function to the build.
SOC_AMD_COMMON_BLOCK_CAR	soc/amd/common/block/cpu	bool		This option allows the SOC to use a standard AMD cache-as-ram (CAR) implementation. CAR setup is built into bootblock and teardown is in postcar. The teardown procedure does not preserve the stack so it may not be appropriate for a romstage implementation without additional consideration. If this option is not used, the SOC must implement these functions separately. This is only used for AMD CPU before family 17h. From family 17h on the RAM is already initialized by the PSP before the x86 cores are released from reset.
SOC_AMD_COMMON_BLOCK_NONCAR	soc/amd/common/block/cpu	bool		From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any more, since the RAM initialization is already done by the PSP when the x86 cores are released from reset.
SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H	soc/amd/common/block/cpu	bool		Select this option to add the common functions for getting the TSC frequency of AMD family 17h and 19h CPUs/APUs and to provide TSC- based monotonic timer functionality to the build.
SOC_AMD_COMMON_BLOCK_HDA	soc/amd/common/block/hda	bool		Select this option to use AMD common High Definition Audio driver support.
SOC_AMD_COMMON_BLOCK_LPC	soc/amd/common/block/lpc	bool		Select this option to use the traditional LPC-ISA bridge at D14F3.
PROVIDES_ROM_SHARING	soc/amd/common/block/lpc	bool		Select this option if the LPC bridge supports ROM sharing.
SOC_AMD_COMMON_BLOCK_HAS_ESPI	soc/amd/common/block/lpc	bool		Select this option if platform supports eSPI using D14F3 configuration registers.
SOC_AMD_COMMON_BLOCK_USE_ESPI	soc/amd/common/block/lpc	bool		Select this option if mainboard uses eSPI instead of LPC (if supported by platform).
SOC_AMD_COMMON_BLOCK_UART	soc/amd/common/block/uart	bool		Select this option to add the common functions for setting up the UART configuration to the build.
SOC_AMD_COMMON_BLOCK_SMBUS	soc/amd/common/block/smbus	bool		Select this option to add FCH SMBus controller functions to the build.
SOC_AMD_COMMON_BLOCK_SMU	soc/amd/common/block/smu	bool		Select this option to add functions to communicate with the SMU to the build.
SOC_AMD_COMMON_BLOCK_AOAC	soc/amd/common/block/aoac	bool		Select this option to add the common functions for the AOAC block to the build.
SOC_AMD_COMMON_BLOCK_IOMMU	soc/amd/common/block/iommu	bool		Select this option to use AMD common IOMMU support.
SOC_INTEL_ELKHARTLAKE	soc/intel/elkhartlake	bool		Intel Elkhartlake support
DCACHE_RAM_SIZE	soc/intel/elkhartlake	int		The size of the cache-as-ram region required during bootblock and/or romstage.
DCACHE_BSP_STACK_SIZE	soc/intel/elkhartlake	hex		The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB).
FSP_TEMP_RAM_SIZE	soc/intel/elkhartlake	hex		The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup.
PCR_BASE_ADDRESS	soc/intel/elkhartlake	hex		This option allows you to select MMIO Base Address of sideband bus.
SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT	soc/intel/elkhartlake	int	Debug Consent for EHL	This is to control debug interface on SOC. Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details. Desired platform debug type are 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual
SOC_INTEL_ICELAKE	soc/intel/icelake	bool		Intel Icelake support
DCACHE_RAM_SIZE	soc/intel/icelake	bool		The size of the cache-as-ram region required during bootblock and/or romstage.
DCACHE_BSP_STACK_SIZE	soc/intel/icelake	hex		The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
FSP_TEMP_RAM_SIZE	soc/intel/icelake	hex		The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup.
PCR_BASE_ADDRESS	soc/intel/icelake	hex		This option allows you to select MMIO Base Address of sideband bus.
SOC_INTEL_ICELAKE_DEBUG_CONSENT	soc/intel/icelake	int	Debug Consent for ICL	This is to control debug interface on SOC. Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details. Desired platform debug types are 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual
PCR_BASE_ADDRESS	soc/intel/xeon_sp/skx	hex		This option allows you to select MMIO Base Address of sideband bus.
PCR_BASE_ADDRESS	soc/intel/xeon_sp/cpx	hex		This option allows you to select MMIO Base Address of sideband bus.
DCACHE_RAM_SIZE	soc/intel/xeon_sp/cpx	hex		The size of the cache-as-ram region required during bootblock and/or romstage. FSP-T reserves the upper 0x100 for FspReservedBuffer.
DCACHE_BSP_STACK_SIZE	soc/intel/xeon_sp/cpx	hex		The amount of anticipated stack usage in CAR by bootblock and other stages. It needs to include FSP-M stack requirement and CB romstage stack requirement. The integration documentation says this needs to be 256KiB, but practice show this needs to be a lot more.
FSP_TEMP_RAM_SIZE	soc/intel/xeon_sp/cpx	hex		The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. The FSP integration documentation says this needs to be at least 128KiB, but practice show this needs to be 256KiB or more.
INTEL_TXT_SINIT_SIZE	soc/intel/xeon_sp/cpx	hex		According to document number 572782 this needs to be 256KiB for the SINIT module and 64KiB for SINIT data.
INTEL_TXT_HEAP_SIZE	soc/intel/xeon_sp/cpx	hex		This must be 960KiB according to 572782.
SOC_INTEL_SKYLAKE_SP	soc/intel/xeon_sp	bool		Intel Skylake-SP support
SOC_INTEL_COOPERLAKE_SP	soc/intel/xeon_sp	bool		Intel Cooperlake-SP support
PCR_BASE_ADDRESS	soc/intel/xeon_sp	hex		This option allows you to select MMIO Base Address of sideband bus.
SOC_INTEL_BROADWELL	soc/intel/broadwell	bool		Intel Broadwell and Haswell ULT support.
BROADWELL_VBOOT_IN_BOOTBLOCK	soc/intel/broadwell	bool	Start verstage in bootblock	Broadwell can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. Broadwell however uses a mrc.bin to initialse memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region and back to the RW region after the binary is done.
DCACHE_RAM_SIZE	soc/intel/broadwell	hex		The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.
DCACHE_RAM_MRC_VAR_SIZE	soc/intel/broadwell	hex		The amount of cache-as-ram region required by the reference code.
DCACHE_BSP_STACK_SIZE	soc/intel/broadwell	hex		The amount of anticipated stack usage in CAR by bootblock and other stages.
HAVE_MRC	soc/intel/broadwell	bool	Add a Memory Reference Code binary	Select this option to add a Memory Reference Code binary to the resulting coreboot image. Note: Without this binary coreboot will not work
MRC_FILE	soc/intel/broadwell	string	Intel Memory Reference Code path and filename	The filename of the file to use as Memory Reference Code binary.
PRE_GRAPHICS_DELAY	soc/intel/broadwell	int	Graphics initialization delay in ms	On some systems, coreboot boots so fast that connected monitors (mostly TVs) won't be able to wake up fast enough to talk to the VBIOS. On those systems we need to wait for a bit before executing the VBIOS.
SERIRQ_CONTINUOUS_MODE	soc/intel/broadwell	bool		If you set this option to y, the serial IRQ machine will be operated in continuous mode.
HAVE_REFCODE_BLOB	soc/intel/broadwell	bool	An external reference code blob should be put into cbfs.	The reference code blob will be placed into cbfs.
REFCODE_BLOB_FILE	soc/intel/broadwell	string	Path and filename to reference code blob.	The path and filename to the file to be added to cbfs.
SOC_INTEL_ALDERLAKE	soc/intel/alderlake	bool		Intel Alderlake support
SOC_INTEL_ALDERLAKE_PCH_M	soc/intel/alderlake	bool		Choose this option if you have PCH-M chipset.
DCACHE_RAM_SIZE	soc/intel/alderlake	int		The size of the cache-as-ram region required during bootblock and/or romstage.
DCACHE_BSP_STACK_SIZE	soc/intel/alderlake	hex		The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement (~1KiB).
FSP_TEMP_RAM_SIZE	soc/intel/alderlake	hex		The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup.
PCR_BASE_ADDRESS	soc/intel/alderlake	hex		This option allows you to select MMIO Base Address of sideband bus.
SOC_INTEL_ALDERLAKE_DEBUG_CONSENT	soc/intel/alderlake	int	Debug Consent for ADL	This is to control debug interface on SOC. Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details. Desired platform debug type are 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual
SOC_INTEL_BAYTRAIL	soc/intel/baytrail	bool		Bay Trail M/D part support.
HAVE_MRC	soc/intel/baytrail	bool	Add a System Agent binary	Select this option to add a System Agent binary to the resulting coreboot image. Note: Without this binary coreboot will not work
MRC_FILE	soc/intel/baytrail	string	Intel System Agent path and filename	The path and filename of the file to use as System Agent binary.
DCACHE_RAM_SIZE	soc/intel/baytrail	hex		The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.
DCACHE_RAM_MRC_VAR_SIZE	soc/intel/baytrail	hex		The amount of cache-as-ram region required by the reference code.
ENABLE_BUILTIN_COM1	soc/intel/baytrail	bool	Enable builtin COM1 Serial Port	The PMC has a legacy COM1 serial port. Choose this option to configure the pads and enable it. This serial port can be used for the debug console.
HAVE_REFCODE_BLOB	soc/intel/baytrail	bool	Use a binary refcode blob instead of native ModPHY init	Use the ChromeBook refcode to intitialize high-speed PHYs instead of native code.
REFCODE_BLOB_FILE	soc/intel/baytrail	string	Path and filename to reference code blob.	The path and filename to the file to be added to cbfs.
SOC_INTEL_SKYLAKE	soc/intel/skylake	bool		Intel Skylake support
SOC_INTEL_KABYLAKE	soc/intel/skylake	bool		Intel Kabylake support
DCACHE_RAM_SIZE	soc/intel/skylake	hex		The size of the cache-as-ram region required during bootblock and/or romstage.
DCACHE_BSP_STACK_SIZE	soc/intel/skylake	hex		The amount of anticipated stack usage in CAR by bootblock and other stages.
EXCLUDE_NATIVE_SD_INTERFACE	soc/intel/skylake	bool		If you set this option to n, will not use native SD controller.
PCR_BASE_ADDRESS	soc/intel/skylake	hex		This option allows you to select MMIO Base Address of sideband bus.
SKYLAKE_SOC_PCH_H	soc/intel/skylake	bool		Choose this option if you have a PCH-H chipset.
NHLT_DMIC_1CH	soc/intel/skylake	bool		Include DSP firmware settings for 1 channel DMIC array.
NHLT_DMIC_2CH	soc/intel/skylake	bool		Include DSP firmware settings for 2 channel DMIC array.
NHLT_DMIC_4CH	soc/intel/skylake	bool		Include DSP firmware settings for 4 channel DMIC array.
NHLT_NAU88L25	soc/intel/skylake	bool		Include DSP firmware settings for nau88l25 headset codec.
NHLT_MAX98357	soc/intel/skylake	bool		Include DSP firmware settings for max98357 amplifier.
NHLT_MAX98373	soc/intel/skylake	bool		Include DSP firmware settings for max98373 amplifier.
NHLT_SSM4567	soc/intel/skylake	bool		Include DSP firmware settings for ssm4567 smart amplifier.
NHLT_RT5514	soc/intel/skylake	bool		Include DSP firmware settings for rt5514 DSP.
NHLT_RT5663	soc/intel/skylake	bool		Include DSP firmware settings for rt5663 headset codec.
NHLT_MAX98927	soc/intel/skylake	bool		Include DSP firmware settings for max98927 amplifier.
NHLT_DA7219	soc/intel/skylake	bool		Include DSP firmware settings for DA7219 headset codec.
NO_FADT_8042	soc/intel/skylake	bool		Choose this option if you want to disable 8042 Keyboard
SOC_INTEL_DENVERTON_NS	soc/intel/denverton_ns	bool		Intel Denverton-NS SoC support
FSP_T_ADDR	soc/intel/denverton_ns	hex	Intel FSP-T (temp RAM init) binary location	The memory location of the Intel FSP-T binary for this platform.
FSP_M_ADDR	soc/intel/denverton_ns	hex	Intel FSP-M (memory init) binary location	The memory location of the Intel FSP-M binary for this platform.
FSP_S_ADDR	soc/intel/denverton_ns	hex	Intel FSP-S (silicon init) binary location	The memory location of the Intel FSP-S binary for this platform.
PCR_BASE_ADDRESS	soc/intel/denverton_ns	hex		This option allows you to select MMIO Base Address of sideband bus.
NON_LEGACY_UART_MODE	soc/intel/denverton_ns	bool	Non Legacy Mode	Disable legacy UART mode
LEGACY_UART_MODE	soc/intel/denverton_ns	bool	Legacy Mode	Enable legacy UART mode select CONSOLE_SERIAL select DRIVERS_UART select DRIVERS_UART_8250IO
C_ENV_BOOTBLOCK_SIZE	soc/intel/denverton_ns	hex	Cache-as-ram implementation	This option allows you to select how cache-as-ram (CAR) is set up.
USE_DENVERTON_NS_CAR_NEM_ENHANCED	soc/intel/denverton_ns	bool	Enhanced Non-evict mode	A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. With NEM, if there is no physical memory behind the cached area, the modified data will be lost and NEM results will be inconsistent. ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced.
USE_DENVERTON_NS_FSP_CAR	soc/intel/denverton_ns	bool	Use FSP CAR	Use FSP APIs to initialize and tear down the Cache-As-Ram.
SOC_INTEL_BRASWELL	soc/intel/braswell	bool		Braswell M/D part support.
DCACHE_BSP_STACK_SIZE	soc/intel/braswell	hex		The amount of anticipated stack usage in CAR by bootblock and other stages.
DCACHE_RAM_SIZE	soc/intel/braswell	hex		The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.
ENABLE_BUILTIN_COM1	soc/intel/braswell	bool	Enable builtin COM1 Serial Port	The PMC has a legacy COM1 serial port. Choose this option to configure the pads and enable it. This serial port can be used for the debug console.
DISABLE_HPET	soc/intel/braswell	bool	Disable the HPET device	Enable this to disable the HPET support Solves the Linux MP-BIOS bug timer not connected.
USE_GOOGLE_FSP	soc/intel/braswell	bool		Select this to use Google's custom Braswell FSP header/binary instead of the public release on Github. Only google/cyan variants require this; all other boards should use the public release.
FSP_HEADER_PATH	soc/intel/braswell	string		Location of FSP header file FspUpdVpd.h
SOC_INTEL_APOLLOLAKE	soc/intel/apollolake	bool		Intel Apollolake support
SOC_INTEL_GEMINILAKE	soc/intel/apollolake	bool		Intel GLK support
TPM_ON_FAST_SPI	soc/intel/apollolake	bool		TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface.
PCR_BASE_ADDRESS	soc/intel/apollolake	hex		This option allows you to select MMIO Base Address of sideband bus.
DCACHE_RAM_SIZE	soc/intel/apollolake	hex		The size of the cache-as-ram region required during bootblock and/or romstage.
DCACHE_BSP_STACK_SIZE	soc/intel/apollolake	hex		The amount of anticipated stack usage in CAR by bootblock and other stages.
ROMSTAGE_ADDR	soc/intel/apollolake	hex		The base address (in CAR) where romstage should be linked
VERSTAGE_ADDR	soc/intel/apollolake	hex		The base address (in CAR) where verstage should be linked
FSP_M_ADDR	soc/intel/apollolake	hex		The address FSP-M will be relocated to during build time
NEED_LBP2	soc/intel/apollolake	bool	Write contents for logical boot partition 2.	Write the contents from a file into the logical boot partition 2 region defined by LBP2_FMAP_NAME.
LBP2_FMAP_NAME	soc/intel/apollolake	string	Name of FMAP region to put logical boot partition 2	Name of FMAP region to write logical boot partition 2 data.
LBP2_FROM_IFWI	soc/intel/apollolake	bool	Extract the LBP2 from the IFWI binary	The Logical Boot Partition will be automatically extracted from the supplied IFWI binary
LBP2_FILE_NAME	soc/intel/apollolake	string	Path of file to write to logical boot partition 2 region	Name of file to store in the logical boot partition 2 region.
NEED_IFWI	soc/intel/apollolake	bool	Write content into IFWI region	Write the content from a file into IFWI region defined by IFWI_FMAP_NAME.
IFWI_FMAP_NAME	soc/intel/apollolake	string	Name of FMAP region to pull IFWI into	Name of FMAP region to write IFWI.
IFWI_FILE_NAME	soc/intel/apollolake	string	Path of file to write to IFWI region	Name of file to store in the IFWI region.
NHLT_DMIC_1CH_16B	soc/intel/apollolake	bool		Include DSP firmware settings for 1 channel 16B DMIC array.
NHLT_DMIC_2CH_16B	soc/intel/apollolake	bool		Include DSP firmware settings for 2 channel 16B DMIC array.
NHLT_DMIC_4CH_16B	soc/intel/apollolake	bool		Include DSP firmware settings for 4 channel 16B DMIC array.
NHLT_MAX98357	soc/intel/apollolake	bool		Include DSP firmware settings for headset codec.
NHLT_DA7219	soc/intel/apollolake	bool		Include DSP firmware settings for headset codec.
NHLT_RT5682	soc/intel/apollolake	bool		Include DSP firmware settings for headset codec.
NHLT_RT5682	soc/intel/apollolake	bool	Cache-as-ram implementation	This option allows you to select how cache-as-ram (CAR) is set up.
CAR_NEM	soc/intel/apollolake	bool	Non-evict mode	Traditionally, CAR is set up by using Non-Evict mode. This method does not allow CAR and cache to co-exist, because cache fills are block in NEM mode.
CAR_CQOS	soc/intel/apollolake	bool	Cache Quality of Service	Cache Quality of Service allows more fine-grained control of cache usage. As result, it is possible to set up portion of L2 cache for CAR and use remainder for actual caching.
USE_APOLLOLAKE_FSP_CAR	soc/intel/apollolake	bool	Use FSP CAR	Use FSP APIs to initialize & tear down the Cache-As-Ram.
APL_SKIP_SET_POWER_LIMITS	soc/intel/apollolake	bool		Some Apollo Lake mainboards do not need the Running Average Power Limits (RAPL) algorithm for a constant power management. Set this config option to skip the RAPL configuration.
APL_SET_MIN_CLOCK_RATIO	soc/intel/apollolake	bool		If the power budget of the mainboard is limited, it can be useful to limit the CPU power dissipation at the cost of performance by setting the lowest possible CPU clock. Enable this option if you need smallest possible CPU clock. This setting can be overruled by the OS if it has an p-state driver which can adjust the clock to its need.
SOC_ESPI	soc/intel/apollolake	bool		Use eSPI bus instead of LPC
SOC_INTEL_JASPERLAKE	soc/intel/jasperlake	bool		Intel Jasperlake support
DCACHE_RAM_SIZE	soc/intel/jasperlake	bool		The size of the cache-as-ram region required during bootblock and/or romstage.
DCACHE_BSP_STACK_SIZE	soc/intel/jasperlake	hex		The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be sum of FSP-M stack requirement(192 KiB) and CB romstage stack requirement(~1KiB).
FSP_TEMP_RAM_SIZE	soc/intel/jasperlake	hex		The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup.
PCR_BASE_ADDRESS	soc/intel/jasperlake	hex		This option allows you to select MMIO Base Address of sideband bus.
SOC_INTEL_JASPERLAKE_DEBUG_CONSENT	soc/intel/jasperlake	int	Debug Consent for JSL	This is to control debug interface on SOC. Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details. Desired platform debug type are 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual
SOC_INTEL_QUARK	soc/intel/quark	bool		Intel Quark support
ENABLE_BUILTIN_HSUART0	soc/intel/quark	bool	Enable built-in HSUART0	The Quark SoC has two HSUART. Choose this option to configure the pads and enable HSUART0, which can be used for the debug console.
ENABLE_BUILTIN_HSUART1	soc/intel/quark	bool	Enable built-in HSUART1	The Quark SoC has two HSUART. Choose this option to configure the pads and enable HSUART1, which can be used for the debug console.
TTYS0_BASE	soc/intel/quark	hex	HSUART Base Address	Memory mapped MMIO of HSUART.
ENABLE_DEBUG_LED	soc/intel/quark	bool		Enable the use of the SD LED for early debugging before serial output is available. Setting this LED indicates that control has reached the desired check point.
ENABLE_DEBUG_LED_ESRAM	soc/intel/quark	bool	SD LED indicates ESRAM initialized	Indicate that ESRAM has been successfully initialized. If the SD LED does not light then the ESRAM initialization needs to be debugged.
ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY	soc/intel/quark	bool	SD LED indicates bootblock.c successfully entered	Indicate that bootblock_c_entry was entered. If the SD LED does not light then debug the code between ESRAM and bootblock_c_entry.
ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY	soc/intel/quark	bool	SD LED indicates bootblock_soc_early_init successfully entered	Indicate that bootblock_soc_early_init was entered. If the SD LED does not light then debug the code in bootblock_main_with_timestamp.
ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT	soc/intel/quark	bool	SD LED indicates bootblock_soc_early_init successfully exited	Indicate that bootblock_soc_early_init exited. If the SD LED does not light then debug the scripts in bootblock_soc_early_init.
ENABLE_DEBUG_LED_SOC_INIT_ENTRY	soc/intel/quark	bool	SD LED indicates bootblock_soc_init successfully entered	Indicate that bootblock_soc_init was entered. If the SD LED does not light then debug the code in bootblock_mainboard_early_init and console_init. If the SD LED does light but there is no serial then debug the serial port configuration and initialization.
DISPLAY_ESRAM_LAYOUT	soc/intel/quark	bool	Display ESRAM layout	Select this option to display coreboot's use of ESRAM.
CBFS_SIZE	soc/intel/quark	hex		Specify the size of the coreboot file system in the read-only (recovery) portion of the flash part. On Quark systems the firmware image stores more than just coreboot, including: - The chipset microcode (RMU) binary file located at 0xFFF00000 - Intel Trusted Execution Engine firmware
FSP_ESRAM_LOC	soc/intel/quark	hex		The location in ESRAM where a copy of the FSP binary is placed.
ADD_RMU_FILE	soc/intel/quark	bool	Should the RMU binary be added to the flash image?	The RMU file is required to get the chip out of reset.
RMU_FILE	soc/intel/quark	string		The path and filename of the Intel Quark RMU binary.
RMU_LOC	soc/intel/quark	hex		The location in CBFS that the RMU is located. It must match the strap-determined base address.
STORAGE_TEST	soc/intel/quark	bool	Test SD/MMC/eMMC card or device access	Read block 0 from each parition of the storage device. User must also enable one or both of COMMONLIB_STORAGE_SD or COMMONLIB_STORAGE_MMC.
I2C_DEBUG	soc/intel/quark	bool	Enable I2C debugging	Display the I2C segments and controller errors
SOC_INTEL_COFFEELAKE	soc/intel/cannonlake	bool		Intel Coffeelake support
SOC_INTEL_WHISKEYLAKE	soc/intel/cannonlake	bool		Intel Whiskeylake support
SOC_INTEL_COMETLAKE	soc/intel/cannonlake	bool		Intel Cometlake support
SOC_INTEL_CANNONLAKE_PCH_H	soc/intel/cannonlake	bool		Choose this option if you have a PCH-H chipset.
DCACHE_RAM_SIZE	soc/intel/cannonlake	int		The size of the cache-as-ram region required during bootblock and/or romstage.
DCACHE_BSP_STACK_SIZE	soc/intel/cannonlake	hex		The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
FSP_TEMP_RAM_SIZE	soc/intel/cannonlake	hex		The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup.
NHLT_DMIC_1CH_16B	soc/intel/cannonlake	bool		Include DSP firmware settings for 1 channel 16B DMIC array.
NHLT_DMIC_2CH_16B	soc/intel/cannonlake	bool		Include DSP firmware settings for 2 channel 16B DMIC array.
NHLT_DMIC_4CH_16B	soc/intel/cannonlake	bool		Include DSP firmware settings for 4 channel 16B DMIC array.
NHLT_MAX98357	soc/intel/cannonlake	bool		Include DSP firmware settings for headset codec.
NHLT_MAX98373	soc/intel/cannonlake	bool		Include DSP firmware settings for headset codec.
NHLT_DA7219	soc/intel/cannonlake	bool		Include DSP firmware settings for headset codec.
PCR_BASE_ADDRESS	soc/intel/cannonlake	hex		This option allows you to select MMIO Base Address of sideband bus.
MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE	soc/intel/cannonlake	bool		Select this if the board has a SD_PWR_ENABLE pin connected to a active high sensing load switch to turn on power to the card reader. This will enable a workaround in ASL _PS3 and _PS0 methods to force SD_PWR_ENABLE to stay low in D3.
MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE	soc/intel/cannonlake	bool	Cache-as-ram implementation	This option allows you to select how cache-as-ram (CAR) is set up.
USE_CANNONLAKE_CAR_NEM_ENHANCED	soc/intel/cannonlake	bool	Enhanced Non-evict mode	A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. With NEM, if there is no physical memory behind the cached area, the modified data will be lost and NEM results will be inconsistent. ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced.
USE_CANNONLAKE_FSP_CAR	soc/intel/cannonlake	bool	Use FSP CAR	Use FSP APIs to initialize and tear down the Cache-As-Ram.
SOC_INTEL_CANNONLAKE_DEBUG_CONSENT	soc/intel/cannonlake	int	Debug Consent for CNL	This is to control debug interface on SOC. Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details.
SOC_INTEL_TIGERLAKE	soc/intel/tigerlake	bool		Intel Tigerlake support
DCACHE_RAM_SIZE	soc/intel/tigerlake	bool		The size of the cache-as-ram region required during bootblock and/or romstage.
DCACHE_BSP_STACK_SIZE	soc/intel/tigerlake	hex		The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement (~1KiB).
FSP_TEMP_RAM_SIZE	soc/intel/tigerlake	hex		The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup.
PCR_BASE_ADDRESS	soc/intel/tigerlake	hex		This option allows you to select MMIO Base Address of sideband bus.
SOC_INTEL_TIGERLAKE_DEBUG_CONSENT	soc/intel/tigerlake	int	Debug Consent for TGL	This is to control debug interface on SOC. Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details. Desired platform debug type are 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual
EARLY_TCSS_DISPLAY	soc/intel/tigerlake	bool	Enable early TCSS display	Enable displays to be detected over Type-C ports during boot.
SOC_INTEL_COMMON	soc/intel/common.common	bool		common code for Intel SOCs
	soc/intel/common.common	(comment)		Intel SoC Common Code for IP blocks
SOC_INTEL_COMMON_BLOCK	soc/intel/common/block	bool		SoC driver for intel common IP code
SOC_INTEL_COMMON_BLOCK_SMM	soc/intel/common/block/smm	bool		Intel Processor common SMM support
SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP	soc/intel/common/block/smm	bool		Intel Processor trap flag if it is supported
SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE	soc/intel/common/block/smm	bool		Disable eSPI SMI source to prevent the embedded controller from asserting SMI while in firmware.
SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE	soc/intel/common/block/smm	bool	Enable TCO SMI	Enable TCO SMI source to e.g. handle case instrusion.
SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS	soc/intel/common/block/smm	int		Time in milliseconds that SLP_SMI for S5 waits for before enabling sleep. This is required to avoid any race between SLP_SMI and PWRBTN SMI.
HECI_DISABLE_USING_SMM	soc/intel/common/block/smm	bool		HECI disable using SMM. Select this option to make HECI disable using SMM mode, independent of dedicated UPD to perform HECI disable.
SOC_INTEL_COMMON_BLOCK_DSP	soc/intel/common/block/dsp	bool		Intel Processor common DSP support
SOC_INTEL_COMMON_BLOCK_CSE	soc/intel/common/block/cse	bool		Driver for communication with Converged Security Engine (CSE) over Host Embedded Controller Interface (HECI)
SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM	soc/intel/common/block/cse	bool		Use this config to include common CSE block to make HECI function disable in SMM mode
SOC_INTEL_CSE_LITE_SKU	soc/intel/common/block/cse	bool		Enables CSE Lite SKU
SOC_INTEL_CSE_RW_UPDATE	soc/intel/common/block/cse	bool	Enable the CSE RW Update Feature	This config will enable CSE RW firmware update feature and also will be used ensure all the required configs are provided by mainboard.
SOC_INTEL_CSE_FMAP_NAME	soc/intel/common/block/cse	string	Name of CSE Region in FMAP	Name of CSE region in FMAP
SOC_INTEL_CSE_RW_A_FMAP_NAME	soc/intel/common/block/cse	string	Location of CSE RW A in FMAP	Name of CSE RW A region in FMAP
SOC_INTEL_CSE_RW_B_FMAP_NAME	soc/intel/common/block/cse	string	Location of CSE RW B in FMAP	Name of CSE RW B region in FMAP
SOC_INTEL_CSE_RW_CBFS_NAME	soc/intel/common/block/cse	string	CBFS entry name for CSE RW blob	CBFS entry name for Intel CSE CBFS RW blob
SOC_INTEL_CSE_RW_METADATA_CBFS_NAME	soc/intel/common/block/cse	string	CBFS name for CSE RW metadata file	CBFS name for Intel CSE CBFS RW metadata file
SOC_INTEL_CSE_RW_FILE	soc/intel/common/block/cse	string	Intel CSE CBFS RW path and filename	Intel CSE CBFS RW blob path and file name
SOC_INTEL_CSE_RW_VERSION	soc/intel/common/block/cse	string	Intel CSE RW firmware version	This config contains the Intel CSE RW version of the blob that is provided by SOC_INTEL_CSE_RW_FILE config and the version must be set in the format major.minor.hotfix.build (ex: 14.0.40.1209).
SOC_INTEL_COMMON_BLOCK_THERMAL	soc/intel/common/block/thermal	bool		This option allows to configure PCH thermal registers for supported PCH.
SOC_INTEL_COMMON_BLOCK_CNVI	soc/intel/common/block/cnvi	bool		Common CNVI module for Intel PCH
SOC_INTEL_COMMON_BLOCK_SPI	soc/intel/common/block/spi	bool		Intel Processor common SPI support
SOC_INTEL_COMMON_BLOCK_SRAM	soc/intel/common/block/sram	bool		Intel Processor common SRAM support
SOC_INTEL_COMMON_BLOCK_PCIE	soc/intel/common/block/pcie	bool		Intel Processor common PCIE support
SOC_INTEL_COMMON_BLOCK_PCIE_RTD3	soc/intel/common/block/pcie/rtd3	bool		When enabled, this driver will add support for ACPI controlled Runtime D3 using GPIOs for power/reset control of the device attached to a PCIe root port.
PCIE_DEBUG_INFO	soc/intel/common/block/pcie	bool		Enable debug logs in PCIe module. Allows debug information on memory base and limit, prefetchable memory base and limit, prefetchable memory base upper 32 bits and prefetchable memory limit upper 32 bits.
SOC_INTEL_COMMON_BLOCK_I2C	soc/intel/common/block/i2c	bool		Intel Processor Common I2C support
SOC_INTEL_COMMON_BLOCK_DTT	soc/intel/common/block/dtt	bool		Minimal PCI Driver for enabling SSDT generation of Intel Dynamic Tuning Technology (DTT) policies and controls, also known as Intel DPTF (Dynamic Platform and Thermal Framework)
SOC_INTEL_COMMON_BLOCK_P2SB	soc/intel/common/block/p2sb	bool		Intel Processor common P2SB driver
SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG	soc/intel/common/block/chip	bool		Intel Processor common soc/chip configuration support
SOC_INTEL_COMMON_BLOCK_SCS	soc/intel/common/block/scs	bool		Intel Processor common storage and communication subsystem support
SOC_INTEL_COMMON_EARLY_MMC_WAKE	soc/intel/common/block/scs	bool		Send CMD1 early in romstage to improve boot time. It requires emmc DLL tuning parameters to be added to devicetree.cb
SOC_INTEL_COMMON_MMC_OVERRIDE	soc/intel/common/block/scs	bool		Override the MMC settings after FSP-S. It should be used only when there is no FSP UPDs for certain setting.
SOC_INTEL_COMMON_BLOCK_DMI	soc/intel/common/block/dmi	bool		Intel Processor common DMI support
SOC_INTEL_COMMON_BLOCK_GRAPHICS	soc/intel/common/block/graphics	bool		Intel Processor common Graphics support
SOC_INTEL_CONFIGURE_DDI_A_4_LANES	soc/intel/common/block/graphics	bool		Selected by platforms that require DDI-A bifurcation setup.
SOC_INTEL_DISABLE_IGD	soc/intel/common/block/graphics	bool	Disable Integrated GFX Controller (0:2:0)	Selected by mainboard user that need to skip IGD initialization where OS can only use one GPU hence need to disable IGD and don't need to run FSP GOP.
SOC_INTEL_COMMON_BLOCK_IPU	soc/intel/common/block/ipu	bool		Intel Image Processing Unit driver
SOC_INTEL_COMMON_BLOCK_FAST_SPI	soc/intel/common/block/fast_spi	bool		Intel Processor common FAST_SPI support
FAST_SPI_DISABLE_WRITE_STATUS	soc/intel/common/block/fast_spi	bool	Disable write status SPI opcode	Disable the write status SPI opcode in Intel Fast SPI block.
FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW	soc/intel/common/block/fast_spi	bool		Fast SPI controller on the platform supports additional window for memory mapping BIOS region (region 1) on the SPI flash beyond the standard limit of 16MiB. Depending upon the size of the SPI flash part used by the mainboard, two decode windows will be enabled: 1. Fixed decode window up to a maximum size of 16MiB under 4G boundary. 2. Extended decode window up to a maximum size provided by the platform to map the rest of the BIOS region. SoC selecting this config is expected to provide the base and maximum size of the extended window in the host address space using configs EXT_BIOS_WIN_BASE and EXT_BIOS_WIN_SIZE.
EXT_BIOS_WIN_BASE	soc/intel/common/block/fast_spi	hex		If an additional window for mapping BIOS region greater than 16MiB is supported, then this config is used to provide the base address reserved for the mapping. Since the mapping is done at the top of the window, depending upon the size of the BIOS region, the actual base address configured in the fast SPI controller can be higher at runtime.
EXT_BIOS_WIN_SIZE	soc/intel/common/block/fast_spi	hex		Maximum size of the extended window reserved for mapping BIOS region greater than 16MiB. The actual mapped window might be smaller depending upon the size of the BIOS region.
SOC_INTEL_COMMON_BLOCK_ITSS	soc/intel/common/block/itss	bool		Intel Processor common interrupt timer subsystem support
SOC_INTEL_COMMON_BLOCK_GPIO	soc/intel/common/block/gpio	bool		Intel Processor common GPIO support
SOC_INTEL_COMMON_BLOCK_SATA	soc/intel/common/block/sata	bool		Common SATA module for Intel PCH
SOC_INTEL_COMMON_BLOCK_XHCI	soc/intel/common/block/xhci	bool		Intel Processor common XHCI support
SOC_INTEL_COMMON_BLOCK_XHCI_ELOG	soc/intel/common/block/xhci	bool		Set this option to identify if XHCI caused a wake up and log that information into the event log.
SOC_INTEL_COMMON_BLOCK_ACPI	soc/intel/common/block/acpi	bool		Intel Processor common code for ACPI
SOC_INTEL_COMMON_BLOCK_ACPI_LPIT	soc/intel/common/block/acpi	bool		Generate LPIT table with LPI state entries.
SOC_INTEL_COMMON_BLOCK_ACPI_CPPC	soc/intel/common/block/acpi	bool		Generate CPPC entries for Intel SpeedShift
SOC_INTEL_COMMON_BLOCK_RTC	soc/intel/common/block/rtc	bool		Intel Processor common RTC support
SOC_INTEL_COMMON_BLOCK_TIMER	soc/intel/common/block/timer	bool		Intel Processor common TIMER support
USE_LEGACY_8254_TIMER	soc/intel/common/block/timer	bool	Use Legacy 8254 Timer	Setting this makes the Legacy 8254 Timer available by disabling clock gating. This needs to be enabled in order to boot a legacy BIOS or OS not supporting other timers like PM timer or TSC. While SeaBIOS does not require this timer anymore, it is needed when OpRoms are being used. Disable this setting to save power, when the timer is not needed.
SOC_INTEL_COMMON_BLOCK_XDCI	soc/intel/common/block/xdci	bool		Intel Processor common XDCI support
SOC_INTEL_COMMON_BLOCK_CPU	soc/intel/common/block/cpu	bool		This option selects Intel Common CPU Model support code which provides various CPU related APIs which are common between all Intel Processor families. Common CPU code is supported for SOCs starting from SKL,KBL,APL, and future.
SOC_INTEL_COMMON_BLOCK_CPU_MPINIT	soc/intel/common/block/cpu	bool		This option selects Intel Common CPU MP Init code. In this common MP Init mechanism, the MP Init is occurring before calling FSP Silicon Init. Hence, MP Init will be pulled to BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is ensured that all MTRRs are re-programmed based on the DRAM resource settings.
SOC_INTEL_COMMON_BLOCK_CAR	soc/intel/common/block/cpu	bool		This option allows you to select how cache-as-ram (CAR) is set up.
INTEL_CAR_NEM	soc/intel/common/block/cpu	bool		Traditionally, CAR is set up by using Non-Evict mode. This method does not allow CAR and cache to co-exist, because cache fills are blocked in NEM.
INTEL_CAR_CQOS	soc/intel/common/block/cpu	bool		Cache Quality of Service allows more fine-grained control of cache usage. As result, it is possible to set up a portion of L2 cache for CAR and use the remainder for actual caching.
INTEL_CAR_NEM_ENHANCED	soc/intel/common/block/cpu	bool		A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. With NEM, if there is no physical memory behind the cached area, the modified data will be lost and NEM results will be inconsistent. ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced.
CAR_HAS_SF_MASKS	soc/intel/common/block/cpu	bool		In the case of non-inclusive cache architecture Snoop Filter MSR IA32_L3_SF_MASK_x programming is required along with the data ways. This is applicable for TGL and beyond.
COS_MAPPED_TO_MSB	soc/intel/common/block/cpu	bool		On TGL and JSL platform the class of service configuration is mapped to MSB of MSR IA32_PQR_ASSOC.
USE_INTEL_FSP_MP_INIT	soc/intel/common/block/cpu	bool	Perform MP Initialization by FSP	This option allows FSP to perform multiprocessor initialization.
USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI	soc/intel/common/block/cpu	bool	Perform MP Initialization by FSP using coreboot MP PPI service	This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization.
INTEL_TME	soc/intel/common/block/cpu	bool	Total Memory Encryption (TME)/Multi-key TME (MKTME)	Enable Total Memory Encryption (TME)/Multi-key TME (MKTME). The spec is available at "https://software.intel.com/sites/default/files/managed/a5 /16/Multi-Key-Total-Memory-Encryption-Spec.pdf". If CPU supports TME, it would get enabled. If CPU supports MKTME, this same config option enables MKTME.
CPU_XTAL_HZ	soc/intel/common/block/cpu	int		Base clock which virtually everything runs on.
CPU_SUPPORTS_PM_TIMER_EMULATION	soc/intel/common/block/cpu	bool		Select this if the SoC's ucode supports PM ACPI timer emulation (Common timer Copy), which is required to be able to disable the TCO PM ACPI timer for power saving.
SOC_INTEL_COMMON_BLOCK_POWER_LIMIT	soc/intel/common/block/power_limit	bool		This option allows to configure processor power limit values.
SOC_INTEL_COMMON_BLOCK_PCR	soc/intel/common/block/pcr	bool		Intel Processor common Private configuration registers (PCR)
PCR_COMMON_IOSF_1_0	soc/intel/common/block/pcr	bool		The mapping of addresses via the SBREG_BAR assumes the IOSF-SB agents are using 32-bit aligned accesses for their configuration registers. For IOSF versions greater than 1_0, IOSF-SB agents can use any access (8/16/32 bit aligned) for their configuration registers
SOC_INTEL_COMMON_BLOCK_HDA	soc/intel/common/block/hda	bool		Intel Processor common High Definition Audio driver support
SOC_INTEL_COMMON_BLOCK_HDA_VERB	soc/intel/common/block/hda	bool		Enable initialization of HDA codecs.
SOC_INTEL_COMMON_BLOCK_GSPI	soc/intel/common/block/gspi	bool		Intel Processor Common GSPI support
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ	soc/intel/common/block/gspi	int		The input clock speed into the SPI controller IP block, in MHz. No default is set here as this is an SOC-specific value and must be provided by the SOC.
SOC_INTEL_COMMON_BLOCK_GSPI_MAX	soc/intel/common/block/gspi	int		Maximum number of GSPI controllers supported by the PCH. SoC must define this config if SOC_INTEL_COMMON_BLOCK_GSPI is selected.
SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2	soc/intel/common/block/gspi	bool		Intel Processor Common GSPI support with quirks to handle SPI_CS_CONTROL changes introduced in CNL.
SOC_INTEL_COMMON_BLOCK_LPC	soc/intel/common/block/lpc	bool		Use common LPC code for platform. Only soc specific code needs to be implemented as per requirement.
SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE	soc/intel/common/block/lpc	bool		By default COMA range to LPC is enable. COMB range to LPC is optional and should select based on platform dedicated selection.
SOC_INTEL_COMMON_BLOCK_UART	soc/intel/common/block/uart	bool		Intel Processor common UART support
INTEL_LPSS_UART_FOR_CONSOLE	soc/intel/common/block/uart	bool		Selected by mainboards that use one of the SoC's LPSS UARTS for the coreboot console. WARNING: UART_FOR_CONSOLE has to be set to a correct value, otherwise wrong pad configurations might be selected.
SOC_INTEL_COMMON_BLOCK_PMC	soc/intel/common/block/pmc	bool		Intel Processor common code for Power Management controller(PMC) subsystem
SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE	soc/intel/common/block/pmc	bool		Select this on platforms where the PMC device is discoverable when scanning busses.
PMC_INVALID_READ_AFTER_WRITE	soc/intel/common/block/pmc	bool		Enable this for PMC devices where a read back of ACPI BAR and IO access bit does not return the previously written value.
PMC_IPC_ACPI_INTERFACE	soc/intel/common/block/pmc	bool		Enable this to have the PMC IPC mailbox ACPI interface added to the SSDT for use by other drivers.
PMC_GLOBAL_RESET_ENABLE_LOCK	soc/intel/common/block/pmc	bool		Enable this for PMC devices where the reset configuration and lock register is located under PMC BASE at offset ETR. Note that the reset register is still at 0xCF9 this only controls the enable and lock feature.
PMC_LOW_POWER_MODE_PROGRAM	soc/intel/common/block/pmc	bool		Enable this for PMC devices to perform registers programming to ensure low power in active idle scenario.
PM_ACPI_TIMER_OPTIONAL	soc/intel/common/block/pmc	bool		This needs to be selected by SoCs, where the hardware PM Timer can be disabled, to show the ACPI PM Timer Kconfig in menuconfig.
USE_PM_ACPI_TIMER	soc/intel/common/block/pmc	bool	Enable ACPI PM timer	This should be disabled for devices running on battery since it can draw much power. Further, it must be disabled, if S0ix is enabled. Disabling this option also stops the hardware TCO timer and makes the TCO watchdog unavailable.
SOC_INTEL_COMMON_BLOCK_LPSS	soc/intel/common/block/lpss	bool		Intel Processor common LPSS support
SOC_INTEL_COMMON_BLOCK_USB4	soc/intel/common/block/usb4	bool		Minimal PCI Driver for enabling SSDT generation for the DMA component of Intel Thunderbolt/USB4 ports.
SOC_INTEL_COMMON_BLOCK_USB4_PCIE	soc/intel/common/block/usb4	bool		Chip driver for adding PCI ops and SSDT generation for common Intel USB4/Thunderbolt root ports.
SOC_INTEL_COMMON_BLOCK_USB4_XHCI	soc/intel/common/block/usb4	bool		Minimal PCI driver for adding PCI ops and SSDT generation for common Intel USB4/Thunderbolt North XHCI ports.
SOC_INTEL_COMMON_BLOCK_SA	soc/intel/common/block/systemagent	bool		Intel Processor common System Agent support
SA_PCIEX_LENGTH	soc/intel/common/block/systemagent	hex		This option allows you to select length of PCIEX region.
SA_ENABLE_IMR	soc/intel/common/block/systemagent	bool		This option allows you to add the isolated memory ranges (IMRs).
SA_ENABLE_DPR	soc/intel/common/block/systemagent	bool		This option allows you to add the DMA Protected Range (DPR).
SOC_INTEL_COMMON_BLOCK_SMBUS	soc/intel/common/block/smbus	bool		Intel Processor common SMBus support
SOC_INTEL_COMMON_BLOCK_TCO	soc/intel/common/block/smbus	bool		Intel Processor common TCO support
SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS	soc/intel/common/block/smbus	bool		Select this config to enable TCO BAR through SMBUS
SOC_INTEL_COMMON_BLOCK_SGX	soc/intel/common/block/sgx	bool		Intel Processor common SGX support
SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY	soc/intel/common/block/sgx	bool		Lock memory before SGX activation. This is only needed if MCHECK does not do it.
SOC_INTEL_COMMON_BLOCK_SGX_ENABLE	soc/intel/common/block/sgx	bool	Enable Software Guard Extensions (SGX) if available	Intel Software Guard Extensions (SGX) is a set of new CPU instructions that can be used by applications to set aside private regions (so-called Secure Enclaves) of code and data. SGX will only be enabled when supported by the CPU!
SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE	soc/intel/common/block/sgx	int	PRMRR size	PRMRR (Protected Memory Range) is the space in RAM that is used to provide a protected memory area (e.g. for the Intel SGX Secure Enclaves). The memory region is accessible only by the processor itself to protect the data from unauthorized access. This option selects the maximum size that gets reserved. Depending on the SoC a lower, compatible value may be chosen at runtime as not all values are supported on all families.
	soc/intel/common.common	(comment)		Intel SoC Common PCH Code
SOC_INTEL_COMMON_PCH_BASE	soc/intel/common/pch	bool		All common PCH code blocks between Gen-6 till latest-PCH should be part of this directory. A SoC Kconfig might select this option to include base PCH package while building new SOC block. Currently majority of common IP code blocks are part of soc/intel/common/block/ and SoC Kconfig just select those Kconfig option. Addition to that SoC code now having option to select required base PCH block to include common IP block.
SOC_INTEL_COMMON_PCH_LOCKDOWN	soc/intel/common/pch/lockdown	bool		This option allows to have chipset lockdown for DMI, FAST_SPI and soc_lockdown_config() to implement any additional lockdown as PMC, LPC for supported PCH.
	soc/intel/common.common	(comment)		Intel SoC Common coreboot stages and non-IP blocks
SOC_INTEL_COMMON_BASECODE	soc/intel/common/basecode	bool		Common coreboot stages and non-IP block for Intel platform
ACPI_CONSOLE	soc/intel/common.common	bool		Provide a mechanism for serial console based ACPI debug.
PAVP	soc/intel/common.common	bool	Enable PAVP (Protected Audio-Video Path) support	Protected Audio-Video Path is an Intel technology used to enforce digital rights protections on multimedia content. Streaming or other media playback services may require it to be enabled for correct functioning. Users might disable PAVP if the concept of digital rights management (DRM) offends them, or if they have concerns about the security of the Management Engine, which is where this technology is implemented. Set this option to n to disable support.
MMA	soc/intel/common.common	bool	Enable MMA (Memory Margin Analysis) support for Intel Core	Set this option to y to enable MMA (Memory Margin Analysis) support
TPM_TIS_ACPI_INTERRUPT	soc/intel/common.common	int		acpi_get_gpe() is used to provide interrupt status to TPM layer. This option specifies the GPE number.
SOC_INTEL_DEBUG_CONSENT	soc/intel/common.common	bool	Enable SOC debug interface	Set this option to enable default debug interface of SoC such as DBC or DCI.
INTEL_HAS_TOP_SWAP	soc/intel	bool		Set this config if the Intel SoC supports top swap feature
INTEL_ADD_TOP_SWAP_BOOTBLOCK	soc/intel	bool	Include a Top swap bootblock	Intel PCH/Southbridges have feature that it is possible to have the southbridge/PCH look for the bootblock at a 64K or 128K/256K/512K/1MB (in case of newer SoCs) offset instead of the usual top of flash. Select this to put a 'second' bootblock.
INTEL_TOP_SWAP_BOOTBLOCK_SIZE	soc/intel	hex	Size of top swap boot block	Set this config to a supported topswap size. Valid sizes: 0x10000 0x20000 0x40000 0x80000 0x100000
INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG	soc/intel	string		Use this config to specify the name of a FMAP region (which should hold a microcode) whose address as the first entry in the topswap FIT. This is useful in creating a asymmetric FIT in top swap bootblock than the one in non-topswap bootblock. This string will be passed onto ifittool (-A -n option). ifittool will not parse the region for MCU entries, and only locate the region and insert its address into FIT.
RK3399_SPREAD_SPECTRUM_DDR	soc/rockchip/rk3399	bool	Spread-spectrum DDR clock	Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to modulate the frequency of the Silicon Creations' Fractional PLL in order to reduce EMI.
SOC_EXAMPLE_MIN86	soc/example/min86	bool		This example SoC code along with the example/min86 mainboard should serve as a minimal example how a buildable x86 SoC code base can look like. This can serve, for instance, as a basis to add new SoCs to coreboot. Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes.
MAINBOARD_DO_DSI_INIT	soc/nvidia/tegra210	bool	Use dsi graphics interface	Initialize dsi display
MAINBOARD_DO_SOR_INIT	soc/nvidia/tegra210	bool	Use dp graphics interface	Initialize dp display
CONSOLE_SERIAL_TEGRA210_UARTA	soc/nvidia/tegra210	bool	UARTA	Serial console on UART A.
CONSOLE_SERIAL_TEGRA210_UARTB	soc/nvidia/tegra210	bool	UARTB	Serial console on UART B.
CONSOLE_SERIAL_TEGRA210_UARTC	soc/nvidia/tegra210	bool	UARTC	Serial console on UART C.
CONSOLE_SERIAL_TEGRA210_UARTD	soc/nvidia/tegra210	bool	UARTD	Serial console on UART D.
CONSOLE_SERIAL_TEGRA210_UARTE	soc/nvidia/tegra210	bool	UARTE	Serial console on UART E.
CONSOLE_SERIAL_TEGRA210_UART_ADDRESS	soc/nvidia/tegra210	hex		Map the UART names to the respective MMIO addres.
BOOTROM_SDRAM_INIT	soc/nvidia/tegra210	bool	SoC BootROM does SDRAM init with full BCT	Use during Foster LPDDR4 bringup.
TRUSTZONE_CARVEOUT_SIZE_MB	soc/nvidia/tegra210	hex	Size of Trust Zone region	Size of Trust Zone area in MiB to reserve in memory map.
TTB_SIZE_MB	soc/nvidia/tegra210	hex	Size of TTB	Maximum size of Translation Table Buffer in MiB.
SEC_COMPONENT_SIZE_MB	soc/nvidia/tegra210	hex	Size of resident EL3 components	Maximum size of resident EL3 components in MiB including BL31 and Secure OS.
HAVE_MTC	soc/nvidia/tegra210	bool	Add external Memory controller Training Code binary	Select this option to add emc training firmware
MTC_FILE	soc/nvidia/tegra210	string	tegra mtc firmware filename	The filename of the mtc firmware
MTC_DIRECTORY	soc/nvidia/tegra210	string	Directory where MTC firmware file is located	Path to directory where MTC firmware file is located.
MTC_ADDRESS	soc/nvidia/tegra210	hex		The DRAM location where MTC firmware to be loaded in. This location needs to be consistent with the location defined in tegra_mtc.ld
	toplevel	(comment)		CPU
PARALLEL_MP	cpu/x86	bool		This option uses common MP infrastructure for bringing up APs in parallel. It additionally provides a more flexible mechanism for sequencing the steps of bringing up the APs.
PARALLEL_MP_AP_WORK	cpu/x86	bool		Allow APs to do other work after initialization instead of going to sleep.
LAPIC_MONOTONIC_TIMER	cpu/x86	bool		Expose monotonic time using the local APIC.
TSC_MONOTONIC_TIMER	cpu/x86	bool		Expose monotonic time using the TSC.
TSC_SYNC_LFENCE	cpu/x86	bool		The CPU driver should select this if the CPU needs to execute an lfence instruction in order to synchronize rdtsc. This is true for all modern AMD CPUs.
TSC_SYNC_MFENCE	cpu/x86	bool		The CPU driver should select this if the CPU needs to execute an mfence instruction in order to synchronize rdtsc. This is true for all modern Intel CPUs.
SETUP_XIP_CACHE	cpu/x86	bool		Select this option to set up an MTRR to cache XIP stages loaded from the bootblock. This is useful on platforms lacking a non-eviction mode and therefore need to be careful to avoid eviction.
SMM_MODULE_HEAP_SIZE	cpu/x86	hex		This option determines the size of the heap within the SMM handler modules.
SMM_MODULE_STACK_SIZE	cpu/x86	hex		This option determines the size of the stack within the SMM handler modules.
SMM_STUB_STACK_SIZE	cpu/x86	hex		This option determines the size of the stack within the SMM handler modules.
X86_SMM_LOADER_VERSION2	cpu/x86	bool		This option enables SMM module loader that works with server platforms which may contain more than 32 CPU threads.
SERIALIZED_SMM_INITIALIZATION	cpu/x86	bool		On some CPUs, there is a race condition in SMM. This can occur when both hyperthreads change SMM state variables in parallel without coordination. Setting this option serializes the SMM initialization to avoid an ugly hang in the boot process at the cost of a slightly longer boot time.
X86_AMD_FIXED_MTRRS	cpu/x86	bool		This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs.
X86_AMD_INIT_SIPI	cpu/x86	bool		This option limits the number of SIPI signals sent during during the common AP setup. Intel documentation specifies an INIT SIPI SIPI sequence, however this doesn't work on some AMD platforms.
SOC_SETS_MSRS	cpu/x86	bool		The SoC requires different access methods for reading and writing the MSRs. Use SoC specific routines to handle the MSR access.
ENABLE_MRC_CACHE	cpu/amd/agesa	bool	Use cached memory configuration	Try to restore memory training results from non-volatile memory.
FORCE_AM1_SOCKET_SUPPORT	cpu/amd/agesa/family16kb	bool		Force AGESA to ignore package type mismatch between CPU and northbridge in memory code. This enables Socket AM1 support with current AGESA version for Kabini platform. Enable this option only if you have Socket AM1 board. Note that the AGESA release shipped with coreboot does not officially support the AM1 socket. Selecting this option might damage your hardware.
CPU_INTEL_SOCKET_FCBGA559	cpu/intel/socket_FCBGA559	bool		Select this socket on Intel Pineview
DCACHE_BSP_STACK_SIZE	cpu/intel/socket_FCBGA559	hex		The amount of anticipated stack usage in CAR by bootblock and other stages.
CPU_INTEL_FIRMWARE_INTERFACE_TABLE	cpu/intel/fit	None		This option selects building a Firmware Interface Table (FIT).
CPU_INTEL_NUM_FIT_ENTRIES	cpu/intel/fit	int		This option selects the number of empty entries in the FIT table.
CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED	cpu/intel/turbo	None		This option indicates that the turbo mode setting is not package scoped. i.e. enable_turbo() needs to be called on not just the bsp
SET_IA32_FC_LOCK_BIT	cpu/intel/common	bool	Set IA32_FEATURE_CONTROL lock bit	Although the Intel manual says you must set the lock bit in addition to the VMX bit in order for VMX to work, this isn't strictly true, so we have the option to leave it unlocked and allow the OS (e.g. Linux) to manage things itself. This is beneficial for testing purposes as there is no need to reflash the firmware just to toggle the lock bit. However, leaving the lock bit unset will break Windows' detection of VMX support and built-in virtualization features like Hyper-V.
SET_MSR_AESNI_LOCK_BIT	cpu/intel/common	bool	Lock the AES-NI enablement state	This config sets the AES-NI lock bit, if available, to prevent any further change of AES-NI enablement. This may be disabled for e.g. testing or debugging.
MICROCODE_UPDATE_PRE_RAM	cpu/intel/microcode	bool		Select this option if you want to update the microcode during the cache as RAM setup.
CPU_HAS_L2_ENABLE_MSR	cpu/intel/car/non-evict	bool		Select this in Kconfig of CPU sockets/SOC where the CPU has an MSR to enable the L2 CPU cache
SMP	cpu	bool		This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems.
MMX	cpu	bool		Select MMX in your socket or model Kconfig if your CPU has MMX streaming SIMD instructions.
SSE	cpu	bool		Select SSE in your socket or model Kconfig if your CPU has SSE streaming SIMD instructions.
SSE2	cpu	bool		Select SSE2 in your socket or model Kconfig if your CPU has SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available.
USES_MICROCODE_HEADER_FILES	cpu	bool		This is selected by a board or chipset to set the default for the microcode source choice to a list of external microcode headers
MICROCODE_BLOB_NOT_IN_BLOB_REPO	cpu	bool		Selected by platforms that don't maintain microcode updates in the blobs repo yet.
MICROCODE_BLOB_NOT_HOOKED_UP	cpu	bool		Selected by platforms that haven't hooked microcode updates up yet.
MICROCODE_BLOB_UNDISCLOSED	cpu	bool		Selected by work-in-progress platforms that don't have microcode updates available yet.
USE_CPU_MICROCODE_CBFS_BINS	cpu	bool		Automatically selected below to add binary microcode files (`cpu_microcode_bins` in the makefiles) to CBFS.
CPU_MICROCODE_CBFS_DEFAULT_BINS	cpu	bool	Generate from tree	Select this option if you want microcode updates to be assembled when building coreboot and included in the final image as a separate CBFS file. Microcode will not be hard-coded into ramstage. The microcode file may be removed from the ROM image at a later time with cbfstool, if desired. If unsure, select this option.
CPU_MICROCODE_CBFS_EXTERNAL_BINS	cpu	bool	Include external microcode binary	Select this option if you want to include external binary files in the CPUs native format. They will be included as a separate file in CBFS. A word of caution: only select this option if you are sure the microcode that you have is newer than the microcode shipping with coreboot. The microcode file may be removed from the ROM image at a later time with cbfstool, if desired. If unsure, and applicable, select "Generate from tree"
CPU_MICROCODE_CBFS_EXTERNAL_HEADER	cpu	bool	Include external microcode header files	Select this option if you want to include external c header files containing the CPU microcode. This will be included as a separate file in CBFS. A word of caution: only select this option if you are sure the microcode that you have is newer than the microcode shipping with coreboot. The microcode file may be removed from the ROM image at a later time with cbfstool, if desired. If unsure, and applicable, select "Generate from tree"
CPU_MICROCODE_CBFS_NONE	cpu	bool	Do not include microcode updates	Select this option if you do not want CPU microcode included in CBFS. Microcode may be added to the ROM image at a later time with cbfstool, if desired. If unsure, and applicable, select "Generate from tree" The GOOD: Microcode updates intend to solve issues that have been discovered after CPU production. The expected effect is that systems work as intended with the updated microcode, but we have also seen cases where issues were solved by not applying microcode updates. The BAD: Note that some operating system include these same microcode patches, so you may need to also disable microcode updates in your operating system for this option to have an effect. The UGLY: A word of CAUTION: some CPUs depend on microcode updates to function correctly. Not updating the microcode may leave the CPU operating at less than optimal performance, or may cause outright hangups. There are CPUs where coreboot cannot properly initialize the CPU without microcode updates For example, if running with the factory microcode, some Intel SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs will hang when changing the frequency. Make sure you have a way of flashing the ROM externally before selecting this option.
CPU_MICROCODE_MULTIPLE_FILES	cpu	bool		Select this option to install separate microcode container files into CBFS instead of using the traditional monolithic microcode file format.
CPU_MICROCODE_HEADER_FILES	cpu	string	List of space separated microcode header files with the path	A list of one or more microcode header files with path from the coreboot directory. These should be separated by spaces.
CPU_UCODE_BINARIES	cpu	string	Microcode binary path and filename	Some platforms have microcode in the blobs directory, and these can be hardcoded in the makefiles. For platforms with microcode binaries that aren't in the makefile, set this option to pull in the microcode. This should contain the full path of the file for one or more microcode binary files to include, separated by spaces. If unsure, leave this blank.
	toplevel	(comment)		Northbridge
BOTTOMIO_POSITION	northbridge/amd/agesa	hex	Bottom of 32-bit IO space	If PCI peripherals with big BARs are connected to the system the bottom of the IO must be decreased to allocate such devices. Declare the beginning of the 128MB-aligned MMIO region. This option is useful when PCI peripherals requesting large address ranges are present, for example, graphic cards.
VGA_BIOS_ID	northbridge/amd/agesa/family16kb	string		The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.
BOTTOMIO_POSITION	northbridge/amd/pi	hex	Bottom of 32-bit IO space	If PCI peripherals with big BARs are connected to the system the bottom of the IO must be decreased to allocate such devices. Declare the beginning of the 128MB-aligned MMIO region. This option is useful when PCI peripherals requesting large address ranges are present.
VGA_BIOS_ID	northbridge/amd/pi/00630F01	string		The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.
VGA_BIOS_ID	northbridge/amd/pi/00730F01	string		The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.
DCACHE_BSP_STACK_SIZE	northbridge/intel/ironlake	hex		The amount of anticipated stack usage in CAR by bootblock and other stages.
SANDYBRIDGE_VBOOT_IN_ROMSTAGE	northbridge/intel/sandybridge	bool		Selected by boards to force VBOOT_STARTS_IN_ROMSTAGE.
SANDYBRIDGE_VBOOT_IN_BOOTBLOCK	northbridge/intel/sandybridge	bool	Start verstage in bootblock	Sandy Bridge can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. Sandy Bridge however uses a mrc.bin to initialize memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region and back to the RW region after the binary is done.
USE_NATIVE_RAMINIT	northbridge/intel/sandybridge	bool	Use native raminit	Select if you want to use coreboot implementation of raminit rather than System Agent/MRC.bin. You should answer Y.
NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES	northbridge/intel/sandybridge	bool	Ignore vendor programmed fuses that limit max. DRAM frequency	Ignore the mainboard's vendor programmed fuses that might limit the maximum DRAM frequency. By selecting this option the fuses will be ignored and the only limits on DRAM frequency are set by RAM's SPD and hard fuses in southbridge's clockgen. Disabled by default as it might causes system instability. Handle with care!
NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS	northbridge/intel/sandybridge	bool	Ignore XMP profile max DIMMs per channel	Ignore the max DIMMs per channel restriciton defined in XMP profiles. Disabled by default as it might cause system instability. Handle with care!
NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE	northbridge/intel/sandybridge	bool	Ignore XMP profile requested voltage	Native raminit only supports 1.5V operation, but there are DIMMs which request 1.65V operation in XMP profiles. This option allows raminit to use these XMP profiles anyway, instead of falling back to non-XMP settings. Disabled by default because it allows forcing memory to run out of specification. Consider this to be an overclocking option. Handle with care!
MMCONF_BASE_ADDRESS	northbridge/intel/sandybridge	hex		The MRC blob requires it to be at 0xf0000000.
DCACHE_BSP_STACK_SIZE	northbridge/intel/sandybridge	hex		The amount of BSP stack anticipated in bootblock and other stages.
RAMINIT_ALWAYS_ALLOW_DLL_OFF	northbridge/intel/sandybridge	bool	Also enable memory DLL-off mode on desktops and servers	If enabled, allow enabling DLL-off mode for platforms other than mobile. Saves power at the expense of higher exit latencies. Has no effect on mobile platforms, where DLL-off is always allowed. Power down is disabled for stability when running at high clocks.
RAMINIT_ENABLE_ECC	northbridge/intel/sandybridge	bool	Enable ECC if supported	Enable ECC if supported by both, host and RAM.
MRC_FILE	northbridge/intel/sandybridge	string	Intel System Agent path and filename	The path and filename of the file to use as System Agent binary.
SDRAMPWR_4DIMM	northbridge/intel/i440bx	bool		This option affects how the SDRAMC register is programmed. Memory clock signals will not be routed properly if this option is set wrong. If your board has 4 DIMM slots, you must use select this option, in your Kconfig file of the board. On boards with 3 DIMM slots, do _not_ select this option.
I945_LVDS	northbridge/intel/i945	string		Selected by mainboards that use native graphics initialization for the LVDS port. A linear framebuffer is only supported for LVDS.
OVERRIDE_CLOCK_DISABLE	northbridge/intel/i945	bool		Usually system firmware turns off system memory clock signals to unused SO-DIMM slots to reduce EMI and power consumption. However, some boards do not like unused clock signals to be disabled.
MAXIMUM_SUPPORTED_FREQUENCY	northbridge/intel/i945	int		If non-zero, this designates the maximum DDR frequency the board supports, despite what the chipset should be capable of.
CHECK_SLFRCS_ON_RESUME	northbridge/intel/i945	int		On some boards it may be neccessary to hard reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other boards the check always creates a false positive, effectively making it impossible to resume.
HASWELL_VBOOT_IN_BOOTBLOCK	northbridge/intel/haswell	bool	Start verstage in bootblock	Haswell can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. Haswell however uses a mrc.bin to initialize memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region and back to the RW region after the binary is done.
DCACHE_RAM_SIZE	northbridge/intel/haswell	hex		The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.
DCACHE_RAM_MRC_VAR_SIZE	northbridge/intel/haswell	hex		The amount of cache-as-ram region required by the reference code.
DCACHE_BSP_STACK_SIZE	northbridge/intel/haswell	hex		The amount of anticipated stack usage in CAR by bootblock and other stages.
HAVE_MRC	northbridge/intel/haswell	bool	Add a System Agent binary	Select this option to add a System Agent binary to the resulting coreboot image. Note: Without this binary coreboot will not work
MRC_FILE	northbridge/intel/haswell	string	Intel System Agent path and filename	The path and filename of the file to use as System Agent binary.
HASWELL_HIDE_PEG_FROM_MRC	northbridge/intel/haswell	bool	Hide PEG devices from MRC to work around hardcoded MRC behavior	If set, hides all PEG devices from MRC. This allows the iGPU to be used even when a dedicated graphics card is present. However, it prevents MRC from programming PEG AFE registers, which can make PEG devices unstable. When unsure, choose N.
PRE_GRAPHICS_DELAY	northbridge/intel/haswell	int	Graphics initialization delay in ms	On some systems, coreboot boots so fast that connected monitors (mostly TVs) won't be able to wake up fast enough to talk to the VBIOS. On those systems we need to wait for a bit before executing the VBIOS.
ENABLE_DDR_2X_REFRESH	northbridge/intel/haswell	bool	Enable DRAM Refresh 2x support	When enabled, the memory controller will refresh the DRAM twice as often. This probably only happens when the DRAM gets hot, but what MRC exactly does when this setting is enabled has not been investigated.
	toplevel	(comment)		Southbridge
HUDSON_XHCI_ENABLE	southbridge/amd/agesa/hudson	bool	Enable Hudson XHCI Controller	The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI controller if the XHCI firmware is available but the XHCI controller is not enabled by coreboot.
HUDSON_XHCI_FWM	southbridge/amd/agesa/hudson	bool	Add xhci firmware	Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
HUDSON_IMC_FWM	southbridge/amd/agesa/hudson	bool	Add IMC firmware	Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
HUDSON_GEC_FWM	southbridge/amd/agesa/hudson	bool		Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
HUDSON_SATA_MODE	southbridge/amd/agesa/hudson	int	SATA Mode	Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE. 0: NATIVE mode does not require a ROM. 1: RAID mode must have the two ROM files. 2: AHCI may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM. 3: LEGACY IDE 4: IDE to AHCI 5: AHCI7804: ROM Required, and AMD driver required in the OS. 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
	southbridge/amd/agesa/hudson	(comment)		NATIVE
	southbridge/amd/agesa/hudson	(comment)		RAID
	southbridge/amd/agesa/hudson	(comment)		AHCI
	southbridge/amd/agesa/hudson	(comment)		LEGACY IDE
	southbridge/amd/agesa/hudson	(comment)		IDE to AHCI
	southbridge/amd/agesa/hudson	(comment)		AHCI7804
	southbridge/amd/agesa/hudson	(comment)		IDE to AHCI7804
RAID_ROM_ID	southbridge/amd/agesa/hudson	string	RAID device PCI IDs	1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
RAID_MISC_ROM_POSITION	southbridge/amd/agesa/hudson	hex	RAID Misc ROM Position	The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must be larger than 0x100000.
HUDSON_LEGACY_FREE	southbridge/amd/agesa/hudson	bool	System is legacy free	Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI.
AZ_PIN	southbridge/amd/agesa/hudson	hex		bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3
ENABLE_IDE_COMBINED_MODE	southbridge/amd/cimx/sb800	bool	Enable SATA IDE combined mode	If Combined Mode is enabled. IDE controller is exposed and SATA controller has control over Port0 through Port3, IDE controller has control over Port4 and Port5. If Combined Mode is disabled, IDE controller is hidden and SATA controller has full control of all 6 Ports when operating in non-IDE mode.
IDE_COMBINED_MODE	southbridge/amd/cimx/sb800	hex	SATA Mode	Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is AHCI.
SB800_SATA_IDE	southbridge/amd/cimx/sb800	bool	NATIVE	NATIVE does not require a ROM.
SB800_SATA_AHCI	southbridge/amd/cimx/sb800	bool	AHCI	AHCI is the default and may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM.
SB800_SATA_RAID	southbridge/amd/cimx/sb800	bool	RAID	sb800 RAID mode must have the two required ROM files.
RAID_ROM_ID	southbridge/amd/cimx/sb800	string	RAID device PCI IDs	1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
RAID_MISC_ROM_POSITION	southbridge/amd/cimx/sb800	hex	RAID Misc ROM Position	The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must larger than 0x100000.
SB800_IMC_FWM	southbridge/amd/cimx/sb800	bool	Add IMC firmware	Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.
SB800_FWM_AT_FFFA0000	southbridge/amd/cimx/sb800	bool	0xFFFA0000	The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.
SB800_FWM_AT_FFF20000	southbridge/amd/cimx/sb800	bool	0xFFF20000	The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.
SB800_FWM_AT_FFE20000	southbridge/amd/cimx/sb800	bool	0xFFE20000	The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.
SB800_FWM_AT_FFC20000	southbridge/amd/cimx/sb800	bool	0xFFC20000	The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.
SB800_FWM_AT_FF820000	southbridge/amd/cimx/sb800	bool	0xFF820000	The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.
EHCI_BAR	southbridge/amd/cimx/sb800	hex	Fan Control	Select the method of SB800 fan control to be used. None would be for either fixed maximum speed fans connected to the SB800 or for an external chip controlling the fan speeds. Manual control sets up the SB800 fan control registers. IMC fan control uses the SB800 IMC to actively control the fan speeds.
SB800_NO_FAN_CONTROL	southbridge/amd/cimx/sb800	bool	None	No SB800 Fan control - Do not set up the SB800 fan control registers.
SB800_MANUAL_FAN_CONTROL	southbridge/amd/cimx/sb800	bool	Manual	Configure the SB800 fan control registers in devicetree.cb.
SB800_IMC_FAN_CONTROL	southbridge/amd/cimx/sb800	bool	IMC Based	Set up the SB800 to use the IMC based Fan controller. This requires the IMC ROM from AMD. Configure the registers in devicetree.cb.
HUDSON_XHCI_ENABLE	southbridge/amd/pi/hudson	bool	Enable Hudson XHCI Controller	The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI controller if the XHCI firmware is available but the XHCI controller is not enabled by coreboot.
HUDSON_XHCI_FWM	southbridge/amd/pi/hudson	bool	Add xhci firmware	Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
HUDSON_IMC_FWM	southbridge/amd/pi/hudson	bool	Add IMC firmware	Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
HUDSON_GEC_FWM	southbridge/amd/pi/hudson	bool		Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
HUDSON_SATA_MODE	southbridge/amd/pi/hudson	int	SATA Mode	Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE. 0: NATIVE mode does not require a ROM. 1: RAID mode must have the two ROM files. 2: AHCI may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM. 3: LEGACY IDE 4: IDE to AHCI 5: AHCI7804: ROM Required, and AMD driver required in the OS. 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
	southbridge/amd/pi/hudson	(comment)		NATIVE
	southbridge/amd/pi/hudson	(comment)		RAID
	southbridge/amd/pi/hudson	(comment)		AHCI
	southbridge/amd/pi/hudson	(comment)		LEGACY IDE
	southbridge/amd/pi/hudson	(comment)		IDE to AHCI
	southbridge/amd/pi/hudson	(comment)		AHCI7804
	southbridge/amd/pi/hudson	(comment)		IDE to AHCI7804
RAID_ROM_ID	southbridge/amd/pi/hudson	string	RAID device PCI IDs	1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
RAID_MISC_ROM_POSITION	southbridge/amd/pi/hudson	hex	RAID Misc ROM Position	The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must be larger than 0x100000.
HUDSON_LEGACY_FREE	southbridge/amd/pi/hudson	bool	System is legacy free	Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI.
AZ_PIN	southbridge/amd/pi/hudson	hex		bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3
AMDFW_OUTSIDE_CBFS	southbridge/amd/pi/hudson	hex		The AMDFW (PSP) is typically locatable in cbfs. Select this option to manually attach the generated amdfw.rom at an offset of 0x20000 from the bottom of the coreboot ROM image.
SERIRQ_CONTINUOUS_MODE	southbridge/amd/pi/hudson	bool		Set this option to y for serial IRQ in continuous mode. Otherwise it is in quiet mode.
HUDSON_ACPI_IO_BASE	southbridge/amd/pi/hudson	hex		Base address for the ACPI registers. This value must match the hardcoded value of AGESA.
HUDSON_UART	southbridge/amd/pi/hudson	bool	UART controller on Kern	There are two UART controllers in Kern. The UART registers are memory-mapped. UART controller 0 registers range from FEDC_6000h to FEDC_6FFFh. UART controller 1 registers range from FEDC_8000h to FEDC_8FFFh.
SERIRQ_CONTINUOUS_MODE	southbridge/intel/ibexpeak	bool		If you set this option to y, the serial IRQ machine will be operated in continuous mode.
INTEL_LYNXPOINT_LP	southbridge/intel/lynxpoint	bool		Set this option to y for Lynxpont LP (Haswell ULT).
SERIRQ_CONTINUOUS_MODE	southbridge/intel/lynxpoint	bool		If you set this option to y, the serial IRQ machine will be operated in continuous mode.
FINALIZE_USB_ROUTE_XHCI	southbridge/intel/lynxpoint	bool	Route all ports to XHCI controller in finalize step	If you set this option to y, the USB ports will be routed to the XHCI controller during the finalize SMM callback.
INTEL_DESCRIPTOR_MODE_CAPABLE	southbridge/intel/common	bool		This config simply states that the platform is capable of running in descriptor mode (when the descriptor in flash is valid).
INTEL_DESCRIPTOR_MODE_REQUIRED	southbridge/intel/common	bool		This config states descriptor mode is required for the platform to function properly, or to function at all.
VALIDATE_INTEL_DESCRIPTOR	southbridge/intel/common	bool	Validate Intel firmware descriptor	This config enables validating the Intel firmware descriptor against the fmap layout. If the firmware descriptor layout does not match the fmap then the bootimage cannot be built.
INTEL_CHIPSET_LOCKDOWN	southbridge/intel/common	bool	Lock down chipset in coreboot	Some registers within host bridge on particular chipsets should be locked down on each normal boot path (done by either coreboot or payload) and S3 resume (always done by coreboot). Select this to let coreboot to do this on normal boot path.
SERIRQ_CONTINUOUS_MODE	southbridge/intel/bd82x6x	bool		If you set this option to y, the serial IRQ machine will be operated in continuous mode.
	toplevel	(comment)		Super I/O
SUPERIO_NUVOTON_COMMON_COM_A	superio/nuvoton/common	bool		When enabled, the 'nuvoton_enable_serial()' function will unset global CR 0x2a bit 7 to route COM A to the GPIO8 pin group.
W83977TF_HAVE_SEPARATE_IR_DEVICE	superio/winbond/w83977tf	bool		Mainboard should select this option if it contains an old version of W83977TF with a separate IR logical device.
SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG	superio/ite/common	bool		Enable extended, 16-bit wide tacho counters.
SUPERIO_ITE_ENV_CTRL_8BIT_PWM	superio/ite/common	bool		PWM duty cycles are set in 8-bit registers (instead of 7 bit).
SUPERIO_ITE_ENV_CTRL_PWM_FREQ2	superio/ite/common	bool		The second FAN controller has a separate frequency setting.
SUPERIO_ITE_ENV_CTRL_NO_ONOFF	superio/ite/common	bool		FAN controller always works in SmartGuardian mode.
SUPERIO_ITE_ENV_CTRL_5FANS	superio/ite/common	bool		ITE FAN controller has 5 independent outputs.
SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG	superio/ite/common	bool		Slope PWM registers have no separate BIT6 and are set directly by 7-bit values instead.
SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN	superio/ite/common	bool		Temperature can be read to any TMPIN from an external sensor via SST/PECI (instead of TMPIN3 only).
SUPERIO_ASPEED_USE_UART_DELAY_WORKAROUND	superio/aspeed/common	bool	Workaround for BMC serial console setup bug	Some mainboards with an ASPEED BMC have scrambled console output in early boot phases because the serial output routing is not set up fast enough by the BMC. By enabling this a delay of 500ms gets added before setting up the console and before any console output gets printed. Note: this problem may disappear with future BMC firmware versions. Another approach is using a different BMC firmware like OpenBMC, u-bmc, ...
	toplevel	(comment)		Embedded Controllers
EC_ACPI	ec/acpi	bool		ACPI Embedded Controller interface. Mostly found in laptops.
EC_SUPPORTS_DPTF_TEVT	ec/acpi	bool		The EC ASL code supports calling of TEVT method when provided by SoC or mainboard.
EC_HP_KBC1126	ec/hp/kbc1126	bool		Interface to SMSC KBC1126 embedded controller in HP laptops.
	ec/hp/kbc1126	(comment)		Please select the following otherwise your laptop cannot be powered on.
KBC1126_FIRMWARE	ec/hp/kbc1126	bool	Add firmware images for KBC1126 EC	Select this option to add the two firmware blobs for KBC1126. You need these two blobs to power on your machine.
KBC1126_FW1	ec/hp/kbc1126	string	KBC1126 firmware #1 path and filename	The path and filename of the file to use as KBC1126 firmware #1. You can use util/kbc1126/kbc1126_ec_dump to dump it from the vendor firmware.
KBC1126_FW2	ec/hp/kbc1126	string	KBC1126 filename #2 path and filename	The path and filename of the file to use as KBC1126 firmware #2. You can use util/kbc1126/kbc1126_ec_dump to dump it from the vendor firmware.
EC_KONTRON_IT8516E	ec/kontron/it8516e	bool		Kontron uses an ITE IT8516E on the KTQM77. Its firmware might come from Fintek (mentioned as Fintec somewhere in their Linux driver). The KTQM77 is an embedded board and the IT8516E seems to be only used for fan control and GPIO.
EC_KONTRON_KEMPLD	ec/kontron/kempld	bool		Driver for Kontron's express module programmable logic device used on their COMexpress modules.
EC_GOOGLE_CHROMEEC	ec/google/chromeec	bool		Google's Chrome EC
EC_GOOGLE_CHROMEEC_ACPI_MEMMAP	ec/google/chromeec	bool		When defined, ACPI accesses EC memmap data on ports 66h/62h. When not defined, the memmap data is instead accessed on 900h-9ffh via the LPC bus.
EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER	ec/google/chromeec	bool		Expose methods for enabling and disabling port power on individual USB ports through the EC.
EC_GOOGLE_CHROMEEC_BOARDID	ec/google/chromeec	bool		Provides common routine for reading boardid from Chrome EC.
EC_GOOGLE_CHROMEEC_I2C	ec/google/chromeec	bool		Google's Chrome EC via I2C bus.
EC_GOOGLE_CHROMEEC_I2C_PROTO3	ec/google/chromeec	bool		Use only proto3 for i2c EC communication.
EC_GOOGLE_CHROMEEC_ESPI	ec/google/chromeec	bool		Google Chrome EC via eSPI bus. The EC communication code is the same between eSPI and LPC, so this option simply enables the LPC EC code. The eSPI device still needs to correctly configure the bus transactions.
EC_GOOGLE_CHROMEEC_LPC	ec/google/chromeec	bool		Google Chrome EC via LPC bus.
EC_GOOGLE_CHROMEEC_MEC	ec/google/chromeec	bool		Microchip EC variant for LPC register access.
EC_GOOGLE_CHROMEEC_PD	ec/google/chromeec	bool		Indicates that Google's Chrome USB PD chip is present.
EC_GOOGLE_CHROMEEC_SPI	ec/google/chromeec	bool		Google's Chrome EC via SPI bus.
EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US	ec/google/chromeec	int		Force delay after asserting /CS to allow EC to wakeup.
EC_GOOGLE_CHROMEEC_SKUID	ec/google/chromeec	hex		Provides common routine for reporting the skuid to ChromeOS.
EC_GOOGLE_CHROMEEC_BOARDNAME	ec/google/chromeec	string	Chrome EC board name for EC	The board name used in the Chrome EC code base to build the EC firmware. If set, the coreboot build with also build the EC firmware and add it to the image.
EC_GOOGLE_CHROMEEC_PD_BOARDNAME	ec/google/chromeec	string	Chrome EC board name for PD	The board name used in the Chrome EC code base to build the PD firmware. If set, the coreboot build with also build the EC firmware and add it to the image.
EC_GOOGLE_CHROMEEC_RTC	ec/google/chromeec	bool	Enable Chrome OS EC RTC	Enable support for the real-time clock on the Chrome OS EC. This uses the EC_CMD_RTC_GET_VALUE command to read the current time.
EC_GOOGLE_CHROMEEC_FIRMWARE_NONE	ec/google/chromeec	bool	No EC firmware is included	Disable building and including any EC firmware in the image. config EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL bool "External EC firmware is included" help Include EC firmware binary in the image from an external source. It is expected to be built externally. config EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN bool "Builtin EC firmware is included" help Build and include EC firmware binary in the image.
EC_GOOGLE_CHROMEEC_FIRMWARE_FILE	ec/google/chromeec	string	Chrome EC firmware path and filename	The path and filename of the EC firmware file to use.
EC_GOOGLE_CHROMEEC_PD_FIRMWARE_NONE	ec/google/chromeec	bool	No PD firmware is included	Disable building and including any PD firmware in the image. config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_EXTERNAL bool "External PD firmware is included" help Include PD firmware binary in the image from an external source. It is expected to be built externally. config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_BUILTIN bool "Builtin PD firmware is included" help Build and include PD firmware binary in the image.
EC_GOOGLE_CHROMEEC_PD_FIRMWARE_FILE	ec/google/chromeec	string	Chrome EC firmware path and filename for PD	The path and filename of the PD firmware file to use.
EC_GOOGLE_CHROMEEC_SWITCHES	ec/google/chromeec	bool		Enable support for Chrome OS mode switches provided by the Chrome OS EC.
EC_GOOGLE_CHROMEEC_I2C_TUNNEL	ec/google/chromeec/i2c_tunnel	bool		This enables the Cros EC I2C tunnel driver that is required to fill the SSDT nodes for the I2C tunnel used by the mainboard.
EC_GOOGLE_CHROMEEC_AUDIO_CODEC	ec/google/chromeec/audio_codec	bool		This enables the Cros EC audio codec driver that is required to fill the SSDT nodes for the codec device used by the mainboard.
EC_GOOGLE_COMMON_MEC	ec/google/common	bool		Google common EC functions for Microchip EMI region.
EC_GOOGLE_WILCO	ec/google/wilco	bool		Google Wilco Embedded Controller interface.
EC_BASE_ACPI_DATA	ec/google/wilco	hex		This option provides the 16-bit IO base address for the ACPI data interface. This is the standard ACPI EC interface that is used by the ACPI EC drivers in the OS.
EC_BASE_ACPI_COMMAND	ec/google/wilco	hex		This option provides the 16-bit IO base address for the ACPI EC command interface. This is the standard ACPI EC interface that is used by the ACPI EC drivers in the OS.
EC_BASE_HOST_DATA	ec/google/wilco	hex		This option provides the 16-bit IO base address for the host data interface. This is the interface that is used to drive the mailbox protocol.
EC_BASE_HOST_COMMAND	ec/google/wilco	hex		This option provides the 16-bit IO base address for the host command interface. This is the interface that is used to drive the mailbox protocol.
EC_BASE_PACKET	ec/google/wilco	hex		This option provides the 16-bit IO base address for the EC mailbox interface data region. This data buffer is used along with the host command and data registers to drive the EC mailbox interface. This is also the MEC EMI base address.
EC_QUANTA_IT8518	ec/quanta/it8518	bool		Interface to QUANTA IT8518 Embedded Controller.
EC_QUANTA_ENE_KB3940Q	ec/quanta/ene_kb3940q	bool		Interface to QUANTA ENE KB3940Q Embedded Controller.
H8_BEEP_ON_DEATH	ec/lenovo/h8	bool	Beep on fatal error	Beep when encountered a fatal error.
H8_FLASH_LEDS_ON_DEATH	ec/lenovo/h8	bool	Flash LEDs on fatal error	Flash all LEDs when encountered a fatal error.
H8_SUPPORT_BT_ON_WIFI	ec/lenovo/h8	bool	Support bluetooth on wifi cards	Disable BDC detection and assume bluetooth is installed. Required for bluetooth on wifi cards, as it's not possible to detect it in coreboot.
H8_FN_KEY_AS_VBOOT_RECOVERY_SW	ec/lenovo/h8	bool	Enable Fn-Key as VBOOT recovery switch	If VBOOT is enabled, press Fn-Key at power on to force a recovery mode boot instead of regular FW_MAIN_x boot.
THINKPADEC_HKEY_EISAID	ec/lenovo/h8	string		Motherboards of newer thinkpad models can override the default to match vendor drivers and quirks.
EC_RODA_IT8518	ec/roda/it8518	bool		Interface to IT8518 embedded controller in Roda notebooks.
EC_SMSC_MEC1308	ec/smsc/mec1308	bool		Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.
EC_COMPAL_ENE932	ec/compal/ene932	bool		Interface to COMPAL ENE932 Embedded Controller.
EC_SYSTEM76_EC	ec/system76/ec	bool		System76 EC
EC_PURISM_LIBREM	ec/purism/librem	bool		Purism Librem EC
EC_51NB_NPCE985LA0DX	ec/51nb/npce985la0dx	bool		Support for the 51NB NPCE985LA0DX EC
	ec/51nb/npce985la0dx	(comment)		Please select the following otherwise your laptop cannot be powered on.
EC_51NB_NPCE985LA0DX_FIRMWARE	ec/51nb/npce985la0dx	bool	Add firmware image for 51NB NPCE985LA0DX EC	Select this option to add the firmware blob for the 51NB EC. You need this blob to power on your machine.
EC_51NB_NPCE985LA0DX_FW	ec/51nb/npce985la0dx	string	51NB EC firmware path	The path and filename of the file to use as 51NB firmware.
HAVE_INTEL_FIRMWARE	southbridge/intel/common/firmware	bool		Platform uses the Intel Firmware Descriptor to describe the layout of the SPI ROM chip. Enabling this option will allow you to select further features that rely on this like providing individual firmware blobs.
	southbridge/intel/common/firmware	(comment)		Intel Firmware
HAVE_IFD_BIN	southbridge/intel/common/firmware	bool	Add Intel descriptor.bin file	The descriptor binary
HAVE_ME_BIN	southbridge/intel/common/firmware	bool	Add Intel ME/TXE firmware	The Intel processor in the selected system requires a special firmware for an integrated controller. This might be called the Management Engine (ME), the Trusted Execution Engine (TXE) or something else depending on the chip. This firmware might or might not be available in coreboot's 3rdparty/blobs repository. If it is not and if you don't have access to the firmware from elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME/TXE firmware on your flash ROM.
CHECK_ME	southbridge/intel/common/firmware	bool	Verify the integrity of the supplied ME/TXE firmware	Verify the integrity of the supplied Intel ME/TXE firmware before proceeding with the build, in order to prevent an accidental loading of a corrupted ME/TXE image.
ME_REGION_ALLOW_CPU_READ_ACCESS	southbridge/intel/common/firmware	bool	Allows HOST/CPU read access to ME region	The config ensures Host has read access to the ME region if it is locked through LOCK_MANAGEMENT_ENGINE config. This config is enabled when the CSE Lite SKU is integrated.
USE_ME_CLEANER	southbridge/intel/common/firmware	bool	Strip down the Intel ME/TXE firmware	Use me_cleaner to remove all the non-fundamental code from the Intel ME/TXE firmware. The resulting Intel ME/TXE firmware will have only the code responsible for the very basic hardware initialization, leaving the ME/TXE subsystem essentially in a disabled state. Don't flash a modified ME/TXE firmware and a new coreboot image at the same time, test them in two different steps. WARNING: this tool isn't based on any official Intel documentation but only on reverse engineering and trial & error. See the project's page https://github.com/corna/me_cleaner or the wiki https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F https://github.com/corna/me_cleaner/wiki/me_cleaner-status for more info about this tool If unsure, say N.
	southbridge/intel/common/firmware	(comment)		Please test the modified ME/TXE firmware and coreboot in two steps
HAVE_GBE_BIN	southbridge/intel/common/firmware	bool	Add gigabit ethernet configuration	The integrated gigabit ethernet controller needs a configuration file. Select this if you are going to use the PCH integrated controller and want to add that file.
HAVE_EC_BIN	southbridge/intel/common/firmware	bool	Add EC firmware	The embedded controller needs a firmware file. Select this if you are going to use the PCH integrated controller and have the EC firmware. EC firmware will be added to final image through ifdtool.
EC_BIN_PATH	southbridge/intel/common/firmware	string	Protect flash regions	This option allows you to protect flash regions.
DO_NOT_TOUCH_DESCRIPTOR_REGION	southbridge/intel/common/firmware	bool	Use the preset values to protect the regions	Read and write access permissions to different regions in the flash can be controlled via dedicated bitfields in the flash descriptor. These permissions can be modified with the Intel Flash Descriptor Tool (ifdtool). If you don't want to change these permissions and keep the ones provided in the initial descriptor, use this option.
LOCK_MANAGEMENT_ENGINE	southbridge/intel/common/firmware	bool	Lock ME/TXE section	The Intel Firmware Descriptor supports preventing write and read accesses from the host to the ME or TXE section. If the section is locked, it can only be overwritten with an external SPI flash programmer or HECI HMRFPO_ENABLE command needs to be sent to CSE before writing to the ME Section. If CSE Lite SKU is integrated, the Kconfig prevents only writing to the ME section. If unsure, select "Unlock flash regions".
UNLOCK_FLASH_REGIONS	southbridge/intel/common/firmware	bool	Unlock flash regions	All regions are completely unprotected and can be overwritten using a flash programming tool.
CBFS_SIZE	southbridge/intel/common/firmware	hex		Reduce CBFS size to give room to the IFD blobs.
Menu: ChromeOS
CHROMEOS	vendorcode/google/chromeos	bool	Build for ChromeOS	Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported board will most likely break your build.
NO_TPM_RESUME	vendorcode/google/chromeos	bool		On some boards the TPM stays powered up in S3. On those boards, booting Windows will break if the TPM resume command is sent during an S3 resume.
HAVE_REGULATORY_DOMAIN	vendorcode/google/chromeos	bool	Add regulatory domain methods	This option is needed to add ACPI regulatory domain methods
CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME	vendorcode/google/chromeos	bool		Disable the platform heirarchy on resume path if the firmware is involved in resume. The hierarchy is disabled prior to jumping to the OS. Note that this option is sepcific to TPM2 boards. This option is auto selected if CHROMEOS because it matches with vboot_reference model which disables the platform hierarchy in the boot loader. However, those operations need to be symmetric on normal boot as well as resume and coreboot is only involved in the resume piece w.r.t. the platform hierarchy.
CHROMEOS_USE_EC_WATCHDOG_FLAG	vendorcode/google/chromeos	bool		Use the AP watchdog flag stored in EC.
CHROMEOS_DSM_CALIB	vendorcode/google/chromeos	bool		On some boards, there are calibrated parameters for Dynamic Speaker Management(DSM) stored in VPD. Enable this config to read and parse these VPD values and write them to ACPI DSD table in device driver. These parameters will be applied by kernel driver through device property at boot.
CHROMEOS_CSE_BOARD_RESET_OVERRIDE	vendorcode/google/chromeos	bool		On some boards that run old firmware version in cr50, Embedded Controller (EC) needs to trigger the cold reset of Application Processor (AP) when CSE jumps from RO to RW so that cr50 resets the TPM state. This is required on boards where the cr50 firmware does not understand the new cr50 strap config (applicable only to boards using strap config 0xe). Enabling this config will help to override the default global reset.
CHROMEOS_DRAM_PART_NUMBER_IN_CBI	vendorcode/google/chromeos	bool		Some boards declare the DRAM part number in the CBI instead of the SPD. This option allows those boards to declare that their DRAM part number is stored in the CBI.
GOOGLE_SMBIOS_MAINBOARD_VERSION	vendorcode/google	bool		Provide a common implementation for mainboard version, which returns a formatted 'rev%d' board_id() string.
CAVIUM_BDK	vendorcode/cavium	None		Build Cavium's BDK in romstage.
Menu: BDK
CAVIUM_BDK_VERBOSE_INIT	vendorcode/cavium	bool	Enable verbose init	Build Cavium's BDK with verbose init code.
CAVIUM_BDK_VERBOSE_DRAM	vendorcode/cavium	bool	Enable verbose dram init	Build Cavium's BDK with verbose dram init code.
CAVIUM_BDK_VERBOSE_DRAM_TEST	vendorcode/cavium	bool	Enable verbose raminit tests	Build Cavium's BDK with verbose DRAM testing code.
CAVIUM_BDK_VERBOSE_QLM	vendorcode/cavium	bool	Enable verbose qlm init	Build Cavium's BDK with verbose QLM code.
CAVIUM_BDK_VERBOSE_PCIE_CONFIG	vendorcode/cavium	bool	Enable verbose pcie config	Build Cavium's BDK with verbose PCIe config code.
CAVIUM_BDK_VERBOSE_PCIE	vendorcode/cavium	bool	Enable verbose pcie init	Build Cavium's BDK with verbose PCIe code.
CAVIUM_BDK_VERBOSE_PHY	vendorcode/cavium	bool	Enable verbose phy init	Build Cavium's BDK with verbose PHY code.
CAVIUM_BDK_DDR_TUNE_HW_OFFSETS	vendorcode/cavium	bool	Hardware assisted DLL read offset tuning	Automatically tune the data byte DLL read offsets. Always done by default, but allow use of HW-assist. NOTE: HW-assist will also tune the ECC byte.
Menu: AMD Platform Initialization
None	vendorcode/amd	None	AGESA source	Select the method for including the AMD Platform Initialization code into coreboot. Platform Initialization code is required for all AMD processors.
CPU_AMD_AGESA_BINARY_PI	vendorcode/amd	bool	binary PI	Use a binary PI package. Generally, these will be stored in the "3rdparty/blobs" directory. For some processors, these must be obtained directly from AMD Embedded Processors Group (http://www.amd.com/embedded).
CPU_AMD_AGESA_OPENSOURCE	vendorcode/amd	bool	open-source AGESA	Build the PI package ("AGESA") from source code in the "vendorcode" directory.
None	vendorcode/amd/agesa	None	DDR3 memory profile	Choose the DDR3 memory profile to use for your RAM sticks, e.g. XMP 1. XMP support is experimental, and your PC will fail booting if you choose a profile which does not exist on ANY of your RAM sticks! If in doubt check their SPD Data using a coreboot's great fork of memtest86+ 5.01.
CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC	vendorcode/amd/agesa	bool	JEDEC	JEDEC memory profile, standard and stable. Is guaranteed to be working.
CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1	vendorcode/amd/agesa	bool	XMP 1	XMP 1 memory profile. Check that it exists on ALL of your RAM sticks!
CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2	vendorcode/amd/agesa	bool	XMP 2	XMP 2 memory profile. Check that it exists on ALL of your RAM sticks!
CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM	vendorcode/amd/agesa	bool	CUSTOM	Custom memory profile. Use the XMP SPD values as the base, if available.
AGESA_BINARY_PI_VENDORCODE_PATH	vendorcode/amd/pi	string	AGESA PI directory path	Specify where to find the AGESA header files for AMD platform initialization.
AGESA_BINARY_PI_FILE	vendorcode/amd/pi	string	AGESA PI binary file name	Specify the binary file to use for AMD platform initialization.
AGESA_BINARY_PI_AS_STAGE	vendorcode/amd/pi	bool	AGESA Binary PI is added as stage to CBFS.	AGESA will be added as a stage utilizing --xip cbfstool options as needed relocating the image to the proper location in memory-mapped cpu address space. It's required that the file be in ELF format containing the relocations necessary for relocating at runtime.
AGESA_SPLIT_MEMORY_FILES	vendorcode/amd/pi	bool	Split AGESA Binary PI into pre- and post-memory files.	Specifies that AGESA is split into two binaries for pre- and post-memory.
AGESA_PRE_MEMORY_BINARY_PI_FILE	vendorcode/amd/pi	string	Pre memory Binary PI file name	Specify the binary file to use for pre-memory AMD platform initialization.
AGESA_POST_MEMORY_BINARY_PI_FILE	vendorcode/amd/pi	string	Post memory Binary PI file name	Specify the binary file to use for post-memory AMD platform initialization.
AGESA_BINARY_PI_LOCATION	vendorcode/amd/pi	hex	AGESA PI binary address in ROM	Specify the ROM address at which to store the binary Platform Initialization code.
AGESA_EXTRA_TIMESTAMPS	vendorcode/amd	bool	Add instrumentation for AGESA calls	Insert additional timestamps around each entrypoint into AGESA vendorcode.
UDK_VERSION	vendorcode/intel	int		UEFI Development Kit version for Platform
ARCH_ARMV8_EXTENSION	arch/arm64/armv8	int		Specify ARMv8 extension, for example '1' for ARMv8.1, to control the '-march' option passed into the compiler. Defaults to 0 for vanilla ARMv8 but may be overridden in the SoC's Kconfig. All ARMv8 implementations are downwards-compatible, so this does not need to be changed unless specific features (e.g. new instructions) are used by the SoC's coreboot code.
ARM64_BL31_EXTERNAL_FILE	arch/arm64	string	Path to external BL31.ELF (leave empty to build from source)	The blob to use instead of building the Arm Trusted Firmware from tree. It is discouraged as compatibility with out-of-tree blobs may break anytime.
ARM64_SECURE_OS_FILE	arch/arm64	string	Secure OS binary file	Secure OS binary file.
ARM64_A53_ERRATUM_843419	arch/arm64	bool		Some early Cortex-A53 revisions had a hardware bug that results in incorrect address calculations in rare cases. This option enables a linker workaround to avoid those cases if your toolchain supports it. Should be selected automatically by SoCs that are affected.
RISCV_OPENSBI	arch/riscv	bool	Use OpenSBI to hand over control to payload	Load OpenSBI after payload has been loaded and use it to provide the SBI and to handover control to payload.
OPENSBI_PLATFORM	arch/riscv	string		The OpenSBI platform to build for.
OPENSBI_TEXT_START	arch/riscv	hex		The linking address used to build opensbi.
ARCH_X86_64_PGTBL_LOC	arch/x86	hex	x86_64 page table location in CBFS	The position where to place pagetables. Needs to be known at compile time. Must not overlap other files in CBFS.
USE_MARCH_586	arch/x86	hex		Allow a platform or processor to select to be compiled using the '-march=i586' option instead of the typical '-march=i686'
RESET_VECTOR_IN_RAM	arch/x86	bool		Select this option if the x86 processor's reset vector is in preinitialized DRAM instead of the traditional 0xfffffff0 location.
PRERAM_CBMEM_CONSOLE_SIZE	arch/x86	hex		Increase this value if preram cbmem console is getting truncated
CBFS_MCACHE_SIZE	arch/x86	hex		Increase this value if you see CBFS mcache overflow warnings.
BOOTBLOCK_DEBUG_SPINLOOP	arch/x86	bool		Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait for a JTAG debugger to break into the execution sequence.
VERSTAGE_DEBUG_SPINLOOP	arch/x86	bool		Add a spin (JMP .) in assembly_entry.S during early verstage to wait for a JTAG debugger to break into the execution sequence.
ROMSTAGE_DEBUG_SPINLOOP	arch/x86	bool		Add a spin (JMP .) in assembly_entry.S during early romstage to wait for a JTAG debugger to break into the execution sequence.
SKIP_MAX_REBOOT_CNT_CLEAR	arch/x86	bool	Do not clear reboot count after successful boot	Do not clear the reboot count immediately after successful boot. Set to allow the payload to control normal/fallback image recovery. Note that it is the responsibility of the payload to reset the normal boot bit to 1 after each successful boot.
ACPI_BERT	arch/x86	bool		Build an ACPI Boot Error Record Table.
COLLECT_TIMESTAMPS_NO_TSC	arch/x86	bool		Use a non-TSC platform-dependent source for timestamps.
COLLECT_TIMESTAMPS_TSC	arch/x86	bool		Use the TSC as the timestamp source.
PAGING_IN_CACHE_AS_RAM	arch/x86	bool		Chipsets scan select this option to preallocate area in cache-as-ram for storing paging data structures. PAE paging is currently the only thing being supported.
NUM_CAR_PAGE_TABLE_PAGES	arch/x86	int		The number of 4KiB pages that should be pre-allocated for page tables.
MAX_PIRQ_LINKS	arch/x86	int		This variable specifies the number of PIRQ interrupt links which are routable. On most chipsets, this is 4, INTA through INTD. Some chipsets offer more than four links, commonly up to INTH. They may also have a separate link for ATA or IOAPIC interrupts. When the PIRQ table specifies links greater than 4, pirq_route_irqs will not function properly, unless this variable is correctly set.
MAX_ACPI_TABLE_SIZE_KB	arch/x86	int		Set the maximum size of all ACPI tables in KiB.
CHIPSET_DEVICETREE	toplevel	string		This symbol allows a chipset to provide a set of default settings in a devicetree which are common to all mainboards. This may include devices (including alias names), chip drivers, register settings, and others. This path is relative to the src/ directory. Example: "chipset.cb"
Menu: Devices
HAVE_VGA_TEXT_FRAMEBUFFER	device	bool		Selected by graphics drivers that support legacy VGA text mode.
HAVE_VBE_LINEAR_FRAMEBUFFER	device	bool		Selected by graphics drivers that can set up a VBE linear-framebuffer mode.
HAVE_LINEAR_FRAMEBUFFER	device	bool		Selected by graphics drivers that can set up a generic linear framebuffer.
HAVE_FSP_GOP	device	bool		Selected by drivers that support to run a blob that implements the Graphics Output Protocol (GOP).
MAINBOARD_NO_FSP_GOP	device	bool		Selected by mainboards that do not have any graphics ports connected to the SoC.
MAINBOARD_HAS_NATIVE_VGA_INIT	device	bool		Selected by mainboards / drivers that provide native graphics init within coreboot.
MAINBOARD_FORCE_NATIVE_VGA_INIT	device	bool		Selected by mainboards / chipsets whose graphics driver can't or shouldn't be disabled.
VGA_ROM_RUN_DEFAULT	device	bool		Selected by mainboards whose graphics initialization depends on VGA OpROM. coreboot needs to load/execute legacy VGA OpROM in order to initialize GFX.
MAINBOARD_HAS_LIBGFXINIT	device	bool		Selected by mainboards that implement support for `libgfxinit`. Usually this requires a list of ports to be probed for displays.
MAINBOARD_DO_NATIVE_VGA_INIT	device	bool	Use native graphics init	Some mainboards, such as the Google Link, allow initializing the display without the need of a binary only VGA OPROM. Enabling this option may be faster, but also lacks flexibility in setting modes.
MAINBOARD_USE_LIBGFXINIT	device	bool	Use libgfxinit	Use the SPARK library `libgfxinit` for the native graphics initialization. This requires an Ada toolchain.
VGA_ROM_RUN	device	bool	Run VGA Option ROMs	Execute VGA Option ROMs in coreboot if found. This can be used to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS payload. When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly.
RUN_FSP_GOP	device	bool	Run a GOP driver	Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support to run a GOP blob. This option enables graphics initialization with such a blob.
NO_GFX_INIT	device	bool	None	Select this to not perform any graphics initialization in coreboot. This is useful if the payload (e.g. SeaBIOS) can initialize graphics or if pre-boot graphics are not required.
ONBOARD_VGA_IS_PRIMARY	device	bool	Use onboard VGA as primary video device	This option lets you select which VGA device will be used to decode legacy VGA cycles. Not all chipsets implement this however. If not selected, the last adapter found will be used, else the onboard adapter is used.
S3_VGA_ROM_RUN	device	bool	Re-run VGA Option ROMs on S3 resume	Execute VGA Option ROMs in coreboot when resuming from S3 suspend. When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly. If unsure, say N when using SeaBIOS as payload, Y otherwise.
ALWAYS_LOAD_OPROM	device	bool		Always load option ROMs if any are found. The decision to run the ROM is still determined at runtime, but the distinction between loading and not running comes into play for CHROMEOS. An example where this is required is that VBT (Video BIOS Tables) are needed for the kernel's display driver to know how a piece of hardware is configured to be used.
ALWAYS_RUN_OPROM	device	bool		Always uncondtionally run the option regardless of other policies.
ON_DEVICE_ROM_LOAD	device	bool	Load Option ROMs on PCI devices	Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot. If disabled, only Option ROMs stored in CBFS will be executed by coreboot. If you are concerned about security, you might want to disable this option, but it might leave your system in a state of degraded functionality. When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly. If unsure, say N when using SeaBIOS as payload, Y otherwise.
PCI_OPTION_ROM_RUN_REALMODE	device	bool	Native mode	If you select this option, PCI Option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, so this is the fastest, but also the least secure option. (only works on x86/x64 systems)
PCI_OPTION_ROM_RUN_YABEL	device	bool	Secure mode	If you select this option, the x86emu CPU emulator will be used to execute PCI Option ROMs. This option prevents Option ROMs from doing dirty tricks with the system (such as installing SMM modules or hypervisors), but it is also significantly slower than the native Option ROM initialization method. This is the default choice for non-x86 systems.
YABEL_PCI_ACCESS_OTHER_DEVICES	device	bool	Allow Option ROMs to access other devices	Per default, YABEL only allows Option ROMs to access the PCI device that they are associated with. However, this causes trouble for some onboard graphics chips whose Option ROM needs to reconfigure the north bridge.
YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG	device	bool	Fake success on writing other device's config space	By default, YABEL aborts when the Option ROM tries to write to other devices' config spaces. With this option enabled, the write doesn't follow through, but the Option ROM is allowed to go on. This can create issues such as hanging Option ROMs (if it depends on that other register changing to the written value), so test for impact before using this option.
YABEL_VIRTMEM_LOCATION	device	hex	Location of YABEL's virtual memory	YABEL requires 1MB memory for its CPU emulation. This memory is normally located at 16MB.
YABEL_DIRECTHW	device	bool	Direct hardware access	YABEL consists of two parts: It uses x86emu for the CPU emulation and additionally provides a PC system emulation that filters bad device and memory access (such as PCI config space access to other devices than the initialized one). When choosing this option, x86emu will pass through all hardware accesses to memory and I/O devices to the underlying memory and I/O addresses. While this option prevents Option ROMs from doing dirty tricks with the CPU (such as installing SMM modules or hypervisors), they can still access all devices in the system. Enable this option for a good compromise between security and speed.
Menu: Display
FRAMEBUFFER_SET_VESA_MODE	device	bool	Set framebuffer graphics resolution	Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
FRAMEBUFFER_SET_VESA_MODE	device	bool	framebuffer graphics resolution	This option sets the resolution used for the coreboot framebuffer (and bootsplash screen).
VGA_TEXT_FRAMEBUFFER	device	bool	Legacy VGA text mode	If this option is enabled, coreboot will initialize graphics in legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set, switch to text mode before handing control to a payload.
VBE_LINEAR_FRAMEBUFFER	device	bool	VESA framebuffer	This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a framebuffer entry in its coreboot table and the payload will need a compatible driver.
GENERIC_LINEAR_FRAMEBUFFER	device	bool	Linear \"high-resolution\" framebuffer	This option enables a high-resolution, linear framebuffer. If this option is enabled, coreboot will pass a framebuffer entry in its coreboot table and the payload will need a compatible driver.
BOOTSPLASH	device	bool	Show graphical bootsplash	This option shows a graphical bootsplash screen. The graphics are loaded from the CBFS file bootsplash.jpg. You can either specify the location and file name of the image in the 'General' section or add it manually to CBFS, using, for example, cbfstool.
LINEAR_FRAMEBUFFER_MAX_WIDTH	device	int	Maximum width in pixels	Set the maximum width of the framebuffer. This may help with default fonts too tiny for high-resolution displays.
LINEAR_FRAMEBUFFER_MAX_HEIGHT	device	int	Maximum height in pixels	Set the maximum height of the framebuffer. This may help with default fonts too tiny for high-resolution displays.
PCI_ALLOW_BUS_MASTER	device	bool	Allow coreboot to set optional PCI bus master bits	For security reasons, bus mastering should be enabled as late as possible. In coreboot, it's usually not necessary and payloads should only enable it for devices they use. Since not all payloads enable bus mastering properly yet, this option gives some sort of "backwards compatibility" and is enabled by default to keep the traditional behaviour for now. This is currently necessary, for instance, for libpayload based payloads as the drivers don't enable bus mastering for PCI bridges.
PCI_SET_BUS_MASTER_PCI_BRIDGES	device	bool	PCI bridges	Let coreboot configure bus mastering for PCI bridges. Enabling bus mastering for a PCI bridge also allows it to forward requests from downstream devices. Currently, payloads ignore this and only enable bus mastering for the downstream device. Hence, this option is needed for compatibility until payloads are fixed.
PCI_ALLOW_BUS_MASTER_ANY_DEVICE	device	bool	Any devices	Allow coreboot to enable PCI bus mastering for any device. The actual selection of devices depends on the various PCI drivers in coreboot.
PCIEXP_COMMON_CLOCK	device	bool	Enable PCIe Common Clock	Detect and enable Common Clock on PCIe links.
PCIEXP_ASPM	device	bool	Enable PCIe ASPM	Detect and enable ASPM (Active State Power Management) on PCIe links.
PCIEXP_CLK_PM	device	bool	Enable PCIe Clock Power Management	Detect and enable Clock Power Management on PCIe.
PCIEXP_L1_SUB_STATE	device	bool	Enable PCIe ASPM L1 SubState	Detect and enable ASPM on PCIe links.
PCIEXP_HOTPLUG	device	bool	Enable PCIe Hotplug Support	Allocate resources for PCIe hotplug bridges
PCIEXP_HOTPLUG_BUSES	device	int	PCI Express Hotplug Buses	This is the number of buses allocated for hotplug PCI express bridges, for use by hotplugged child devices. The default is 32 buses.
PCIEXP_HOTPLUG_MEM	device	hex	PCI Express Hotplug Memory	This is the amount of memory space, in bytes, to allocate to hotplug PCI express bridges, for use by hotplugged child devices. This size should be page-aligned. The default is 8 MiB.
PCIEXP_HOTPLUG_PREFETCH_MEM	device	hex	PCI Express Hotplug Prefetch Memory	This is the amount of pre-fetchable memory space, in bytes, to allocate to hot-plug PCI express bridges, for use by hotplugged child devices. This size should be page-aligned. The default is 256 MiB.
PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G	device	bool		This enables prefetch memory allocation above 4G boundary for the hotplug resources.
PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G	device	bool	PCI Express Hotplug Prefetch Memory Allocation below 4G boundary	This enables prefetch memory allocation below 4G boundary for the hotplug resources.
PCIEXP_HOTPLUG_IO	device	hex	PCI Express Hotplug I/O Space	This is the amount of I/O space to allocate to hot-plug PCI express bridges, for use by hotplugged child devices. The default is 8 KiB.
EARLY_PCI_BRIDGE	device	bool	Early PCI bridge	While coreboot is executing code from ROM, the coreboot resource allocator has not been running yet. Hence PCI devices living behind a bridge are not yet visible to the system. This option enables static configuration for a single pre-defined PCI bridge function on bus 0.
SUBSYSTEM_VENDOR_ID	device	hex	Override PCI Subsystem Vendor ID	This config option will override the devicetree settings for PCI Subsystem Vendor ID. Note: This option is not meant for a board's Kconfig; use the devicetree setting `subsystemid` instead.
SUBSYSTEM_DEVICE_ID	device	hex	Override PCI Subsystem Device ID	This config option will override the devicetree settings for PCI Subsystem Device ID. Note: This option is not meant for a board's Kconfig; use the devicetree setting `subsystemid` instead.
VGA_BIOS	device	bool	Add a VGA BIOS image	Select this option if you have a VGA BIOS image that you would like to add to your ROM. You will be able to specify the location and file name of the image later.
VGA_BIOS_FILE	device	string	VGA BIOS path and filename	The path and filename of the file to use as VGA BIOS.
VGA_BIOS_ID	device	string	VGA device PCI IDs	The comma-separated PCI vendor and device ID with optional revision if that feature is enabled that would associate your vBIOS to your video card. Example: 1106,3230 or 1106,3230,a3 In the above example 1106 is the PCI vendor ID (in hex, but without the "0x" prefix) and 3230 specifies the PCI device ID of the video card (also in hex, without "0x" prefix). a3 specifies the revision. Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
VGA_BIOS_SECOND	device	bool	Add a 2nd video BIOS image	Select this option if you have a 2nd video BIOS image that you would like to add to your ROM.
VGA_BIOS_SECOND_FILE	device	string	2nd video BIOS path and filename	The path and filename of the file to use as video BIOS.
VGA_BIOS_SECOND_ID	device	string	Graphics device PCI IDs	The comma-separated PCI vendor and device ID with optional revision if that feature is enabled that would associate your vBIOS to your video card. Example: 1106,3230 or 1106,3230,a3 In the above example 1106 is the PCI vendor ID (in hex, but without the "0x" prefix) and 3230 specifies the PCI device ID of the video card (also in hex, without "0x" prefix). a3 specifies the revision. Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
CHECK_REV_IN_OPROM_NAME	device	string		Select this in the platform BIOS or chipset if the option rom has a revision that needs to be checked when searching CBFS.
VGA_BIOS_DGPU	device	bool	Add a discrete VGA BIOS image	Select this option if you have a VGA BIOS image for discrete GPU that you would like to add to your ROM. You will be able to specify the location and file name of the image later.
VGA_BIOS_DGPU_FILE	device	string	Discrete VGA BIOS path and filename	The path and filename of the file to use as VGA BIOS for discrete GPU.
VGA_BIOS_DGPU_ID	device	string	Discrete VGA device PCI IDs	The comma-separated PCI vendor and device ID that would associate your VGA BIOS to your discrete video card. Examples: 1002,6663 for HD 8570M 1002,6665 for R5 M230 In the above examples 1002 is the PCI vendor ID (in hex, but without the "0x" prefix) and 6663 / 6665 specifies the PCI device ID of the discrete video card (also in hex, without "0x" prefix). Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
INTEL_GMA_HAVE_VBT	device	bool		Select this in the mainboard Kconfig to indicate the board has a data.vbt file.
INTEL_GMA_ADD_VBT	device	bool	Add a Video BIOS Table (VBT) binary to CBFS	Add a VBT data file to CBFS. The VBT describes the integrated GPU and connections, and is needed by the GOP driver integrated into FSP and the OS driver in order to initialize the display.
INTEL_GMA_VBT_FILE	device	string	VBT binary path and filename	The path and filename of the VBT binary.
SOFTWARE_I2C	device	bool	Enable I2C controller emulation in software	This config option will enable code to override the i2c_transfer routine with a (simple) software emulation of the protocol. This may be useful for debugging or on platforms where a driver for the real I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines.
RESOURCE_ALLOCATOR_V3	device	bool		This config option enables resource allocator v3 which performs top down allocation of resources in a single MMIO window. This is the old resource allocator meant to be used only until the broken AMD chipsets are fixed. DO NOT USE THIS FOR ANY NEW CHIPSETS!
RESOURCE_ALLOCATOR_V4	device	bool		This config option enables resource allocator v4 which uses multiple ranges for allocating resources. This allows allocation of resources above 4G boundary as well.
XHCI_UTILS	device	bool		Provides xHCI utility functions.
Menu: Generic Drivers
CACHE_MRC_SETTINGS	drivers/mrc_cache	bool		Save cached MRC settings
MRC_WRITE_NV_LATE	drivers/mrc_cache	bool		MRC settings are normally written to NVRAM at BS_DEV_ENUMERATE-EXIT. If a platform requires MRC settings written to NVRAM later than normal, select this item. This will cause the write to occur at BS_OS_RESUME_CHECK-ENTRY.
MRC_STASH_TO_CBMEM	drivers/mrc_cache	bool		Instead of writing back MRC_CACHE training data back to the MRC_CACHE right away, stash the data into cbmem. This data will be written back later to MRC_CACHE. This is selected for platforms which either do not support writes to SPI flash in early stages (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES) or the platforms that need to write back the MRC data in late ramstage boot states (MRC_WRITE_NV_LATE).
MRC_SAVE_HASH_IN_TPM	drivers/mrc_cache	bool	Save a hash of the MRC_CACHE data in TPM NVRAM	Store a hash of the MRC_CACHE training data in a TPM NVRAM space to ensure that it cannot be tampered with.
COMMON_CBFS_SPI_WRAPPER	drivers/spi	bool		Use common wrapper to interface CBFS to SPI bootrom.
SPI_FLASH	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI flash.
SPI_SDCARD	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI sdcard.
BOOT_DEVICE_SPI_FLASH_BUS	drivers/spi	int		Which SPI bus the boot device is connected to.
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP	drivers/spi	bool		Provide common implementation of the RW boot device that doesn't provide mmap() operations.
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES	drivers/spi	bool		For platforms who do not allow writes to SPI flash in early stages like romstage. Not selecting this config will result in the auto-selection of BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP is selected by the platform.
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY	drivers/spi	bool		Include the common implementation in all stages, including the early ones.
SPI_FLASH_SMM	drivers/spi	bool		Select this option if you want SPI flash support in SMM.
SPI_FLASH_NO_FAST_READ	drivers/spi	bool	Disable Fast Read command	Select this option if your setup requires to avoid "fast read"s from the SPI flash parts.
SPI_FLASH_ADESTO	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Adesto Technologies.
SPI_FLASH_AMIC	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by AMIC.
SPI_FLASH_ATMEL	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Atmel.
SPI_FLASH_EON	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by EON.
SPI_FLASH_GIGADEVICE	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Gigadevice.
SPI_FLASH_MACRONIX	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Macronix.
SPI_FLASH_SPANSION	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Spansion.
SPI_FLASH_SST	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by SST.
SPI_FLASH_STMICRO	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by ST MICRO.
SPI_FLASH_WINBOND	drivers/spi	bool		Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Winbond.
SPI_FLASH_HAS_VOLATILE_GROUP	drivers/spi	bool		Allows chipset to group write/erase operations under a single volatile group.
REALTEK_8168_RESET	drivers/net	bool		This forces a realtek 10ec:8168 card to reset to ensure power state is correct at boot.
REALTEK_8168_MACADDRESS	drivers/net	string	Realtek rt8168 mac address	This is a string to set the mac address on a Realtek rt8168 card. It must be in the form of "xx:xx:xx:xx:xx:xx", where x is a hexadecimal number for it to be valid. Failing to do so will result in the default macaddress being used.
RT8168_SUPPORT_LEGACY_VPD_MAC	drivers/net	bool		Previously VPD expected that device_indexes set to zero were special cased. Selecting this Kconfig restores the legacy VPD format and behaviour. If unsure, you likely do not need this!
RT8168_SET_LED_MODE	drivers/net	bool		This is to set a customized LED mode to distinguish 10/100/1000 link and speed status with limited LEDs avaiable on a board. Please refer to RTL811x datasheet section 7.2 Customizable LED Configuration for details. With this flag enabled, the customized_leds variable will be read from devicetree setting.
ATHEROS_ATL1E_SETMAC	drivers/net	bool		This sets the MAC address on boards featuring the atheros 1968:1026 NIC which lack an eeprom to store it.
ATHEROS_ATL1E_MACADDRESS	drivers/net	string	Atheros AR8121/AR8113/AR8114 mac address	This is a string to set the mac address on an Atheros atl1e card. It must be in the form of "xx:xx:xx:xx:xx:xx", where x is a hexadecimal number for it to be valid. Failing to do so will result in the default MAC address being used.
TPM_INIT	drivers/tpm	bool		This driver automatically initializes the TPM if vboot is not used. The TPM driver init is done during the ramstage chip init phase.
TPM_PPI	drivers/tpm	bool	Generate ACPI code to implement TPM physical presence interface	This driver automatically generates ACPI tables for the Physical Presence Interface defined by the TCG. If not activated only a stub will be generated without any functionality.
GIC	drivers/gic	None		This option enables GIC support, the ARM generic interrupt controller.
VPD	drivers/vpd	bool	Support for Vital Product Data tables	Enable support for flash based vital product data.
VPD_FMAP_NAME	drivers/vpd	string		Name of the FMAP region created in the default FMAP to store VPD tables.
VPD_FMAP_SIZE	drivers/vpd	hex		Size in bytes of the FMAP region created to store VPD tables.
DIGITIZER_AUTODETECT	drivers/lenovo	bool	Autodetect	The presence of digitizer is inferred from model number stored in AT24RF chip.
DIGITIZER_PRESENT	drivers/lenovo	bool	Present	The digitizer is assumed to be present.
DIGITIZER_ABSENT	drivers/lenovo	bool	Absent	The digitizer is assumed to be absent.
USBDEBUG	drivers/usb	bool	USB 2.0 EHCI debug dongle support	This option allows you to use a so-called USB EHCI Debug device (such as the Ajays NET20DC, AMIDebug RX, or a system using the Linux "EHCI Debug Device gadget" driver found in recent kernel) to retrieve the coreboot debug messages (instead, or in addition to, a serial port). This feature is NOT supported on all chipsets in coreboot! It also requires a USB2 controller which supports the EHCI Debug Port capability. See https://www.coreboot.org/EHCI_Debug_Port for an up-to-date list of supported controllers. If unsure, say N.
USBDEBUG_IN_PRE_RAM	drivers/usb	bool	Enable early (pre-RAM) usbdebug	Configuring USB controllers in system-agent binary may cause problems to usbdebug. Disabling this option delays usbdebug to be setup on entry to ramstage. If unsure, say Y.
USBDEBUG_HCD_INDEX	drivers/usb	int	Index for EHCI controller to use with usbdebug	Some boards have multiple EHCI controllers with possibly only one having the Debug Port capability on an external USB port. Mapping of this index to PCI device functions is southbridge specific and mainboard level Kconfig should already provide a working default value here.
USBDEBUG_DEFAULT_PORT	drivers/usb	int	Default USB port to use as Debug Port	Selects which physical USB port usbdebug dongle is connected to. Setting of 0 means to scan possible ports starting from 1. Intel platforms have hardwired the debug port location and this setting makes no difference there. Hence, if you select the correct port here, you can speed up your boot time. Which USB port number refers to which actual port on your mainboard (potentially also USB pin headers on your mainboard) is highly board-specific, and you'll likely have to find out by trial-and-error.
USBDEBUG_DONGLE_STD	drivers/usb	bool	USB gadget driver or Net20DC	Net20DC, BeagleBone Black, Raspberry Pi Zero W
USBDEBUG_DONGLE_BEAGLEBONE	drivers/usb	bool	BeagleBone (not BeagleBone Black)	Use this to configure the USB hub on BeagleBone board. Do NOT select this for the BeagleBone Black.
USBDEBUG_DONGLE_FTDI_FT232H	drivers/usb	bool	FTDI FT232H UART	Use this with FT232H usb-to-uart. Configuration is hard-coded to use 8n1, no flow control.
USBDEBUG_DONGLE_FTDI_FT232H_BAUD	drivers/usb	int	FTDI FT232H baud rate	Select baud rate for FT232H in the range 733..12,000,000. Make sure that your receiving side supports the same setting and your connection works with it. Multiples of 115,200 seem to be a good choice, and EHCI debug usually can't saturate more than 576,000.
SMMSTORE_V2	drivers/smmstore	bool	Use version 2 of SMMSTORE API	Version 2 of SMMSTORE allows secure communication with SMM and makes no assumptions on the structure of the data stored within. It splits the store into chunks to allows fault tolerant writes. By using version 2 you cannot make use of software that expects a version 1 SMMSTORE.
SMMSTORE_IN_CBFS	drivers/smmstore	bool		Select this if you want to add an SMMSTORE region to a cbfsfile in a cbfs FMAP region
SMMSTORE_SIZE	drivers/smmstore	hex	size of the SMMSTORE FMAP region	Sets the size of the default SMMSTORE FMAP region. If using an UEFI payload, note that UEFI specifies at least 64K. The current implementation of SMMSTORE is append only, so until garbage collection is implemented it is better to set this to a rather large value.
CRB_TPM	drivers/crb	bool		CRB TPM driver is enabled!
CRB_TPM_BASE_ADDRESS	drivers/crb	hex		Base Address of the CRB TPM Command Structure
MAINBOARD_HAS_CRB_TPM	drivers/crb	bool		Mainboard has Command Response Buffer support
IPMI_KCS_REGISTER_SPACING	drivers/ipmi	int		KCS status and command register IO port address spacing
IPMI_FRU_SINGLE_RW_SZ	drivers/ipmi	int		The data size in a single IPMI FRU read/write command. IPMB messages are limited to 32-bytes total. When the data size is larger than this value, IPMI can complete reading/writing the data over multiple commands.
IPMI_KCS_ROMSTAGE	drivers/ipmi	bool		IPMI KCS support in romstage.
BMC_KCS_BASE	drivers/ipmi	hex		The PNP base address of BMC KCS. It must be equal to the pnp port value defined in devicetree for chip drivers/ipmi.
IPMI_KCS_TIMEOUT_MS	drivers/ipmi	int		The time unit is millisecond for each IPMI KCS transfer. IPMI spec v2.0 rev 1.1 Sec. 9.15, a five-second timeout or greater is recommended.
DRIVERS_IPMI_SUPERMICRO_OEM	drivers/ipmi	bool	Supermicro IPMI OEM BMC support	Tested on X11SSH only. Different BMCs might not support these OEM commands. The following features are implemented: * Communicates the BIOS version to the BMC * Communicates the BIOS date to the BMC
UART_OVERRIDE_INPUT_CLOCK_DIVIDER	drivers/uart	bool		Set to "y" when the platform overrides the uart_input_clock_divider routine.
UART_OVERRIDE_REFCLK	drivers/uart	bool		Set to "y" when the platform overrides the uart_platform_refclk routine.
DRIVERS_UART_OXPCIE	drivers/uart	bool	Oxford OXPCIe952	Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID 0xc158 or 0xc11b will work.
UART_USE_REFCLK_AS_INPUT_CLOCK	drivers/uart	bool		Use uart_platform_refclk to specify the input clock value.
UART_PCI_ADDR	drivers/uart	hex	UART's PCI bus, device, function address	Specify zero if the UART is connected to another bus type. For PCI based UARTs, build the value as: * 1 << 31 - Valid bit, PCI UART in use * Bus << 20 * Device << 15 * Function << 12
ELOG	drivers/elog	bool	Support for flash based event log	Enable support for flash based event logging.
ELOG_CBMEM	drivers/elog	bool	Store a copy of ELOG in CBMEM	This option will have ELOG store a copy of the flash event log in a CBMEM region and export that address in SMBIOS to the OS. This is useful if the ELOG location is not in memory mapped flash, but it means that events added at runtime via the SMI handler will not be reflected in the CBMEM copy of the log.
ELOG_GSMI	drivers/elog	bool	SMI interface to write and clear event log	This interface is compatible with the linux kernel driver available with CONFIG_GOOGLE_GSMI and can be used to write kernel reset/shutdown messages to the event log.
ELOG_BOOT_COUNT	drivers/elog	bool	Maintain a monotonic boot number in CMOS	Store a monotonic boot number in CMOS and provide an interface to read the current value and increment the counter. This boot counter will be logged as part of the System Boot event.
ELOG_BOOT_COUNT_CMOS_OFFSET	drivers/elog	int	Offset in CMOS to store the boot count	This value must be greater than 16 bytes so as not to interfere with the standard RTC region. Requires 8 bytes.
CHROMEOS_CAMERA	drivers/camera	bool		Camera with identifiers following Chrome OS Camera Info. The info is usually available on MIPI camera EEPROM for identifying correct drivers and config.
OCP_DMI	drivers/ocp/dmi	bool		It implements the SMBIOS IPMI FRU mapping table defined in https://www.opencompute.org/documents/facebook-xeon-motherboard-v31 22.3 SMBIOS FRU mapping table
DRIVER_PARADE_PS8625	drivers/parade/ps8625	bool		Parade ps8625 display port to lvds bridge
DRIVER_PARADE_PS8640	drivers/parade/ps8640	bool		Parade PS8640 MIPI DSI to eDP Converter
SPI_TPM	drivers/spi/tpm	bool		SPI TPM driver is enabled!
MAINBOARD_HAS_SPI_TPM_CR50	drivers/spi/tpm	bool		Board has a CR50 SPI TPM
MAINBOARD_HAS_SPI_TPM	drivers/spi/tpm	bool		Board has SPI TPM support
DRIVERS_EMULATION_QEMU_BOCHS	drivers/emulation/qemu	bool	bochs dispi interface vga driver	VGA driver for qemu emulated vga cards supporting the bochs dispi interface. This includes standard vga, vmware svga and qxl. The default vga (cirrus) is not supported, so you have to pick another one explicitly via 'qemu -vga $card'.
DRIVERS_I2C_SX9310	drivers/i2c/sx9310	bool		Board has a Semtech SX9310 proximity sensor.
DRIVERS_I2C_PCA9538	drivers/i2c/pca9538	bool		Enable support for I2C I/O expander PCA9538.
DRIVERS_I2C_PTN3460	drivers/i2c/ptn3460	bool		Enable support for external display bridge (eDP to LVDS) PTN3460.
DRIVERS_I2C_GPIO_MUX	drivers/i2c/gpiomux	bool		When enabled, add identifiers in ACPI tables for GPIO based I2C multiplexer.
DRIVERS_I2C_NCT7802Y	drivers/i2c/nct7802y	bool		The NCT7802Y by Nuvoton is a Hardware Monitoring IC.
I2C_TPM	drivers/i2c/tpm	bool		I2C TPM driver is enabled!
MAINBOARD_HAS_I2C_TPM_ATMEL	drivers/i2c/tpm	bool		Board has an Atmel I2C TPM support
MAINBOARD_HAS_I2C_TPM_CR50	drivers/i2c/tpm	bool		Board has a Cr50 I2C TPM support
MAINBOARD_HAS_I2C_TPM_GENERIC	drivers/i2c/tpm	bool		Board has a generic I2C TPM support
DRIVERS_I2C_LM96000	drivers/i2c/lm96000	bool		Hardware-monitoring IC LM96000.
DRIVERS_I2C_DESIGNWARE	drivers/i2c/designware	bool		Designware I2C support
DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ	drivers/i2c/designware	int		The i2c ip block's clock.
DRIVERS_I2C_SX9324	drivers/i2c/sx9324	bool		Board has a Semtech SX9324 proximity sensor.
DRIVERS_I2C_RTD2132	drivers/i2c/rtd2132	bool		Enable support for Realtek RTD2132 DisplayPort to LVDS bridge chip.
DRIVERS_I2C_RX6110SA	drivers/i2c/rx6110sa	bool		Enable support for external RTC chip RX6110 SA.
DRIVERS_WIFI_GENERIC	drivers/wifi/generic	bool		When enabled, add identifiers in ACPI tables that are common to WiFi chipsets from multiple vendors.
DRIVERS_INTEL_WIFI	drivers/wifi/generic	bool	Support Intel PCI-e WiFi adapters	When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets.
USE_SAR	drivers/wifi/generic	bool		Enable it when wifi driver uses SAR configuration feature. VPD entry "wifi_sar" is read to get SAR settings, if its not found driver may look into CBFS for default settigs. WIFI_SAR_CBFS is option to enable CBFS lookup.
WIFI_SAR_CBFS	drivers/wifi/generic	bool	Enable SAR table addition to CBFS	wifi driver would look for "wifi_sar" vpd key and load SAR settings from it, if the vpd key is not found then the driver tries to look for sar settings from CBFS with file name wifi_sar_defaults.hex. So OEM/ODM can override wifi sar with VPD.
DSAR_SET_NUM	drivers/wifi/generic	hex	Number of SAR sets when D-SAR is enabled	There can be up to 3 optional SAR table sets.
DRIVERS_TI_SN65DSI86BRIDGE	drivers/ti/sn65dsi86bridge	bool		TI SN65DSI86 eDP bridge driver
DRIVER_TI_TPS65090	drivers/ti/tps65090	bool		TI TPS65090
DRIVERS_USB_PCI_XHCI	drivers/usb/pci_xhci	None		PCI driver that generates ACPI nodes for an xHCI compatible controller.
MAINBOARD_HAS_LPC_TPM	drivers/pc80/tpm	bool		Board has LPC TPM support
TPM_TIS_BASE_ADDRESS	drivers/pc80/tpm	hex		This can be used to adjust the TPM memory base address. The default is specified by the TCG PC Client Specific TPM Interface Specification 1.2 and should not be changed unless the TPM being used does not conform to TPM TIS 1.2.
TPM_PIRQ	drivers/pc80/tpm	hex		This can be used to specify a PIRQ to use instead of SERIRQ, which is needed for SPI TPM interrupt support on x86.
VGA	drivers/pc80/vga	bool		Include legacy VGA support code.
DRIVERS_PS2_KEYBOARD	drivers/pc80/pc	bool	PS/2 keyboard init	Enable this option to initialize PS/2 keyboards found connected to the PS/2 port. Some payloads (eg, filo) require this option. Other payloads (eg, GRUB 2, SeaBIOS, Linux) do not require it. Initializing a PS/2 keyboard can take several hundred milliseconds. If you know you will only use a payload which does not require this option, then you can say N here to speed up boot time. Otherwise say Y.
PS2K_EISAID	drivers/pc80/pc	string		Mainboards can override the default to match vendor drivers and quirks.
PS2M_EISAID	drivers/pc80/pc	string		Mainboards can override the default to match vendor drivers and quirks.
IPMI_OCP	drivers/ipmi/ocp	bool		This implements OCP specific IPMI command
DRIVERS_INTEL_PMC	drivers/intel/pmc_mux	bool		When enabled, driver/intel/pmc_mux will add support for mux configuration of USB Type-C ports via the SoC's muxes.
INTEL_DDI	drivers/intel/gma	bool		helper functions for intel DDI operations
INTEL_GMA_SSC_ALTERNATE_REF	drivers/intel/gma	bool		Set when the SSC reference clock for LVDS runs at a different fre- quency than the general display reference clock. To be set by northbridge or mainboard Kconfig. For most platforms, there is no choice, i.e. for i945 and gm45 the SSC reference always differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Arrandale and newer, it's the same frequency for SSC/non-SSC (120MHz). The only, currently supported platform with a choice seems to be Pineview, where the alternative is 100MHz vs. the default 96MHz.
INTEL_GMA_SWSMISCI	drivers/intel/gma	bool		Select this option for Atom-based platforms which use the SWSMISCI register (0xe0) rather than the SWSCI register (0xe8).
GFX_GMA_IGNORE_PRESENCE_STRAPS	drivers/intel/gma	bool		libgfxinit uses the GPU presence straps to determine if a display port is present/enabled. Select this option if a board doesn't correctly implement these straps, causing libgfxinit to fail to detect an attached panel.
GFX_GMA_DYN_CPU	drivers/intel/gma	bool		Activates runtime CPU detection in libgfxinit.
GFX_GMA_ANALOG_I2C_PORT	drivers/intel/gma	string		Boards with a DVI-I connector share the I2C pins for both analog and digital displays. In that case, the EDID for a VGA display has to be read over the I2C interface of the coupled digital port.
DRIVERS_INTEL_DPTF	drivers/intel/dptf	bool		When enabled, entries in the devicetree are used to generate Intel DPTF Tables at runtime in the SSDT.
DPTF_USE_EISA_HID	drivers/intel/dptf	bool		Prior to Tiger Lake, all DPTF devices used 7-character EISA IDs. If selected, the 7-character _HIDs will be emitted, otherwise, it will use the "new" style, which are regular 8-character _HIDs.
DRIVERS_INTEL_MIPI_CAMERA	drivers/intel/mipi_camera	bool		MIPI CSI I2C camera SSDT generator. Generates SSDB and PWDB structures which are used by the Intel kernel drivers.
HAVE_INTEL_PTT	drivers/intel/ptt	bool		Activate if your platform has Intel Platform Trust Technology like Intel iTPM and you want to use it.
DRIVERS_INTEL_ISH	drivers/intel/ish	bool		When enabled, chip driver/intel/ish will publish information to the SSDT _DSD table for the ISH device.
PLATFORM_USES_FSP1_1	drivers/intel/fsp1_1	bool		Does the code require the Intel Firmware Support Package?
	drivers/intel/fsp1_1	(comment)		Intel FSP 1.1
HAVE_FSP_BIN	drivers/intel/fsp1_1	bool	Add Intel FSP binary to flash image	Select this option to add an Intel FSP binary to the resulting coreboot image. Note: Without this binary, coreboot builds relying on the FSP will not boot
FSP_FILE	drivers/intel/fsp1_1	string	Intel FSP binary path and filename	The path and filename of the Intel FSP binary for this platform.
FSP_LOC	drivers/intel/fsp1_1	hex	Intel FSP Binary location in CBFS	The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).
DISPLAY_UPD_DATA	drivers/intel/fsp1_1	bool	Display UPD data	Display the user specified product data prior to memory initialization.
USE_GENERIC_FSP_CAR_INC	drivers/intel/fsp1_1	bool		The chipset can select this to use a generic cache_as_ram.inc file that should be good for all FSP based platforms.
SKIP_FSP_CAR	drivers/intel/fsp1_1	bool		Selected by platforms that implement their own CAR setup.
FSP1_1_DISPLAY_LOGO	drivers/intel/fsp1_1	bool	Enable logo	Uses the FSP to display the boot logo. This method supports a BMP file only. The uncompressed size can be up to 1 MB.
PLATFORM_USES_FSP2_0	drivers/intel/fsp2_0	bool		Include FSP 2.0 wrappers and functionality
PLATFORM_USES_FSP2_1	drivers/intel/fsp2_0	bool		Include FSP 2.1 wrappers and functionality. Feature added into FSP 2.1 specification that impacts coreboot is: 1. Remove FSP stack switch and use the same stack with boot firmware
PLATFORM_USES_FSP2_2	drivers/intel/fsp2_0	bool		Include FSP 2.2 wrappers and functionality. Features added into FSP 2.2 specification that impact coreboot are: 1. Added multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API 2. FSP_INFO_HEADER changes to add FspMultiPhaseSiInitEntryOffset 3. Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change.
HAVE_INTEL_FSP_REPO	drivers/intel/fsp2_0	bool		Select this, if the FSP binaries for the platform are public and available in 3rdparty/fsp/. When selecting this option, the platform must also set FSP_HEADER_PATH and FSP_FD_PATH correctly.
FSP_USE_REPO	drivers/intel/fsp2_0	bool	Use binaries of the Intel FSP repository on GitHub	Select this option to use the default FSP headers and binaries found in the IntelFsp GitHub repository at https://github.com/IntelFsp/FSP/ If unsure, say Y.
FSP_HEADER_PATH	drivers/intel/fsp2_0	string	Location of FSP headers	Include directory with the FSP ABI header files.
ADD_FSP_BINARIES	drivers/intel/fsp2_0	bool	Add Intel FSP 2.0 binaries to CBFS	Add the FSP-M and FSP-S binaries to CBFS.
FSP_FULL_FD	drivers/intel/fsp2_0	bool	Use a combined FSP FD file	Use a combined FSP FD file instead of specifying individual, already split binaries and split the file at build-time.
FSP_FD_PATH	drivers/intel/fsp2_0	string	Location of FSP FD file	Path to the FSP FD file that contains the individual FSP-T, FSP-M and FSP-S binaries. The file gets split at build-time.
FSP_T_FILE	drivers/intel/fsp2_0	string	Intel FSP-T (temp RAM init) binary path and filename	The path and filename of the Intel FSP-T binary for this platform.
FSP_M_FILE	drivers/intel/fsp2_0	string	Intel FSP-M (memory init) binary path and filename	The path and filename of the Intel FSP-M binary for this platform.
FSP_S_FILE	drivers/intel/fsp2_0	string	Intel FSP-S (silicon init) binary path and filename	The path and filename of the Intel FSP-S binary for this platform.
FSP_CAR	drivers/intel/fsp2_0	bool		Use FSP APIs to initialize & Tear Down the Cache-As-Ram
FSP_M_XIP	drivers/intel/fsp2_0	bool		Select this value when FSP-M is execute-in-place.
FSP_T_XIP	drivers/intel/fsp2_0	bool		Select this value when FSP-T is execute-in-place.
FSP_USES_CB_STACK	drivers/intel/fsp2_0	bool		Enable support for fsp to use same stack as coreboot. This option allows fsp to continue using coreboot stack without reinitializing stack pointer. This feature is supported Icelake onwards.
FSP_TEMP_RAM_SIZE	drivers/intel/fsp2_0	hex		The amount of memory coreboot reserves for the FSP to use. In the case of FSP 2.1 and newer that share the stack with coreboot instead of having its own stack, this is the amount of anticipated heap usage in CAR by FSP to setup HOB and needs to be the recommended value from the Platform FSP integration guide. In the case of the FSP having its own stack that will be placed in DRAM and not in CAR, this is the amount of memory the FSP needs for its stack and heap.
FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS	drivers/intel/fsp2_0	bool		This is selected by SoC or mainboard to supply their own concept of a version for the memory settings respectively. This allows deployed systems to bump their version number with the same FSP which will trigger a retrain of the memory.
FSP_PEIM_TO_PEIM_INTERFACE	drivers/intel/fsp2_0	bool		This option allows SOC user to create specific PPI for Intel FSP usage, coreboot will provide required PPI structure definitions along with all APIs as per EFI specification. So far this feature is limited till EFI_PEI_MP_SERVICE_PPI and this option might be useful to add further PPI if required.
FSP2_0_DISPLAY_LOGO	drivers/intel/fsp2_0	bool	Enable logo	Uses the FSP to display the boot logo. This method supports a BMP file only. The uncompressed size can be up to 1 MB. The logo can be compressed using LZMA.
FSP_M_ADDR	drivers/intel/fsp2_0	hex		The address FSP-M will be relocated to during build time
FSP_STATUS_GLOBAL_RESET_REQUIRED_3	drivers/intel/fsp2_0	bool		FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
FSP_STATUS_GLOBAL_RESET_REQUIRED_4	drivers/intel/fsp2_0	bool		FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
FSP_STATUS_GLOBAL_RESET_REQUIRED_5	drivers/intel/fsp2_0	bool		FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
FSP_STATUS_GLOBAL_RESET_REQUIRED_6	drivers/intel/fsp2_0	bool		FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
FSP_STATUS_GLOBAL_RESET_REQUIRED_7	drivers/intel/fsp2_0	bool		FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
FSP_STATUS_GLOBAL_RESET_REQUIRED_8	drivers/intel/fsp2_0	bool		FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2
FSP_STATUS_GLOBAL_RESET	drivers/intel/fsp2_0	hex		If global reset is supported by SoC then select the correct status value for global reset type from SoC Kconfig based on available Kconfig options FSP_STATUS_GLOBAL_RESET_REQUIRED_X. Default is unsupported.
SOC_INTEL_COMMON_FSP_RESET	drivers/intel/fsp2_0	bool		Common code block to handle platform reset request raised by FSP. The FSP will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset is required.
FSP_USES_MP_SERVICES_PPI	drivers/intel/fsp2_0/ppi	bool		This option allows SoC user to create MP service PPI for Intel FSP usage, coreboot will provide EFI_PEI_MP_SERVICES_PPI structure definitions along with all APIs as per EDK2 specification. Intel FSP will use this PPI to run CPU feature programming on APs.
DRIVERS_SIL_3114	drivers/sil/3114	bool	Silicon Image SIL3114	It sets PCI class to IDE compatible native mode, allowing SeaBIOS, FILO etc... to boot from it.
DRIVERS_GENESYSLOGIC_GL9755	drivers/genesyslogic/gl9755	bool	Genesys Logic GL9755	GL9755 is a PCI Express Rev. 2.1 compliant card reader controller which integrates PCI Express PHY, UHS-II PHY, memory card access interface, regulators (3.3V-to-1.8V and 3.3V-to-1.2V) and card power switch.
DRIVERS_GFX_GENERIC	drivers/gfx/generic	bool		Include support for generic graphics device in devicetree
DRIVER_MAXIM_MAX77686	drivers/maxim/max77686	bool		Maxim MAX77686 power regulator
DRIVERS_GENERIC_CBFS_SERIAL	drivers/generic/cbfs-serial	bool	Serial number in CBFS	Enable this option to read the board serial number from a text file located in CBFS.
DRIVERS_INTEL_USB4_RETIMER	drivers/intel/usb4/retimer	bool		A retimer is a device that retransmits a fresh copy of the signal it receives, by doing CDR and retransmitting the data (i.e., it is protocol-aware). If your mainboard has a USB4 retimer (usually located close to the USB4 ports), then select this driver.
FSP_USES_MP_SERVICES_PPI	drivers/intel/fsp2_0/ppi	bool		This option allows SoC user to create MP service PPI for Intel FSP usage, coreboot will provide EFI_PEI_MP_SERVICES_PPI structure definitions along with all APIs as per EDK2 specification. Intel FSP will use this PPI to run CPU feature programming on APs.
STORAGE_ERASE	commonlib/storage	bool	Support SD/MMC erase operations	Select to enable SD/MMC erase oprations
STORAGE_WRITE	commonlib/storage	bool	Support SD/MMC write operations	Select to enable SD/MMC write oprations
SD_MMC_DEBUG	commonlib/storage	bool	Debug SD/MMC card/devices operations	Display overview of SD/MMC card/device operations
SD_MMC_TRACE	commonlib/storage	bool	Trace SD/MMC card/device operations	Display details of SD/MMC card/device operations
SDHC_DEBUG	commonlib/storage	bool	Debug SD/MMC controller settings	Display clock speed and bus width settings
SDHC_TRACE	commonlib/storage	bool	Trace SD/MMC controller operations	Display the operations performed by the SD/MMC controller
SDHCI_ADMA_IN_BOOTBLOCK	commonlib/storage	bool		Determine if bootblock is able to use ADMA2 or ADMA64
SDHCI_ADMA_IN_ROMSTAGE	commonlib/storage	bool		Determine if romstage is able to use ADMA2 or ADMA64
SDHCI_ADMA_IN_VERSTAGE	commonlib/storage	bool		Determine if verstage is able to use ADMA2 or ADMA64
Menu: Security
CBFS_VERIFICATION	lib.cbfs_verification	bool	# TODO: make user selectable once it works	Work in progress. Do not use (yet).
TOCTOU_SAFETY	lib.cbfs_verification	bool		Work in progress. Not actually TOCTOU safe yet. Do not use. Design idea here is that mcache overflows in this mode are only legal for the RW CBFS, because it's relatively easy to retrieve the RW metadata hash from persistent vboot context at any time, but the RO metadata hash is lost after the bootblock is unloaded. This avoids the need to carry yet another piece forward through the stages. Mcache overflows are mostly a concern for RW updates (if an update adds more files than originally planned for), for the RO section it should always be possible to dimension the mcache correctly beforehand, so this should be an acceptable limitation.
Menu: Verified Boot (vboot)
VBOOT_LIB	security/vboot	bool		Build and link the vboot library. Makes the vboot API accessible across all coreboot stages, without enabling vboot verification. For verification, please see the VBOOT option below.
VBOOT	security/vboot	bool	Verify firmware with vboot.	Enabling VBOOT will use vboot to verify the components of the firmware (stages, payload, etc).
	security/vboot	(comment)		Anti-Rollback Protection disabled because mocking secdata is enabled.
VBOOT_SLOTS_RW_A	security/vboot	bool	Firmware RO + RW_A	Have one update partition beside the RO partition.
VBOOT_SLOTS_RW_AB	security/vboot	bool	Firmware RO + RW_A + RW_B	Have two update partitions beside the RO partition.
VBOOT_VBNV_CMOS	security/vboot	bool		VBNV is stored in CMOS
VBOOT_VBNV_OFFSET	security/vboot	hex		CMOS offset for VbNv data. This value must match cmos.layout in the mainboard directory, minus 14 bytes for the RTC.
VBOOT_VBNV_CMOS_BACKUP_TO_FLASH	security/vboot	bool		Vboot non-volatile storage data will be backed up from CMOS to flash and restored from flash if the CMOS is invalid due to power loss.
VBOOT_VBNV_EC	security/vboot	bool		VBNV is stored in EC
VBOOT_VBNV_FLASH	security/vboot	bool		VBNV is stored in flash storage
VBOOT_STARTS_BEFORE_BOOTBLOCK	security/vboot	bool		Firmware verification happens before the main processor is brought online.
VBOOT_STARTS_IN_BOOTBLOCK	security/vboot	bool		Firmware verification happens during the end of or right after the bootblock. This implies that a static VBOOT2_WORK() buffer must be allocated in memlayout.
VBOOT_STARTS_IN_ROMSTAGE	security/vboot	bool		Firmware verification happens during the end of romstage (after memory initialization). This implies that the vboot work buffer is in CBMEM from the start and doesn't need to be reserved in memlayout.
VBOOT_MOCK_SECDATA	security/vboot	bool	Mock secdata for firmware verification	Enabling VBOOT_MOCK_SECDATA will mock secdata for the firmware verification to avoid access to a secdata storage (typically TPM). All operations for a secdata storage will be successful. This option can be used during development when a TPM is not present or broken. THIS SHOULD NOT BE LEFT ON FOR PRODUCTION DEVICES.
VBOOT_DISABLE_DEV_ON_RECOVERY	security/vboot	bool		When this option is enabled, the Chrome OS device leaves the developer mode as soon as recovery request is detected. This is handy on embedded devices with limited input capabilities.
VBOOT_SEPARATE_VERSTAGE	security/vboot	bool		If this option is set, vboot verification runs in a standalone stage that is loaded from the bootblock and exits into romstage. If it is not set, the verification code is linked directly into the bootblock or the romstage and runs as part of that stage (cf. related options VBOOT_STARTS_IN_BOOTBLOCK/_ROMSTAGE and VBOOT_RETURN_FROM_VERSTAGE).
VBOOT_RETURN_FROM_VERSTAGE	security/vboot	bool		If this is set, the verstage returns back to the calling stage instead of exiting to the succeeding stage so that the verstage space can be reused by the succeeding stage. This is useful if a RAM space is too small to fit both the verstage and the succeeding stage.
VBOOT_MUST_REQUEST_DISPLAY	security/vboot	bool		Set this option to indicate to vboot that this platform will skip its display initialization on a normal (non-recovery, non-developer) boot. Unless display is specifically requested, the video option ROM is not loaded, and any other native display initialization code is not run.
VBOOT_ALWAYS_ENABLE_DISPLAY	security/vboot	bool	Force to always enable display	Set this option to indicate to vboot that display should always be enabled.
VBOOT_ALWAYS_ALLOW_UDC	security/vboot	bool	Always allow UDC	This option allows UDC to be enabled regardless of the vboot state.
VBOOT_HAS_REC_HASH_SPACE	security/vboot	bool		Set this option to indicate to vboot that recovery data hash space is present in TPM.
VBOOT_LID_SWITCH	security/vboot	bool		Whether this platform has a lid switch. If it does, vboot will not decrement try counters for boot failures if the lid is closed.
VBOOT_WIPEOUT_SUPPORTED	security/vboot	bool		When this option is enabled, the firmware provides the ability to signal the application the need for factory reset (a.k.a. wipe out) of the device
VBOOT_FWID_MODEL	security/vboot	string	Firmware ID model	This is the first part of the FWID written to various regions of a vboot firmware image to identify its version.
VBOOT_FWID_VERSION	security/vboot	string	Firmware ID version	This is the second part of the FWID written to various regions of a vboot firmware image to identify its version.
VBOOT_NO_BOARD_SUPPORT	security/vboot	bool	Allow the use of vboot without board support	Enable weak functions for get_write_protect_state and get_recovery_mode_switch in order to proceed with refactoring of the vboot2 code base. Later on this code is removed and replaced by interfaces.
RO_REGION_ONLY	security/vboot	string	Additional files that should not be copied to RW	Add a space delimited list of filenames that should only be in the RO section.
RW_REGION_ONLY	security/vboot	string		Add a space delimited list of filenames that should only be in the RW sections.
RWA_REGION_ONLY	security/vboot	string		Add a space-delimited list of filenames that should only be in the RW-A section.
RWB_REGION_ONLY	security/vboot	string		Add a space-delimited list of filenames that should only be in the RW-B section.
VBOOT_ENABLE_CBFS_FALLBACK	security/vboot	bool		When this option is enabled cbfs_boot_locate will look for a file in the RO (COREBOOT) region if it isn't available in the active RW region.
VBOOT_EARLY_EC_SYNC	security/vboot	bool		Enables CrOS EC software sync in romstage, before memory training runs. This is useful mainly as a way to achieve full USB-PD negotiation earlier in the boot flow, as the EC will only do this once it has made the sysjump to its RW firmware. It should not significantly impact boot time, as this operation will be performed later in the boot flow if it is disabled here.
VBOOT_EC_EFS	security/vboot	bool	Early firmware selection (EFS) EC	CrosEC can support EFS: Early Firmware Selection. If it's enabled, software sync needs to also support it. This setting tells vboot to perform EFS software sync.
Menu: GBB configuration
GBB_HWID	security/vboot	string	Hardware ID	A hardware identifier for device. On Chrome OS this is used for auto update and recovery, and will be generated when manufacturing by the factory software, in a strictly defined format. Leave empty to get a test-only Chrome OS HWID v2 string generated.
Menu: Vboot Keys
VBOOT_HASH_BLOCK_SIZE	security/vboot	hex		Set the default hash size. Generally 1k is reasonable, but in some cases it may improve hashing speed to increase the size. Note that this buffer is allocated in the stack. Although the build should fail if the stack size is exceeded, it's something to be aware of when changing the size.
POWER_OFF_ON_CR50_UPDATE	security/tpm/tss/vendor/cr50	bool		Power off machine while waiting for CR50 update to take effect.
CR50_USE_LONG_INTERRUPT_PULSES	security/tpm/tss/vendor/cr50	bool		Whether to request longer interrupt pulses using Cr50 BOARD_CFG register. If the Cr50 firmware is too old, it will not be able to honor the request.
Menu: Trusted Platform Module
USER_TPM1	security/tpm	bool	1.2	Enable this option to enable TPM 1.0 - 1.2 support in coreboot. If unsure, say N.
USER_TPM2	security/tpm	bool	2.0	Enable this option to enable TPM 2.0 support in coreboot. If unsure, say N.
TPM_DEACTIVATE	security/tpm	bool	Deactivate TPM	Deactivate TPM by issuing deactivate command.
DEBUG_TPM	security/tpm	bool	Output verbose TPM debug messages	This option enables additional TPM related debug messages.
TPM_RDRESP_NEED_DELAY	security/tpm	bool	Enable Delay Workaround for TPM	Certain TPMs seem to need some delay when reading response to work around a race-condition-related issue, possibly caused by ill-programmed TPM firmware.
TPM_STARTUP_IGNORE_POSTINIT	security/tpm	bool		Select this to ignore POSTINIT INVALID return codes on TPM startup. This is useful on platforms where a previous stage issued a TPM startup. Examples of use cases are Intel TXT or VBOOT on the Intel Arrandale processor, which issues a CPU-only reset during the romstage.
TPM_MEASURED_BOOT	security/tpm	bool	Enable Measured Boot	Enables measured boot (experimental)
TPM_MEASURED_BOOT_RUNTIME_DATA	security/tpm	string	Runtime data whitelist	Runtime data whitelist of cbfs filenames. Needs to be a space delimited list
Menu: Memory initialization
PLATFORM_HAS_DRAM_CLEAR	security/memory	bool		Selected by platforms that support clearing all DRAM after DRAM initialization.
SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT	security/memory	bool	Always clear all DRAM on regular boot	Always clear the DRAM after DRAM initialization regardless of additional security implementations in use. This increases boot time depending on the amount of DRAM installed.
INTEL_TXT_BIOSACM_FILE	security/intel/txt	string	BIOS ACM file	Intel TXT BIOS ACM file. This file can be obtained through privileged access to Intel resources. Or for some platforms found inside the blob repository.
INTEL_TXT_SINITACM_FILE	security/intel/txt	string	SINIT ACM file	Intel TXT SINIT ACM file. This file can be obtained through privileged access to Intel resources. Or for some platforms found inside the blob repository.
INTEL_TXT_DPR_SIZE	security/intel/txt	int		Specify the size the DPR region needs to have. On at least Haswell, the MRC does not have an input to specify the size of DPR, so this field is only used to check if the programmed size is large enough.
INTEL_TXT_TEST_BIOS_ACM_CALLING_CODE	security/intel/txt	bool	Test BIOS ACM calling code with NOP function	Run a NOP function of the BIOS ACM to check that the ACM calling code is functioning properly. Use in pre-production environments only!
INTEL_TXT_LOGGING	security/intel/txt	bool	Enable verbose logging	Print more TXT related debug output. Use in pre-production environments only!
INTEL_TXT_BIOSACM_ALIGNMENT	security/intel/txt	hex		Exceptions are Ivy and Sandy Bridge with 64 KiB and Purley with 256 KiB alignment size. If necessary, override from platform-specific Kconfig.
INTEL_TXT_SINIT_SIZE	security/intel/txt	hex		This is the size that will be programmed in TXT_SINIT_SIZE. This needs to be at least the size of the SINIT ACM. This is platform dependent. For instance on CPX this has to be the ACM size + 64K.
INTEL_TXT_HEAP_SIZE	security/intel/txt	hex		This is the size that will be programmed in TXT_HEAP_SIZE. This is platform dependent.
STM	security/intel/stm	bool	Enable STM	Enabling the STM will load a simple hypervisor into SMM that will restrict the actions of the SMI handler, which is the part of BIOS that functions in system management mode (SMM). The kernel can configure the STM to prevent the SMI handler from accessing platform resources. The STM closes a vulnerability in Intel TXT (D-RTM) The SMI handler provides a list of platform resources that it requires access to the STM during STM startup, which the kernel cannot override. An additional capability, called STM-PE, provides a protected execution capability that allows modules to be executed without observation and interference. Examples of usage include kernel introspection and virtualized trusted platform module (vTPM). Requirement: SMM must be enabled and there must be sufficient room within the TSEG to fit the MSEG.
Menu: SMI Transfer Monitor (STM)
MSEG_SIZE	security/intel/stm	hex	mseg size	The MSEG_SIZE of 0x100000 assumes that: IED_REGION_SIZE = 0x400000 SMM_RESERVED_SIZE = 0x200000 SMM_TSEG_SIZE = 0x800000 To use STM/PE, a larger MSEG_SIZE is necessary. This can be done by either increasing SMM_TSEG_SIZE or reducing the IED_REGION_SIZE and/or SMM_RESERVED_SIZE or some combination of the three. NOTE: The authors experience is that these configuration parameters have to be changed at the soc Konfig for them to be applied. Minimum sizes: STM only - 0x100000 - Supports up to 38 processor threads - 0x200000 - Supports up to 102 processor threads STM/PE - 0x300000+ depending on the amount of memory needed for the protected execution virtual machine (VM/PE)
STM_STMPE_ENABLED	security/intel/stm	bool	STM/PE Enabled	STM/PE provides for additional virtual machines in SMRAM that provides a protected execution environment for applications such as introspection, which need to be protected from malicious code. More information can be found on the stmpe branch of https://review.coreboot.org/STM
BIOS_RESOURCE_LIST_SIZE	security/intel/stm	hex	bios resource list size	The BIOS resource list defines the resources that the SMI handler needs. This list is created during the coreboot bootup. Unless there has been a lot of elements added to this list, this value should not change.
STM_BINARY_FILE	security/intel/stm	string	STM binary file	Location of the STM binary file. The default location is where the file will be located when coreboot builds the STM.
STM_HEAPSIZE	security/intel/stm	hex	stm heapsize	The STM_HEAPSIZE defines the heap space that is available to the STM. The default size assumes a MSEG_SIZE of 0x100000. For STM/PE this size should be a minimum of 0x246000.
STM_TTYS0_BASE	security/intel/stm	hex	stm uart	Defines the serial port for STM console output. 0x000 indicates no serial port.
STM_CBMEM_CONSOLE	security/intel/stm	bool	STM cbmem console	Places the STM console output into the cbmem.
STM_CONSOLE_DEBUG	security/intel/stm	bool	Debug output	"Produces all STM console output"
STM_CONSOLE_RELEASE	security/intel/stm	bool	Deactivate console output	"No console output is produced"
INTEL_CBNT_SUPPORT	security/intel/cbnt	bool	Intel CBnT support	Enables Intel Converged Bootguard and Trusted Execution Technology Support. This will enable one to add a Key Manifest (KM) and a Boot Policy Manifest (BPM) to the filesystem. It will also wrap a FIT around the firmware and update appropriate entries.
INTEL_CBNT_KEY_MANIFEST_BINARY	security/intel/cbnt	string	KM (Key Manifest) binary location	Location of the Key Manifest (KM)
INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY	security/intel/cbnt	string	BPM (Boot Policy Manifest) binary location	Location of the Boot Policy Manifest (BPM)
BOOTMEDIA_LOCK_CONTROLLER	security/lockdown	bool	Lock boot media using the controller	Select this if you want the controller to lock specific regions. This only works on some platforms, please check the code or boot log. On Intel platforms for e.g. this will make use of the SPIBAR PRRs.
BOOTMEDIA_LOCK_CHIP	security/lockdown	bool	Lock boot media using the chip	Select this if you want the chip to lock specific regions. This only works on some chips, please check the code or search the boot log for "BM-LOCKDOWN".
BOOTMEDIA_LOCK_WHOLE_RO	security/lockdown	bool	Write-protect the whole boot medium	Select this if you want to write-protect the whole firmware boot medium. The locking will take place during the chipset lockdown. Chipset lockdown is platform specific und might be done unconditionally, when INTEL_CHIPSET_LOCKDOWN is set or has to be triggered later (e.g. by the payload or the OS). NOTE: If you trigger the chipset lockdown unconditionally, you won't be able to write to the whole flash chip using the internal controller any more.
BOOTMEDIA_LOCK_WHOLE_NO_ACCESS	security/lockdown	bool	Read- and write-protect the whole boot medium	Select this if you want to protect the firmware boot medium against all further accesses. On platforms that memory map a part of the boot medium the corresponding region is still readable. The locking will take place during the chipset lockdown. Chipset lockdown is platform specific und might be done unconditionally, when INTEL_CHIPSET_LOCKDOWN is set or has to be triggered later (e.g. by the payload or the OS). NOTE: If you trigger the chipset lockdown unconditionally, you won't be able to write to the whole flash chip using the internal controller any more.
BOOTMEDIA_LOCK_WPRO_VBOOT_RO	security/lockdown	bool	Write-protect WP_RO FMAP region in boot medium	Select this if you want to write-protect the WP_RO region as specified in the VBOOT FMAP. You will be able to write every region outside of WP_RO using the internal controller (eg. FW_MAIN_A/FW_MAIN_B). In case of BOOTMEDIA_LOCK_IN_VERSTAGE the locking will take place early, preventing locking of facilities used in ramstage, like the MRC cache. If not using BOOTMEDIA_LOCK_IN_VERSTAGE the chipset lockdown is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. by the payload or the OS).
BOOTMEDIA_LOCK_IN_VERSTAGE	security/lockdown	bool	Lock boot media down in verstage	Select this if you want to write-protect the WP_RO region as soon as possible. This option prevents using write protecting facilities in ramstage, like the MRC cache for example. Use this option if you don't trust code running after verstage.
BOOTMEDIA_SPI_LOCK_REBOOT	security/lockdown	bool	Lock SPI flash until next reboot	The SPI chip is locked until power is removed and re-applied. Supported by Winbond parts.
BOOTMEDIA_SPI_LOCK_PIN	security/lockdown	bool	Lock SPI flash using WP# pin	The SPI chip is locked using a non-volatile configuration bit. Writes are only possible if the WP# is not asserted. Supported by Winbond and Macronix parts.
BOOTMEDIA_SPI_LOCK_PERMANENT	security/lockdown	bool	Lock SPI flash permanently	The SPI chip is permanently locked using a non-volatile configuration bit. No writes are ever possible again after we perform the lock. Supported by Winbond parts.
Menu: Eltan Security Settings
Menu: Measured Boot (mboot)
VENDORCODE_ELTAN_MBOOT	vendorcode/eltan/security/mboot	bool	Measure firmware with mboot.	Enabling MBOOT will use mboot to measure the components of the firmware (stages, payload, etc).
Menu: Verified Boot (verified_boot)
VENDORCODE_ELTAN_VBOOT_USE_SHA512	vendorcode/eltan/security/verified_boot	bool	SHA512 hashes	Use SHA512 for the vboot operations, this applies to the digest in the manifest and the manifest digest.
ACPI_AMD_HARDWARE_SLEEP_VALUES	acpi	None		Provide common definitions for AMD hardware PM1_CNT register sleep values.
ACPI_CPU_STRING	acpi	string		Sets the ACPI name string in the processor scope as written by the acpigen function. Default is \_SB.CPxx. Note that you need the \ escape character in the string.
ACPI_INTEL_HARDWARE_SLEEP_VALUES	acpi	string		Provide common definitions for Intel hardware PM1_CNT register sleep values.
ACPI_SOC_NVS	acpi	bool		Set to indicate <soc/nvs.h> exists for the platform with a definition for global_nvs.
ACPI_NO_PCAT_8259	acpi	bool		Selected by platforms that don't expose a PC/AT 8259 PIC pair.
HAVE_ACPI_TABLES	acpi	bool		This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig.
ACPI_LPIT	acpi	bool		Selected by platforms that support and fill Intel Low Power Idle Table.
BOOT_DEVICE_MEMORY_MAPPED	toplevel	bool		Inform system if SPI is memory-mapped or not.
BOOT_DEVICE_SUPPORTS_WRITES	toplevel	bool		Indicate that the platform has writable boot device support.
Menu: Console
BOOTBLOCK_CONSOLE	console	bool	Enable early (bootblock) console output.	Use console during the bootblock if supported
POSTCAR_CONSOLE	console	bool	Enable console output during postcar.	Use console during the postcar if supported
SQUELCH_EARLY_SMP	console	bool	Squelch AP CPUs from early console.	When selected only the BSP CPU will output to early console. Console drivers have unpredictable behaviour if multiple threads attempt to share the same resources without a spinlock. If unsure, say Y.
CONSOLE_SERIAL	console	bool	Serial port console output	Send coreboot debug output to a serial port. The type of serial port driver selected based on your configuration is shown on the following menu line. Supporting multiple different types of UARTs in one build is not supported.
FIXED_UART_FOR_CONSOLE	console	bool		Select to remove the prompt from UART_FOR_CONSOLE in case a specific UART has to be used (e.g. when the platform code performs dangerous configurations).
	console	(comment)		I/O mapped, 8250-compatible
	console	(comment)		memory mapped, 8250-compatible
	console	(comment)		device-specific UART
OVERRIDE_UART_FOR_CONSOLE	console	bool		Set to "y" when the platform overrides the index of uart port by providing a get_uart_for_console routine.
UART_FOR_CONSOLE	console	int	Index for UART port to use for console	Select an I/O port to use for serial console: 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8
TTYS0_BASE	console	hex		Map the COM port number to the respective I/O port.
	console	(comment)		Serial port base address = 0x3f8
	console	(comment)		Serial port base address = 0x2f8
	console	(comment)		Serial port base address = 0x3e8
	console	(comment)		Serial port base address = 0x2e8
UART_OVERRIDE_BAUDRATE	console	bool		Set to "y" when the platform overrides the baudrate by providing a get_uart_baudrate routine.
CONSOLE_SERIAL_921600	console	bool	921600	Set serial port Baud rate to 921600.
CONSOLE_SERIAL_460800	console	bool	460800	Set serial port Baud rate to 460800.
CONSOLE_SERIAL_230400	console	bool	230400	Set serial port Baud rate to 230400.
CONSOLE_SERIAL_115200	console	bool	115200	Set serial port Baud rate to 115200.
CONSOLE_SERIAL_57600	console	bool	57600	Set serial port Baud rate to 57600.
CONSOLE_SERIAL_38400	console	bool	38400	Set serial port Baud rate to 38400.
CONSOLE_SERIAL_19200	console	bool	19200	Set serial port Baud rate to 19200.
CONSOLE_SERIAL_9600	console	bool	9600	Set serial port Baud rate to 9600.
TTYS0_BAUD	console	int		Map the Baud rates to an integer.
SPKMODEM	console	bool	spkmodem (console on speaker) console output	Send coreboot debug output through speaker
CONSOLE_USB	console	bool	USB dongle console output	Send coreboot debug output to USB. Configuration for USB hardware is under menu Generic Drivers.
CONSOLE_NE2K	console	bool	Network console over NE2000 compatible Ethernet adapter	Send coreboot debug output to a Ethernet console, it works same way as Linux netconsole, packets are received to UDP port 6666 on IP/MAC specified with options bellow. Use following netcat command: nc -u -l -p 6666
CONSOLE_NE2K_DST_MAC	console	string	Destination MAC address of remote system	Type in either MAC address of logging system or MAC address of the router.
CONSOLE_NE2K_DST_IP	console	string	Destination IP of logging system	This is IP address of the system running for example netcat command to dump the packets.
CONSOLE_NE2K_SRC_IP	console	string	IP address of coreboot system	This is the IP of the coreboot system
CONSOLE_NE2K_IO_PORT	console	hex	NE2000 adapter fixed IO port address	This is the IO port address for the IO port on the card, please select some non-conflicting region, 32 bytes of IO spaces will be used (and align on 32 bytes boundary, qemu needs broader align)
CONSOLE_CBMEM	console	bool	Send console output to a CBMEM buffer	Enable this to save the console output in a CBMEM buffer. This would allow to see coreboot console output from Linux space.
CONSOLE_CBMEM_BUFFER_SIZE	console	hex	Room allocated for console output in CBMEM	Space allocated for console output storage in CBMEM. The default value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level.
CONSOLE_CBMEM_DUMP_TO_UART	console	bool	Dump CBMEM console on resets	Enable this to have CBMEM console buffer contents dumped on the serial output in case serial console is disabled and the device resets itself while trying to boot the payload.
CONSOLE_SPI_FLASH	console	bool	SPI Flash console output	Send coreboot debug output to the SPI Flash in the FMAP CONSOLE area This option can cause premature wear on the SPI flash and should not be used as a normal means of debugging. It is only to be enabled and used when porting a new motherboard which has no other console available (no UART, no POST, no cbmem access(non bootable)). Since a non bootable machine will require the use of an external SPI Flash programmer, the developer can grab the console log at the same time. The flash console will not be erased on reboot, so once it is full, the flashconsole driver will stop writing to it. This is to avoid wear on the flash, and to avoid erasing sectors (which may freeze the SPI controller on skylake). The 'CONSOLE' area can be extracted from the FMAP with : cbfstool rom.bin read -r CONSOLE -f console.log
CONSOLE_SPI_FLASH_BUFFER_SIZE	console	hex	Room allocated for console output in FMAP	Space allocated for console output storage in FMAP. The default value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level.
CONSOLE_QEMU_DEBUGCON	console	bool	QEMU debug console output	Send coreboot debug output to QEMU's isa-debugcon device: qemu-system-x86_64 \ -chardev file,id=debugcon,path=/dir/file.log \ -device isa-debugcon,iobase=0x402,chardev=debugcon
EM100PRO_SPI_CONSOLE	console	bool	EM100Pro SPI debug console output	Enable support for the debug console on the Dediprog EM100Pro. This is currently working only in ramstage due to how the spi drivers are written.
CONSOLE_SYSTEM76_EC	console	bool	System76 EC console output	Send coreboot debug output to a System76 embedded controller.
CONSOLE_OVERRIDE_LOGLEVEL	console	bool		Set to "y" when the platform overrides the loglevel by providing a get_console_loglevel routine.
DEFAULT_CONSOLE_LOGLEVEL_8	console	bool	8: SPEW	Way too many details.
DEFAULT_CONSOLE_LOGLEVEL_7	console	bool	7: DEBUG	Debug-level messages.
DEFAULT_CONSOLE_LOGLEVEL_6	console	bool	6: INFO	Informational messages.
DEFAULT_CONSOLE_LOGLEVEL_5	console	bool	5: NOTICE	Normal but significant conditions.
DEFAULT_CONSOLE_LOGLEVEL_4	console	bool	4: WARNING	Warning conditions.
DEFAULT_CONSOLE_LOGLEVEL_3	console	bool	3: ERR	Error conditions.
DEFAULT_CONSOLE_LOGLEVEL_2	console	bool	2: CRIT	Critical conditions.
DEFAULT_CONSOLE_LOGLEVEL_1	console	bool	1: ALERT	Action must be taken immediately.
DEFAULT_CONSOLE_LOGLEVEL_0	console	bool	0: EMERG	System is unusable.
DEFAULT_CONSOLE_LOGLEVEL	console	int		Map the log level config names to an integer.
CMOS_POST	console	bool	Store post codes in CMOS for debugging	If enabled, coreboot will store post codes in CMOS and switch between two offsets on each boot so the last post code in the previous boot can be retrieved. This uses 3 bytes of CMOS.
CMOS_POST_OFFSET	console	hex	Offset into CMOS to store POST codes	If CMOS_POST is enabled then an offset into CMOS must be provided. If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value defined in the mainboard option table.
CONSOLE_POST	console	bool	Show POST codes on the debug console	If enabled, coreboot will additionally print POST codes (which are usually displayed using a so-called "POST card" ISA/PCI/PCI-E device) on the debug console.
POST_IO	console	bool	Send POST codes to an IO port	If enabled, POST codes will be written to an IO port.
POST_IO_PORT	console	hex	IO port for POST codes	POST codes on x86 are typically written to the LPC bus on port 0x80. However, it may be desirable to change the port number depending on the presence of coprocessors/microcontrollers or if the platform does not support IO in the conventional x86 manner.
NO_EARLY_BOOTBLOCK_POSTCODES	console	hex		Some chipsets require that the routing for the port 80h POST code be configured before any POST codes are sent out. This can be done in the boot block, but there are a couple of POST codes that go out before the chipset's bootblock initialization can happen. This option suppresses those POST codes.
DISABLE_ACPI_HIBERNATE	toplevel	bool		Removes S4 from the available sleepstates
RESUME_PATH_SAME_AS_BOOT	toplevel	bool		This option indicates that when a system resumes it takes the same path as a regular boot. e.g. an x86 system runs from the reset vector at 0xfffffff0 on both resume and warm/cold boot.
HAVE_MONOTONIC_TIMER	toplevel	bool		The board/chipset provides a monotonic timer.
GENERIC_UDELAY	toplevel	bool		The board/chipset uses a generic udelay function utilizing the monotonic timer.
TIMER_QUEUE	toplevel	bool		Provide a timer queue for performing time-based callbacks.
COOP_MULTITASKING	toplevel	bool		Cooperative multitasking allows callbacks to be multiplexed on the main thread of ramstage. With this enabled it allows for multiple execution paths to take place when they have udelay() calls within their code.
NUM_THREADS	toplevel	int		How many execution threads to cooperatively multitask with.
HAVE_OPTION_TABLE	toplevel	bool		This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. It defaults to 'n' but can be selected in mainboard/*/Kconfig.
GFXUMA	toplevel	bool		Enable Unified Memory Architecture for graphics.
HAVE_MP_TABLE	toplevel	bool		This variable specifies whether a given board has MP table support. It is usually set in mainboard/*/Kconfig. Whether or not the MP table is actually generated by coreboot is configurable by the user via GENERATE_MP_TABLE.
HAVE_PIRQ_TABLE	toplevel	bool		This variable specifies whether a given board has PIRQ table support. It is usually set in mainboard/*/Kconfig. Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE.
ACPI_NHLT	toplevel	bool		Build support for NHLT (non HD Audio) ACPI table generation.
Menu: System tables
GENERATE_MP_TABLE	toplevel	bool	Generate an MP table	Generate an MP table (conforming to the Intel MultiProcessor specification 1.4) for this board. If unsure, say Y.
GENERATE_PIRQ_TABLE	toplevel	bool	Generate a PIRQ table	Generate a PIRQ table for this board. If unsure, say Y.
GENERATE_SMBIOS_TABLES	toplevel	bool	Generate SMBIOS tables	Generate SMBIOS tables for this board. If unsure, say Y.
MAINBOARD_SERIAL_NUMBER	toplevel	string	SMBIOS Serial Number	The Serial Number to store in SMBIOS structures.
MAINBOARD_VERSION	toplevel	string	SMBIOS Version Number	The Version Number to store in SMBIOS structures.
MAINBOARD_SMBIOS_MANUFACTURER	toplevel	string	SMBIOS Manufacturer	Override the default Manufacturer stored in SMBIOS structures.
MAINBOARD_SMBIOS_PRODUCT_NAME	toplevel	string	SMBIOS Product name	Override the default Product name stored in SMBIOS structures.
VPD_SMBIOS_VERSION	toplevel	bool	Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'	Selecting this option will read firmware_version from VPD_RO and override SMBIOS type 0 version. One special scenario of using this feature is to assign a BIOS version to a coreboot image without the need to rebuild from source.
Menu: Payload
PAYLOAD_NONE	payloads	bool	None	Select this option if you want to create an "empty" coreboot ROM image for a certain mainboard, i.e. a coreboot ROM image which does not yet contain a payload. For such an image to be useful, you have to use 'cbfstool' to add a payload to the ROM image later.
PAYLOAD_ELF	payloads	bool	An ELF executable payload	Select this option if you have a payload image (an ELF file) which coreboot should run as soon as the basic hardware initialization is completed. You will be able to specify the location and file name of the payload image later.
PAYLOAD_FIT	payloads	bool	A FIT payload	Select this option if you have a payload image (a FIT file) which coreboot should run as soon as the basic hardware initialization is completed. You will be able to specify the location and file name of the payload image later.
PAYLOAD_DEPTHCHARGE	payloads/external/depthcharge.name	bool	Depthcharge	Select this option if you want to build a coreboot image with a depthcharge payload. See https://coreboot.org/Payloads for more information.
PAYLOAD_FILO	payloads/external/FILO.name	bool	FILO	Select this option if you want to build a coreboot image with a FILO payload. If you don't know what this is about, just leave it enabled. See https://coreboot.org/Payloads for more information.
PAYLOAD_SEABIOS	payloads/external/SeaBIOS.name	bool	SeaBIOS	Select this option if you want to build a coreboot image with a SeaBIOS payload. If you don't know what this is about, just leave it enabled. See https://coreboot.org/Payloads for more information.
PAYLOAD_TIANOCORE	payloads/external/tianocore.name	bool	Tianocore payload	Select this option if you want to build a coreboot image with a Tianocore payload. If you don't know what this is about, just leave it enabled. See https://coreboot.org/Payloads for more information.
PAYLOAD_LINUX	payloads/external/linux.name	bool	A Linux payload	Select this option if you have a Linux bzImage which coreboot should run as soon as the basic hardware initialization is completed. You will be able to specify the location and file name of the payload image later.
PAYLOAD_YABITS	payloads/external/Yabits.name	bool	Yabits - Yet another UEFI Bootloader (Under Development)	Yabits - yabits.github.io yabits is a pure UEFI coreboot payload. Compared with TianoCore, it is fast and lightweight. yabits is based on the part of Minoca OS. It can run GRUB2, Linux, OpenBSD, and other UEFI applications. It is still under the development and not ready for production.
PAYLOAD_BOOTBOOT	payloads/external/BOOTBOOT.name	bool	BOOTBOOT	Select this option if you want to build a coreboot image with a BOOTBOOT Protocol payload. See https://gitlab.com/bztsrc/bootboot for more information.
PAYLOAD_LINUXBOOT	payloads/external/LinuxBoot.name	bool	LinuxBoot	Select this option if you want to build a coreboot image with a LinuxBoot payload. If you don't know what this is about, just leave it enabled. See https://coreboot.org/Payloads for more information.
PAYLOAD_UBOOT	payloads/external/U-Boot.name	bool	U-Boot (Experimental)	Select this option if you want to build a coreboot image with a U-Boot payload. See https://coreboot.org/Payloads and U-Boot's documentation at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86 for more information.
PAYLOAD_GRUB2	payloads/external/GRUB2.name	bool	GRUB2	Select this option if you want to build a coreboot image with a GRUB2 payload. If you don't know what this is about, just leave it enabled. See https://coreboot.org/Payloads for more information.
DEPTHCHARGE_STABLE	payloads/external/depthcharge	bool	stable	Latest stable version.
DEPTHCHARGE_MASTER	payloads/external/depthcharge	bool	master	Newest Depthcharge version.
DEPTHCHARGE_REVISION	payloads/external/depthcharge	bool	git revision	Select this option if you have a specific commit or branch that you want to use as the revision from which to build Depthcharge. You will be able to specify the name of a branch or a commit SHA later.
DEPTHCHARGE_REVISION_ID	payloads/external/depthcharge	string	Insert a commit's SHA-1 or a branch name	The commit's SHA-1 or branch name of the revision to use.
MAINBOARD_DEPTHCHARGE	payloads/external/depthcharge	string		Override BOARD setting for depthcharge
LP_DEFCONFIG_OVERRIDE	payloads/external/depthcharge	bool	Use default libpayload config	The Depthcharge makefile looks for a file config.<boardname> in the libpayload/configs directory. Say Y here to use the file defconfig instead. This is can be a convenience for development purposes, or if the defaults in defconfig are sufficient for your system.
FILO_STABLE	payloads/external/FILO	bool	tested	Tested FILO version
FILO_MASTER	payloads/external/FILO	bool	HEAD	Newest FILO version
SEABIOS_STABLE	payloads/external/SeaBIOS	bool	1.14.0	Stable SeaBIOS version
SEABIOS_MASTER	payloads/external/SeaBIOS	bool	master	Newest SeaBIOS version
SEABIOS_REVISION	payloads/external/SeaBIOS	bool	git revision	Select this option if you have a specific commit or branch that you want to use as the revision from which to build SeaBIOS. You will be able to specify the name of a branch or a commit id later.
SEABIOS_REVISION_ID	payloads/external/SeaBIOS	string	Insert a commit's SHA-1 or a branch name	The commit's SHA-1 or branch name of the revision to use.
SEABIOS_PS2_TIMEOUT	payloads/external/SeaBIOS	int	PS/2 keyboard controller initialization timeout (milliseconds)	Some PS/2 keyboard controllers don't respond to commands immediately after powering on. This specifies how long SeaBIOS will wait for the keyboard controller to become ready before giving up.
SEABIOS_THREAD_OPTIONROMS	payloads/external/SeaBIOS	bool	Hardware init during option ROM execution	Allow hardware init to run in parallel with optionrom execution. This can reduce boot time, but can cause some timing variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option.
SEABIOS_HARDWARE_IRQ	payloads/external/SeaBIOS	bool	Hardware Interrupts	Program and support hardware interrupts using the i8259 programmable interrupt controller (PIC). Deselected by boards which would otherwise hang at the boot menu (eg, google/rambi).
SEABIOS_VGA_COREBOOT	payloads/external/SeaBIOS	bool	Include generated option rom that implements legacy VGA BIOS compatibility	coreboot can initialize the GPU of some mainboards. After initializing the GPU, the information about it can be passed to the payload. Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
PAYLOAD_CONFIGFILE	payloads/external/SeaBIOS	string	SeaBIOS config file	This option allows a platform to set Kconfig options for a basic SeaBIOS payload. In general, if the option is used, the default would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
SEABIOS_BOOTORDER_FILE	payloads/external/SeaBIOS	string	SeaBIOS bootorder file	Add a SeaBIOS bootorder file. From the wiki: "The bootorder file may be used to configure the boot up order. The file should be ASCII text and contain one line per boot method. The description of each boot method follows an Open Firmware device path format. SeaBIOS will attempt to boot from each item in the file - first line of the file first." See: https://www.coreboot.org/SeaBIOS#Configuring_boot_order If used, a typical value would be: $(top)/src/mainboard/$(MAINBOARDDIR)/bootorder
SEABIOS_ADD_SERCON_PORT_FILE	payloads/external/SeaBIOS	bool	Add SeaBIOS sercon-port file to CBFS	Select this option to enable SeaBIOS' VGA adapter emulation on serial port.
SEABIOS_SERCON_PORT_ADDR	payloads/external/SeaBIOS	hex	SeaBIOS sercon-port base address	Set this field to the IO address of a serial port for SeaBIOS' VGA adapter emulation. By default primary console UART defined by TTYS0_BASE is used.
SEABIOS_DEBUG_LEVEL	payloads/external/SeaBIOS	int	SeaBIOS debug level (verbosity)	The higher the number, the more verbose SeaBIOS will be. See the table below for the current values corresponding to various items as of SeaBIOS version 1.10.1. Set this value to -1 to use SeaBIOS' default. Output at various SeaBIOS log levels: level 0 - Logging disabled level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts level 4 - BIOS tables, more optionrom level 5 - Extra bootsplash, more XHCI level 6 - ATA commands, extra optionrom level 7 - extra ps2 commands, more OHCI & EHCI level 8 - extra malloc info, more AHCI level 9 - interrupts 15h, 16h, 1ah, APM, PCI, SMIs, PCIBIOS, USB-HID commands, SDcard commands, Floppy commands level 10 - interrupt 13h (Drives other than floppy) level 20 - interrupt 10h (Display)
	payloads/external/SeaBIOS	(comment)		Using default SeaBIOS log level
	payloads/external/SeaBIOS	(comment)		SeaBIOS logging disabled
PAYLOAD_FILE	payloads/external/tianocore	string	Tianocore binary	The result of a corebootPkg build
PAYLOAD_FILE	payloads/external/tianocore	string	Tianocore payload	Select which type of payload Tianocore will build (default is CorebootPayload) CorebootPayload: MrChromebox's customized version of Tianocore which works on most (all?) x86_64 devices UEFIPayload: Use upstream Tianocore payload from https://github.com/tianocore/edk2
TIANOCORE_COREBOOTPAYLOAD	payloads/external/tianocore	bool	CorebootPayload	Select this option to build using MrChromebox's custom Tianocore tree i.e. a version of Tianocore that builds without any errors and just works.
TIANOCORE_UEFIPAYLOAD	payloads/external/tianocore	bool	UEFIPayload	Select this option if you want to use upstream EDK2 to build Tianocore.
TIANOCORE_REVISION_ID	payloads/external/tianocore	string	Insert a commit's SHA-1 or a branch name	The commit's SHA-1 or branch name of the revision to use. Choose "upstream/master" for master branch of Tianocore release on github.
TIANOCORE_REVISION_ID	payloads/external/tianocore	string	Target architecture	The Tianocore coreboot Payload Package binary can be built for either only IA32 or both X64 and IA32 architectures. Select which architecture(s) to build for; default is to build for both X64 and IA32.
TIANOCORE_TARGET_IA32	payloads/external/tianocore	bool	IA32	By selecting this option, the target architecture will be built for only IA32.
TIANOCORE_TARGET_X64	payloads/external/tianocore	bool	X64	By selecting this option, the target architecture will be built for X64 and IA32.
TIANOCORE_TARGET_X64	payloads/external/tianocore	bool	Tianocore build	Select whether to generate a debug or release build for Tianocore; default is to generate a release build.
TIANOCORE_DEBUG	payloads/external/tianocore	bool	Generate Tianocore debug build	Generate a debug build.
TIANOCORE_RELEASE	payloads/external/tianocore	bool	Generate Tianocore release build	Generate a release build.
TIANOCORE_USE_8254_TIMER	payloads/external/tianocore	bool	TianoCore 8254 Timer	Use 8254 Timer for legacy support.
TIANOCORE_BOOTSPLASH_IMAGE	payloads/external/tianocore	bool	Use a custom bootsplash image	Select this option if you have a bootsplash image that you would like to be used. If this option is not selected, the default coreboot logo (European Brown Hare) will used.
TIANOCORE_BOOTSPLASH_FILE	payloads/external/tianocore	string	Tianocore Bootsplash path and filename	The path and filename of the file to use as graphical bootsplash screen. The file format must be uncompressed BMP, and the file's resolution must be less than the native resolution of the display. If an absolute path is not given, the path will assumed to be relative to the coreboot root directory.
TIANOCORE_BOOT_TIMEOUT	payloads/external/tianocore	int		The length of time in seconds for which the boot splash/menu prompt will be displayed. For boards with an internal display, the default value of 2s is generally sufficient. For boards without an internal display, a value of 5s is generally sufficient.
PAYLOAD_FILE	payloads/external/linux	string	Linux path and filename	The path and filename of the bzImage kernel to use as payload.
LINUX_COMMAND_LINE	payloads/external/linux	string	Linux command line	A command line to add to the Linux kernel.
LINUX_INITRD	payloads/external/linux	string	Linux initrd	An initrd image to add to the Linux kernel.
YABITS_STABLE	payloads/external/Yabits	bool	Stable	Stable Yabits version. For reproducible builds, this option must be selected.
YABITS_MASTER	payloads/external/Yabits	bool	Master	Newest version. This option will fetch the newest version of the Yabits code, updating as new changes are committed. This makes the build non-reproducible, as it can fetch different code each time.
YABITS_REVISION	payloads/external/Yabits	bool	git revision	Select this option if you have a specific commit or branch that you want to use as the revision from which to build Yabits. Using a branch name makes the build non-reproducible, as it can fetch different code as the branch changes. You will be able to specify the name of a branch or a commit id later.
YABITS_REVISION_ID	payloads/external/Yabits	string	Insert a commit's SHA-1 or a branch name	The commit's SHA-1 or branch name of the revision to use.
LINUXBOOT_X86_64	payloads/external/LinuxBoot	bool	x86_64	AMD64 kernel and initramfs
LINUXBOOT_X86	payloads/external/LinuxBoot	bool	x86	X86 kernel and initramfs
LINUXBOOT_ARM64	payloads/external/LinuxBoot	bool	arm64	AARCH64 kernel and initramfs
LINUXBOOT_RISCV	payloads/external/LinuxBoot	bool	RISC-V	RISC-V kernel and initramfs
	payloads/external/LinuxBoot	(comment)		Linux kernel
	payloads/external/LinuxBoot	(comment)		parse linux crosscompiler with: LINUXBOOT_CROSS_COMPILE
LINUXBOOT_KERNEL_PATH	payloads/external/LinuxBoot	string	Kernel release	Choose the kernel release. Select 'custom' if your want to define the kernel version. For more information about the current 'mainline', 'stable' or 'longterm' version, visit: https://www.kernel.org/
LINUXBOOT_KERNEL_MAINLINE	payloads/external/LinuxBoot	bool	mainline	Mainline kernel version
LINUXBOOT_KERNEL_STABLE	payloads/external/LinuxBoot	bool	stable	Stable kernel version
LINUXBOOT_KERNEL_LONGTERM	payloads/external/LinuxBoot	bool	longterm	Longterm (LTS) kernel version
LINUXBOOT_KERNEL_CUSTOM	payloads/external/LinuxBoot	bool	custom	Custom kernel version
LINUXBOOT_KERNEL_CUSTOM_VERSION	payloads/external/LinuxBoot	string	kernel version	Choose the Linux kernel version number. (x.x.x) Release candidate kernels (rc) are currently are not supported.
LINUXBOOT_KERNEL_ARCH_DEFAULT_CONFIG	payloads/external/LinuxBoot	bool	Default architecture configuration	This option will use the default configuration for the selected architecture.
LINUXBOOT_KERNEL_CONFIGFILE	payloads/external/LinuxBoot	string	Config file path	Path to the kernel configuration file. Note: this can be a defconfig file or a complete .config file.
LINUX_COMMAND_LINE	payloads/external/LinuxBoot	string	Kernel command-line	Add your own kernel command-line arguments.
	payloads/external/LinuxBoot	(comment)		Linux initramfs
LINUXBOOT_UROOT	payloads/external/LinuxBoot	bool	u-root	Enable u-root linuxboot mode. See http://u-root.tk/ for more information.
LINUXBOOT_UROOT_CUSTOM	payloads/external/LinuxBoot	bool	custom	choose a custom u-root branch
LINUXBOOT_UROOT_MASTER	payloads/external/LinuxBoot	bool	master	Latest u-root version
LINUXBOOT_UROOT_VERSION	payloads/external/LinuxBoot	string	Build format	u-root build format (e.g. bb or source). (default "bb")
LINUXBOOT_UROOT_FILES	payloads/external/LinuxBoot	string	Add files to u-root base	Additional files, directories, and binaries (with their ldd dependencies) to add to archive. Can be speficified multiple times.
LINUXBOOT_UROOT_INITCMD	payloads/external/LinuxBoot	string	Init target	Symlink target for /init. Can be an absolute path or a u-root command name. (default "init")
LINUXBOOT_UROOT_SHELL	payloads/external/LinuxBoot	string	default shell	Default shell. Can be an absolute path or a u-root command name. (default "elvish")
LINUXBOOT_UROOT_COMMANDS	payloads/external/LinuxBoot	string	U-root commands	List of additional modules to include, separated by space. (default "coreboot-app")
UBOOT_STABLE	payloads/external/U-Boot	bool	v2019.4	Stable U-Boot version
UBOOT_MASTER	payloads/external/U-Boot	bool	master	Newest U-Boot version
PAYLOAD_CONFIGFILE	payloads/external/U-Boot	string	U-Boot config file	This option allows a platform to set Kconfig options for a basic U-Boot payload. In general, if the option is used, the default would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_uboot" for a config stored in the coreboot mainboard directory, or "$(project_dir)/configs/coreboot-x86_defconfig" to use a config from the U-Boot config directory
GRUB2_STABLE	payloads/external/GRUB2	bool	2.04	Stable GRUB2 version
GRUB2_MASTER	payloads/external/GRUB2	bool	HEAD	Newest GRUB2 version
GRUB2_REVISION	payloads/external/GRUB2	bool	git revision	Select this option if you have a specific commit or branch that you want to use as the revision from which to build GRUB2. You will be able to specify the name of a branch or a commit id later.
GRUB2_REVISION_ID	payloads/external/GRUB2	string	Insert a commit's SHA-1 or a branch name	The commit's SHA-1 or branch name of the revision to use.
GRUB2_EXTRA_MODULES	payloads/external/GRUB2	string	Extra modules to include in GRUB image	Space-separated list of additional modules to include. Few common ones: * bsd for BSD png/jpg for PNG/JPG images * gfxmenu for graphical menus (you'll need a theme as well) * gfxterm_background for setting background
GRUB2_INCLUDE_RUNTIME_CONFIG_FILE	payloads/external/GRUB2	bool	Include GRUB2 runtime config file into ROM image	The GRUB2 payload reads its runtime configuration file from etc/grub.cfg stored in the CBFS on the flash ROM chip. Without that, it’ll just drop into a rescue shell. This configuration may need to be coreboot specific. Select this option, if you want to include the GRUB2 runtime configuration file into CBFS as `etc/grub.cfg` automatically. You will be able to specify the path of the configuration file later. Without this option you would need to add this file manually with build/cbfstool build/coreboot.rom add -f grub.cfg -n etc/grub.cfg -t raw
GRUB2_RUNTIME_CONFIG_FILE	payloads/external/GRUB2	string	Path of grub.cfg	The path of the GRUB2 runtime configuration file to be added to CBFS.
Menu: PXE Options
PXE_ROM	payloads/external/iPXE	bool	Add an existing PXE ROM image	Select this option if you have a PXE ROM image that you would like to add to your ROM.
BUILD_IPXE	payloads/external/iPXE	bool	Build and add an iPXE ROM	Select this option to fetch and build a ROM from the iPXE project.
IPXE_STABLE	payloads/external/iPXE	bool	2019.3	iPXE uses a rolling release with no stable version, for reproducibility, use the last commit of a given month as the 'stable' version. This is iPXE from the end of March, 2019.
IPXE_MASTER	payloads/external/iPXE	bool	master	Newest iPXE version.
PXE_ROM_FILE	payloads/external/iPXE	string	PXE ROM filename	The path and filename of the file to use as PXE ROM.
PXE_ROM_ID	payloads/external/iPXE	string	network card PCI IDs	The comma-separated PCI vendor and device ID that would associate your PXE ROM to your network card. Example: 10ec,8168 In the above example 10ec is the PCI vendor ID (in hex, but without the "0x" prefix) and 8168 specifies the PCI device ID of the network card (also in hex, without "0x" prefix). Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
PXE_SERIAL_CONSOLE	payloads/external/iPXE	bool	Enable iPXE serial console	Enable/disable iPXE serial console. Since SeaBIOS supports serial console this option might be helpful to avoid duplicated output. Unselect to let only SeaBIOS handle printing output.
PXE_NO_PROMPT	payloads/external/iPXE	bool	Do not show prompt to boot from PXE	Don't wait for the user to press Ctrl-B. The PXE still can be run as it shows up in SeaBIOS's payload list.
PXE_ADD_SCRIPT	payloads/external/iPXE	bool	Embed an iPXE script for automated provisioning	Enable to embed a script that is run instead of an iPXE shell.
PXE_SCRIPT	payloads/external/iPXE	string	Embedded iPXE script path and filename	Path to a script that is embedded into the iPXE binary. Example: startup.ipxe Uses the ipxe script instead showing the prompt: "Press Ctrl-B to start iPXE..."
PXE_HAS_HTTPS	payloads/external/iPXE	bool	Enable HTTPS protocol	Enable HTTPS protocol, which allows you to encrypt all communication with a web server and to verify the server's identity
PAYLOAD_FILE	payloads	string	Payload path and filename	The path and filename of the ELF executable file to use as payload.
PAYLOAD_FILE	payloads	string	Payload compression algorithm	Choose the compression algorithm for the chosen payloads. You can choose between None, LZMA, or LZ4.
COMPRESSED_PAYLOAD_NONE	payloads	bool	Use no compression for payloads	Do not compress the payload.
COMPRESSED_PAYLOAD_LZMA	payloads	bool	Use LZMA compression for payloads	In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm.
COMPRESSED_PAYLOAD_LZ4	payloads	bool	Use LZ4 compression for payloads	In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZ4 algorithm.
PAYLOAD_OPTIONS	payloads	string		Additional cbfstool options for the payload
PAYLOAD_IS_FLAT_BINARY	payloads	string		Add the payload to cbfs as a flat binary type instead of as an elf payload
PAYLOAD_FIT_SUPPORT	payloads	bool	FIT support	Select this option if your payload is of type FIT. Enables FIT parser and devicetree patching. The FIT is non self-extracting and needs to have a compatible compression format.
COMPRESS_SECONDARY_PAYLOAD	payloads	bool	Use LZMA compression for secondary payloads	In order to reduce the size secondary payloads take up in the ROM chip they can be compressed using the LZMA algorithm.
Menu: Secondary Payloads
COREINFO_SECONDARY_PAYLOAD	payloads	bool	Load coreinfo as a secondary payload	coreinfo can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads.
MEMTEST_SECONDARY_PAYLOAD	payloads	bool	Load Memtest86+ as a secondary payload	Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads.
NVRAMCUI_SECONDARY_PAYLOAD	payloads	bool	Load nvramcui as a secondary payload	nvramcui can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads.
TINT_SECONDARY_PAYLOAD	payloads	bool	Load tint as a secondary payload	tint can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads.
MEMTEST_STABLE	payloads/external/Memtest86Plus.secondary	bool	Stable	Stable Memtest86+ version. For reproducible builds, this option must be selected.
MEMTEST_MASTER	payloads/external/Memtest86Plus.secondary	bool	Master	Newest Memtest86+ version. This option will fetch the newest version of the Memtest86+ code, updating as new changes are committed. This makes the build non-reproducible, as it can fetch different code each time.
MEMTEST_REVISION	payloads/external/Memtest86Plus.secondary	bool	git revision	Select this option if you have a specific commit or branch that you want to use as the revision from which to build Memtest86+. This makes the build non-reproducible, as it can fetch different code each time. You will be able to specify the name of a branch or a commit id later.
MEMTEST_REVISION_ID	payloads/external/Memtest86Plus.secondary	string	Insert a commit's SHA-1 or a branch name	The commit's SHA-1 or branch name of the revision to use.
Menu: Debugging
	toplevel	(comment)		CPU Debug Settings
	toplevel	(comment)		BLOB Debug Settings
DISPLAY_FSP_CALLS_AND_STATUS	drivers/intel/fsp2_0.debug_blob	bool	Display the FSP calls and status	Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP.
DISPLAY_FSP_HEADER	drivers/intel/fsp2_0.debug_blob	bool	Display the FSP header	Display the FSP header information when the FSP file is found.
DISPLAY_HOBS	drivers/intel/fsp2_0.debug_blob	bool	Display the hand-off-blocks	Display the FSP HOBs which are provided for coreboot.
DISPLAY_UPD_DATA	drivers/intel/fsp2_0.debug_blob	bool	Display UPD data	Display the user specified product data prior to memory initialization.
VERIFY_HOBS	drivers/intel/fsp2_0.debug_blob	bool	Verify the FSP hand-off-blocks	Verify that the HOBs required by coreboot are returned by FSP and that the resource HOBs are in the correct order and position.
DISPLAY_FSP_VERSION_INFO	drivers/intel/fsp2_0.debug_blob	bool	Display Firmware Ingredient Version Information	Select this option to display Firmware version information.
	toplevel	(comment)		General Debug Settings
GDB_STUB	toplevel	bool	GDB debugging support	If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/lib/c_start.S for details.
GDB_WAIT	toplevel	bool	Wait for a GDB connection in the ramstage	If enabled, coreboot will wait for a GDB connection in the ramstage.
FATAL_ASSERTS	toplevel	bool	Halt when hitting a BUG() or assertion error	If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
DEBUG_CBFS	toplevel	bool	Output verbose CBFS debug messages	This option enables additional CBFS related debug messages.
DEBUG_RAM_SETUP	toplevel	bool	Output verbose RAM init debug messages	This option enables additional RAM init related debug messages. It is recommended to enable this when debugging issues on your board which might be RAM init related. Note: This option will increase the size of the coreboot image. If unsure, say N.
DEBUG_PIRQ	toplevel	bool	Check PIRQ table consistency	If unsure, say N.
DEBUG_SMBUS	toplevel	bool	Output verbose SMBus debug messages	This option enables additional SMBus (and SPD) debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
DEBUG_SMI	toplevel	bool	Output verbose SMI debug messages	This option enables additional SMI related debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
DEBUG_MALLOC	toplevel	bool	Output verbose malloc debug messages	This option enables additional malloc related debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
DEBUG_RESOURCES	toplevel	bool	Output verbose PCI MEM and IO resource debug messages	This option enables additional PCI memory and IO debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
DEBUG_CONSOLE_INIT	toplevel	bool	Debug console initialisation code	With this option printk()'s are attempted before console hardware initialisation has been completed. Your mileage may vary. Typically you will need to modify source in console_hw_init() such that a working console appears before the one you want to debug. If unsure, say N.
REALMODE_DEBUG	toplevel	bool	Enable debug messages for option ROM execution	This option enables additional x86emu related debug messages. Note: This option will increase the time to emulate a ROM. If unsure, say N.
X86EMU_DEBUG	toplevel	bool	Output verbose x86emu debug messages	This option enables additional x86emu related debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_JMP	toplevel	bool	Trace JMP/RETF	Print information about JMP and RETF opcodes from x86emu. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_TRACE	toplevel	bool	Trace all opcodes	Print _all_ opcodes that are executed by x86emu. WARNING: This will produce a LOT of output and take a long time. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_PNP	toplevel	bool	Log Plug&Play accesses	Print Plug And Play accesses made by option ROMs. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_DISK	toplevel	bool	Log Disk I/O	Print Disk I/O related messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_PMM	toplevel	bool	Log PMM	Print messages related to POST Memory Manager (PMM). Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_VBE	toplevel	bool	Debug VESA BIOS Extensions	Print messages related to VESA BIOS Extension (VBE) functions. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_INT10	toplevel	bool	Redirect INT10 output to console	Let INT10 (i.e. character output) calls print messages to debug output. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_INTERRUPTS	toplevel	bool	Log intXX calls	Print messages related to interrupt handling. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_CHECK_VMEM_ACCESS	toplevel	bool	Log special memory accesses	Print messages related to accesses to certain areas of the virtual memory (e.g. BDA (BIOS Data Area) or interrupt vectors) Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_MEM	toplevel	bool	Log all memory accesses	Print memory accesses made by option ROM. Note: This also includes accesses to fetch instructions. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_IO	toplevel	bool	Log IO accesses	Print I/O accesses made by option ROM. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_TIMINGS	toplevel	bool	Output timing information	Print timing information needed by i915tool. If unsure, say N.
DEBUG_SPI_FLASH	toplevel	bool	Output verbose SPI flash debug messages	This option enables additional SPI flash related debug messages.
DEBUG_INTEL_ME	toplevel	bool	Verbose logging for Intel Management Engine	Enable verbose logging for Intel Management Engine driver that is present on Intel 6-series chipsets.
DEBUG_FUNC	toplevel	bool	Enable function entry and exit reporting macros	This option enables additional function entry and exit debug messages for select functions. Note: This option will increase the size of the coreboot image. If unsure, say N.
DEBUG_COVERAGE	toplevel	bool	Debug code coverage	If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped.
DEBUG_BOOT_STATE	toplevel	bool	Debug boot state machine	Control debugging of the boot state machine. When selected displays the state boundaries in ramstage.
DEBUG_ADA_CODE	toplevel	bool	Compile debug code in Ada sources	Add the compiler switch `-gnata` to compile code guarded by `pragma Debug`.
HAVE_EM100_SUPPORT	toplevel	bool	Platform can support the Dediprog EM100 SPI emulator	This is enabled by platforms which can support using the EM100.
EM100	toplevel	bool	Configure image for EM100 usage	The Dediprog EM100 SPI emulator allows fast loading of new SPI images over USB. However it only supports a maximum SPI clock of 20MHz and single data output. Enable this option to use a 20MHz SPI clock and disable "Dual Output Fast Read" Support. On AMD platforms this changes the SPI speed at run-time if the mainboard code supports this. On supported Intel platforms this works by changing the settings in the descriptor.bin file.
MISSING_BOARD_RESET	lib	bool		Selected by boards that don't provide a do_board_reset() implementation. This activates a stub that logs the missing board reset and halts execution.
RAMSTAGE_ADA	lib	bool		Selected by features that use Ada code in ramstage.
RAMSTAGE_LIBHWBASE	lib	bool		Selected by features that require `libhwbase` in ramstage.
FLATTENED_DEVICE_TREE	lib	bool		Selected by features that require to parse and manipulate a flattened devicetree in ramstage.
HAVE_SPD_IN_CBFS	lib	bool		If enabled, add support for adding spd.hex files in cbfs as spd.bin and locating it runtime to load SPD.
DIMM_MAX	lib	int		Total number of memory DIMM slots available on motherboard. It is multiplication of number of channel to number of DIMMs per channel
DIMM_SPD_SIZE	lib	int		Total SPD size that will be used for DIMM. Ex: DDR3 256, DDR4 512.
SPD_CACHE_IN_FMAP	lib	bool		Enables capability to cache DIMM SPDs in a dedicated FMAP region to speed loading of SPD data. Currently requires board-level romstage implementation to read/write/utilize cached SPD data. When the default FMAP is used, will create a region named RW_SPD_CACHE to store the cached SPD data.
SPD_CACHE_FMAP_NAME	lib	string		Name of the FMAP region created in the default FMAP to cache SPD data.
NO_FMAP_CACHE	lib	bool		If your platform really doesn't want to use an FMAP cache (e.g. due to space constraints), you can select this to disable warnings and save a bit more code.
ESPI_DEBUG	lib	bool		This option enables eSPI library helper functions for displaying debug information.
NO_CBFS_MCACHE	lib	bool		Disables the CBFS metadata cache. This means that your platform does not need to provide a CBFS_MCACHE section in memlayout and can save the associated CAR/SRAM size. In that case every single CBFS file lookup must re-read the same CBFS directory entries from flash to find the respective file.
CBFS_MCACHE_RW_PERCENTAGE	lib	int		The amount of the CBFS_MCACHE area that's used for the RW CBFS, in percent from 0 to 100. The remaining area will be used for the RO CBFS. Default is an even 50/50 split. When VBOOT is disabled, this will automatically be 0 (meaning the whole MCACHE is used for RO).
POWER_BUTTON_DEFAULT_ENABLE	toplevel	bool		Select when the board has a power button which can optionally be disabled by the user.
POWER_BUTTON_DEFAULT_DISABLE	toplevel	bool		Select when the board has a power button which can optionally be enabled by the user, e.g. when the board ships with a jumper over the power switch contacts.
POWER_BUTTON_FORCE_ENABLE	toplevel	bool		Select when the board requires that the power button is always enabled.
POWER_BUTTON_FORCE_DISABLE	toplevel	bool		Select when the board requires that the power button is always disabled, e.g. when it has been hardwired to ground.
POWER_BUTTON_IS_OPTIONAL	toplevel	bool		Internal option that controls ENABLE_POWER_BUTTON visibility.
REG_SCRIPT	toplevel	bool		Internal option that controls whether we compile in register scripts.
MAX_REBOOT_CNT	toplevel	int		Internal option that sets the maximum number of bootblock executions allowed with the normal image enabled before assuming the normal image is defective and switching to the fallback image.
NO_XIP_EARLY_STAGES	toplevel	bool		Identify if early stages are eXecute-In-Place(XIP).
EARLY_CBMEM_LIST	toplevel	bool		Enable display of CBMEM during romstage and postcar.
RELOCATABLE_MODULES	toplevel	bool		If RELOCATABLE_MODULES is selected then support is enabled for building relocatable modules in the RAM stage. Those modules can be loaded anywhere and all the relocations are handled automatically.
GENERIC_GPIO_LIB	toplevel	bool		If enabled, compile the generic GPIO library. A "generic" GPIO implies configurability usually found on SoCs, particularly the ability to control internal pull resistors.
MEMLAYOUT_LD_FILE	toplevel	string		This variable allows SoC/mainboard to supply in a custom linker file if required. This determines the linker file used for all the stages (bootblock, romstage, verstage, ramstage, postcar) in src/arch/${ARCH}/Makefile.inc.