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| This is an automatically generated list of '''coreboot compile-time options'''.
| | {{#externalredirect: https://coreboot.org/status/kconfig-options.html }} |
| | |
| Last update: 2011/06/23 18:44:41.
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| {| border="0" style="font-size: smaller" | |
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| ! align="left" | Option
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| ! align="left" | Source
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| ! align="left" | Format
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| ! align="left" | Short Description
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| ! align="left" | Description
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: General setup || || || ||
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| |- bgcolor="#eeeeee"
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| | EXPERT || toplevel || bool || Expert mode ||
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| This allows you to select certain advanced configuration options.
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| Warning: Only enable this option if you really know what you are
| |
| doing! You have been warned!
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| |- bgcolor="#eeeeee"
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| | LOCALVERSION || toplevel || string || Local version string ||
| |
| Append an extra string to the end of the coreboot version.
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| | |
| This can be useful if, for instance, you want to append the
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| respective board's hostname or some other identifying string to
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| the coreboot version number, so that you can easily distinguish
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| boot logs of different boards from each other.
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| |- bgcolor="#eeeeee"
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| | CBFS_PREFIX || toplevel || string || CBFS prefix to use ||
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| Select the prefix to all files put into the image. It's "fallback"
| |
| by default, "normal" is a common alternative.
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| |- bgcolor="#eeeeee"
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| | CBFS_PREFIX || toplevel || string || Compiler ||
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| This option allows you to select the compiler used for building
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| coreboot.
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| ||
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| |- bgcolor="#eeeeee"
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| | SCANBUILD_ENABLE || toplevel || bool || Build with scan-build for static analysis ||
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| Changes the build process to scan-build is used.
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| Requires scan-build in path.
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| | SCANBUILD_REPORT_LOCATION || toplevel || string || Directory to put scan-build report in ||
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| Where the scan-build report should be stored
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| ||
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| |- bgcolor="#eeeeee"
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| | CCACHE || toplevel || bool || ccache ||
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| Enables the use of ccache for faster builds.
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| Requires ccache in path.
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| ||
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| |- bgcolor="#eeeeee"
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| | SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison ||
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| Enable this option if you are working on the sconfig
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| device tree parser and made changes to sconfig.l and
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| sconfig.y.
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| Otherwise, say N.
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| |- bgcolor="#eeeeee"
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| | USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||
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| Enable this option if coreboot shall read options from the "CMOS"
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| NVRAM instead of using hard coded values.
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| |- bgcolor="#eeeeee"
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| | COMPRESS_RAMSTAGE || toplevel || bool || Compress ramstage with LZMA ||
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| Compress ramstage to save memory in the flash image. Note
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| that decompression might slow down booting if the boot flash
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| is connected through a slow Link (i.e. SPI)
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| |- bgcolor="#eeeeee"
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| | INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot config file into the ROM image ||
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| Include in CBFS the coreboot config file that was used to compile the ROM image
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: Mainboard || || || ||
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| |- bgcolor="#eeeeee"
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| | BOARD_LENOVO_X60 || mainboard/lenovo || bool || ThinkPad X60 / X60s ||
| |
| The following X60 series ThinkPad machines have been verified to
| |
| work correctly:
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| ThinkPad X60s (Model 1702, 1703)
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| ThinkPad X60 (Model 1709)
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| ||
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| |- bgcolor="#eeeeee"
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| | BOARD_LENOVO_T60 || mainboard/lenovo || bool || ThinkPad T60 / T60p ||
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| The following T60 series ThinkPad machines have been verified to
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| work correctly:
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| Thinkpad T60p (Model 2007)
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| ||
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| |- bgcolor="#eeeeee"
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| | BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||
| |
| Look on the bottom side for a number like 406-0001-30. The last 2
| |
| digits state the PCB revision (3.0 in this example). For 2.0 or older
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| boards choose Y, for 3.0 and newer say N.
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| | |
| Old revision boards need a jumper shorting the power button to
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| power on automatically. You may enable the button only after this
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| jumper has been removed. New revision boards are not restricted
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| in this way, and always have the power button enabled.
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| ||
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| |- bgcolor="#eeeeee"
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| | ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||
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| If selected, both on-board serial ports will operate in RS485 mode
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| instead of RS232.
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| ||
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| |- bgcolor="#eeeeee"
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| | ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||
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| If selected, the first two on-board serial ports will operate in RS485
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| mode instead of RS232.
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| ||
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| |- bgcolor="#eeeeee"
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| | ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave ||
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| If selected, the on-board Compact Flash card socket will act as IDE
| |
| Slave instead of Master.
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| ||
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| |- bgcolor="#eeeeee"
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| | ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||
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| If selected, both on-board serial ports will operate in RS485 mode
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| instead of RS232.
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| ||
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| |- bgcolor="#eeeeee"
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| | ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||
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| If selected, both on-board serial ports will operate in RS485 mode
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| instead of RS232.
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| ||
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| |- bgcolor="#eeeeee"
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| | ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||
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| If selected, the on-board SSD will act as IDE Slave instead of Master.
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| |- bgcolor="#eeeeee"
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| | BOARD_ROMSIZE_KB_16384 || mainboard || bool || ROM chip size ||
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| Select the size of the ROM chip you intend to flash coreboot on.
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| The build system will take care of creating a coreboot.rom file
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| of the matching size.
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| ||
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||
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| Choose this option if you have a 128 KB ROM chip.
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||
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| Choose this option if you have a 256 KB ROM chip.
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||
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| Choose this option if you have a 512 KB ROM chip.
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||
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| Choose this option if you have a 1024 KB (1 MB) ROM chip.
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||
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| Choose this option if you have a 2048 KB (2 MB) ROM chip.
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||
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| Choose this option if you have a 4096 KB (4 MB) ROM chip.
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||
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| Choose this option if you have a 8192 KB (8 MB) ROM chip.
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| ||
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||
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| Choose this option if you have a 16384 KB (16 MB) ROM chip.
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| |- bgcolor="#eeeeee"
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| | ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button ||
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| The selected mainboard can optionally have the power button tied
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| to ground with a jumper so that the button appears to be
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| constantly depressed. If this option is enabled and the jumper is
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| installed then the board will turn on, but turn off again after a
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| short timeout, usually 4 seconds.
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| | |
| Select Y here if you have removed the jumper and want to use an
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| actual power button. Select N if you have the jumper installed.
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: Architecture (x86) || || || ||
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| |- bgcolor="#eeeeee"
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| | UPDATE_IMAGE || arch/x86 || bool || Update existing coreboot.rom image ||
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| If this option is enabled, no new coreboot.rom file
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| is created. Instead it is expected that there already
| |
| is a suitable file for further processing.
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| The bootblock will not be modified.
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: Chipset || || || ||
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| |- bgcolor="#eeeeee"
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| | || || (comment) || || CPU ||
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| |- bgcolor="#eeeeee"
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| | UPDATE_CPU_MICROCODE || cpu/amd/model_10xxx || bool || Update CPU microcode ||
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| Select this to apply patches to the CPU microcode provided by
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| AMD without source, and distributed with coreboot, to address
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| issues in the CPU post production.
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| Microcode updates distributed with coreboot are not necessarily
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| the latest version available from AMD. Updates are only applied
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| if they are newer than the microcode already in your CPU.
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| Unselect this to let Fam10h CPUs run with microcode as shipped
| |
| from factory. No binary microcode patches will be included in the
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| coreboot image in that case, which can help with creating an image
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| for which complete source code is available, which in turn might
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| simplify license compliance.
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| Microcode updates intend to solve issues that have been discovered
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| after CPU production. The common case is that systems work as
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| intended with updated microcode, but we have also seen cases where
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| issues were solved by not applying the microcode updates.
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| Note that some operating system include these same microcode
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| patches, so you may need to also disable microcode updates in
| |
| your operating system in order for this option to matter.
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| ||
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| |- bgcolor="#eeeeee"
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| | GEODE_VSA_FILE || cpu/amd/model_gx2 || bool || Add a VSA image ||
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| Select this option if you have an AMD Geode GX2 vsa that you would
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| like to add to your ROM.
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| You will be able to specify the location and file name of the
| |
| image later.
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| ||
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| |- bgcolor="#eeeeee"
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| | VSA_FILENAME || cpu/amd/model_gx2 || string || AMD Geode GX2 VSA path and filename ||
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| The path and filename of the file to use as VSA.
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| ||
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| |- bgcolor="#eeeeee"
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| | GEODE_VSA_FILE || cpu/amd/model_lx || bool || Add a VSA image ||
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| Select this option if you have an AMD Geode LX vsa that you would
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| like to add to your ROM.
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| | |
| You will be able to specify the location and file name of the
| |
| image later.
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| ||
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| |- bgcolor="#eeeeee"
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| | VSA_FILENAME || cpu/amd/model_lx || string || AMD Geode LX VSA path and filename ||
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| The path and filename of the file to use as VSA.
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| |- bgcolor="#eeeeee"
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| | SMP || cpu || bool || ||
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| This option is used to enable certain functions to make coreboot
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| work correctly on symmetric multi processor (SMP) systems.
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| |- bgcolor="#eeeeee"
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| | MMX || cpu || bool || ||
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| Select MMX in your socket or model Kconfig if your CPU has MMX
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| streaming SIMD instructions. ROMCC can build more efficient
| |
| code if it can spill to MMX registers.
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| |- bgcolor="#eeeeee"
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| | SSE || cpu || bool || ||
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| Select SSE in your socket or model Kconfig if your CPU has SSE
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| streaming SIMD instructions. ROMCC can build more efficient
| |
| code if it can spill to SSE (aka XMM) registers.
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| |- bgcolor="#eeeeee"
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| | SSE2 || cpu || bool || ||
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| Select SSE2 in your socket or model Kconfig if your CPU has SSE2
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| streaming SIMD instructions. Some parts of coreboot can be built
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| with more efficient code if SSE2 instructions are available.
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| |- bgcolor="#eeeeee"
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| | VAR_MTRR_HOLE || cpu || bool || ||
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| Unset this if you don't want the MTRR code to use
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| subtractive MTRRs
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| |- bgcolor="#eeeeee"
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| | || || (comment) || || Northbridge ||
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| |- bgcolor="#eeeeee"
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| | SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || ||
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| Select this for boards with a Voltage Regulator able to operate
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| at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
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| ||
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: HyperTransport setup || || || ||
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| |- bgcolor="#eeeeee"
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| | None || northbridge/amd || None || HyperTransport frequency ||
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| This option sets the maximum permissible HyperTransport link
| |
| frequency.
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| Use of this option will only limit the autodetected HT frequency.
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| It will not (and cannot) increase the frequency beyond the
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| autodetected limits.
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| This is primarily used to work around poorly designed or laid out
| |
| HT traces on certain motherboards.
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| ||
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| |- bgcolor="#eeeeee"
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| | LIMIT_HT_SPEED_AUTO || northbridge/amd || bool || HyperTransport downlink width ||
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| This option sets the maximum permissible HyperTransport
| |
| downlink width.
| |
| | |
| Use of this option will only limit the autodetected HT width.
| |
| It will not (and cannot) increase the width beyond the autodetected
| |
| limits.
| |
| | |
| This is primarily used to work around poorly designed or laid out HT
| |
| traces on certain motherboards.
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| ||
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| |- bgcolor="#eeeeee"
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| | LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd || bool || HyperTransport uplink width ||
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| This option sets the maximum permissible HyperTransport
| |
| uplink width.
| |
| | |
| Use of this option will only limit the autodetected HT width.
| |
| It will not (and cannot) increase the width beyond the autodetected
| |
| limits.
| |
| | |
| This is primarily used to work around poorly designed or laid out HT
| |
| traces on certain motherboards.
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| ||
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| |- bgcolor="#eeeeee"
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| | SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool || ||
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| This option affects how the SDRAMC register is programmed.
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| Memory clock signals will not be routed properly if this option
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| is set wrong.
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| If your board has 4 DIMM slots, you must use select this option, in
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| your Kconfig file of the board. On boards with 3 DIMM slots,
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| do _not_ select this option.
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| ||
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| |- bgcolor="#eeeeee"
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| | OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || ||
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| Usually system firmware turns off system memory clock
| |
| signals to unused SO-DIMM slots to reduce EMI and power
| |
| consumption.
| |
| However, some boards do not like unused clock signals to
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| be disabled.
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| ||
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| |- bgcolor="#eeeeee"
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| | MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || ||
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| If non-zero, this designates the maximum DDR frequency
| |
| the board supports, despite what the chipset should be
| |
| capable of.
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| ||
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| |- bgcolor="#eeeeee"
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| | || || (comment) || || Southbridge ||
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: AMD Geode GX1 video support || || || ||
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| |- bgcolor="#eeeeee"
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| | EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || ||
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| Select if RS690 should be setup to support MMCONF.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | USBDEBUG_DEFAULT_PORT || southbridge/amd/sb600 || int || SATA Mode ||
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| Select the mode in which SATA should be driven. IDE or AHCI.
| |
| The default is IDE.
| |
| | |
| config SATA_MODE_IDE
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| bool "IDE"
| |
| | |
| config SATA_MODE_AHCI
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| bool "AHCI"
| |
| ||
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| |- bgcolor="#eeeeee"
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| | HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary ||
| |
| Select this option to add a CMC state machine binary to
| |
| the resulting coreboot image.
| |
| | |
| Note: Without this binary coreboot will not work
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename ||
| |
| The path and filename of the file to use as CMC state machine
| |
| binary.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | || || (comment) || || Super I/O ||
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| |- bgcolor="#eeeeee"
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| | || || (comment) || || Devices ||
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| |- bgcolor="#eeeeee"
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| | VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter ||
| |
| Allow bridges to set up legacy decoding ranges for VGA. Don't disable
| |
| this unless you're sure you don't want the briges setup for VGA.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | VGA_ROM_RUN || devices || bool || Run VGA option ROMs ||
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| Execute VGA option ROMs, if found. This is required to enable
| |
| PCI/AGP/PCI-E video cards.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs ||
| |
| Execute non-VGA PCI option ROMs, if found.
| |
| | |
| Examples include IDE/SATA controller option ROMs and option ROMs
| |
| for network cards (NICs).
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Native mode ||
| |
| If you select this option, PCI option ROMs will be executed
| |
| natively on the CPU in real mode. No CPU emulation is involved,
| |
| so this is the fastest, but also the least secure option.
| |
| (only works on x86/x64 systems)
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | PCI_OPTION_ROM_RUN_YABEL || devices || bool || Secure mode ||
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| If you select this option, the x86emu CPU emulator will be used to
| |
| execute PCI option ROMs.
| |
| | |
| This option prevents option ROMs from doing dirty tricks with the
| |
| system (such as installing SMM modules or hypervisors), but it is
| |
| also significantly slower than the native option ROM initialization
| |
| method.
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| | |
| This is the default choice for non-x86 systems.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | YABEL_PCI_ACCESS_OTHER_DEVICES || devices || bool || Allow option ROMs to access other devices ||
| |
| Per default, YABEL only allows option ROMs to access the PCI device
| |
| that they are associated with. However, this causes trouble for some
| |
| onboard graphics chips whose option ROM needs to reconfigure the
| |
| north bridge.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | YABEL_VIRTMEM_LOCATION || devices || hex || Location of YABEL's virtual memory ||
| |
| YABEL requires 1MB memory for its CPU emulation. This memory is
| |
| normally located at 16MB.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | YABEL_DIRECTHW || devices || bool || Direct hardware access ||
| |
| YABEL consists of two parts: It uses x86emu for the CPU emulation and
| |
| additionally provides a PC system emulation that filters bad device
| |
| and memory access (such as PCI config space access to other devices
| |
| than the initialized one).
| |
| | |
| When choosing this option, x86emu will pass through all hardware
| |
| accesses to memory and I/O devices to the underlying memory and I/O
| |
| addresses. While this option prevents option ROMs from doing dirty
| |
| tricks with the CPU (such as installing SMM modules or hypervisors),
| |
| they can still access all devices in the system.
| |
| Enable this option for a good compromise between security and speed.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
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| | || || (comment) || || Embedded Controllers ||
| |
| |- bgcolor="#eeeeee"
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| | EC_ACPI || ec/acpi || bool || ||
| |
| ACPI Embedded Controller interface. Mostly found in laptops.
| |
| | |
| ||
| |
| ||
| |
| | |
| |- bgcolor="#6699dd"
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| ! align="left" | Menu: Generic Drivers || || || ||
| |
| |- bgcolor="#eeeeee"
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| | DRIVERS_OXFORD_OXPCIE || drivers/oxford/oxpcie || bool || Oxford OXPCIe952 ||
| |
| Support for Oxford OXPCIe952 serial port PCIe cards.
| |
| Currently only devices with the vendor ID 0x1415 and device ID
| |
| 0xc158 will work.
| |
| NOTE: Right now you have to set the base address of your OXPCIe952
| |
| card to exactly the value that the device allocator would set them
| |
| later on, or serial console functionality will stop as soon as the
| |
| resource allocator assigns a new base address to the device.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
| |
| | OXFORD_OXPCIE_BRIDGE_BUS || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge bus number ||
| |
| While coreboot is executing code from ROM, the coreboot resource
| |
| allocator has not been running yet. Hence PCI devices living behind
| |
| a bridge are not yet visible to the system. In order to use an
| |
| OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
| |
| that controls the OXPCIe952 controller first.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | OXFORD_OXPCIE_BRIDGE_DEVICE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge device number ||
| |
| While coreboot is executing code from ROM, the coreboot resource
| |
| allocator has not been running yet. Hence PCI devices living behind
| |
| a bridge are not yet visible to the system. In order to use an
| |
| OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
| |
| that controls the OXPCIe952 controller first.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | OXFORD_OXPCIE_BRIDGE_FUNCTION || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge function number ||
| |
| While coreboot is executing code from ROM, the coreboot resource
| |
| allocator has not been running yet. Hence PCI devices living behind
| |
| a bridge are not yet visible to the system. In order to use an
| |
| OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
| |
| that controls the OXPCIe952 controller first.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | OXFORD_OXPCIE_BRIDGE_SUBORDINATE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge subordinate bus ||
| |
| While coreboot is executing code from ROM, the coreboot resource
| |
| allocator has not been running yet. Hence PCI devices living behind
| |
| a bridge are not yet visible to the system. In order to use an
| |
| OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
| |
| that controls the OXPCIe952 controller first.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | OXFORD_OXPCIE_BASE_ADDRESS || drivers/oxford/oxpcie || hex || Base address for rom stage console ||
| |
| While coreboot is executing code from ROM, the coreboot resource
| |
| allocator has not been running yet. Hence PCI devices living behind
| |
| a bridge are not yet visible to the system. In order to use an
| |
| OXPCIe952 based PCIe card, coreboot has to set up a temporary address
| |
| for the OXPCIe952 controller.
| |
| | |
| | |
| ||
| |
| | |
| ||
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_SIL_3114 || drivers/sil || bool || Silicon Image SIL3114 ||
| |
| It sets PCI class to IDE compatible native mode, allowing
| |
| SeaBIOS, FILO etc... to boot from it.
| |
| | |
| | |
| | |
| ||
| |
| ||
| |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Console || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL8250 || console || bool || Serial port console output ||
| |
| Send coreboot debug output to an I/O mapped serial port console.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL8250MEM || console || bool || Serial port console output (memory mapped) ||
| |
| Send coreboot debug output to a memory mapped serial port console.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 ||
| |
| Serial console on COM1/ttyS0 at I/O port 0x3f8.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 ||
| |
| Serial console on COM2/ttyS1 at I/O port 0x2f8.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 ||
| |
| Serial console on COM3/ttyS2 at I/O port 0x3e8.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 ||
| |
| Serial console on COM4/ttyS3 at I/O port 0x2e8.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TTYS0_BASE || console || hex || ||
| |
| Map the COM port names to the respective I/O port.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_115200 || console || bool || 115200 ||
| |
| Set serial port Baud rate to 115200.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_57600 || console || bool || 57600 ||
| |
| Set serial port Baud rate to 57600.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_38400 || console || bool || 38400 ||
| |
| Set serial port Baud rate to 38400.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_19200 || console || bool || 19200 ||
| |
| Set serial port Baud rate to 19200.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_SERIAL_9600 || console || bool || 9600 ||
| |
| Set serial port Baud rate to 9600.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | TTYS0_BAUD || console || int || ||
| |
| Map the Baud rates to an integer.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USBDEBUG || console || bool || USB 2.0 EHCI debug dongle support ||
| |
| This option allows you to use a so-called USB EHCI Debug device
| |
| (such as the Ajays NET20DC, AMIDebug RX, or a system using the
| |
| Linux "EHCI Debug Device gadget" driver found in recent kernel)
| |
| to retrieve the coreboot debug messages (instead, or in addition
| |
| to, a serial port).
| |
| | |
| This feature is NOT supported on all chipsets in coreboot!
| |
| | |
| It also requires a USB2 controller which supports the EHCI
| |
| Debug Port capability.
| |
| | |
| See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
| |
| of supported controllers.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | USBDEBUG_DEFAULT_PORT || console || int || Default USB port to use as Debug Port ||
| |
| This option selects which physical USB port coreboot will try to
| |
| use as EHCI Debug Port first (valid values are: 1-15).
| |
| | |
| If coreboot doesn't detect an EHCI Debug Port dongle on this port,
| |
| it will try all the other ports one after the other. This will take
| |
| a few seconds of time though, and thus slow down the booting process.
| |
| | |
| Hence, if you select the correct port here, you can speed up
| |
| your boot time. Which USB port number (1-15) refers to which
| |
| actual port on your mainboard (potentially also USB pin headers
| |
| on your mainboard) is highly board-specific, and you'll likely
| |
| have to find out by trial-and-error.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | ONBOARD_VGA_IS_PRIMARY || console || bool || Use onboard VGA as primary video device ||
| |
| If not selected, the last adapter found will be used.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_NE2K || console || bool || Network console over NE2000 compatible Ethernet adapter ||
| |
| Send coreboot debug output to a Ethernet console, it works
| |
| same way as Linux netconsole, packets are received to UDP
| |
| port 6666 on IP/MAC specified with options bellow.
| |
| Use following netcat command: nc -u -l -p 6666
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_NE2K_DST_MAC || console || string || Destination MAC address of remote system ||
| |
| Type in either MAC address of logging system or MAC address
| |
| of the router.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||
| |
| This is IP adress of the system running for example
| |
| netcat command to dump the packets.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_NE2K_SRC_IP || console || string || IP address of coreboot system ||
| |
| This is the IP of the coreboot system
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_NE2K_IO_PORT || console || hex || NE2000 adapter fixed IO port address ||
| |
| This is the IO port address for the IO port
| |
| on the card, please select some non-conflicting region,
| |
| 32 bytes of IO spaces will be used (and align on 32 bytes
| |
| boundary, qemu needs broader align)
| |
| | |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
| |
| Way too many details.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
| |
| Debug-level messages.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
| |
| Informational messages.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
| |
| Normal but significant conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
| |
| Warning conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
| |
| Error conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
| |
| Critical conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
| |
| Action must be taken immediately.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
| |
| System is unusable.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MAXIMUM_CONSOLE_LOGLEVEL || console || int || ||
| |
| Map the log level config names to an integer.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
| |
| Way too many details.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
| |
| Debug-level messages.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
| |
| Informational messages.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
| |
| Normal but significant conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
| |
| Warning conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
| |
| Error conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
| |
| Critical conditions.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
| |
| Action must be taken immediately.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
| |
| System is unusable.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEFAULT_CONSOLE_LOGLEVEL || console || int || ||
| |
| Map the log level config names to an integer.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | CONSOLE_POST || console || bool || Show POST codes on the debug console ||
| |
| If enabled, coreboot will additionally print POST codes (which are
| |
| usually displayed using a so-called "POST card" ISA/PCI/PCI-E
| |
| device) on the debug console.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#eeeeee"
| |
| | HAVE_HARD_RESET || toplevel || bool || ||
| |
| This variable specifies whether a given board has a hard_reset
| |
| function, no matter if it's provided by board code or chipset code.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_OPTION_TABLE || toplevel || bool || ||
| |
| This variable specifies whether a given board has a cmos.layout
| |
| file containing NVRAM/CMOS bit definitions.
| |
| It defaults to 'n' but can be selected in mainboard/*/Kconfig.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA || toplevel || bool || ||
| |
| Build board-specific VGA code.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GFXUMA || toplevel || bool || ||
| |
| Enable Unified Memory Architecture for graphics.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_ACPI_TABLES || toplevel || bool || ||
| |
| This variable specifies whether a given board has ACPI table support.
| |
| It is usually set in mainboard/*/Kconfig.
| |
| Whether or not the ACPI tables are actually generated by coreboot
| |
| is configurable by the user via GENERATE_ACPI_TABLES.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_MP_TABLE || toplevel || bool || ||
| |
| This variable specifies whether a given board has MP table support.
| |
| It is usually set in mainboard/*/Kconfig.
| |
| Whether or not the MP table is actually generated by coreboot
| |
| is configurable by the user via GENERATE_MP_TABLE.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_PIRQ_TABLE || toplevel || bool || ||
| |
| This variable specifies whether a given board has PIRQ table support.
| |
| It is usually set in mainboard/*/Kconfig.
| |
| Whether or not the PIRQ table is actually generated by coreboot
| |
| is configurable by the user via GENERATE_PIRQ_TABLE.
| |
| | |
| ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: System tables || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables ||
| |
| Generate ACPI tables for this board.
| |
| | |
| If unsure, say Y.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||
| |
| Generate an MP table (conforming to the Intel MultiProcessor
| |
| specification 1.4) for this board.
| |
| | |
| If unsure, say Y.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||
| |
| Generate a PIRQ table for this board.
| |
| | |
| If unsure, say Y.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Payload || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_NONE || toplevel || bool || None ||
| |
| Select this option if you want to create an "empty" coreboot
| |
| ROM image for a certain mainboard, i.e. a coreboot ROM image
| |
| which does not yet contain a payload.
| |
| | |
| For such an image to be useful, you have to use 'cbfstool'
| |
| to add a payload to the ROM image later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_ELF || toplevel || bool || An ELF executable payload ||
| |
| Select this option if you have a payload image (an ELF file)
| |
| which coreboot should run as soon as the basic hardware
| |
| initialization is completed.
| |
| | |
| You will be able to specify the location and file name of the
| |
| payload image later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_SEABIOS || toplevel || bool || SeaBIOS ||
| |
| Select this option if you want to build a coreboot image
| |
| with a SeaBIOS payload. If you don't know what this is
| |
| about, just leave it enabled.
| |
| | |
| See http://coreboot.org/Payloads for more information.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_FILO || toplevel || bool || FILO ||
| |
| Select this option if you want to build a coreboot image
| |
| with a FILO payload. If you don't know what this is
| |
| about, just leave it enabled.
| |
| | |
| See http://coreboot.org/Payloads for more information.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEABIOS_STABLE || toplevel || bool || stable ||
| |
| Stable SeaBIOS version
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | SEABIOS_MASTER || toplevel || bool || master ||
| |
| Newest SeaBIOS version
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FILO_STABLE || toplevel || bool || 0.6.0 ||
| |
| Stable FILO version
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FILO_MASTER || toplevel || bool || HEAD ||
| |
| Newest FILO version
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PAYLOAD_FILE || toplevel || string || Payload path and filename ||
| |
| The path and filename of the ELF executable file to use as payload.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||
| |
| In order to reduce the size payloads take up in the ROM chip
| |
| coreboot can compress them using the LZMA algorithm.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: VGA BIOS || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS || toplevel || bool || Add a VGA BIOS image ||
| |
| Select this option if you have a VGA BIOS image that you would
| |
| like to add to your ROM.
| |
| | |
| You will be able to specify the location and file name of the
| |
| image later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename ||
| |
| The path and filename of the file to use as VGA BIOS.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | VGA_BIOS_ID || toplevel || string || VGA device PCI IDs ||
| |
| The comma-separated PCI vendor and device ID that would associate
| |
| your VGA BIOS to your video card.
| |
| | |
| Example: 1106,3230
| |
| | |
| In the above example 1106 is the PCI vendor ID (in hex, but without
| |
| the "0x" prefix) and 3230 specifies the PCI device ID of the
| |
| video card (also in hex, without "0x" prefix).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | INTEL_MBI || toplevel || bool || Add an MBI image ||
| |
| Select this option if you have an Intel MBI image that you would
| |
| like to add to your ROM.
| |
| | |
| You will be able to specify the location and file name of the
| |
| image later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | MBI_FILE || toplevel || string || Intel MBI path and filename ||
| |
| The path and filename of the file to use as VGA BIOS.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Bootsplash || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOTSPLASH || toplevel || bool || Show graphical bootsplash ||
| |
| This option shows a graphical bootsplash screen. The grapics are
| |
| loaded from the CBFS file bootsplash.jpg.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||
| |
| The path and filename of the file to use as graphical bootsplash
| |
| screen. The file format has to be jpg.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | FRAMEBUFFER_VESA_MODE || toplevel || hex || VESA framebuffer video mode ||
| |
| This option sets the resolution used for the coreboot framebuffer and
| |
| bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
| |
| some day make this a "choice".
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | COREBOOT_KEEP_FRAMEBUFFER || toplevel || bool || Keep VESA framebuffer ||
| |
| This option keeps the framebuffer mode set after coreboot finishes
| |
| execution. If this option is enabled, coreboot will pass a
| |
| framebuffer entry in its coreboot table and the payload will need a
| |
| framebuffer driver. If this option is disabled, coreboot will switch
| |
| back to text mode before handing control to a payload.
| |
| | |
| ||
| |
| | |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Debugging || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | GDB_STUB || toplevel || bool || GDB debugging support ||
| |
| If enabled, you will be able to set breakpoints for gdb debugging.
| |
| See src/arch/x86/lib/c_start.S for details.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages ||
| |
| This option enables additional RAM init related debug messages.
| |
| It is recommended to enable this when debugging issues on your
| |
| board which might be RAM init related.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_CAR || toplevel || bool || Output verbose Cache-as-RAM debug messages ||
| |
| This option enables additional CAR related debug messages.
| |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DEBUG_PIRQ || toplevel || bool || Check PIRQ table consistency ||
| |
| If unsure, say N.
| |
| | |
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| |- bgcolor="#eeeeee"
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| | DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages ||
| |
| This option enables additional SMBus (and SPD) debug messages.
| |
| | |
| Note: This option will increase the size of the coreboot image.
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| | |
| If unsure, say N.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages ||
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| This option enables additional SMI related debug messages.
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| | |
| Note: This option will increase the size of the coreboot image.
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| | |
| If unsure, say N.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | DEBUG_SMM_RELOCATION || toplevel || bool || Debug SMM relocation code ||
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| This option enables additional SMM handler relocation related
| |
| debug messages.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | DEBUG_MALLOC || toplevel || bool || Output verbose malloc debug messages ||
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| This option enables additional malloc related debug messages.
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| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
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| ||
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| |- bgcolor="#eeeeee"
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| | REALMODE_DEBUG || toplevel || bool || Enable debug messages for option ROM execution ||
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| This option enables additional x86emu related debug messages.
| |
| | |
| Note: This option will increase the time to emulate a ROM.
| |
| | |
| If unsure, say N.
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| ||
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| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages ||
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| This option enables additional x86emu related debug messages.
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| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF ||
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| Print information about JMP and RETF opcodes from x86emu.
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| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes ||
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| Print _all_ opcodes that are executed by x86emu.
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| | |
| WARNING: This will produce a LOT of output and take a long time.
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| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&Play accesses ||
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| Print Plug And Play accesses made by option ROMs.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O ||
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| Print Disk I/O related messages.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG_PMM || toplevel || bool || Log PMM ||
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| Print messages related to POST Memory Manager (PMM).
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
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| | |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions ||
| |
| Print messages related to VESA BIOS Extension (VBE) functions.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console ||
| |
| Let INT10 (i.e. character output) calls print messages to debug output.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls ||
| |
| Print messages related to interrupt handling.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses ||
| |
| Print messages related to accesses to certain areas of the virtual
| |
| memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses ||
| |
| Print memory accesses made by option ROM.
| |
| Note: This also includes accesses to fetch instructions.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses ||
| |
| Print I/O accesses made by option ROM.
| |
| | |
| Note: This option will increase the size of the coreboot image.
| |
| | |
| If unsure, say N.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | LLSHELL || toplevel || bool || Built-in low-level shell ||
| |
| If enabled, you will have a low level shell to examine your machine.
| |
| Put llshell() in your (romstage) code to start the shell.
| |
| See src/arch/x86/llshell/llshell.inc for details.
| |
| | |
| ||
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| | |
| |- bgcolor="#eeeeee"
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| | POWER_BUTTON_DEFAULT_ENABLE || toplevel || hex || ||
| |
| Select when the board has a power button which can optionally be
| |
| disabled by the user.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | POWER_BUTTON_DEFAULT_DISABLE || toplevel || hex || ||
| |
| Select when the board has a power button which can optionally be
| |
| enabled by the user, e.g. when the board ships with a jumper over
| |
| the power switch contacts.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
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| | POWER_BUTTON_FORCE_ENABLE || toplevel || hex || ||
| |
| Select when the board requires that the power button is always
| |
| enabled.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
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| | POWER_BUTTON_FORCE_DISABLE || toplevel || hex || ||
| |
| Select when the board requires that the power button is always
| |
| disabled, e.g. when it has been hardwired to ground.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
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| | POWER_BUTTON_IS_OPTIONAL || toplevel || bool || ||
| |
| Internal option that controls ENABLE_POWER_BUTTON visibility.
| |
| | |
| ||
| |
| |- bgcolor="#6699dd"
| |
| ! align="left" | Menu: Deprecated || || || ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOARD_HAS_HARD_RESET || toplevel.deprecated_options || bool || ||
| |
| This variable specifies whether a given board has a reset.c
| |
| file containing a hard_reset() function.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | BOARD_HAS_FADT || toplevel.deprecated_options || bool || ||
| |
| This variable specifies whether a given board has a board-local
| |
| FADT in fadt.c. Long-term, those should be moved to appropriate
| |
| chipset components (eg. southbridge).
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | HAVE_BUS_CONFIG || toplevel.deprecated_options || bool || ||
| |
| This variable specifies whether a given board has a get_bus_conf.c
| |
| file containing information about bus routing.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | DRIVERS_PS2_KEYBOARD || toplevel.deprecated_options || bool || PS/2 keyboard init ||
| |
| Enable this option to initialize PS/2 keyboards found connected
| |
| to the PS/2 port.
| |
| | |
| Some payloads (eg, filo) require this option. Other payloads
| |
| (eg, SeaBIOS, Linux) do not require it.
| |
| Initializing a PS/2 keyboard can take several hundred milliseconds.
| |
| | |
| If you know you will only use a payload which does not require
| |
| this option, then you can say N here to speed up boot time.
| |
| Otherwise say Y.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
| |
| | PCIE_TUNING || toplevel.deprecated_options || bool || ||
| |
| This variable enables certain PCIe optimizations. Right now it's
| |
| only ASPM and it's untested.
| |
| | |
| ||
| |
| | |
| |}
| |