The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
Thanks for your interest in Lenovo X220 port. Issues:
- no MRC cache (longer boot time)
- yellow USB port isn't powered in power-off state.
- Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)
Tested (and works):
- RAM module combinations of 4G+0, 4G+4G, 8G+8G
- S3 (Suspend to RAM)
- digitizer on x220t variant
- WLAN (first minipcie slot)
- Linux (through GRUB-as-payload)
- Fn hotkeys
- Video (both internal and VGA, including native gfx init)
- battery indicator
- Fingerprint reader
- Thermal management
- Expresscard slot (including hotplugging)
- USB (all 3 ports)
- SD card slot
- Sound (integrated speakers, integrated mic, external headphones, external mic)
- WLAN slot USB
- Windows (through SeaBIOS; you have to use extracted VGA blob, dumped from memory isn't good enough)
- dock (Mini Dock Series 3 TYPE 4337 tested)
- USB 3.0 in some models (probably doesn't work)
proprietary components status
- CPU Microcode
- VGA option rom (optional): you need it if you want graphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode), SeaBIOS works with coreboot native gfx init
- ME(Management Engine) => you do not have to touch it(just leave it where it is)
- EC(Embedded Controller) => you do not have to touch it(just leave it where it is)
X220 has 1 flash chip of 8M. It's subdivided in roughly in 3 parts:
- Descriptor (12K)
- ME firmware (5M-12K)
- System flash (7M)
ME firmware is not readable. Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).
Proceeds as follows:
- Turn off your laptop, remove battery and AC adapter.
- Remove the keyboard.
- Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 8M chip.
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate 3.3V source. Make sure not to feed more than 3.3V to the chip. You can use any device such as Raspberry Pi, BeagleBoard or Buspirate -- the latter being the slowest. For how to wire up the clip, see this guide (just for the setup).
- Read the flash. Twice. Compare the files to be sure. Save a copy of it on external media.
flashrom -c "<yourchipname>" -p <yourprogrammer> -r flash.bin flashrom -c "<yourchipname>" -p <yourprogrammer> -r flash2.bin diff flash.bin flash2.bin
If they don't match, do not proceed.
- Recover descriptor and me firmware; you can use dd:
dd if=flash.bin of=coreboot/3rdparty/blobs/mainboard/lenovo/x220/descriptor.bin \ count=12288 bs=1M iflag=count_bytes dd if=flash.bin of=coreboot/3rdparty/blobs/mainboard/lenovo/x220/me.bin \ skip=12288 count=5230592 bs=1M iflag=count_bytes,skip_bytes
Or a much simpler solution is to just use ifdtool (coreboot/util/ifdtool, you may need to compile it):
ifdtool -x </path/to/extracted/flash.bin>
Which will give you your flashdescriptor, bios, intel_me and gbe .bin files.
- Compile coreboot. Before you do this, you will need to make a folder for the .bin files and copy them there:
cd </path/to/coreboot> mkdir -p 3rdparty/blobs/mainboard/lenovo/x220 cd 3rdparty/blobs/mainboard/lenovo/x220 cp </path/to/flashregion_0_flashdescriptor.bin> descriptor.bin cp <flashregion_2_intel_me.bin> me.bin cp <flashregion_3_gbe.bin> gbe.bin
- Follow the Build HOWTO page and flash the resulting build/coreboot.rom
If you have trouble reading the chip successfully, the most common problems are
- insufficient power supply
- bad contacts
- too long wires
- bad pinout
The cable shipped with buspirate was too long, and needed to be trimmed.
Once you are running coreboot any subsequent flashes can be done internally, however you will have to force flashrom:
flashrom -c "<yourchip>" -p internal:laptop=force_I_want_a_brick <-r/-w> file.rom
See also In-System Programming